A 1T1PFC paraferroelectric storage cell and memory array

Abstract

This application relates to the field of in-memory computing memory technology, and more particularly to a 1T1PFC paraferroelectric memory cell and memory array. The 1T1PFC paraferroelectric memory cell includes: a memory transistor; a paraferroelectric capacitor connected to the gate of the memory transistor; and a memory gate line electrically coupled to the bottom electrode of the paraferroelectric capacitor and the gate of the memory transistor via a vertical connection structure. The memory gate line is configured to: after a logic value is written, be biased to a holding-enhanced voltage or floating state, blocking the charge discharge path of the bottom electrode, thereby creating charge isolation between the gate of the memory transistor and the bottom electrode of the paraferroelectric capacitor. The 1T1PFC paraferroelectric memory cell of this application uses a dedicated memory gate line, preventing charge dissipation after writing and enhancing non-volatility and data retention capabilities.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of in-memory computing memory, and particularly to a 1T1PFC ferroelectric memory cell and a memory array. BACKGROUND

[0002] The evolution of artificial intelligence (AI) and neuromorphic computing has driven the demand for memory systems that are not only high-speed and high-density, but also support in-memory computing (CIM). Traditional memory technologies, such as SRAM and DRAM, while fast, suffer from volatility issues and significant energy consumption. Ferroelectric field effect transistor FeFET and single transistor single capacitor (1T1C) ferroelectric structures have become viable candidates for non-volatile memory.

[0003] However, these architectures tend to exhibit reduced endurance, charge retention issues, and limited resistance to read-write interference in high-frequency operation.

[0004] Compared to FeFET, the ferroelectric metal field effect transistor (FeMFET) structure has better endurance, is compatible with CMOS back-end-of-line (BEOL), and is very suitable for embedded memory and AI applications due to its multi-bit capability (similar to FeFET).

[0005] However, the ferroelectric metal field effect transistor (FeMFET) structure causes charge leakage in the device during use due to its floating gate characteristics, affecting data retention capability. SUMMARY

[0006] To solve the defects of the prior art, the purpose of the present application is to provide a 1T1PFC ferroelectric memory cell and a memory array, which uses a dedicated storage gate line to prevent spontaneous charge dissipation after writing in the 1T1PFC ferroelectric memory cell, and enhances data retention capability.

[0007] To achieve the above purpose, the present application provides a 1T1PFC ferroelectric memory cell, comprising:

[0008] a storage transistor;

[0009] a ferroelectric capacitor connected to the gate of the storage transistor;

[0010] a storage gate line electrically coupled to the bottom electrode of the ferroelectric capacitor and the gate of the storage transistor through a vertical connection structure;

[0011] wherein the ferroelectric capacitor is configured to write a logic value through a polarization reaction and modulate the threshold voltage of the storage transistor;

[0012] The storage transistor is configured to read a logic value through a modulated threshold voltage;

[0013] The storage gate line is configured to be biased at a retention boost voltage or a floating state after writing a logic value, blocking a charge leakage path of the bottom electrode, and forming charge isolation between the gate of the storage transistor and the bottom electrode of the ferroelectric capacitor.

[0014] Further, the drain electrode of the storage transistor is electrically connected to a bit line, and the source electrode of the storage transistor is electrically connected to a source line.

[0015] Further, the storage gate line is configured to:

[0016] When writing a logic value, a polarization voltage is formed between the storage gate line and the bit line to induce polarization of the ferroelectric capacitor.

[0017] Further, the storage gate line is further configured to:

[0018] When reading a logic value, it is pulled to a floating state.

[0019] Further, the storage transistor is formed in a front-end-of-line (FEOL) region, and the ferroelectric capacitor is formed in a back-end-of-line (BEOL) region.

[0020] Further, the ferroelectric capacitor comprises:

[0021] a bottom electrode,

[0022] a ferroelectric layer, which is composed of a quantum well layer structure of hafnium silicon oxide and a transition material and a ferroelectric dielectric layer;

[0023] a top electrode.

[0024] To achieve the above-mentioned purpose, the application further provides a preparation method of a 1T1PFC ferroelectric memory cell, comprising the following steps:

[0025] forming a gate stack of the storage transistor in an active device region;

[0026] defining a source region and a drain region, activating a dopant and forming a low resistance junction, forming a bit line contact and a source line contact;

[0027] forming a storage gate line on the gate stack of the storage transistor;

[0028] stacking to form a ferroelectric capacitor;

[0029] forming a plate line;

[0030] metallization and patterning of the wiring.

[0031] Further, the step of forming a storage gate line on the gate stack of the storage transistor comprises:

[0032] forming a storage gate pad on the gate stack of the storage transistor;

[0033] forming a storage gate contact directly coupled to the gate stack of the storage transistor;

[0034] forming a storage gate contact pad on the storage gate contact;

[0035] forming a storage gate line coupled to the storage gate contact pad;

[0036] connecting the storage gate line to the bottom electrode of the ferroelectric capacitor.

[0037] Further, the step of forming the stack includes:

[0038] etching a via pad adjacent to the storage gate line;

[0039] filling the via with a conductive material;

[0040] forming a bottom electrode metal pad;

[0041] depositing the bottom electrode by a plasma enhanced atomic layer deposition method;

[0042] depositing the ferroelectric layer by an atomic layer deposition method;

[0043] depositing the top electrode.

[0044] To achieve the above object, the present application further provides a memory array comprising the 1T1PFC ferroelectric memory cell as described above, wherein the 1T1PFC ferroelectric memory cells in the same row are configured as the same bit line, the same plate line and the same source line, and the 1T1PFC ferroelectric memory cells in the same column are configured as the same storage gate line.

[0045] Further, the write operation of the memory array comprises:

[0046] applying corresponding write voltages to the plate line and the storage gate line of the selected 1T1PFC ferroelectric memory cell respectively, and programming the selected 1T1PFC ferroelectric memory cell;

[0047] configuring other plate lines and other storage gate lines as stepped voltages.

[0048] Further, the read operation of the memory array comprises:

[0049] applying corresponding read voltages to the plate line, the bit line and the storage gate line of the selected 1T1PFC ferroelectric memory cell respectively, and reading the selected 1T1PFC ferroelectric memory cell;

[0050] Configure other plate lines, other storage gate lines, and other bit lines to 0V.

[0051] Further, the reset operation of the memory array includes:

[0052] Configure all plate lines, storage gate lines, bit lines, and source lines to 0V.

[0053] To achieve the above object, the application further provides an AI chip comprising the memory array as described above.

[0054] The 1T1PFC ferroelectric memory cell provided by the application prevents the dissipation of charges after writing by using a dedicated storage gate line to control the flow of charges after writing, thereby enhancing the non-volatility and data retention capability.

[0055] The 1T1PFC ferroelectric memory cell provided by the application can realize low-voltage writing with strong retention, and is suitable for edge AI devices with limited energy; the modulated ferroelectric capacitor realizes multi-level state control, supports analog weight storage and computing functions, and has low power consumption and high reliability.

[0056] The 1T1PFC ferroelectric memory cell provided by the application integrates the ferroelectric capacitor and the storage transistor, greatly reduces the cell size of the ferroelectric memory cell, and improves the storage density.

[0057] Other features and advantages of the application will be described in the following description, and some will become apparent from the description, or will be understood by those skilled in the art through implementation of the application. BRIEF DESCRIPTION OF DRAWINGS

[0058] The accompanying drawings are intended to provide a further understanding of the application, and constitute a part of the specification, and together with the embodiments of the application, serve to explain the application, and do not constitute a limitation on the application. In the drawings:

[0059] Figure 1 The structure schematic diagram of the 1T1PFC ferroelectric memory cell of the embodiment 1 of the application;

[0060] Figure 2 The write "1" operation schematic diagram of the 1T1PFC ferroelectric memory cell of the embodiment 1 of the application;

[0061] Figure 3 The write "0" operation schematic diagram of the 1T1PFC ferroelectric memory cell of the embodiment 1 of the application;

[0062] Figure 4 The read operation schematic diagram of the 1T1PFC ferroelectric memory cell of the embodiment 1 of the application;

[0063] Figure 5Schematic diagram of a write "1" operation for the memory array of Example 2 of the present application;

[0064] Figure 6 Schematic diagram of a write "0" operation for the memory array of Example 2 of the present application;

[0065] Figure 7 Schematic diagram of a reset operation for the memory array of Example 2 of the present application;

[0066] Figure 8 Schematic diagram of a read operation for the memory array of Example 2 of the present application;

[0067] Figure 9 Schematic diagram of a flow for fabricating a 1T1P FC ferroelectric memory cell of Example 3 of the present application;

[0068] Figure 10 Schematic diagram of forming an active device region of Example 3 of the present application;

[0069] Figure 11 Schematic diagram of forming a storage transistor into a gate stack of Example 3 of the present application;

[0070] Figure 12 Schematic diagram of forming a storage gate pad of Example 3 of the present application;

[0071] Figure 13 Schematic diagram of forming a drain contact, a source contact, and a storage gate contact of Example 3 of the present application;

[0072] Figure 14 Schematic diagram of forming a bit line and a source line of Example 3 of the present application;

[0073] Figure 15 Schematic diagram of forming a storage gate contact landing pad (SGCLP) of Example 3 of the present application;

[0074] Figure 16 Schematic diagram of forming a storage gate line (SGL) of Example 3 of the present application;

[0075] Figure 17 Schematic diagram of forming a via landing pad (LP) of Example 3 of the present application;

[0076] Figure 18 Schematic diagram of forming a bottom electrode (BE) of Example 3 of the present application;

[0077] Figure 19 Schematic diagram of forming a ferroelectric layer and a top electrode layer of Example 3 of the present application;

[0078] Figure 20 Schematic diagram of forming a plate line of Example 3 of the present application.

[0079] Reference signs:

[0080] 10 - silicon substrate, 11 - active device region, 12 - memory transistor, 13 - shallow trench isolation, 14 - drain diffusion, 15 - source diffusion, 16 - gate stack, 17 - memory gate pad, 171 - memory gate line, 18 - drain contact, 19 - source contact, 20 - memory gate contact, 21 - bit line, 22 - source line, 23 - memory gate contact pad, 24 - memory gate line, 25 - via pad, 26 - bottom electrode, 27 - ferroelectric layer, 28 - top electrode, 29 - plate line, 30 - ferroelectric capacitor. DETAILED DESCRIPTION

[0081] The preferred embodiments of the present application will be described herein below with reference to the accompanying drawings; it should be understood that the preferred embodiments described herein are merely used to illustrate and explain the present application, and should not be used to limit the present application.

[0082] Embodiments of the present application will be described below in greater detail with reference to the accompanying drawings. While certain embodiments of the present application are shown in the drawings, it is understood that the present application can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein, but rather, the embodiments are provided so as to more completely and comprehensively understand the present application. It should be understood that the drawings and embodiments of the present application are merely for exemplary purposes and should not be used to limit the scope of protection of the present application.

[0083] The term "comprising" and variations thereof as used herein are used inclusively, i.e., "comprising, but not limited to". The term "based on" is "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Related terms are defined in the description that follows.

[0084] It should be noted that the terms "first", "second", and the like in the present application can be used to distinguish different devices, components or parts, and are not intended to limit the order or interdependence of the functions performed by these devices, components or parts.

[0085] It should be noted that the terms "one", "multiple" mentioned in the present application are illustrative and not restrictive, and those skilled in the art should understand that unless otherwise explicitly stated in the context, it should be understood as "one or more". "Multiple" should be understood as two or more.

[0086] It is noted that the "1T1PFC" in the present application, which refers to a transistor and a single para-ferroelectric capacitor, means a transistor and a para-ferroelectric capacitor.

[0087] Embodiment 1

[0088] In the embodiments of the present application, a 1T1PFC para-ferroelectric memory cell is provided, Figure 1 A structure diagram of the 1T1PFC para-ferroelectric memory cell of Embodiment 1 of the present application is shown in FIG. 1, which includes: Figure 1

[0089] A storage transistor 12 is configured to read a logic value through a modulated threshold voltage;

[0090] A para-ferroelectric capacitor 30 is connected to the gate of the storage transistor 12, and the para-ferroelectric capacitor 30 is configured to write a logic value through a polarization reaction and modulate the threshold voltage of the storage transistor 12;

[0091] In the present embodiment, the para-ferroelectric capacitor 30 includes a bottom electrode 26, a para-ferroelectric layer 27, and a top electrode 28, and a plate line (PL) 29 is formed on the top electrode 28. The para-ferroelectric layer 27 is composed of a quantum well layer structure and a ferroelectric dielectric layer formed by hafnium silicon oxide and a transition material, and the transition material can be HfO2, ZrO2, TiO2, TiN, TaN, Al2O3, and TaO x In the present embodiment, the para-ferroelectric layer 27 is further provided with a layer of TiN on the upper and lower surfaces.

[0092] In the present embodiment, the para-ferroelectric layer 27 is further provided with a layer of TiN on the upper and lower surfaces.

[0093] A storage gate line (SGL) 24 is electrically coupled to the bottom electrode 26 of the para-ferroelectric capacitor 30 and the gate of the storage transistor 12 through a vertical connection structure, and is configured to be biased at a retention enhancement voltage or a floating state after writing a logic value, to block the charge discharge path of the bottom electrode 26, and to form charge isolation between the gate of the storage transistor 12 and the bottom electrode 26 of the para-ferroelectric capacitor 30;

[0094] In the embodiments of the present application, the 1T1PFC para-ferroelectric memory cell allows non-destructive reading, programmable writing capability, compatibility with back-end-of-line (BEOL) 3D integration, and in-memory computing by modulating the threshold voltage of the storage transistor through the ferroelectric polarization state.

[0095] ​In the embodiments of this application, the drain of the storage transistor 12 is electrically connected to the bit line (BL) 21 through the drain contact 18, and the source of the storage transistor 12 is electrically connected to the active line (SL) 22 through the source contact 19.

[0096] In this embodiment, the storage transistor 12 is formed on the active device region 11 of the silicon substrate 10, including a gate stack 16 (corresponding to the gate), a source diffusion region 15 (corresponding to the source), and a drain diffusion region 14 (corresponding to the drain). The drain diffusion region 14 is electrically connected to the bit line (BL) 21 through the drain contact 18, and the source diffusion region 15 is electrically connected to the active line (SL) 22 through the source contact 19. The active device region 11 is isolated by a shallow trench isolation 13.

[0097] In this embodiment, a storage gate pad 17 is provided on the gate stack 16, and a storage gate contact 20 is provided on the storage gate pad 17. A storage gate contact pad 23 is formed on the storage gate contact 20, and a storage gate line 24 is formed on the storage gate contact pad 23.

[0098] It should be noted that the storage gate contact 20, source contact 19 and drain contact 18 are all composed of interlayer dielectric, contact holes formed on the interlayer dielectric, and conductive metal (such as W or Cu) filled in the contact holes.

[0099] This application provides a write operation for the aforementioned 1T1PFC ferroelectric storage cell. Figure 2 This is a schematic diagram of the write "1" operation of the 1T1PFC ferroelectric storage cell in Embodiment 1 of this application. Figure 3 This is a schematic diagram illustrating the writing of "1" and writing of "0" in the 1T1PFC ferroelectric storage cell of Embodiment 1 of this application, as shown below. Figure 2 and Figure 3 As shown, during writing, a 0V voltage is applied to the storage gate line 24, and a programming voltage of +Vpp or -Vpp is applied to the board line 29, causing opposite polarization voltages to be formed across the paraferroelectric capacitor 30, making the paraferroelectric capacitor 30 polarize in opposite directions, thereby realizing the writing of logic 1 and logic 0 respectively.

[0100] This application embodiment provides an enhanced data retention operation. After writing is completed, the storage gate line 24 is configured to float or maintain an enhanced voltage (0V~0.2V) to block the charge discharge path of the bottom electrode 26, thereby forming charge isolation between the gate of the storage transistor 12 and the bottom electrode 26 of the paraferroelectric capacitor 30.

[0101] It is understandable that the paraferroelectric capacitor 30 will modulate and change the threshold voltage of the storage transistor 12 after polarization. Different polarization directions will modulate and generate the corresponding threshold voltage of the storage transistor 12.

[0102] This application provides a read operation for the aforementioned 1T1PFC ferroelectric storage unit. Figure 4 This is a schematic diagram of the read operation of the 1T1PFC ferroelectric storage unit in Embodiment 1 of this application, as shown below. Figure 4 As shown, during reading, a read voltage of 0.7-0.9V is applied to board line 29, a Vd voltage of 0.2-0.7V is applied to bit line 21, and a floating voltage is applied to storage gate line 24, which in turn converts to a readable logic state according to the conduction state of storage transistor 12.

[0103] In this embodiment, due to the isolated access path, the read operation does not interfere with the polarization state.

[0104] The 1T1PFC paraferroelectric memory cell of this application uses a dedicated SGL to prevent spontaneous charge dissipation after writing, enhancing non-volatility; the separation of the storage path and read control path minimizes accidental flipping during read / write cycles; lower write current stress and isolated gate structure extend device lifetime; it can achieve low-voltage writing with strong retention, making it suitable for energy-constrained edge AI devices; multi-level state control is achieved through modulated FeCAPs, supporting analog weighted storage and computation functions, and featuring low power consumption and high reliability.

[0105] It is understood that the 1T1PFC paraferroelectric memory cell with a storage gate line in this application embodiment introduces an independent read control path, which has the following technical improvements and advantages:

[0106] Read gating allows memory cells to be isolated when not explicitly accessed;

[0107] Leakage current suppression is crucial for large arrays;

[0108] Reduce inter-unit interference, especially during partial access;

[0109] Improved durability because the programming voltage is distributed across the FeCAPs.

[0110] These technological improvements significantly enhance reliability, especially in low-voltage or battery-limited environments (e.g., edge AI chips, IoT memory modules).

[0111] Example 2

[0112] In the embodiments of this application, a memory array is also provided, including a plurality of 1T1PFC ferroelectric memory cells arranged in an array as described above, wherein the 1T1PFC ferroelectric memory cells in the same row are configured to have the same bit line, the same board line and the same source line, and the 1T1PFC ferroelectric memory cells in the same column are configured to have the same memory gate line, and the plurality of 1T1PFC ferroelectric memory cells perform in-memory computing operations in parallel.

[0113] The memory array in this embodiment further includes: a high-voltage pulse driver for FeCAP writing, a sense amplifier optimized for low-leakage reads, and peripheral circuitry for an address decoder for multi-line control (BL, SGL, PL, SL).

[0114] Figure 5 This is a schematic diagram of a write "1" operation of the memory array in Embodiment 2 of this application, as shown below. Figure 5 As shown, the memory array consists of 12 1T1PFC ferroelectric memory cells arranged in three rows and four columns. The four 1T1PFC ferroelectric memory cells in the first row are configured to be connected to the same bit line BL(1), the same board line PL(1), and the same source line SL(1); the four 1T1PFC ferroelectric memory cells in the second row are configured to be connected to the same bit line BL(2), the same board line PL(2), and the same source line SL(2); the four 1T1PFC ferroelectric memory cells in the third row are configured to be connected to the same bit line BL(3). The three 1T1PFC ferroelectric memory cells in the first column are configured to be connected to the same memory gate line SGL (4); the three 1T1PFC ferroelectric memory cells in the second column are configured to be connected to the same memory gate line SGL (3); the three 1T1PFC ferroelectric memory cells in the third column are configured to be connected to the same memory gate line SGL (2); the three 1T1PFC ferroelectric memory cells in the fourth column are configured to be connected to the same memory gate line SGL (1).

[0115] Among them, the 1T1PFC ferroelectric memory cell 500 to be selected for the write 1 operation is located in the second row and fourth column. When writing 1, the board line PL (2) is configured to Vpp programming voltage, the memory gate line SGL (1) is configured to 0V, the other board lines are configured to graded voltage 1 / 3Vpp, the other memory gate lines are configured to another graded voltage 2 / 3Vpp, and all bit lines and source lines are configured to 0V.

[0116] Figure 6 This is a schematic diagram of the write "0" operation of the memory array in Embodiment 2 of this application, as shown below. Figure 6As shown, the 1T1PFC ferroelectric memory cell 500 to be selected for write 1 operation is located in the second row and fourth column. When writing 0, the board line PL (2) is configured to be -Vpp programming voltage, the memory gate line SGL (1) is configured to be 0V, the other board lines are configured to be graded voltage -1 / 3Vpp, the other memory gate lines are configured to be another graded voltage -2 / 3Vpp, and all bit lines and source lines are configured to be 0V.

[0117] Figure 7 This is a schematic diagram of the memory array reset operation in Embodiment 2 of this application, as shown below. Figure 7 As shown, after a write operation, all board lines, bit lines, source lines, and memory gate lines are configured to 0V to enhance data retention. The memory gate line SGL(1) is configured to 0V.

[0118] Figure 8 This is a schematic diagram of the read operation of the memory array in Embodiment 2 of this application, as shown below. Figure 8 As shown, during the read operation, the bit line BL(2) is configured with a Vd voltage of 0.2-0.7V, the board line PL(2) is configured with a Vread voltage of less than 1 / 3Vpp, the memory gate line SGL(1) is configured with a floating voltage, and other memory gate lines, other board lines, other source lines and other bit lines are configured with 0V.

[0119] Generally speaking, 2 / 3Vpp - Vdd < Vc < Vdd, Vpp < 3Vdd.

[0120] The memory array in this application embodiment can be used for:

[0121] AI inference accelerator: Storing synaptic weights in a non-volatile and analog computing manner;

[0122] Edge devices: Reduce power consumption by minimizing DRAM access and maintaining weights locally;

[0123] Neuromorphic systems: non-volatile components that enable programmability, analog-like design, and high durability.

[0124] Example 3

[0125] Embodiment 3 of the application also provides a method for fabricating a 1T1PFC paraferroelectric memory cell with a storage gate line, which is compatible with standard CMOS back-end process (BEOL) processing. The structure is designed to be stacked on top of logic devices and uses layers and materials commonly used in BEOL processing.

[0126] Figure 9 This is a schematic flowchart illustrating the fabrication method of the 1T1PFC paraferroelectric memory cell according to Embodiment 3 of this application. The following will refer to... Figure 9The preparation method of the 1T1PFC paraferroelectric memory cell of Embodiment 3 of this application is described in detail below:

[0127] Step 101: Isolate the active device region on the silicon substrate.

[0128] In this embodiment, firstly, shallow trench isolation regions need to be defined on the silicon substrate by photolithography, and then shallow trench isolation (STI) of a predetermined depth is formed by dry etching (such as HBr / Cl2 plasma) of the shallow trench isolation regions. The shallow trench isolation 13 isolates multiple active device regions 11 on the silicon substrate 10. Then, oxides (such as SiO2, deposited by high-density plasma chemical vapor deposition (HDP-CVD)) are deposited in the formed shallow trench isolation 13 to fill the trenches; excess material is removed by chemical mechanical polishing (CMP) to retain a flat surface, such as... Figure 10 As shown, multiple active device regions 11 are formed on the silicon substrate 10.

[0129] Step 102: Form the gate stack and diffusion region of the storage transistor on the active device region.

[0130] In this embodiment, firstly, a gate oxide layer is grown or deposited on the active device region 11 of the silicon substrate 10, such as growing SiO2 (silicon dioxide) or silicon oxynitride gate oxide (SiON gate oxide), wherein SiON has a higher dielectric constant than SiO2 (improving the interface states of high-k dielectrics).

[0131] Then, a high-k dielectric layer and a gate electrode are deposited on the gate oxide layer: a high-k dielectric layer and a TiN gate electrode are deposited by atomic layer deposition (ALD) to form a gate stack 16, and a memory gate line 171 is formed by photolithography and dry etching, as shown. Figure 11 As shown;

[0132] Then, source diffusion region 15 and drain diffusion region 14 were defined by ion implantation, followed by high-temperature annealing to activate the dopant and form a low-resistance junction, such as... Figure 11 As shown.

[0133] Finally, the memory line 171 is cut to form the memory gate pad (SGP) 17, as shown. Figure 12 As shown.

[0134] In step 103, bit line contacts, source line contacts, and memory gate contacts are formed;

[0135] In this embodiment, an interlayer dielectric (ILD) is deposited on the drain diffusion region 14, the source diffusion region 15, and the storage gate pad (SGP) 17, respectively. Contact vias are etched and filled with a conductive metal (such as W or Cu) to form a bit line contact (BL contact) 18, a source line contact (SL contact) 19, and a storage gate contact 20. Figure 13 As shown.

[0136] Step 104: Form the bit line and source line;

[0137] In this embodiment, a bit line (BL) 21 is formed on the bit line contact 18, and a source line (SL) 22 is formed on the source line contact 19, as follows. Figure 14 As shown.

[0138] Step S105: Form the memory gate line;

[0139] The specific process of forming the memory gate line is as follows:

[0140] A storage gate contact pad (SGCLP) 23 is formed on the storage gate contact, such as Figure 15 As shown;

[0141] Forming a storage gate line (SFL) 24 coupled to the storage gate contact pad 23, such as Figure 16 As shown,

[0142] Step S106: Form a paraferroelectric capacitor;

[0143] The specific process of forming the paraferroelectric capacitor 30 is as follows:

[0144] Etch via pads (LP) 25 adjacent to the SGL (memory gate line), such as Figure 17 As shown;

[0145] Fill the through-hole with conductive material;

[0146] Forming the bottom electrode (BE) 26, such as Figure 18 As shown;

[0147] A bottom TIN pad, a paraferroelectric layer 27, and a top TIN pad are deposited using plasma-enhanced atomic layer deposition (PEALD). The paraferroelectric layer 27 consists of a quantum well layered structure formed from hafnium silicon oxide and a transition material, and a ferroelectric dielectric layer. The transition material can be HfO2, ZrO2, TiO2, TiN, TaN, Al3O3, or TaO. x The ferroelectric dielectric layer is HfZrO2; finally, the top electrode 28 is deposited to form a paraferroelectric capacitor 30, such as... Figure 19 As shown;

[0148] In step 107, plate lines are formed.

[0149] In this embodiment, the upper BEOL metal layer is used to form a PL interconnect, routing the voltage of the board line (PL) 29 to the top electrode 28, such as... Figure 20 As shown.

[0150] In step 108, metallization and patterning of wiring are performed.

[0151] In this embodiment, the gate lines, bit lines, source lines, board lines, and additional peripheral circuits are wired and the remaining interconnects are patterned, and passivation and planarization layers are applied to protect the structure.

[0152] Example 4

[0153] In the embodiments of this application, an AI chip is also provided, including a memory array as described in Embodiment 2. AI chips employing this memory array significantly improve area efficiency and signal tolerance.

[0154] It will be understood by those skilled in the art that the above descriptions are merely preferred embodiments of this application and are not intended to limit this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A 1T1P FC ferroelectric memory cell, comprising: Comprising: a storage transistor; a ferroelectric capacitor in series, connected to the gate of the storage transistor; a storage gate line, electrically coupled to the bottom electrode of the ferroelectric capacitor and the gate of the storage transistor through a vertical connection structure; wherein the ferroelectric capacitor is configured to write a logic value by a polarization reaction and modulate the threshold voltage of the storage transistor; the storage transistor is configured to read the logic value by the modulated threshold voltage; the storage gate line is configured to be biased at a retention enhancement voltage or a floating state after writing the logic value, block the charge leakage path of the bottom electrode, and form charge isolation between the gate of the storage transistor and the bottom electrode of the ferroelectric capacitor.

2. The 1T1P FC ferroelectric memory cell of claim 1, wherein, The drain of the storage transistor is electrically connected to a bit line, and the source of the storage transistor is electrically connected to a source line.

3. The 1T1P FC ferroelectric memory cell of claim 2, wherein, The storage gate line is configured to: form a polarization voltage with the bit line to induce the ferroelectric capacitor to polarize when writing a logic value.

4. The 1T1P FC ferroelectric memory cell of claim 1, wherein, The storage gate line is also configured to: pull to a floating state when reading a logic value.

5. The 1T1P FC ferroelectric memory cell of claim 1, wherein, The storage transistor is formed in a front-end-of-line region, and the ferroelectric capacitor is formed in a back-end-of-line region.

6. The 1T1P FC ferroelectric memory cell of claim 5, wherein, The ferroelectric capacitor comprises: a bottom electrode, a ferroelectric layer composed of a quantum well layered structure of hafnium silicon oxide and a transition material and a ferroelectric dielectric layer; a top electrode.

7. A method for manufacturing a 1T1PFC ferroelectric capacitor memory cell, comprising the following steps: forming a gate stack of a storage transistor in an active device region; defining a source region and a drain region, activating dopants and forming a low resistance junction, forming a bit line contact, a source line contact; forming a storage gate line on the gate stack of the storage transistor; stacking to form a ferroelectric capacitor; forming a plate line; metallization and patterning of the wiring.

8. The method of claim 7, wherein the 1T1P FC ferroelectric memory cell is formed by: The step of forming a storage gate line on the gate stack of the storage transistor comprises: forming a storage gate pad on the gate stack of the storage transistor; forming a storage gate contact directly coupled to the gate stack of the storage transistor; forming a storage gate contact pad on the storage gate contact; forming a storage gate line coupled to the storage gate contact pad; connecting the storage gate line to the bottom electrode of the ferroelectric capacitor.

9. The method of claim 7, wherein the 1T1P FC ferroelectric memory cell is formed by: The step of stacking to form a ferroelectric capacitor comprises: etching a via pad adjacent to the storage gate line; filling the via with a conductive material; forming a bottom electrode metal pad; depositing the bottom electrode by plasma-enhanced atomic layer deposition; depositing the ferroelectric layer by atomic layer deposition; depositing the top electrode.

10. A memory array, comprising: Comprising a plurality of 1T1PFC ferroelectric capacitor memory cells according to any one of claims 1-6 arranged in an array, wherein the 1T1PFC ferroelectric capacitor memory cells in the same row are configured with the same bit line, the same plate line and the same source line, and the 1T1PFC ferroelectric capacitor memory cells in the same column are configured with the same storage gate line.

11. The memory array of claim 10, wherein, The write operation of the memory array comprises: applying corresponding write voltages to the selected 1T1PFC ferroelectric capacitor memory cell plate line and storage gate line, respectively, to program the selected 1T1PFC ferroelectric capacitor memory cell; configuring other plate lines and other storage gate lines to be stepped voltages.

12. The memory array of claim 10, wherein, The read operation of the memory array, comprising: applying corresponding read voltages to the selected 1T1P FC ferroelectric memory cell's plate line, bit line and storage gate line respectively, and reading the selected 1T1P FC ferroelectric memory cell; configuring other plate lines, other storage gate lines and other bit lines to 0V.

13. The memory array of claim 10, wherein, The reset operation of the memory array, comprising: configuring all plate lines, storage gate lines, bit lines and source lines to 0V.

14. An AI chip, comprising: The memory array of any one of claims 10-13.

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