Read control method of memory, read operation control device and memory

Abstract

The embodiment of the invention provides a reading control method of a memory, a reading operation control device and the memory. The reading control method comprises the following steps: applying a first detection voltage to each memory unit of the memory; acquiring hard information corresponding to the first detection voltage through hard decision; decoding the hard information by adopting a first hard decoding algorithm; repeating the steps of applying the first detection voltage, obtaining the hard information corresponding to the first detection voltage and decoding the hard information until an end condition is met; for the storage unit with decoding failure output by the first hard decoding algorithm, selecting a first detection voltage corresponding to the best decoding effect as an optimal detection voltage; and for the storage unit with decoding failure output by the first hard decoding algorithm, decoding the hard information under the optimal detection voltage by adopting a second hard decoding algorithm. The combination of the two decoding algorithms is beneficial to reducing the decoding time and improving the decoding efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of memory, and more particularly to a read control method of memory, a read operation control device and memory. BACKGROUND

[0002] In a storage system such as a flash memory, a decoder is usually required to decode the read data to obtain the data content when a read operation is performed. When a decoding algorithm is iteratively performed in the decoder, a certain number of error data bits are corrected using an error correction code (ECC). In existing error correction code technology, an LDPC code (i.e., a low-density parity-check code) has a significant advantage in decoding algorithm.

[0003] There are three main ways of decoding an LDPC code: hard decision decoding, soft decision decoding and hybrid decoding. In hard decision decoding, a digital demodulator directly outputs 0 or 1 according to a decision threshold after judging the received signal waveform, and 0 or 1 constitutes hard information, and then a decoder uses a decoding algorithm to verify and correct the hard information (i.e., decoding). In soft decision decoding, an analog quantity is directly output, or the demodulator output waveform is quantized to multiple levels, i.e., so-called soft information, which is judged by the decoder. Hybrid decoding is a combination of hard decision decoding and soft decision decoding.

[0004] For the same LDPC code, different decoding methods and decoding algorithms can obtain different error correction performance. Existing storage systems mostly use hybrid decoding, and a common scheme is: first, a Min-Sum algorithm is used for hard decision decoding, and then for the storage unit whose decoding fails, "soft information" is obtained on the basis of the last several groups of detection voltages that are successfully decoded, and then the "soft information" is used for decoding, but the overall time overhead of this scheme is large and needs to be improved. SUMMARY

[0005] Therefore, the present application provides a read control method of memory, a read operation control device and memory, which reduces the time overhead to some extent and improves the data read efficiency.

[0006] According to an embodiment of the present disclosure, a read control method of memory is provided, comprising:

[0007] applying different first detection voltages to each storage unit of the memory;

[0008] obtaining hard information corresponding to the first detection voltages by hard decision;

[0009] decoding the hard information using a first hard decoding algorithm;

[0010] repeating the steps of applying the first detection voltage, obtaining the hard information corresponding to the first detection voltage, and decoding the hard information until a termination condition is met;

[0011] for the storage unit whose decoding fails in the output of the first hard decoding algorithm, selecting a first detection voltage corresponding to the best decoding effect from the plurality of first detection voltages as a best detection voltage;

[0012] for the storage unit whose decoding fails in the output of the first hard decoding algorithm, decoding the hard information under the best detection voltage by using a second hard decoding algorithm.

[0013] In some embodiments, further comprising: adjusting the bias voltage symmetrically left and right based on the best detection voltage to obtain a plurality of second detection voltages applied to the storage unit whose decoding fails in the output of the second hard decoding algorithm to obtain soft information;

[0014] decoding the soft information by using a soft decoding algorithm.

[0015] In some embodiments, further comprising: for the storage unit whose decoding fails in the output of the soft decoding algorithm, performing a best voltage search algorithm with the best detection voltage as an input reference to obtain an actual bottom voltage, and simultaneously obtaining soft information for decoding in the process of searching for the bottom voltage.

[0016] In some embodiments, the first hard decoding algorithm is a bit flipping algorithm, and the first hard decoding algorithm is an LLR belief propagation algorithm or a min-sum algorithm

[0017] In some embodiments, the corresponding steps of the read control method are performed in parallel.

[0018] According to another embodiment of the present disclosure, a read operation control device of a memory is provided, comprising:

[0019] a first read module configured to apply a first detection voltage to each storage unit of the memory and obtain hard information corresponding to the first detection voltage by hard decision;

[0020] a hard information cache unit configured to store the hard information;

[0021] an LDPC decoder comprising a first decoding unit and a second decoding unit, the first decoding unit being configured to decode by using a first hard decoding algorithm, and the second decoding unit being configured to decode by using a second hard decoding algorithm,

[0022] The first decoding unit stops decoding when a termination condition is met, and outputs a best detection voltage corresponding to a storage unit with the best decoding effect in case of decoding failure.

[0023] In some embodiments, the method further comprises:

[0024] The second reading module adjusts the bias voltage symmetrically left and right based on the best detection voltage to obtain a plurality of second detection voltages, and applies the plurality of second detection voltages to the storage unit with decoding failure output by the second hard decoding algorithm to obtain soft information.

[0025] The third decoding unit decodes the soft information using a soft decoding algorithm.

[0026] In some embodiments, the third decoding unit is further configured to: for the storage unit with decoding failure output by the soft decoding algorithm, execute a best voltage search algorithm with the best detection voltage as an input reference to obtain an actual valley bottom voltage, and obtain soft information for decoding in the process of searching for the valley bottom voltage.

[0027] In some embodiments, the first hard decoding algorithm is a bit flipping algorithm, and the first hard decoding algorithm is a LLR belief propagation algorithm or a min-sum algorithm.

[0028] According to still another embodiment of the present disclosure, a memory controller is provided, comprising the read operation control device described above.

[0029] According to yet another embodiment of the present disclosure, a memory is provided, comprising a flash memory chip and the memory controller described above.

[0030] The read control method of the memory provided by the embodiments of the present disclosure performs hard decision decoding through the first decoding unit and the second decoding unit, the hard decision decoding supports die-parallel operation, and more data is successfully hard-decision decoded in the first decoding unit and the second decoding unit without entering the soft decision decoding of the third decoding unit, thereby reducing the decoding time and improving the decoding efficiency as a whole. Moreover, the best detection voltage corresponding to the storage unit with unsuccessful decoding is screened out by the first decoding unit, and the hard information corresponding to the best detection voltage is continuously used in the second decoding unit to continue decoding the data with unsuccessful decoding, which also helps to reduce the decoding time. BRIEF DESCRIPTION OF DRAWINGS

[0031] The above and other objects, features and advantages of the present application will become more apparent from the following description when taken in conjunction with the accompanying drawings, in which:

[0032] Figure 1 a schematic block diagram of a storage system is shown;

[0033] Figure 2 a schematic block diagram of a read operation control apparatus in a storage system according to an embodiment of the present disclosure is shown;

[0034] Figure 3 a flow chart of a read operation control method of a storage system according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0035] The present application is described below based on embodiments, but the present application is not limited to only these embodiments. In the following detailed description of the present application, some specific details are described in detail. The present application can be fully understood without the description of these specific details. In order to avoid confusion of the essence of the present application, the well-known methods, processes, and flows are not described in detail. In addition, the drawings are not necessarily drawn to scale.

[0036] The flow charts and block diagrams in the drawings illustrate the possible architectural, functional and operational scenarios of systems, methods and apparatuses according to embodiments of the present application. The blocks on the flow charts and block diagrams can represent a module, a program segment or only a piece of code, which are executable instructions for implementing the specified logic functions. It should also be noted that the executable instructions for implementing the specified logic functions can be recombined to generate new modules and program segments. Therefore, the blocks of the drawings and the block sequence are only used to better illustrate the processes and steps of the embodiments, and should not be regarded as a limitation on the present application itself.

[0037] Figure 1 A schematic block diagram of a storage system is shown. The storage system is, for example, a computer system using a solid state drive (SSD). The storage system includes a host 110. The solid state drive includes a memory controller 120 and a storage medium 130. The host 110 accesses the storage medium 130 via the memory controller 120. The storage medium 130 includes at least one flash memory chip 131. In the storage system, the stored data is encoded data generated by encoding the original data, and the original data is obtained by decoding the stored data in the reading process.

[0038] The host 110 includes, for example, a processor. In the use state, the processor loads programs or reads data from the storage medium 130, and writes data to the storage medium 130.

[0039] The memory controller 120 is, for example, a separate integrated circuit chip including a write control device and a read operation control device. During a write operation, the write control device LDPC encodes the original data, generates storage data, and writes the storage data into the storage medium 130. During a read operation, the read operation control device sequentially acquires storage data from each storage page of the storage medium 130, then performs LDPC hard decision decoding based on the storage data to obtain the original data, and for a storage page in which the LDPC hard decision decoding fails, performs a plurality of read operations at a plurality of detection voltages to obtain soft information, and performs soft decision decoding on the soft information to obtain the original data.

[0040] The storage medium 130 includes a plurality of flash memory chips 131, and each flash memory chip 131 is composed of a plurality of storage pages. Each storage page can be composed of single-layer cells (SLC), each single-layer cell (SLC) storing a single bit. Each storage page can also be composed of multi-layer cells (e.g., MLC, TLC, QLC), each multi-layer cell storing a plurality of bits.

[0041] In this embodiment, a computer system using a solid state disk is taken as an example of a storage system. However, the present application is not limited thereto, and the storage medium 130 can be any one of a solid state disk, a memory stick, a USB flash disk, and a flash memory card.

[0042] Figure 2 A schematic block diagram of a read operation control device in a storage system according to an embodiment of the present disclosure is shown. As described above, the memory controller 120 includes a write control device and a read operation control device. Embodiments of the present application are mainly about improvements to the read operation control device.

[0043] The read operation control device 121 includes a first reading module 122, a second reading module 123, a hard information cache unit 124, a soft information cache unit 125, and an LDPC decoder 126. The LDPC decoder 126 includes a first decoding unit 1261, a second decoding unit 1262, and a third decoding unit 1263.

[0044] The first reading module 122 applies a detection voltage to each storage unit of the storage medium 130, and then obtains the level voltage of each storage unit, determines whether the level voltage of each storage unit is higher or lower than a threshold voltage, according to the determination, determines the bit data stored in each storage unit, and stores the bit data as hard information in the hard information cache unit 124. For example, if the storage unit is an SLC that can only store one bit, only one detection voltage needs to be applied, and according to the comparison between the level voltage of the current SLC and a threshold voltage, it can be determined whether the stored bit is 0 or 1. If the storage unit is a TLC that stores three bits, multiple detection voltages are applied, and according to the respective comparison between the current storage unit and multiple threshold voltages, the stored bit data can be determined. For example, the storage unit A can store 3-bit data, i.e., the binary data that can be stored is 000, 001, 010, 011, 100, 101, 110, and 111. These 8 binary data correspond to 8 threshold voltages. When reading data, based on the comparison between the level voltage read based on the detection voltage applied to the storage unit A and the 8 threshold voltages, it can be determined which of the above 8 binary data is stored in the storage unit A.

[0045] The first decoding unit 1261 obtains the hard information from the hard information cache unit 124. The first decoding unit 1261 first verifies and corrects the hard information of each storage unit using a first hard decoding algorithm. If the data verification and correction of some storage units fail, the first reading module 122 then applies a new detection voltage to the failed storage unit, thereby obtaining new hard information, and then verifies and corrects the new hard information using the first hard decoding algorithm. This process is repeated. Generally, an end condition for ending the verification and correction is set in the system, for example, when the verification and correction of the first decoding unit 1261 for a storage unit exceeds a threshold number of times, the verification and correction process for the storage unit is stopped. For another example, when the first reading module 122 has used all the predetermined detection voltages for a storage unit, the verification and correction process for the storage unit is stopped. When the first decoding unit 1261 ends the execution, there are usually two results: the first result is that the hard information of all storage units is successfully decoded; the second result is that most of the storage units are successfully decoded. For the storage units that are not successfully decoded in the second result, the first decoding unit 1261 determines the detection voltage that has the best error correction effect among the multiple detection voltages applied thereon in advance, and takes it as the corresponding best detection voltage.

[0046] The second decoding unit 1262 obtains the hard information of the storage unit that fails to be decoded successfully by the first decoding unit 1261 at the optimal detection voltage and verifies and corrects it by using a second hard decoding algorithm. The second hard decoding algorithm has a higher decoding capability than the first hard decoding algorithm, but needs to consume more time. The second decoding unit 1262 can obtain the hard information of the storage unit that fails to be decoded successfully by the first decoding unit 1261 at the optimal detection voltage from the hard information cache unit 124, but if the hard information cache unit 124 has already covered the hard information, the first reading module 122 can apply the optimal detection voltage to the corresponding storage unit to obtain the corresponding hard information again.

[0047] The third decoding unit 1263 obtains the storage unit that fails to be decoded successfully by the second decoding unit 1262 and the optimal detection voltage thereof, applies multiple detection voltages to the corresponding storage unit based on the optimal detection voltage to obtain soft information, and stores the soft information in the soft information cache unit 125. For example, the multiple detection voltages can be obtained by adjusting the bias voltage symmetrically left and right based on the optimal detection voltage. The soft information includes more information than the hard information, and thus the soft decision decoding based on the soft information has a higher accuracy. The soft information can include not only the hard information but also associated data related to the hard information, but the specific associated data includes different definitions due to different manufacturers. The associated data related to the hard information is, for example, LLR data, which indicates the confidence of each data bit being 0 or 1.

[0048] In some embodiments, the first decoding unit 1261 verifies and corrects by using a bit-flipping algorithm. The bit-flipping algorithm substitutes a predetermined check matrix and a vector composed of hard information into multiple check equations. If all the check equations are satisfied, the decoding is successful. If there is a check equation that is not satisfied, the decoding fails, a code word in the vector is flipped, and a new vector obtained by the flipped code word is substituted into the multiple check equations. If all the check equations are satisfied, the decoding is successful. In this way, for each code word in the vector, the number of check equations that are not satisfied is counted, and the code word corresponding to the maximum number is selected to replace the code word. If there is still data that fails to be decoded successfully by the bit-flipping algorithm, the first reading module obtains new hard information, and the bit-flipping algorithm is used to verify and correct the new hard information, and so on.

[0049] In some embodiments, the second decoding unit 1262 adopts an LLR (log likelihood ratio) BP (belief propagation) algorithm or a Min-Sum algorithm for verification and error correction. The LLR BP algorithm decodes the hard decision information by means of log likelihood ratio information. The Min-Sum algorithm is based on the LLR BP algorithm, and simplifies the expression thereof, and the remaining steps are consistent with the LLR BP algorithm. Both the LLR BP algorithm and the Min-Sum algorithm are prior art, and will not be described in detail here.

[0050] In some embodiments, both the third decoding unit 1263 and the second decoding unit 1262 adopt an LLR (log likelihood ratio) BP (belief propagation) algorithm or a Min-Sum algorithm for verification and error correction. However, the second decoding unit 1262 adopts a fixed LLR, while the third decoding unit 1263 reduces the LLR according to a preset ratio, that is, gives a low-weight LLR value, so as to reduce the damage to the soft decision.

[0051] In some embodiments, when the third decoding unit 1263 fails to perform soft decoding by taking the optimal detection voltage as an input reference, the optimal voltage acquisition algorithm is executed by taking the optimal detection voltage as an input reference, so as to obtain the actual bottom voltage, and the soft information is obtained in the process of searching for the bottom voltage and is used for decoding.

[0052] It should be emphasized that the first decoding unit and the second decoding unit in the above embodiments belong to hard decision decoding, support die-parallel operation, the third decoding unit belongs to soft decision decoding, adopts software dynamic configuration of LLR, and only supports serial operation, and by means of decoding more data in the first decoding unit and the second decoding unit successfully, the decoding time can be reduced, and the decoding efficiency can be improved. In addition, the optimal detection voltage corresponding to the storage unit that fails to decode is screened out by means of the first decoding unit, and the optimal detection voltage is used for continuing decoding of the storage unit that fails to decode in the second decoding unit, which also helps to reduce the overall decoding time.

[0053] Figure 3 A flowchart of a read operation control method of a memory provided by an embodiment of the present disclosure is shown.

[0054] In step S301, a first detection voltage is applied to each storage unit of the memory.

[0055] In step S302, hard information corresponding to the first detection voltage is obtained by means of hard decision.

[0056] In step S303, the hard information is decoded by means of a first hard decoding algorithm.

[0057] In step S304, for the memory cells whose decoding fails in the output of the first hard-decoding algorithm, the first detection voltage corresponding to the best decoding effect is selected as the best detection voltage.

[0058] In step S305, for the memory cells whose decoding fails in the output of the first hard-decoding algorithm, the hard information under the best detection voltage is decoded by using the second hard-decoding algorithm.

[0059] According to the present embodiment, the hard-decision decoding stage is first used to decode the hard information under the first detection voltage by using the first hard-decoding algorithm, and this process is repeated until the end condition (for example, all the predetermined detection voltages have been used for each memory cell) is reached, at which time generally the hard information read out from most of the memory cells has been successfully decoded. Then for the memory cells whose decoding fails in the output of the first hard-decoding algorithm, the second hard-decoding algorithm is used for decoding. Since the second hard-decoding algorithm is more complex but has stronger decoding capability than the first hard-decoding algorithm, it is possible to successfully decode the memory cells whose decoding fails in the output of the first hard-decoding algorithm, and for these memory cells, the hard information used for decoding is the hard information corresponding to the best detection voltage, and the accuracy of the hard information is also relatively higher, thus also helping the decoding success of the second hard-decoding algorithm.

[0060] Further, for the memory cells whose decoding fails in the output of the second hard-decoding algorithm, the best voltage search algorithm is continued to be executed with the best detection voltage as the input reference to obtain the actual bottom voltage, and the soft information is obtained for decoding in the process of searching for the bottom voltage. It should be noted that the soft-decoding algorithm and the second hard-decoding algorithm can also be the same decoding algorithm, for example, the LLR BP algorithm or the Min-Sum algorithm can be used for both soft-decision decoding and hard-decision decoding.

[0061] The read operation control method provided by the present embodiment corresponds to the read operation control device described above, and thus the read operation control method will be described in a relatively brief manner.

[0062] The term "module" used herein can refer to, be part of, or include an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and / or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and / or other suitable components that provide the described functionality.

[0063] Those skilled in the art can understand that the various modules or units of the data processing system according to the present application can be implemented by hardware, firmware or software. The software includes, for example, coded programs formed by using various programming languages such as JAVA, C / C++ / C#, SQL, etc. Although the steps and the order of the steps of the embodiments of the present application are given in the method and the method legend, the executable instructions implementing the logic functions of the steps can be recombined to generate new steps. The order of the steps should not be limited to the order of the steps in the method and the method legend, and can be adjusted at any time according to the needs of the functions. For example, some of the steps can be executed in parallel or in reverse order.

[0064] The data processing system and method according to the present application can be deployed on a single or multiple servers. For example, different modules can be deployed on different servers respectively to form dedicated servers. Alternatively, the same functional units, modules or systems can be distributedly deployed on multiple servers to alleviate the load pressure. The servers include, but are not limited to, multiple PC machines, PC servers, blade machines, supercomputers, etc. in the same local area network and connected through the Internet.

[0065] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. The present application can be variously modified and changed for those skilled in the art. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A read control method of a memory, comprising: applying different first detection voltages to each memory cell of the memory; obtaining hard information corresponding to the first detection voltages by hard decision; decoding the hard information using a first hard decoding algorithm; repeating the steps of applying first detection voltages, obtaining hard information corresponding to the first detection voltages, and decoding the hard information until a termination condition is met; for a memory cell whose decoding fails in the output of the first hard decoding algorithm, selecting a first detection voltage corresponding to the best decoding effect from the plurality of first detection voltages as a best detection voltage; for the memory cell whose decoding fails in the output of the first hard decoding algorithm, decoding the hard information under the best detection voltage using a second hard decoding algorithm. 2.The read control method of claim 1, further comprising: adjusting a bias voltage symmetrically left and right based on the best detection voltage to obtain a plurality of second detection voltages applied to the memory cell whose decoding fails in the output of the second hard decoding algorithm to obtain soft information; decoding the soft information using a soft decoding algorithm.

3. The read control method of claim 2, further comprising: for the memory cell whose decoding fails in the output of the soft decoding algorithm, performing a best voltage search algorithm with the best detection voltage as an input reference to obtain an actual bottom voltage and simultaneously obtaining soft information for decoding in the process of searching for the bottom voltage.

4. The read control method of claim 1, wherein, the first hard decoding algorithm is a bit flipping algorithm, and the second hard decoding algorithm is a LLR belief propagation algorithm or a min-sum algorithm.

5. The read control method of claim 1, wherein, the corresponding steps of the read control method are performed in parallel. 6.A read operation control device of a memory, comprising: a first reading module configured to apply first detection voltages to each memory cell of the memory and obtain hard information corresponding to the first detection voltages by hard decision; a hard information cache unit configured to store the hard information; an LDPC decoder comprising a first decoding unit and a second decoding unit, the first decoding unit being configured to decode using a first hard decoding algorithm, and the second decoding unit being configured to decode using a second hard decoding algorithm; wherein the first decoding unit stops decoding when a termination condition is met and outputs a best detection voltage corresponding to a memory cell whose decoding fails in the best decoding effect, and the second decoding unit decodes the hard information under the best detection voltage using a second hard decoding algorithm for the memory cell whose decoding fails. 7.The read operation control device of claim 6, further comprising: a second reading module configured to adjust a bias voltage symmetrically left and right based on the best detection voltage to obtain a plurality of second detection voltages, and apply the plurality of second detection voltages to the memory cell whose decoding fails in the output of the second hard decoding algorithm to obtain soft information; a third decoding unit configured to decode the soft information using a soft decoding algorithm.

8. The read operation control device according to claim 7, wherein the first hard decoding algorithm is a bit flipping algorithm, and the first hard decoding algorithm is a LLR belief propagation algorithm or a min-sum algorithm. 9.A controller of a memory, comprising the read operation control device of any one of claims 6 to 8.

10. A storage system comprising a storage medium and the controller of claim 9.

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