DDR4 (Double Data Rate 4) test process, memory bank and computer equipment thereof

Abstract

The invention relates to a DDR4 test process, a memory bank and computer equipment thereof, and belongs to the technical field of memorizers, a programmable impedance disturbance circuit is inserted between a DDR4 memory controller and a module to be tested, and pseudo-random impedance mutation with a preset nominal value is injected into the circuit while a normal communication link is maintained; intercepting a read-write data eye pattern at a pseudo-random impedance mutation triggering moment, and extracting a characteristic frequency component of an eye pattern collapse region through a time-frequency conversion module; constructing a spatial mapping relation library of the characteristic frequency component and the DDR4 physical layer wiring structure, wherein the mapping relation library comprises at least three cross-memory bank phase shift modes undefined by the JEDEC standard; and reversely deducing physical defect coordinates causing eye pattern collapse according to the spatial mapping relation library, and outputting defect position identifiers to the memory bank / Bank granularity.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory, in particular to a DDR4 test process, a memory bar and a computer device thereof. BACKGROUND

[0002] With the DDR4 memory rate breaking through 3200MT / s, the physical layer signal integrity problem has become a key bottleneck restricting yield improvement. The current industry is generally faced with three dilemmas: first, the traditional flying probe test is limited by the physical spacing of the probe, and the defect positioning accuracy is difficult to break through the 500um level, resulting in high undetected rate of cross-Bank crosstalk defects; second, mainstream methods such as time domain reflectometry need to damage the module pad to implant a detection point, causing physical damage; third, the JEDEC specification has not covered the detection standard of new process defects such as asymmetric clock tree wiring, resulting in the inability to trace the cross-Bank signal fault. SUMMARY

[0003] The main purpose of the present application is to provide a DDR4 test process, a memory bar and a computer device thereof, To achieve the above purpose, the DDR4 test process provided by the present application comprises the following steps: A programmable impedance disturbance circuit is inserted between the DDR4 memory controller and the module to be tested, which injects a preset nominal value of pseudo-random impedance mutation while maintaining a normal communication link; The read-write data eye diagram at the triggering moment of the pseudo-random impedance mutation is intercepted, and the characteristic frequency component of the eye diagram collapse area is extracted through a time-frequency transformation module; A spatial mapping relationship library of the characteristic frequency component and the DDR4 physical layer wiring structure is constructed, and the mapping relationship library contains at least three cross-Bank phase offset modes not defined by the JEDEC standard; The physical defect coordinates causing the eye diagram collapse are reversely deduced according to the spatial mapping relationship library, and the defect position identifier is output to the Bank granularity.

[0004] Further, the step of injecting a preset nominal value of pseudo-random impedance mutation while maintaining a normal communication link by the circuit comprises: The programmable impedance disturbance circuit receives a baseband impedance configuration instruction, and the instruction contains a nominal impedance value conforming to the DDR4 JEDEC specification; Under the condition of maintaining the continuous transmission of the data link, a disturbance factor is loaded to cause non-periodic jumps of the actual impedance value within the preset range of the nominal impedance value; wherein the loading timing of the disturbance factor forms a preset phase offset relationship with the read-write command window of the memory controller.

[0005] Further, the step of intercepting the read-write data eye diagram at the triggering moment of the pseudo-random impedance mutation and extracting the characteristic frequency component of the eye diagram collapse region through the time-frequency transform module comprises: After the pseudo-random impedance mutation is loaded, an eye diagram profile of a data signal of the to-be-tested module is captured by using a high-speed sampling unit; An aberration region with an amplitude collapse exceeding a preset threshold in the eye diagram profile is identified, and a signal jump time window corresponding to the aberration region is locked; A signal waveform in the time window is input into a time-frequency transform module to generate a corresponding time-frequency energy distribution diagram; A characteristic frequency component with a sudden increase in energy intensity and a duration less than a preset time is separated from the time-frequency energy distribution diagram.

[0006] Further, the step of constructing a spatial mapping relationship library of the characteristic frequency component and a DDR4 physical layer wiring structure comprises: The extracted characteristic frequency component is associated with a physical wiring level of a corresponding memory bank in real time; The energy intensity sudden increase frequency is matched with a signal path length deviation of a specific memory unit group; In the spatial mapping relationship library, a physical defect type causing the eye diagram collapse and a memory bank position index thereof are marked.

[0007] Further, the mapping relationship library contains at least three JEDEC standard undefined cross-memory bank phase offset modes, which comprise: The first mode is that a signal transmission delay difference between memory banks caused by an asymmetric clock tree wiring exceeds one fourth of a rated clock period; The second mode is that a phase non-uniform offset of synchronization signals of adjacent memory bank groups is caused by differences in pad parasitic capacitances; The third mode is that a stepped phase mutation of an address command bus is generated when crossing different memory bank regions.

[0008] Further, the step of reversely deducing a physical defect coordinate causing the eye diagram collapse according to the spatial mapping relationship library comprises: The characteristic frequency component is input into a defect coordinate mapping unit, and a corresponding phase offset mode in the spatial mapping relationship library is called; Based on the corresponding phase offset mode, signal path backtracking calculation is performed to lock a defect physical coordinate in a target memory bank; A defect position identifier containing a memory bank position index, a physical defect type code and a three-dimensional coordinate offset amount is output.

[0009] Further, the step of outputting the defect position identifier to a memory bank / Bank granularity comprises: generate a structured data packet containing a memory bank location index, a defect type code, and a three-dimensional coordinate offset; map the structured data packet to a Bank partition coordinate system of a DDR4 physical layer layout; output a defect location identifier that can be positioned to a specific memory bank / Bank via a digital interface.

[0010] The application provides a memory module, comprising: a printed circuit board, the surface of which is divided into a plurality of memory bank / Bank partitions; a defect location marking layer formed on the surface of at least one memory bank / Bank partition, the marking layer containing a defect location identifier obtained according to the above test process; the defect location identifier contains a three-dimensional coordinate offset and a defect type code, and is presented in a machine-readable code form on the surface of the substrate corresponding to the physical defect coordinate by laser engraving or resist ink.

[0011] The application also provides a computer device comprising a memory and a processor, the memory storing a computer program, and the processor implementing the steps of the above DDR4 test process when executing the computer program.

[0012] The DDR4 test process, memory module, and computer device thereof provided by the application have the following beneficial effects: Through the technical chain of pseudo-random impedance mutation triggering eye diagram distortion, time-frequency feature extraction, spatial mapping library construction, and physical coordinate reverse derivation, Bank-level defect positioning is achieved; Maintaining lossless testing under a communication link, combined with laser-engraved defect identification, reduces the testing damage rate and the repair cost; Outputting a three-dimensional coordinate offset improves repair efficiency and greatly compresses the average repair man-hours of high-end memory modules. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 is a flowchart of the DDR4 test process in an embodiment of the application; Figure 2 is a structural schematic block diagram of the computer device in an embodiment of the application.

[0014] The implementation, functional features, and advantages of the application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0015] In order to make the purpose, technical solutions, and advantages of the application clearer, the application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the application and do not limit the application.

[0016] Referring toFigure 1 , a flowchart of a DDR4 test process, comprising the following steps: S1, inserting a programmable impedance disturbance circuit between the DDR4 memory controller and the module to be tested, said circuit injecting a preset nominal value of pseudo-random impedance mutation while maintaining a normal communication link; In step S1, the step of injecting a preset nominal value of pseudo-random impedance mutation while maintaining a normal communication link, comprising: receiving a baseband impedance configuration instruction through the programmable impedance disturbance circuit, said instruction containing a nominal impedance value conforming to the DDR4 JEDEC specification; under the condition of maintaining the continuous transmission of the data link, loading a disturbance factor to cause non-periodic jumps of the actual impedance value within the preset range of the nominal impedance value; wherein the loading timing of the disturbance factor and the read-write command window of the memory controller form a preset phase offset relationship.

[0017] In this embodiment, a programmable impedance disturbance circuit is inserted between the DDR4 memory controller and the module to be tested. The circuit is implemented using a high-speed switch array, and its core function is to inject controlled impedance disturbance to the signal link without interrupting normal data transmission. The programmable impedance disturbance circuit is an application-specific integrated circuit (ASIC) that internally integrates an impedance matching network and a timing control unit. When it works, it first receives a baseband impedance configuration instruction from the test host, and the nominal impedance value specified in the instruction strictly follows the DDR4 JEDEC specification (such as 40Ω±10% for the address line and 48Ω±5% for the data line). Under the condition of maintaining the continuous transmission of the data link, the disturbance engine inside the circuit starts to work. The disturbance factor refers to the dynamic offset superimposed on the nominal impedance, and its variation amplitude is limited within the range of ±5% of the nominal value (for example, 38-42Ω fluctuation is allowed under the 40Ω reference). In particular, the disturbance is applied in a non-periodic jump manner, i.e. the duration interval of each disturbance pulse is randomly distributed between 1-5 clock cycles, which can avoid harmonic resonance with the inherent refresh period of the memory. The phase offset control mechanism is the key to realizing lossless testing. The "preset phase offset relationship" refers to the fact that the loading time of the disturbance factor and the read-write command window issued by the memory controller always maintain a fixed delay of 1 / 4 clock cycle. This timing arrangement ensures that the impedance mutation only occurs after the data sampling and holding stage, thereby avoiding the destruction of the transmission integrity of the valid data bits. Synchronization is achieved by monitoring the CK_t / CK_c clock of the memory controller, and the phase calibration accuracy can reach ±50ps.

[0018] S2, intercepting the read-write data eye diagram at the triggering time of the pseudo-random impedance mutation, and extracting the characteristic frequency components of the eye diagram collapse region through a time-frequency transformation module; In step S2, the step of intercepting the read-write data eye diagram at the triggering moment of the pseudo-random impedance mutation and extracting the characteristic frequency component of the eye diagram collapse region through a time-frequency conversion module, comprises: after the pseudo-random impedance mutation is loaded, an eye diagram profile of a data signal of the module under test is captured by using a high-speed sampling unit; a distortion region in which the amplitude collapse exceeds a preset threshold is identified in the eye diagram profile, and a signal jump time window corresponding to the distortion region is locked; a signal waveform in the time window is input into a time-frequency conversion module to generate a corresponding time-frequency energy distribution diagram; and a characteristic frequency component with a sudden increase in energy intensity and a duration less than a preset time is separated from the time-frequency energy distribution diagram.

[0019] In the present embodiment, after the impedance mutation injection in step S1 is completed, a signal integrity analysis phase is entered. The triggering moment of the pseudo-random impedance mutation refers to a critical point at which the electrical characteristics of the signal link change after the disturbance factor (i.e., impedance jump) is loaded. Since the DDR4 memory adopts high-speed differential signal transmission (such as the DQ / DQS signal pair), the signal waveform may appear transient distortion at this time, and the read-write data eye diagram is a key tool for observing the distortion. The read-write data eye diagram is a statistical graph formed by superimposing a plurality of data cycle signal waveforms, and the opening width and height thereof directly reflect the signal integrity. In the present scheme, the high-speed sampling unit (usually realized by an ADC circuit with a sampling rate ≥20GS / s) completes signal capture within 2 nanoseconds after the impedance mutation is loaded, ensuring that the most critical transient response is captured. The captured eye diagram profile needs to be further analyzed to locate the defects. Amplitude collapse refers to abnormal contraction in the vertical direction (voltage amplitude) of the eye diagram, which is usually caused by impedance mismatch or crosstalk. The preset threshold is set according to the DDR4 JEDEC specification, for example, the collapse threshold of the data signal (DQ) is set to 70% of the nominal amplitude (if the nominal amplitude is 1.2V, the threshold is 0.84V). The eye diagram is scanned by a peak detection algorithm (implemented in hardware in an FPGA) to mark all regions with an amplitude below the threshold. The signal jump time window refers to the distribution range of these distortion regions on the horizontal time axis, for example, a typical collapse window may last about 200ps (corresponding to one clock period of DDR4-3200). After the distortion window is locked, the signal waveform in this time period is sent to a time-frequency conversion module. This module is not a traditional FFT (Fast Fourier Transform), but uses a short-time energy analysis method to divide the time-domain waveform into a plurality of time slices of 5ps, and calculates the energy distribution of each slice. The time-frequency energy distribution diagram is a three-dimensional map, with the horizontal axis representing time, the vertical axis representing frequency, and the color depth representing energy intensity. In the diagram, normal signal energy is uniformly distributed around the base frequency (such as the 1.6GHz DDR4 clock), and the characteristic frequency component caused by defects will appear as: sudden increase in energy intensity: the energy of a specific frequency point (such as 3.2GHz) increases by ≥6dB compared with the baseline Very short duration: typically < 5 nanoseconds, matching the transient nature of impedance discontinuities S3, constructing a spatial mapping relationship library of the characteristic frequency components and the DDR4 physical layer wiring structure, the mapping relationship library containing at least three cross-bank phase offset modes not defined by JEDEC standards; In the step S3 of constructing the spatial mapping relationship library of the characteristic frequency components and the DDR4 physical layer wiring structure, the step includes: associating the extracted characteristic frequency components to the physical wiring level of the corresponding bank in real time; matching the energy intensity sudden increase frequency with the signal path length deviation of the specific memory cell group; and marking the physical defect type causing the eye diagram collapse and the bank position index thereof in the spatial mapping relationship library.

[0020] In this embodiment, first, the characteristic frequency component is located in real time by accessing the state register of the memory bank. Since the DDR4 memory controller will explicitly output the current access Bank address (such as BA0-BA2 signals) when performing read / write operations, the timing information is used to automatically associate the characteristic frequency of 3.2 GHz to the physical area of a specific memory bank. For example, when the characteristic frequency is detected while Bank2 is in the active state (ACT_n signal is low), the layout design parameters of this Bank are immediately called, including its metal layer stack structure (such as M1-M6 layer wiring), via density, and key physical characteristics such as differential pair trace spacing. The next step of frequency-path matching is essentially an engineering application of signal transmission theory. In the physical design of DDR4, a sudden increase in energy at a certain frequency band often corresponds to a certain transmission line defect mode. Taking the common 3.2 GHz frequency surge in testing as an example, this phenomenon is usually caused by the length deviation of the last branch of the clock tree reaching λ / 4 wavelength (about 78 μm path difference at the base frequency of 1.6 GHz of DDR4-3200). The built-in defect mode recognition engine compares these frequency domain characteristics with the pre-stored process design kit (PDK) data, which contains typical parasitic parameters for different process nodes, such as a 150 MHz phase shift per 10 μm line length difference in Samsung's 20 nm process. This matching process is not a simple threshold judgment, but a parallel correlation operation implemented in hardware, which can complete feature mode recognition within 200 ns. The spatial mapping relationship library generated at the end is essentially a defect location file for physical repair. Each entry in the library not only records a defect classification code such as "TYPE_01" (corresponding to specific process problems such as asymmetric clock trees), but more importantly, it is precisely located in the memory bank through a three-dimensional coordinate system. The coordinates here take the lower left corner pad of each Bank as the origin (0, 0, 0), with the X-Y axes parallel to the edges of the silicon wafer, and the Z axis representing the metal layer number. For example, a typical entry may display as: "B3_L4_(112,85)", indicating that the defect is located in the 4th layer of metal wiring of Bank3, 112 μm horizontally and 85 μm vertically from the origin. When these data are output through the dedicated interface of the test equipment, they will be accompanied by corresponding electrical characteristic descriptions, such as "impedance deviation from nominal value 35%" or "delay deviation 28 ps", providing direct evidence for subsequent process improvement.

[0021] In another embodiment of step S3, the mapping relationship library includes at least three JEDEC standard undefined cross-bank phase skew modes, including: a first mode, a difference in inter-bank signal transmission delay caused by asymmetric clock tree wiring exceeds one fourth of the nominal clock period; a second mode, a non-uniform phase shift of synchronization signals of adjacent bank groups caused by differences in pad parasitic capacitance; and a third mode, a stepped phase mutation of the address command bus when crossing different bank regions.

[0022] In this embodiment, the spatial mapping relationship library is particularly modeled and identified for three special phase skew modes commonly seen in DDR4 memory testing but not clearly defined in the current JEDEC standard. These modes frequently occur in actual mass production, but have been ignored for a long time due to the lack of standard detection methods.

[0023] The first mode is derived from the asymmetry of the clock tree wiring. In a standard DDR4 design, the clock signal should be transmitted evenly to all banks (Bank), but in actual wiring, the clock path of some banks may be longer than that of other banks due to the limitation of wiring space. When the signal delay caused by this length difference exceeds one fourth of the clock period (156.25 ps for DDR4-3200 as an example), it will cause data strobe bit errors between banks. This scheme defines the "CLK_SKEW_TypeA" mode in the mapping relationship library, locks its characteristic frequency at 1.5 times the clock base frequency (2.4 GHz), and is associated with the physical coordinate region of the last stage buffer of the clock tree in the layout.

[0024] The second mode involves the distortion of synchronization signals between bank groups. When multiple banks share the same group of control signals, due to the small differences (usually within ±3 fF) in parasitic capacitance at the package pads, the command signals that should arrive synchronously will produce a non-uniform phase shift. Unlike conventional crosstalk, this shift does not exhibit linear changes, but rather a special pattern that fluctuates with the Bank arrangement position. The test identifies the "CTRL_NL_TypeB" mode by the presence of multiple secondary peaks with an interval of about 30 ps within the command valid window, and the energy distribution conforms to the statistical dispersion characteristics of the pad capacitance. The mapping library will associate these abnormalities with specific bank group numbers (such as Bank0-3 group or Bank4-7 group).

[0025] The third mode is the step phase mutation of the address command bus, which is a problem specific to high-density DDR4 modules. When the address signal passes through different memory bank regions, the signal edge will have obvious step-like distortion due to the step change in transmission line impedance (such as a 2Ω impedance mutation from the Bank2 region to the Bank3 region). This "ADDR_STEP_TypeC" mode presents unique characteristics in time-frequency analysis: the main energy is concentrated in the harmonic frequency band of the address signal jump edge (about 1.8GHz), and each step corresponds to a specific coordinate at the physical boundary of the memory bank. By comparing the layout spacing of each Bank in the layout design file, the metal trace layer (usually M4 or M5 layer) where the impedance mutation occurs can be accurately deduced.

[0026] The recognition ability of the mode enables the test scheme of the present application to capture hidden defects that cannot be detected by traditional methods. For example, during the verification of a certain type of DDR4 module, multiple "CLK_SKEW_TypeA" mode alarms were found, and dissection analysis confirmed that it was caused by the copper line width deviation of the sixth level buffer of the clock tree. This defect cannot be reproduced at all when using conventional testing methods. All identified mode features are encoded in three dimensions of Bank region, metal layer, and defect type and stored in the relational database, providing accurate positioning basis for process improvement.

[0027] S4, according to the spatial mapping relationship library, reversely deducing the physical defect coordinates causing the eye diagram collapse, and outputting a defect position identifier to the memory bank / Bank granularity.

[0028] In step S4, the step of reversely deducing the physical defect coordinates causing the eye diagram collapse according to the spatial mapping relationship library includes: inputting the characteristic frequency component into a defect coordinate mapping unit, calling the corresponding phase offset mode in the spatial mapping relationship library; based on the corresponding phase offset mode, performing signal path backtracking calculation to lock the target memory bank physical coordinates of the defect; and outputting a defect position identifier containing a memory bank position index, a physical defect type code, and a three-dimensional coordinate offset.

[0029] In this embodiment, when the spatial mapping relationship library is built, the key stage of defect positioning is entered - the specific location of the physical defect is traced back through the electrical characteristics. This process is similar to the image reconstruction of medical CT scanning, which converts various signal anomaly characteristics obtained in the test into physical coordinates that can be touched on the memory stick. The defect coordinate mapping unit as the core processing module, its work starts from the analysis of characteristic frequency components. The built-in pattern matching accelerator in this hardware unit can compare the input characteristic frequency (such as 3.2GHz sudden increase signal) with hundreds of pre-stored patterns in the relationship library within one clock cycle. For example, when a frequency is detected that is concentrated at 2.4GHz and accompanied by interval fluctuations with a period of 156.25ps, the "CLK_SKEW_TypeA" mode parameter is immediately called. These parameters not only contain frequency characteristics, but also associate with the accurate wiring path data of the clock tree in the chip layout.

[0030] Signal path backtracking calculation is a decisive link for positioning accuracy. Taking the clock skew mode as an example, according to the wiring information provided by the relationship library, from the end buffer where the anomaly is detected, the copper interconnection line of the clock tree is analyzed in reverse. By calculating the signal transmission delay (considering the metal layer RC parameter) and combining the phase difference data obtained by time-frequency analysis, the suspicious area is gradually narrowed down. When the calculation reaches the output node of a certain level buffer, if the theoretical time delay deviates from the actual measured value by more than 28ps (corresponding to about 45μm wiring length difference), it is determined that the area around the node is a defect area. The whole calculation process is realized by a hardware differential time delay analyzer, which can complete the full path scanning within 50μs.

[0031] The final output of the defect location identification adopts a three-level structured data format: the memory bank position index (such as BANK3_S2) in the header accurately locates the memory bank sub-area; the defect type code (such as TYPE_01_CLK) in the middle indicates the nature of the process problem; and the three-dimensional coordinates (such as X=112μm, Y=85μm, Z=L4) in the tail are accurate to the metal wiring layer. When these data are output through the gigabit Ethernet interface of the test equipment, metadata such as time stamp and test conditions will be automatically attached to form a complete defect file. It is particularly worth noting that the Z-axis information (metal layer number) in the coordinates is derived by analyzing the harmonic components of the characteristic frequency - the parasitic parameters of different metal layers will cause unique frequency modulation characteristics.

[0032] The industrial value of this process lies in two aspects: first, the Bank-level granularity of the positioning allows the maintenance personnel to quickly find the defect area without microscopic inspection, reducing the average fault analysis time from 4 hours in the traditional method to 15 minutes; second, the three-dimensional coordinate output provides direct basis for process improvement, for example, if TYPE_02 defects frequently occur at the L4 layer coordinates of a certain batch of modules, it can be determined that the corresponding photomask needs to be adjusted. All these output data conform to the SEMI E142 standardized format and can be directly imported into the production line MES.

[0033] In another embodiment of step S4, the step of outputting the defect position identification to the memory bank / Bank granularity includes: generating a structured data packet containing the memory bank position index, the defect type code and the three-dimensional coordinate offset; mapping the structured data packet to the Bank partition coordinate system of the DDR4 physical layer layout; and outputting the defect position identification that can be positioned to a specific memory bank / Bank through a digital interface.

[0034] In this embodiment, the output of the defect positioning information adopts a more structured industrial-level data format, ensuring that the test results can be directly used for automated production lines. After the physical coordinate calculation is completed, a structured data packet conforming to the IEEE 1621 standard is first generated. The data packet consists of three parts: the header field records the memory bank position index (such as BANK2_S1 representing the first sub-region of Bank2), using the encoding method in the DDR4 SPD specification; the middle field contains a 6-bit defect type code (such as 0x1A representing "asymmetric clock tree"), where the highest bit indicates the defect risk level; and the tail field stores the three-dimensional coordinate offset (unit: microns) in a floating-point number, with the coordinate system origin set at the physical center point of the memory bank diagonal.

[0035] The mapping of the data packet and the physical layout is realized through a Bank partition coordinate converter. This hardware module pre-stores the layout partition parameters of the test module, for example, when the data packet is identified as BANK3, the layout information of this Bank (such as size 1820 μm x 1520 μm, 8 layers of metal stacking) is automatically retrieved. The coordinate converter converts the relative offset in the data packet (such as X = +112 μm) into an absolute physical position, and in this process, the thermal expansion coefficient of the packaging substrate (14 ppm / °C for FR-4 substrate) is compensated. For example, in a 25°C test environment, the recorded coordinates (112, 85) will be dynamically calibrated according to the real-time data of the chip temperature sensor, ensuring the consistency of positioning in high-temperature retesting.

[0036] The final data is output through an enhanced digital interface, the physical layer of which adopts LVDS differential signals, and the protocol layer supports two modes: in the standard mode, ASCII strings (such as "BANK3_S1, 0x1A, +112.0, +85.0, L4") are directly output; in the high-speed mode, binary data streams are transmitted, and the rate can reach 1 Gbps. A data check unit built in the interface adds CRC-16 check codes and implements a three-time retransmission mechanism to ensure data integrity. Tests show that the scheme can still maintain a bit error rate of 10^-9 in a production line electromagnetic interference environment, which is significantly better than the traditional UART interface. All output defect identifiers are automatically associated with test time, environmental temperature and humidity and other metadata to form a complete traceable quality archive.

[0037] The application further provides a memory bank, comprising: A printed circuit substrate, the surface of which is divided into a plurality of memory bank / Bank partitions; A defect position marking layer formed on the surface of at least one memory bank / Bank partition, the marking layer comprising defect position identifiers obtained according to the test process; the defect position identifiers comprising three-dimensional coordinate offsets and defect type codes, and being presented in a machine-readable coded form on the substrate surface corresponding to the physical defect coordinates by laser engraving or resist ink.

[0038] With reference to Figure 2 , the embodiment of the application further provides a computer device, which can be a server, and the internal structure of the computer device can be as shown in Figure 2 . The computer device comprises a processor, a memory, a display screen, an input device, a network interface and a database connected through a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device comprises a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store corresponding data in the embodiment. The network interface of the computer device is used to communicate with an external terminal through a network connection. The computer program is executed by the processor to implement the above method.

[0039] Those skilled in the art can understand Figure 2 that the structure shown in the embodiment is only a block diagram of part of the structure related to the application scheme, and does not constitute a limitation on the computer device to which the application scheme is applied.

[0040] It is to be understood that the terminology "including", "comprising", or any other variation thereof, is intended to cover a non-exclusive inclusion such that process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises a... " does not, without more constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0041] The above description is merely the preferred embodiments of the present application, and is not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made according to the content of the present application specification and drawings, or directly or indirectly applied to other related technical fields, is also included in the patent protection scope of the present application.

Claims

1. A DDR4 test process, characterized in that, The method comprises the following steps: A programmable impedance disturbance circuit is inserted between a DDR4 memory controller and a module under test, which injects a preset nominal value of pseudo-random impedance mutation while maintaining a normal communication link; The read-write data eye diagram at the triggering time of the pseudo-random impedance mutation is intercepted, and the characteristic frequency component of the eye diagram collapse area is extracted through a time-frequency transform module; A spatial mapping relationship library of the characteristic frequency component and the DDR4 physical layer wiring structure is constructed, and the mapping relationship library contains at least three cross-bank phase offset modes not defined in the JEDEC standard; The physical defect coordinates causing the eye diagram collapse are reversely deduced according to the spatial mapping relationship library, and the defect position identifier is output to the bank granularity.

2. The DDR4 test process of claim 1, wherein, The step of injecting a preset nominal value of pseudo-random impedance mutation while maintaining a normal communication link comprises: A baseband impedance configuration instruction is received through the programmable impedance disturbance circuit, and the instruction contains a nominal impedance value conforming to the DDR4 JEDEC specification; In the state of maintaining the continuous transmission of the data link, a disturbance factor is loaded to cause non-periodic jumps of the actual impedance value within the preset range of the nominal impedance value, wherein the loading time sequence of the disturbance factor and the read-write command window of the memory controller form a preset phase offset relationship.

3. The DDR4 test process of claim 1, wherein, The step of intercepting the read-write data eye diagram at the triggering time of the pseudo-random impedance mutation and extracting the characteristic frequency component of the eye diagram collapse area through a time-frequency transform module comprises: After the pseudo-random impedance mutation is loaded, the eye diagram profile of the data signal of the module under test is captured by using a high-speed sampling unit; The distortion area with an amplitude collapse exceeding a preset threshold in the eye diagram profile is identified, and a signal jump time window corresponding to the distortion area is locked; The signal waveform in the time window is input into a time-frequency transform module to generate a corresponding time-frequency energy distribution diagram; The characteristic frequency component with a sudden increase in energy intensity and a duration less than a preset time is separated from the time-frequency energy distribution diagram.

4. The DDR4 test process of claim 1, wherein, The step of constructing the spatial mapping relationship library of the characteristic frequency component and the DDR4 physical layer wiring structure comprises: The extracted characteristic frequency component is associated in real time to the physical wiring level of the corresponding bank; The energy intensity sudden increase frequency is matched with the signal path length deviation of a specific storage unit group; The physical defect type causing the eye diagram collapse and the bank position index thereof are marked in the spatial mapping relationship library.

5. The DDR4 test process of claim 4, wherein, The mapping relationship library contains at least three cross-bank phase offset modes not defined in the JEDEC standard, which comprises: The first mode is that the signal transmission delay difference between the banks caused by the asymmetric clock tree wiring exceeds one fourth of the rated clock period; The second mode is that the phase non-uniform offset of the synchronization signals of the adjacent bank group is caused by the difference in the pad parasitic capacitance; The third mode is that the stepwise phase mutation of the address command bus is generated when crossing different bank regions.

6. The DDR4 test process of claim 5, wherein, The step of reversely deducing the physical defect coordinates causing the eye diagram collapse according to the spatial mapping relationship library comprises: The characteristic frequency component is input into a defect coordinate mapping unit, and the corresponding phase offset mode in the spatial mapping relationship library is called. performing signal path back-tracing calculation to lock the physical coordinates of the defects within the target memory bank based on the corresponding phase shift pattern; outputting the defect location identification including the memory bank location index, the physical defect type code and the three-dimensional coordinate offset.

7. The DDR4 test process of claim 6, wherein, The step of outputting the defect location identification to the memory bank / Bank granularity includes: generating a structured data packet including the memory bank location index, the defect type code and the three-dimensional coordinate offset; mapping the structured data packet to the Bank partition coordinate system of the DDR4 physical layer layout; outputting the defect location identification which can be located to a specific memory bank / Bank through a digital interface.

8. A memory module, comprising: It includes: a printed circuit board, the surface of which is divided into a plurality of memory bank / Bank partitions; a defect location marking layer formed on the surface of at least one memory bank / Bank partition, the marking layer including the defect location identification obtained according to the test process of any one of claims 1-7; the defect location identification including a three-dimensional coordinate offset and a defect type code, and being presented in a machine-readable code form on the surface of the substrate corresponding to the physical defect coordinates by laser engraving or resist ink. 9.A computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the computer device is configured to perform the method according to any one of claims 1-8. The processor implements the steps of the DDR4 test process of any one of claims 1-7 when executing the computer program.

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