Substrate wiring method and substrate packaging structure

Abstract

The application provides a substrate wiring method and a substrate packaging structure. The method comprises the following steps: providing a first carrier with a first prepreg; the first prepreg comprises a first part and a second part, and the second part is higher than the first part; forming a first wiring layer on the first part and a second wiring layer on the second part; forming a first dielectric layer covering the first wiring layer and the second wiring layer; covering the second part with a second prepreg, and the surface of the second prepreg is higher than the surface of the first dielectric layer; forming a third wiring layer on the first part and electrically connected with the first wiring layer; forming a second dielectric layer covering the third wiring layer and the second prepreg; and separating the first prepreg and the second prepreg from the interface of the dielectric layer as a separation surface to obtain a first module and a second module. The packaging efficiency is high, and the product flexibility is good.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a substrate wiring method and a substrate packaging structure. Background Technology

[0002] With the rapid development of the semiconductor industry, wafer-level packaging is divided into fan-out and fan-in. Fan-out packaging involves rewiring individual dies on a wafer, then covering the wiring layers with a dielectric layer to achieve the desired process. System-in-package (SiP) and chiplet technologies typically use substrates, PCBs, or leadframes as the substrate wiring layer structure for chip packaging. Other packaging methods use ceramic, silicon, glass, metal, or other materials as carriers, forming multiple wiring layers on the carrier surface, covering them with a dielectric layer, and then removing the carrier to form the substrate wiring layer structure.

[0003] Multilayer wiring layers contain various types of circuit layers, including diode circuit layers, timing circuit layers, signal layers, antenna pattern layers, and inductor circuit layers. When an antenna pattern layer is integrated into a multilayer wiring layer, signal interference can occur between the multiple circuit layers and the dielectric layer, severely affecting its performance or impacting the heat dissipation of the inductor circuit layer. Furthermore, existing substrate wiring layer structures cannot flexibly change the direction of any wiring layer. Changing the routing direction often requires adding extra wiring layers, which also significantly impacts circuit transmission and heat dissipation performance. Summary of the Invention

[0004] The purpose of this invention is to provide a substrate wiring method and a substrate packaging structure that can achieve flexible stacking and routing of multiple circuit layers, which is beneficial to improving the transmission performance and heat dissipation performance of the circuit.

[0005] In a first aspect, the present invention provides a substrate wiring method, comprising:

[0006] A first carrier having a first prepreg is provided; wherein the first prepreg includes a first portion and a second portion, the second portion being higher than the first portion;

[0007] A first wiring layer is formed in the first portion, and a second wiring layer is formed in the second portion;

[0008] A first dielectric layer is formed to cover the first wiring layer and the second wiring layer; wherein the first dielectric layer has a first opening; the first opening is disposed along the outer periphery of the second wiring layer and exposes the first prepreg.

[0009] The second portion is covered with a second prepreg and the first opening is filled; the surface of the second prepreg is higher than the surface of the first dielectric layer.

[0010] A third wiring layer electrically connected to the first wiring layer is formed on the first portion;

[0011] A second dielectric layer is formed that covers the third wiring layer and the second prepreg.

[0012] A first conductive pillar penetrating the second dielectric layer is formed in the corresponding region of the second prepreg;

[0013] Using the interfaces between the first and second prepregs and the dielectric layer as separation surfaces, debonding is performed to separate and obtain a first module and a second module; wherein, the second module includes the first prepreg and the second prepreg; the first module has a groove corresponding to the second prepreg.

[0014] In an optional implementation, prior to the debonding step, the following is also included:

[0015] A fourth wiring layer and a third dielectric layer covering the fourth wiring layer are formed; the fourth wiring layer is electrically connected to the third wiring layer and the first conductive pillar, respectively;

[0016] A first metal layer is formed that is electrically connected to the fourth wiring layer.

[0017] In an optional implementation, after the step of forming the first metal layer electrically connected to the fourth wiring layer, the method further includes:

[0018] The first chip is mounted, and the first chip is electrically connected to the first metal layer.

[0019] In an optional implementation, after the step of manufacturing the second module, the method further includes:

[0020] Remove the first prepreg and the second prepreg from the second module;

[0021] Remove the first carrier to expose the second metal pillar connected to the second wiring layer;

[0022] A first solder ball is formed on the second metal pillar to obtain the first device.

[0023] In an optional implementation, after the step of fabricating the first device, the method further includes:

[0024] The first device is mounted into the groove of the first module, and the first solder ball and the first conductive post are electrically connected.

[0025] In an optional implementation, after the step of mounting the first device, the method further includes:

[0026] A protective film is formed, which covers the first module and the first device.

[0027] In an optional implementation, after the step of mounting the first device, the method further includes:

[0028] A fifth dielectric layer is formed covering the fifth wiring layer, and the fifth wiring layer is electrically connected to the first wiring layer; or, the fifth wiring layer is electrically connected to both the first wiring layer and the second wiring layer.

[0029] A second metal layer is formed on the fifth dielectric layer.

[0030] In an optional embodiment, after the step of forming the second metal layer on the fifth dielectric layer, the method further includes:

[0031] A second chip is mounted, and the second chip is electrically connected to the second metal layer.

[0032] In an optional embodiment, after the step of removing the first prepreg and the second prepreg from the second module, the method further includes:

[0033] A fourth dielectric layer is formed on the first carrier;

[0034] Remove the first vehicle;

[0035] After the first solder ball is formed, the fourth dielectric layer is cut to obtain the first device.

[0036] In an optional implementation, after the step of forming the fourth dielectric layer on the first carrier, the method further includes:

[0037] A second conductive pillar is formed that penetrates the fourth dielectric layer, and the second conductive pillar is electrically connected to the second wiring layer;

[0038] A third metal layer connected to the second conductive pillar is formed on the surface of the fourth dielectric layer;

[0039] A third chip is mounted on the third metal layer.

[0040] In an optional implementation, the step of forming a second wiring layer in the second portion includes:

[0041] A first through hole is opened in the second section, and the first through hole penetrates the first vehicle;

[0042] A second metal pillar is formed by filling the first through-hole with conductive material;

[0043] A second wiring layer is formed that is electrically connected to the second metal pillar;

[0044] A fourth metal layer is formed on the side of the first carrier away from the second portion, and the fourth metal layer is electrically connected to the second metal pillar.

[0045] In an optional embodiment, after the step of removing the first prepreg and the second prepreg from the second module, the method further includes:

[0046] A fourth chip is mounted on the side of the first carrier closest to the second wiring layer;

[0047] A sixth dielectric layer covering the sixth wiring layer is formed on the side of the first carrier away from the second wiring layer; the sixth wiring layer is electrically connected to the fourth metal layer and the fourth chip respectively;

[0048] A seventh dielectric layer is formed on the sixth dielectric layer;

[0049] A fifth metal layer is formed in the seventh dielectric layer.

[0050] In a second aspect, the present invention provides a substrate packaging structure, the substrate packaging structure comprising: a first packaging structure or a second packaging structure;

[0051] The first packaging structure includes a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked sequentially; the first dielectric layer has a first wiring layer, the second dielectric layer has a third wiring layer, and the third dielectric layer has a fourth wiring layer; a first metal layer is disposed on the surface of the third dielectric layer and is electrically connected to the fourth wiring layer; the fourth wiring layer and the third wiring layer are electrically connected, and the third wiring layer and the first wiring layer are electrically connected.

[0052] The first dielectric layer has a groove on the side away from the first metal layer, and the first dielectric layer has a protruding first metal pillar, which is electrically connected to the first wiring layer.

[0053] The fourth wiring layer is connected to a first conductive post, and the end of the first conductive post away from the fourth wiring layer protrudes from the bottom of the groove.

[0054] The second packaging structure includes a second metal pillar, a second wiring layer, and a first dielectric layer; the first dielectric layer covers the second wiring layer, and the second metal pillar is electrically connected to the second wiring layer; the second metal pillar protrudes from the first dielectric layer.

[0055] In an optional embodiment, the system includes a first packaging structure and a second packaging structure, wherein the second packaging structure is disposed in the groove, and the second metal post and the first conductive post are electrically connected.

[0056] In an optional implementation, a first chip is also included, which is electrically connected to the first metal layer.

[0057] In an optional implementation, a second chip is also included, which is electrically connected to the first wiring layer.

[0058] In an optional embodiment, the second packaging structure further includes a third chip, which is electrically connected to the second wiring layer.

[0059] In an optional embodiment, the package further includes a substrate, to which the first package structure is electrically connected; the groove opening faces the substrate.

[0060] In an alternative embodiment, the first chip is electrically connected to the side of the first package structure away from the substrate.

[0061] In an optional embodiment, the second packaging structure further includes a first carrier, on the side of the first carrier away from the second wiring layer, a fourth metal layer is provided, the fourth metal layer being electrically connected to the second wiring layer.

[0062] In an optional embodiment, a fourth chip is provided on the side of the first carrier closer to the second wiring layer, and a sixth wiring layer is provided on the side of the first carrier away from the second wiring layer, wherein the sixth wiring layer and the fourth chip are electrically connected.

[0063] The substrate wiring method and substrate packaging structure provided in this invention have the following advantages:

[0064] In the encapsulation process, a prepreg is used as a bonding release layer. After multi-layer wiring is completed, the packaged product is debonded at the prepreg to form a first module and a second module. This configuration allows for flexible wiring and combination of the first and second modules, facilitating flexible design of the wiring layer routing. It enables modular design, making assembly, disassembly, maintenance, and replacement more convenient, and also improves packaging efficiency. Furthermore, the debonding facilitates improved heat dissipation performance. Attached Figure Description

[0065] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0066] Figure 1 One of the process diagrams of the substrate wiring method provided in the embodiment of the present invention;

[0067] Figure 2 This is a second schematic diagram of the substrate wiring method provided in an embodiment of the present invention;

[0068] Figure 3 The third schematic diagram of the substrate wiring method provided in the embodiment of the present invention;

[0069] Figure 4 Fourth schematic diagram of the substrate wiring method provided in the embodiment of the present invention;

[0070] Figure 5 This is a schematic diagram of the process of mounting a first chip on a first module in the substrate wiring method provided in an embodiment of the present invention;

[0071] Figure 6 This is a schematic diagram of the process of fabricating the second module into the first device in the substrate wiring method provided in the embodiment of the present invention;

[0072] Figure 7 This is one of the process diagrams for mounting a first device onto a first module in the substrate wiring method provided in an embodiment of the present invention;

[0073] Figure 8 This is a second schematic diagram of the process of mounting the first device onto the first module in the substrate wiring method provided in the embodiments of the present invention;

[0074] Figure 9 This is the third schematic diagram of the process of mounting the first device onto the first module in the substrate wiring method provided in the embodiment of the present invention;

[0075] Figure 10 This is one of the process diagrams illustrating the fabrication of a second module as a second device in the substrate wiring method provided in an embodiment of the present invention;

[0076] Figure 11 This is a second schematic diagram of the process of fabricating the second module into a second device in the substrate wiring method provided in the embodiments of the present invention;

[0077] Figure 12 This is a schematic diagram of another process for fabricating the second module in the substrate wiring method provided in this embodiment of the invention;

[0078] Figure 13 This is one of the process diagrams for mounting a fourth chip in the second module in the substrate wiring method provided in an embodiment of the present invention;

[0079] Figure 14 This is a second schematic diagram of the process of mounting the fourth chip in the second module in the substrate wiring method provided in the embodiment of the present invention;

[0080] Figure 15This is a schematic diagram of a first type of packaging structure provided in an embodiment of the present invention;

[0081] Figure 16 This is a schematic diagram of a second structure of the first packaging structure provided in an embodiment of the present invention;

[0082] Figure 17 This is a schematic diagram of a first structure of the second packaging structure provided in an embodiment of the present invention;

[0083] Figure 18 This is a schematic diagram of a second type of packaging structure provided in an embodiment of the present invention;

[0084] Figure 19 This is a schematic diagram of a third structure of the second packaging structure provided in an embodiment of the present invention;

[0085] Figure 20 This is a schematic diagram of a first type of substrate packaging structure provided in an embodiment of the present invention;

[0086] Figure 21 This is a schematic diagram of a second structure of the substrate packaging structure provided in an embodiment of the present invention;

[0087] Figure 22 This is a schematic diagram of a third type of substrate packaging structure provided in an embodiment of the present invention;

[0088] Figure 23 This is a schematic diagram of a fourth type of substrate packaging structure provided in an embodiment of the present invention.

[0089] Icons: 100 - Substrate packaging structure; 110 - First carrier; 120 - First prepreg; 121 - First segment; 122 - First opening; 123 - Second segment; 124 - Second opening; 125 - First metal pillar; 126 - First wiring layer; 127 - Second metal pillar; 128 - Second wiring layer; 129 - First solder ball; 131 - First dielectric layer; 132 - First opening; 133 - Second prepreg; 134 - Second opening; 135 - Third metal pillar; 136 - Third wiring layer; 141 - Second dielectric layer; 142 - Third opening; 143 - First conductive pillar; 144 - Fourth metal pillar; 145 - Fourth wiring layer; 151 - Third dielectric layer; 152 - Fourth opening; 153 - First metal layer; 10 - First module; 101 - Recess 20 - Second module; 210 - First chip; 161 - Fourth dielectric layer; 201 - First device; 162 - Protective film; 163 - Fifth dielectric layer; 164 - Fifth wiring layer; 165 - Second metal layer; 166 - Second solder ball; 220 - Second chip; 171 - Fifth opening; 172 - Second conductive post; 173 - Third metal layer; 230 - Third chip; 174 - Third solder ball; 175 - Molded enclosure; 202 - Second device; 111 - First through hole; 112 - Fourth metal layer; 113 - Second through hole; 114 - Third conductive post; 240 - Fourth chip; 181 - Sixth dielectric layer; 182 - Sixth opening; 183 - Sixth wiring layer; 184 - Seventh dielectric layer; 185 - Fifth metal layer; 186 - Fourth solder ball; 300 - Substrate. Detailed Implementation

[0090] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0091] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0092] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0093] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this invention is in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention. In addition, the terms "first," "second," "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0094] Furthermore, terms such as "horizontal," "vertical," and "sag" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal relative to "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0095] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0096] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0097] The substrate wiring method proposed in this embodiment of the invention generally includes the following main steps:

[0098] Please combine Figure 1 S1. A first carrier 110 is provided having a first prepreg 120. The first prepreg 120 includes a first portion 121 and a second portion 123, with the second portion 123 being higher than the first portion 121. The first prepreg 120 may employ a separable bonding adhesive layer, which can be a thermoplastic material or a photosensitive material. The photosensitive material can be removed by irradiation with light. Alternatively, the bonding adhesive layer can be separated and removed by ultraviolet light irradiation, laser debonding, or heating. The first carrier 110 may be made of materials such as glass, silicon dioxide, or metal.

[0099] S2. A first wiring layer 126 is formed in the first section 121, and a second wiring layer 128 is formed in the second section 123.

[0100] Optionally, a laser-drilled hole process is used to form holes on the first prepreg 120. These holes include a first hole 122 located in the first portion 121 and a second hole 124 located in the second portion 123. The first hole 122 and the second hole 124 are exposed on the first carrier 110. The opening size of the first hole 122 is larger than the bottom size, and the cross-section of the first hole 122 gradually decreases from top to bottom. The opening size of the second hole 124 is smaller than the bottom size, and the cross-section of the second hole 124 gradually increases from top to bottom. It is easy to understand that different shapes of holes can be formed by focusing the light source using convex and concave lenses on a laser lens.

[0101] Conductive material is filled into the openings using either dispensing or electroplating. The conductive material in the first opening 122 forms a first metal pillar 125, and the conductive material in the second opening 124 forms a second metal pillar 127. The shape of the first metal pillar 125 is the same as the shape of the first opening 122, and the shape of the second metal pillar 127 is the same as the shape of the second opening 124. The different shapes of the first metal pillar 125 and the second metal pillar 127 serve as a foolproof design feature. Wiring layer functional traces can be designed on the surface of the first metal pillar 125. Antenna pattern layers or inductor wiring layers, etc., can be designed on the surface of the second metal pillar 127.

[0102] A first wiring layer 126 is formed on the first metal pillar 125, and a second wiring layer 128 is formed on the second metal pillar 127.

[0103] Optionally, a liquid photoresist layer is uniformly coated onto the surface of the first prepreg 120 using a spin coater. A photomask layer (patterning layer) is then applied over the photoresist layer, and patterned openings are formed on the photoresist layer using an exposure and development process. A metal layer is then electroplated within the patterned openings to form a wiring layer. A first wiring layer 126 is formed above the first metal pillar 125. The first wiring layer 126 and the first metal pillar 125 are electrically connected. A second wiring layer 128 is formed above the second metal pillar 127. The second wiring layer 128 and the second metal pillar 127 are electrically connected. Both the first wiring layer 126 and the second wiring layer 128 are made of copper. The photomask layer is removed, and the photoresist layer is removed using a cleaning method or a photosensitive removal method.

[0104] It is understandable that the larger upper end of the first metal pillar 125 increases the contact area with the first wiring layer 126, thereby improving the bonding strength between the first metal pillar 125 and the first wiring layer 126 and enhancing the reliability of the electrical connection. The larger lower end of the second metal pillar 127 will be used in subsequent processes to form the first solder ball 129 or connect to the pad. This increases the contact area between the second metal pillar 127 and the first solder ball 129 or pad, thereby improving the connection reliability between the second metal pillar 127 and the pad and reducing welding stress.

[0105] S3. A first dielectric layer 131 is formed to cover the first wiring layer 126 and the second wiring layer 128. The first dielectric layer 131 is provided with a first opening 132; the first opening 132 is provided along the outer periphery of the second wiring layer 128 and exposes the first prepreg 120.

[0106] Optionally, a liquid first dielectric layer 131 (such as polyimide) is uniformly coated onto the first wiring layer 126 and the second wiring layer 128 using a physical vapor deposition (PVD) or chemical vapor deposition (CVD) process. The layer is then soft-baked on a hot plate to set the film, and then heated again in an oven to accelerate the curing of the first dielectric layer 131 to a fully cured and stable state. The first opening 132 can be formed simultaneously with the formation of the first dielectric layer 131. The area requiring the opening is protected by a mold, and after removing the mold, a first dielectric layer 131 with the first opening 132 is formed. In some embodiments, the first opening 132 can also be formed after the formation of the first dielectric layer 131 by etching, laser grooving, or other methods.

[0107] Please combine Figure 2 S4. Cover the second prepreg 133 with the second portion 123 and fill the first opening 132. The surface of the second prepreg 133 is higher than the surface of the first dielectric layer 131. A debonding adhesive layer can be printed in the area enclosed by the first opening 132 and fill the first opening 132 to form a second prepreg 133 that is higher than the surface of the first dielectric layer 131. The material of the second prepreg 133 is the same as the material of the first prepreg 120.

[0108] S5. A third wiring layer 136 electrically connected to the first wiring layer 126 is formed on the first portion 121.

[0109] Optionally, a second opening 134 is formed on the first dielectric layer 131 using laser drilling or exposure and development. The second opening 134 is then filled with metal to form a connected third metal pillar 135 and a third wiring layer 136. The fabrication method of the third wiring layer 136 is the same as that of the first wiring layer 126, and is not specifically limited here.

[0110] S6. A second dielectric layer 141 is formed, covering the third wiring layer 136 and the second prepreg 133. The material of the second dielectric layer 141 is the same as that of the first dielectric layer 131. The formation method of the second dielectric layer 141 is the same as that of the first dielectric layer 131, and is not specifically limited here.

[0111] Please combine Figure 3 S7. A first conductive pillar 143 is formed in the corresponding area of ​​the second semi-cured sheet 133, penetrating the second dielectric layer 141.

[0112] Optionally, a first conductive post 143 is formed on the second dielectric layer 141 to facilitate the subsequent separation of the first module 10 and other modules through the first conductive post 143.

[0113] Of course, in some embodiments, a fourth wiring layer 145 and a third dielectric layer 151 covering the fourth wiring layer 145 may also be formed on the surface of the second dielectric layer 141. The fourth wiring layer 145 is electrically connected to the third wiring layer 136 and the first conductive pillar 143, respectively. Optionally, a third opening 142 is formed on the second dielectric layer 141, and metal is filled in the third opening 142 to form a fourth metal pillar 144, a first conductive pillar 143, and a fourth wiring layer 145. The fourth metal pillar 144 is located above the third wiring layer 136, and the first conductive pillar 143 is located above the second prepreg 133. The fourth wiring layer 145 is electrically connected to the fourth metal pillar 144 and the first conductive pillar 143, respectively.

[0114] Please combine Figure 4 Optionally, a fourth opening 152 is formed on the third dielectric layer 151, and metal is filled into the fourth opening 152 to form a first metal layer 153 electrically connected to the fourth wiring layer 145. It can be understood that the first metal layer 153 is a pad structure, and the material can be copper. Electroplating nickel, gold, or other materials on the surface of the copper further improves its solderability. Optionally, a green paint layer is printed around the first metal layer 153 to complete the preparation of the pad structure.

[0115] S8. Debonding is performed using the interfaces between the first prepreg 120 and the second prepreg 133 and the dielectric layer as separation surfaces to obtain the first module 10 and the second module 20. The second module 20 includes the first prepreg 120 and the second prepreg 133. The first module 10 has a groove 101 corresponding to the second prepreg 133. It should be noted that the separation surfaces include the interfaces between the second prepreg 133 and the first dielectric layer 131 and the second dielectric layer 141, respectively, and the interface between the first prepreg 120 and the first dielectric layer 131. Optionally, debonding separation can be achieved using light irradiation, heating, or laser debonding methods.

[0116] In this way, by separating the components through debonding, the fabrication of both the first module 10 and the second module 20 can be completed in a single manufacturing process. The two product structures can be stacked together, making the fabrication method more flexible and efficient. The separate mounting method facilitates later repair and replacement. The two product structures can also be individually packaged with other modules, allowing for flexible and varied combination options.

[0117] Please combine Figure 5 Optionally, after the step of forming the first metal layer 153 electrically connected to the fourth wiring layer 145, the method further includes:

[0118] The first chip 210 is mounted, and the first chip 210 is electrically connected to the first metal layer 153. This step can be completed before or after debonding and separation, and no specific limitation is made here.

[0119] Please combine Figure 6 Optionally, after the step of producing the second module 20, the method further includes:

[0120] Remove the first prepreg 120 and the second prepreg 133 from the second module 20. Optionally, form a fourth dielectric layer 161 covering the first dielectric layer 131 on the first carrier 110. Remove the first carrier 110 to expose the second metal pillar 127 connected to the second wiring layer 128. Form first solder balls 129 on the second metal pillar 127, and separate and cut the fourth dielectric layer 161 to obtain the first device 201. In some embodiments, the fourth dielectric layer 161 may be omitted, which is not specifically limited here.

[0121] Please combine Figure 7 Optionally, the first device 201 can be mounted in the first module 10. The following description takes the mounting of the first device 201 in the first module 10 as an example.

[0122] The first device 201 is mounted in the groove 101 of the first module 10, and the first solder ball 129 and the first conductive post 143 are electrically connected to achieve the electrical connection between the first device 201 and the first module 10.

[0123] Optionally, a protective film 162 is formed, which covers the first module 10 and the second module 20. The protective film 162 can make the surface of the first module 10 on which the first device 201 is mounted more flat and protect the first metal pillar 125 on the first module 10.

[0124] Please combine Figure 8Optionally, in some embodiments, after the step of mounting the first device 201, the method further includes: forming a fifth dielectric layer 163 covering the fifth wiring layer 164, wherein the fifth wiring layer 164 is electrically connected to the first wiring layer 126. Alternatively, the fifth wiring layer 164 is electrically connected to both the first wiring layer 126 and the second wiring layer 128. A second metal layer 165 is formed on the fifth dielectric layer 163. The second metal layer 165 is electrically connected to the fifth wiring layer 164. The second metal layer 165 employs a pad structure. In some embodiments, a second solder ball 166 may be formed on the second metal layer 165.

[0125] Please combine Figure 9 Optionally, a second chip 220 is mounted on the fifth dielectric layer 163, and the second chip 220 is electrically connected to the second metal layer 165. If the second metal layer 165 is provided with a second solder ball 166, the second chip 220 and the second solder ball 166 are soldered together to achieve electrical connection.

[0126] Please combine Figure 10 In some embodiments, after the step of forming the fourth dielectric layer 161 on the first carrier 110, the method further includes:

[0127] A second conductive post 172 is formed penetrating the fourth dielectric layer 161, and the second conductive post 172 is electrically connected to the second wiring layer 128. Optionally, a fifth opening 171 is formed in the fourth dielectric layer 161, penetrating the fourth dielectric layer 161 and the first dielectric layer 131, and a second conductive post 172 is formed within the fifth opening 171, and the second conductive post 172 is electrically connected to the second wiring layer 128.

[0128] Optionally, a third metal layer 173 connected to the second conductive pillar 172 is formed on the surface of the fourth dielectric layer 161. The third metal layer 173 has a pad structure. The preparation of the third metal layer 173 is the same as that of the first metal layer 153 and the second metal layer 165.

[0129] Optionally, a third chip 230 may be mounted on the third metal layer 173.

[0130] Please combine Figure 11 Optionally, the third chip 230 is molded to form a molded body 175. The material of the molded body 175 and the fourth dielectric layer 161 can be the same. Optionally, the first carrier 110 is removed. A third solder ball 174 is formed on the second metal post 127. Then, the molded body 175 and the fourth dielectric layer 161 are cut to form a single product, here defined as the second device 202. The second device 202 can also be mounted in the recess 101 of the first module 10, with the third solder ball 174 electrically connected to the first conductive post 143.

[0131] Please combine Figure 12Optionally, in some embodiments, the first carrier 110 may remain in the second module 20. For example, a first prepreg 120 is formed on the first carrier 110. The step of forming the second wiring layer 128 in the second portion 123 includes:

[0132] A first through-hole 111 is formed in the second portion 123, penetrating the first carrier 110. A second metal pillar 127 is formed by filling the first through-hole 111 with conductive material; a second wiring layer 128 is formed, electrically connected to the second metal pillar 127. Furthermore, a fourth metal layer 112 is formed on the side of the first carrier 110 away from the second portion 123, electrically connected to the second metal pillar 127. The fabrication process of the first portion 121 is similar to the aforementioned process. A first metal pillar 125 and a first wiring layer 126 are formed on the first portion 121. The first metal pillar 125 does not penetrate the first carrier 110. Subsequent steps S3 to S8 are similar to the aforementioned process and will not be repeated here. It is worth noting that... Figure 12 and Figure 13 The processes between them omit steps S3 to S8.

[0133] Of course, in some implementations... Figure 13 The structure shown in the first step of the process can also be formed in the following way: after forming the second module 20, the first semi-cured sheet 120 and the second semi-cured sheet 133 are removed, a hole is opened on the back of the first carrier 110 to expose the second metal pillar 127, and a fourth metal layer 112 is formed after filling with conductive material. No specific limitation is made here.

[0134] Please combine Figure 13 , Figure 14 After separating the first module 10 and the second module 20, the first prepreg 120 and the second prepreg 133 in the second module 20 are removed. A fourth chip 240 is mounted on the side of the first carrier 110 near the second wiring layer 128. It is understood that the fourth chip 240 is fixed to the first carrier 110 by an adhesive layer. The fourth chip 240 is then encapsulated or a fourth dielectric layer 161 is formed that covers the first chip 210 and the first dielectric layer 131.

[0135] The product is flipped so that the first carrier 110 faces upward. A second through-hole 113 is formed on the first carrier 110, exposing the pads of the fourth chip 240. A conductive material is filled into the second through-hole 113 to form a third conductive pillar 114. A sixth dielectric layer 181 covering the sixth wiring layer 183 is formed on the side of the first carrier 110 away from the second wiring layer 128. The sixth wiring layer 183 is electrically connected to the fourth metal layer 112 and the fourth chip 240, respectively. Optionally, the sixth dielectric layer 181 is formed on the side of the first carrier 110 away from the second wiring layer 128, and a patterned sixth opening 182 is formed on the sixth dielectric layer 181 by exposure development or laser grooving, exposing the third conductive pillar 114. Metal is filled into the sixth opening 182 to form the sixth wiring layer 183. The sixth wiring layer 183 is electrically connected to the fourth chip 240 through the third conductive pillar 114, and is also electrically connected to the fourth metal layer 112. Optionally, a seventh dielectric layer 184 is formed on the sixth dielectric layer 181; a fifth metal layer 185 is formed on the seventh dielectric layer 184. The fifth metal layer 185 has a pad structure, and its fabrication process is similar to that of the first metal layer 153. Optionally, a fourth solder ball 186 can be formed on the fifth metal layer 185. Finally, the layers are cut and separated to form individual products.

[0136] This invention also provides a substrate packaging structure 100, which can be fabricated using the processes described in any of the above embodiments. The various embodiments described above can be combined with each other without conflict.

[0137] The substrate packaging structure 100 includes: a first packaging structure or a second packaging structure.

[0138] Please combine Figure 15 The substrate packaging structure 100 includes a first packaging structure. The first packaging structure is fabricated using the aforementioned first module 10. The first packaging structure includes a first dielectric layer 131, a second dielectric layer 141, and a third dielectric layer 151 stacked sequentially; the first dielectric layer 131 has a first wiring layer 126, the second dielectric layer 141 has a third wiring layer 136, and the third dielectric layer 151 has a fourth wiring layer 145; a first metal layer 153 is disposed on the surface of the third dielectric layer 151 and is electrically connected to the fourth wiring layer 145; the fourth wiring layer 145 and the third wiring layer 136 are electrically connected, and the third wiring layer 136 and the first wiring layer 126 are electrically connected.

[0139] A groove 101 is provided on the side of the first dielectric layer 131 away from the first metal layer 153, and a first metal post 125 protrudes from the first dielectric layer 131. It is understood that the first metal post 125 protrudes from the surface of the first dielectric layer 131. The first metal post 125 is electrically connected to the first wiring layer 126. A first conductive post 143 is connected to the fourth wiring layer 145, and the end of the first conductive post 143 away from the fourth wiring layer 145 protrudes from the bottom of the groove 101.

[0140] Please combine Figure 16 Optionally, the substrate packaging structure 100 further includes a substrate 300, to which the first packaging structure is attached. The first metal pillar 125 is electrically connected to pads on the substrate 300. The groove 101 faces the substrate 300. This configuration improves heat dissipation performance. Optionally, the first chip 210 is electrically connected to the side of the first module 10 away from the substrate 300, which helps increase the density of the packaged chips and achieve high-density packaging.

[0141] Please combine Figure 17 The substrate packaging structure 100 includes a second packaging structure. The second packaging structure is fabricated using the aforementioned second module 20. The second packaging structure includes a second metal pillar 127, a second wiring layer 128, and a first dielectric layer 131. The first dielectric layer 131 covers the second wiring layer 128, and the second metal pillar 127 is electrically connected to the second wiring layer 128; the second metal pillar 127 protrudes from the first dielectric layer 131.

[0142] Optionally, the second packaging structure further includes a first solder ball 129 connected to the second metal pillar 127. Alternatively, the second module 20 further includes a fourth dielectric layer 161. The fourth dielectric layer 161 covers the first dielectric layer 131 and the second metal pillar 127. The surface of the second metal pillar 127 away from the second wiring layer 128 is exposed from the fourth dielectric layer 161.

[0143] In this second packaging structure, the second wiring layer 128 is a separate antenna layer or inductor coil structure, forming a patch antenna or patch inductor, which has good heat dissipation and unobstructed transmission path.

[0144] Please combine Figure 18Optionally, the second packaging structure further includes a third chip 230, a second conductive post 172, and a third metal layer 173. The second conductive post 172 penetrates the fourth dielectric layer 161 and the first dielectric layer 131, and is electrically connected to the second wiring layer 128. The third metal layer 173 is electrically connected to the second conductive post 172, and the third metal layer 173 protrudes from the surface of the fourth dielectric layer 161. The third chip 230 is disposed on the side of the fourth dielectric layer 161 away from the second wiring layer 128. The third chip 230 and the third metal layer 173 are electrically connected. A molding compound 175 covers the third chip 230. The material of the molding compound 175 may be the same as the material of the first dielectric layer 131 and the fourth dielectric layer 161. Optionally, a third solder ball 174 is provided on the side of the second metal post 127 away from the second wiring layer 128.

[0145] It is understandable that when the third chip 230 is embedded in the second packaging structure, the third chip 230 can be an RF switch chip, etc. By integrating an RF switch chip, etc., into the antenna layer, the antenna layer and the entire module can be dynamically controlled, enabling flexible adjustment of the signal propagation path. It can control the amplitude, phase, polarization, and other states of multiple antenna elements to adapt to different communication needs.

[0146] Please combine Figure 19 Optionally, the second packaging structure includes a first dielectric layer 131, a fourth dielectric layer 161, a first carrier 110, a sixth dielectric layer 181, a seventh dielectric layer 184, a second metal pillar 127, a second wiring layer 128, a fourth chip 240, and a sixth wiring layer 183. The second wiring layer 128 is formed on one side of the first carrier 110, and the first dielectric layer 131 covers the second wiring layer 128. The fourth chip 240 is disposed on the side with the second wiring layer 128. The fourth dielectric layer 161 covers the fourth chip 240 and the first dielectric layer 131. The sixth wiring layer 183 is disposed on the side of the first carrier 110 away from the fourth chip 240. One end of the second metal pillar 127 is electrically connected to the second wiring layer 128, and the other end passes through the first carrier 110 and is connected to the fourth metal layer 112. The fourth metal layer 112 is disposed on the side of the first carrier 110 away from the second wiring layer 128, and the fourth metal layer 112 and the sixth wiring layer 183 are electrically connected. The second packaging structure also includes a third conductive post 114 penetrating the first carrier 110. One end of the third conductive post 114 is electrically connected to the fourth chip 240, and the other end is electrically connected to the sixth wiring layer 183. The sixth dielectric layer 181 covers the sixth wiring layer 183, and a seventh dielectric layer 184 is disposed on the side of the sixth dielectric layer 181 away from the first carrier 110. A fifth metal layer 185 electrically connected to the sixth wiring layer 183 is disposed within the seventh dielectric layer 184. Optionally, a fourth solder ball 186 is electrically connected to the fifth metal layer 185 and protrudes from the surface of the seventh dielectric layer 184.

[0147] It is understandable that if the fourth chip 240 is a radio frequency (RF) chip, the second wiring layer 128 is an antenna layer. The RF chip can achieve transmission through the antenna. If the fourth chip 240 is a power management chip, the second wiring layer 128 is an inductor layer, and the sixth wiring layer 183 at the bottom of the fourth chip 240 is a functional trace. The second metal pillar 127 penetrating the first carrier 110 helps improve the bonding strength between the first carrier 110 and the fourth dielectric layer 161, as well as the bonding strength between the fourth metal layer 112 on the back of the first carrier 110 and the second metal pillar 127.

[0148] In this embodiment, the first carrier can be a glass carrier, which has extremely low dielectric loss (tanδ), typically less than 0.01. This results in less signal attenuation and lower latency when transmitting high-frequency electrical signals, and also improves environmental resistance (such as corrosion resistance and resistance to high and low temperature shocks). Furthermore, glass carriers also help improve the overall structural strength and support, mitigating warpage during the packaging process.

[0149] Please combine Figure 20 Optionally, the substrate packaging structure 100 includes a first packaging structure and a second packaging structure. The second packaging structure is disposed in the groove 101, and the second metal pillar 127 and the first conductive pillar 143 are electrically connected. In this embodiment, the second metal pillar 127 is connected to a first solder ball 129, and the first solder ball 129 and the first conductive pillar 143 are electrically connected. The protective film 162 covers the first packaging structure and the second packaging structure, making the surface of the first packaging structure away from the first metal layer 153 flush, and the first metal pillar 125 exposed from the surface of the protective film 162. The setting of the protective film 162 is beneficial to protect the sidewalls of the first metal pillar 125, and can completely block the path of moisture, dust, etc. from entering the interior of the packaging structure from the gaps, meeting the IP65 protection level (dustproof, water jetproof) requirements. The first metal pillar 125 also helps to improve the adhesion between the protective film 162 and the dielectric layer.

[0150] Please combine Figure 21 Optionally, the substrate packaging structure 100 further includes a fifth dielectric layer 163, which has a fifth wiring layer 164. The fifth wiring layer 164 is electrically connected to the first conductive pillar 143, and a second metal layer 165 electrically connected to the fifth wiring layer 164 is provided on the surface of the fifth dielectric layer 163. Optionally, a second solder ball 166 is connected to the second metal layer 165.

[0151] In some embodiments, the fifth wiring layer 164 may also be electrically connected to the second wiring layer 128 via the second conductive post 172, which is not specifically limited here.

[0152] Optionally, the substrate packaging structure 100 further includes a second chip 220, which is electrically connected to the second metal layer 165. This configuration helps to improve chip integration. Of course, in some other embodiments, the chip can also be mounted on the first metal layer 153; this is not specifically limited here.

[0153] Please combine Figure 22 Optionally, the substrate packaging structure 100 further includes a third chip 230, which is electrically connected to the second wiring layer 128. The second packaging structure, on which the third chip 230 is mounted, is integrally mounted into the recess 101 of the first packaging structure. Optionally, one end of the first metal pillar 125 is connected to the first wiring layer 126, and the other end is connected to the fifth wiring layer 164. A fifth dielectric layer 163 covering the fifth wiring layer 164 is disposed on the side of the second packaging structure with the third chip 230. In this way, the second packaging structure is embedded in the first packaging structure, which is beneficial for reducing volume and improving integration. The protective film 162 in this structure can also be replaced by a dielectric layer, which is not specifically limited here.

[0154] Please combine Figure 23 Optionally, in substrate packaging structure 100, and Figure 20 Compared to the structure shown, the protective film 162 and the fourth dielectric layer 161 can be omitted. The first metal pillar 125 protrudes from the surface of the first dielectric layer 131. The second package structure can be an antenna, an inductor, or other devices. This is beneficial for improving the transmission efficiency of the antenna and the heat dissipation performance of the inductor.

[0155] Optionally, the first metal post 125 is grounded, protruding from the surface of the first dielectric layer 131 and surrounding the outer periphery of the second package structure. In this way, the first metal post 125 around the groove 101 can form a cage-like structure to prevent antenna signals from interfering with surrounding devices; and the first metal post 125 also dissipates static electricity around the antenna, thereby better protecting the antenna structure. When the second package structure is an inductor, the first metal post 125 serves as a static electricity dissipator and prevents inductor signal crosstalk during inductor operation.

[0156] It should be noted that the second packaging structure in this embodiment uses an inductor or antenna structure and is integrated into the substrate packaging structure 100 by surface mounting. This allows the second wiring layer 128 to be designed close to the surface of the structure, or even exposed to the surface of the packaging structure, thereby improving antenna transmission efficiency and inductor heat dissipation. Traditional antenna structures are buried in the circuit layer and located inside the packaging structure, with many circuit layers and dielectric layers above them, which can easily obstruct the transmission of antenna signals. In this embodiment, the antenna and inductor can be designed with specific shapes to facilitate wiring. Traditional antenna and inductor processes involve front-side wiring. In this embodiment, the second wiring layer 128 in the second packaging structure and the second wiring layer 128 mounted after the first packaging structure are mirror-symmetrical (mounted after being flipped 180 degrees). Therefore, this embodiment can achieve a reverse wiring structure. Using this reverse or mirrored wiring can provide a low-impedance path for signal layer return current. Especially in power distribution systems with large current flow, it can effectively reduce return noise and reduce the area of ​​the closed loop formed by the signal and return current, thereby reducing electromagnetic interference (EMI).

[0157] The substrate wiring method and substrate packaging structure 100 provided in this embodiment of the invention have the following beneficial effects, including:

[0158] In the encapsulation process, a prepreg is used as a bonding release layer. After completing multi-layer wiring, the packaged product is debonded at the prepreg to form the first module 10 and the second module 20. This configuration allows for flexible wiring and combination of the first module 10 and the second module 20, facilitating flexible design of the wiring layer routing. It enables modular design, making assembly, disassembly, maintenance, and replacement more convenient, and also improves encapsulation efficiency. Furthermore, the debonding facilitates improved heat dissipation performance.

[0159] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; any modifications, equivalent substitutions, improvements, etc., should be included within the protection scope of the present invention.

Claims

1. A substrate wiring method, characterized in that, include: A first carrier having a first prepreg is provided; wherein the first prepreg includes a first portion and a second portion, the second portion being higher than the first portion; A first wiring layer is formed in the first portion, and a second wiring layer is formed in the second portion; A first dielectric layer is formed to cover the first wiring layer and the second wiring layer; wherein the first dielectric layer has a first opening; the first opening is disposed along the outer periphery of the second wiring layer and exposes the first prepreg. The second portion is covered with a second prepreg and the first opening is filled; the surface of the second prepreg is higher than the surface of the first dielectric layer. A third wiring layer electrically connected to the first wiring layer is formed on the first portion; A second dielectric layer is formed that covers the third wiring layer and the second prepreg. A first conductive pillar penetrating the second dielectric layer is formed in the corresponding region of the second prepreg; Using the interfaces between the first and second prepregs and the dielectric layer as separation surfaces, debonding is performed to separate and obtain a first module and a second module; wherein, the second module includes the first prepreg and the second prepreg; the first module has a groove corresponding to the position of the second prepreg; the separation surface includes the interface between the second prepreg and the first dielectric layer and the second dielectric layer, and the interface between the first prepreg and the first dielectric layer.

2. The substrate wiring method according to claim 1, characterized in that, Before performing the debonding step, the following steps are also included: A fourth wiring layer and a third dielectric layer covering the fourth wiring layer are formed; the fourth wiring layer is electrically connected to the third wiring layer and the first conductive pillar, respectively; A first metal layer is formed that is electrically connected to the fourth wiring layer.

3. The substrate wiring method according to claim 2, characterized in that, After the step of forming the first metal layer electrically connected to the fourth wiring layer, the method further includes: The first chip is mounted, and the first chip is electrically connected to the first metal layer.

4. The substrate wiring method according to claim 1, characterized in that, After the step of obtaining the second module, the method further includes: Remove the first prepreg and the second prepreg from the second module; Remove the first carrier to expose the second metal pillar connected to the second wiring layer; A first solder ball is formed on the second metal pillar to obtain the first device.

5. The substrate wiring method according to claim 4, characterized in that, After the step of producing the first device, the following steps are also included: The first device is mounted into the groove of the first module, and the first solder ball and the first conductive post are electrically connected.

6. The substrate wiring method according to claim 4, characterized in that, After the step of mounting the first device, the method further includes: A protective film is formed, which covers the first module and the first device.

7. The substrate wiring method according to claim 4, characterized in that, After the step of mounting the first device, the method further includes: A fifth dielectric layer is formed covering the fifth wiring layer, and the fifth wiring layer is electrically connected to the first wiring layer; or, the fifth wiring layer is electrically connected to both the first wiring layer and the second wiring layer. A second metal layer is formed on the fifth dielectric layer.

8. The substrate wiring method according to claim 7, characterized in that, After the step of forming the second metal layer on the fifth dielectric layer, the method further includes: A second chip is mounted, and the second chip is electrically connected to the second metal layer.

9. The substrate wiring method according to claim 4, characterized in that, After the step of removing the first prepreg and the second prepreg from the second module, the method further includes: A fourth dielectric layer is formed on the first carrier; Remove the first vehicle; After the first solder ball is formed, the fourth dielectric layer is cut to obtain the first device.

10. The substrate wiring method according to claim 9, characterized in that, Following the step of forming the fourth dielectric layer on the first carrier, the method further includes: A second conductive pillar is formed that penetrates the fourth dielectric layer, and the second conductive pillar is electrically connected to the second wiring layer; A third metal layer connected to the second conductive pillar is formed on the surface of the fourth dielectric layer; A third chip is mounted on the third metal layer.

11. The substrate wiring method according to claim 1, characterized in that, The step of forming the second wiring layer in the second portion includes: A first through hole is opened in the second section, and the first through hole penetrates the first vehicle; A second metal pillar is formed by filling the first through-hole with conductive material; A second wiring layer is formed that is electrically connected to the second metal pillar; A fourth metal layer is formed on the side of the first carrier away from the second portion, and the fourth metal layer is electrically connected to the second metal pillar.

12. The substrate wiring method according to claim 11, characterized in that, After the step of removing the first prepreg and the second prepreg from the second module, the method further includes: A fourth chip is mounted on the side of the first carrier closest to the second wiring layer; A sixth dielectric layer covering the sixth wiring layer is formed on the side of the first carrier away from the second wiring layer; the sixth wiring layer is electrically connected to the fourth metal layer and the fourth chip respectively; A seventh dielectric layer is formed on the sixth dielectric layer; A fifth metal layer is formed in the seventh dielectric layer.

13. A substrate packaging structure, characterized in that, The substrate is manufactured using the substrate wiring method as described in any one of claims 1 to 12; the substrate packaging structure includes: a first packaging structure or a second packaging structure; The first packaging structure includes a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked sequentially; the first dielectric layer has a first wiring layer, the second dielectric layer has a third wiring layer, and the third dielectric layer has a fourth wiring layer; a first metal layer is disposed on the surface of the third dielectric layer and is electrically connected to the fourth wiring layer; the fourth wiring layer and the third wiring layer are electrically connected, and the third wiring layer and the first wiring layer are electrically connected. The first dielectric layer has a groove on the side away from the first metal layer, and the first dielectric layer has a protruding first metal pillar, which is electrically connected to the first wiring layer. The fourth wiring layer is connected to a first conductive post, and the end of the first conductive post away from the fourth wiring layer protrudes from the bottom of the groove. The second packaging structure includes a second metal pillar, a second wiring layer, and a first dielectric layer; the first dielectric layer covers the second wiring layer, and the second metal pillar is electrically connected to the second wiring layer; the second metal pillar protrudes from the first dielectric layer.

14. The substrate packaging structure according to claim 13, characterized in that, It includes a first packaging structure and a second packaging structure, the second packaging structure is disposed in the groove, and the second metal post and the first conductive post are electrically connected.

15. The substrate packaging structure according to claim 14, characterized in that, It also includes a first chip, which is electrically connected to the first metal layer.

16. The substrate packaging structure according to claim 14, characterized in that, It also includes a second chip, which is electrically connected to the first wiring layer.

17. The substrate packaging structure according to claim 14, characterized in that, The first metal post is grounded, protrudes from the surface of the first dielectric layer, and surrounds the outer periphery of the second packaging structure.

18. The substrate packaging structure according to claim 14, characterized in that, A protective film covers the first dielectric layer and the second encapsulation structure, with the first metal pillar exposed from the surface of the protective film.

19. The substrate packaging structure according to any one of claims 13 to 18, characterized in that, The second packaging structure also includes a third chip, which is electrically connected to the second wiring layer.

20. The substrate packaging structure according to claim 13, characterized in that, The second packaging structure further includes a fourth dielectric layer, which covers the first dielectric layer and the second metal pillar, with the second metal pillar exposed from the surface of the fourth dielectric layer.

21. The substrate packaging structure according to claim 13, characterized in that, It also includes a substrate, to which the first packaging structure is electrically connected; the groove opening faces the substrate.

22. The substrate packaging structure according to claim 21, characterized in that, The first chip is electrically connected to the side of the first package structure away from the substrate.

23. The substrate packaging structure according to claim 13, characterized in that, The second packaging structure further includes a first carrier, on the side of the first carrier away from the second wiring layer, a fourth metal layer is provided, and the fourth metal layer is electrically connected to the second wiring layer.

24. The substrate packaging structure according to claim 23, characterized in that, The first carrier has a fourth chip on the side closer to the second wiring layer, and a sixth wiring layer on the side of the first carrier away from the second wiring layer. The sixth wiring layer and the fourth chip are electrically connected.

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