Structure for improving wafer scribing reliability

Abstract

The invention provides a structure for improving wafer scribing reliability. The structure includes a chip region, adjacent scribe lanes, a seal ring within the chip region adjacent the scribe lanes, and a passivation layer covering these regions. The key point is that in the passivation layer, a passivation layer slot is formed between the sealing ring and the scribing channel, and a first safety distance and a second safety distance are respectively defined between the slot and the sealing ring as well as between the slot and the scribing channel. The groove of the passivation layer can release or buffer the generated mechanical stress in the subsequent scribing process and effectively prevent the mechanical stress from being destructively transmitted to the sealing ring and the internal area of the chip, so that the defects of edge breakage, cracks and the like caused by scribing are remarkably reduced, and the structural integrity and the packaging yield of the chip and the long-term reliability of a final product are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, and in particular to a structure for improving the reliability of wafer dicing. BACKGROUND

[0002] In the manufacturing process of semiconductor integrated circuits, hundreds or even thousands of identical chip units are simultaneously formed on a single semiconductor wafer, such as a silicon wafer, through a series of complex process steps. After the wafer is manufactured, in order to obtain individual chips that can be independently packaged, tested, and applied, the wafer needs to be cut and separated along the pre-planned narrow channels on the wafer surface, i.e., the dicing lanes. This cutting process is called dicing. The dicing process is a key link in the back-end manufacturing process of chips, and its operation quality is directly related to the physical integrity, final performance, and long-term reliability of the chips, and significantly affects the overall production yield and manufacturing cost.

[0003] However, materials such as single-crystal silicon, which are the base materials of semiconductor wafers, are inherently highly brittle. When performing the dicing operation, whether using traditional diamond grinding wheel mechanical cutting or advanced technologies such as laser cutting, mechanical stress, thermal stress, or impact force will inevitably be generated in the dicing lanes and the immediately adjacent chip edge regions. When the local stress generated by these forces exceeds the fracture toughness or fatigue limit of the wafer material itself, various microscopic or macroscopic physical damages are easily induced at the chip edge or the boundary of the dicing lane. Common dicing defects include: edge collapse, i.e., irregular small pieces of material peeling off at the chip edge; cracks, which can extend from the edge of the dicing lane to the interior of the chip; and delamination due to the destruction of interlayer adhesion, etc.

[0004] In many traditional chip layout designs, in order to maximize wafer utilization, the dicing lanes are usually designed to be closely adjacent to the boundaries of the chip functional regions. A sealing ring structure is usually provided around the periphery of the chip functional region, which is intended to protect the internal core circuit from the erosion of external environmental factors such as moisture and mobile ions, and to play a certain stress buffering role. However, when the dicing lane is directly adjacent to or connected to the sealing ring, lacking an effective transition or isolation region, the high stress generated during the dicing process is easily directly and quickly transmitted to the fragile sealing ring and the sensitive structures below it, and even further transmitted to the interior of the chip. This not only can directly damage the integrity of the sealing ring and reduce its protective effectiveness, but also can induce the above-mentioned edge collapse, crack, and other defects, directly leading to the chip being judged as a failure before it is shipped, or although it can pass the preliminary test, in the subsequent packaging process (such as wire bonding, plastic encapsulation molding, etc., which involve thermal stress and mechanical stress) or the long-term use process of the terminal product, these initial micro-damages can expand, eventually leading to the early failure of the chip, seriously threatening the reliability of the product.

[0005] Therefore, how to effectively control, reduce or block the adverse effects of dicing stress on the key structures of the chip, reduce physical damage caused by dicing, and thus significantly improve the reliability and yield of the chip during dicing, packaging and even the entire life cycle has become a technical challenge that the semiconductor manufacturing industry continues to focus on and urgently needs to solve. Summary of the Invention

[0006] This invention aims to solve at least some of the technical problems existing in the prior art. As described in the background section, during the semiconductor wafer dicing process, due to the brittleness of the wafer material and the stress generated by the dicing operation, defects such as edge chipping and cracks are easily generated near the dicing ridges and chip edges (especially near the sealing ring). These defects directly transmit stress to critical structures inside the chip, such as the sealing ring, thereby reducing chip reliability and production yield. Therefore, the technical problem to be solved by this invention is how to effectively reduce or isolate the stress generated during the dicing process, reduce its adverse effects on critical structures such as the chip sealing ring, and thus improve the reliability of wafer dicing and subsequent packaging.

[0007] To achieve the above and other related objectives, the present invention provides a structure for improving the reliability of wafer dicing, comprising:

[0008] The chip region and the scribe line adjacent to the chip region;

[0009] A sealing ring located within the chip area and adjacent to the dicing channel;

[0010] A passivation layer covering at least a portion of the chip region and extending into the scribe line direction; and

[0011] A passivation layer groove is formed in the passivation layer, and the passivation layer groove is located between the sealing ring and the dicing channel;

[0012] A first safety distance is defined between the passivation layer groove and the sealing ring, and a second safety distance is defined between the passivation layer groove and the dicing channel.

[0013] Preferably, the width of the passivation layer groove is 0.1 to 10 micrometers.

[0014] Preferably, the width of the passivation layer groove is 2 micrometers.

[0015] Preferably, both the first safety distance and the second safety distance are between 0.1 micrometers and 10 micrometers.

[0016] Preferably, both the first safety distance and the second safety distance are 2 micrometers.

[0017] Preferably, the first safety distance and the second safety distance ensure that the formation of the passivation layer slot does not affect the structural integrity of the seal ring and the structure within the scribe lane area.

[0018] Preferably, the structure within the scribe lane area includes a test key.

[0019] Preferably, the structure is located on an 8-inch semiconductor wafer or a 12-inch semiconductor wafer.

[0020] Preferably, the passivation layer slot is used to release or buffer scribe stress when scribing the scribe lane, so as to prevent stress from being transmitted to the seal ring.

[0021] As described above, the structure for improving wafer scribe reliability of the present application has the following beneficial effects:

[0022] By adding a simple slot structure, the present application can significantly reduce or even avoid common defects such as chip edge collapse and cracks caused by excessive scribe stress, thereby directly improving the yield of scribing. More importantly, it ensures the long-term structural stability and functional reliability of the chip during subsequent processes such as scribing and packaging, and in terminal applications. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 A schematic diagram of a seal ring and scribe lane structure of the prior art is shown;

[0024] Figure 2 A schematic diagram of a structure for improving wafer scribe reliability of the present application is shown. DETAILED DESCRIPTION

[0025] The embodiments of the present application will be described below through specific concrete examples, and those skilled in the art can easily understand other advantages and effects of the present application from the disclosure of the present specification. The present application can also be implemented or applied through other different specific embodiments, and various modifications or changes can be made to the details in the present specification based on different viewpoints and applications without departing from the spirit of the present application.

[0026] Please refer to Figure 2 The present application provides a structure for improving wafer scribe reliability, comprising:

[0027] a chip area and a scribe lane 102 adjacent to the chip area;

[0028] A sealing ring 101 located within the chip area and adjacent to the scribe lane 102, the sealing ring 101 is a critical protective structure that is placed around the periphery of the chip active area. Its main function is to act as a physical and electrical barrier to protect the sensitive circuit units inside the chip from the adverse effects of the external environment, such as preventing the intrusion of moisture, mobile ions (such as sodium ions), corrosive chemicals, etc. from the chip edge, while also possibly helping to absorb or block a portion of the mechanical stress generated during subsequent packaging processes, and preventing cracks generated during the scribing process from spreading into the active area of the chip. In terms of structure, the sealing ring 101 is usually designed as a continuous or quasi-continuous structure that surrounds the entire chip active area, which can be formed by stacking multiple layers of conductive materials (for example, using the metal interconnection layers in the chip manufacturing process, such as M1, M2,..., up to the top layer of metal) and insulating materials (such as interlayer dielectric ILD, intermetal dielectric IMD) and connecting them vertically through vias. These conductive layers are usually connected to fixed potential points of the chip, such as ground (VSS) or power supply (VDD), to provide additional electrical shielding effect. The structural integrity of the sealing ring 101 is crucial to ensure the long-term reliability and yield of the chip, so it must be fully protected during manufacturing and scribing processes;

[0029] A passivation layer 103 covers at least a portion of the chip area and extends towards the scribe lane 102. The passivation layer 103 is typically the final protective dielectric layer on top of the uppermost metal interconnect layer after the semiconductor wafer fabrication process is substantially completed. Its core function is to provide comprehensive physical and chemical protection for the underlying active device area, metal wiring structures, and edge structures including the seal ring 101. Physically, it can resist mechanical damages such as scratches from subsequent processes (e.g., wafer backgrinding, scribing, packaging). Chemically and environmentally, it serves as an effective barrier to prevent moisture, oxygen, alkali metal ions (especially sodium ions), and other corrosive contaminants from penetrating into the chip interior, thus ensuring long-term electrical stability and reliability of the devices. The passivation layer 103 must also have good electrical insulation properties to isolate different metal pads or wiring lines. Common passivation layer 103 materials include inorganic dielectric materials such as silicon dioxide (SiO2), silicon nitride (SiN or Si3N4), silicon oxynitride (SiON), or multilayer stack structures of these materials (e.g., a bottom SiO2 layer for better interface properties and stress matching, and a top SiN layer for excellent densification and barrier properties). In some applications, polymeric materials such as polyimide (Polyimide) can also be used as part of the passivation layer 103, sometimes as an additional stress buffer layer. The passivation layer 103 is typically formed by chemical vapor deposition (CVD) methods, especially plasma-enhanced chemical vapor deposition (PECVD) techniques, at relatively low temperatures to avoid damaging the underlying metal layers. The thickness of the passivation layer 103 depends on the specific process and application requirements, typically in the order of hundreds of nanometers to several micrometers. Finally, windows need to be selectively etched in the passivation layer 103 to expose the underlying metal pads (Bond Pad) for subsequent electrical connections (e.g., wire bonding or bumping). The passivation layer slot 104 in the present invention is a specific structure formed in this critical passivation layer 103 material; and

[0030] A passivation layer slot 104 formed in the passivation layer 103, the passivation layer slot 104 is located between the seal ring 101 and the scribe lane 102; wherein a first safety distance is defined between the passivation layer slot 104 and the seal ring 101, and a second safety distance is defined between the passivation layer slot 104 and the scribe lane 102. This design introduces a physical isolation or buffer structure (passivation layer slot 104) between the stress source (scribe lane 102) and the protected structure (seal ring 101), aiming to interrupt or weaken the propagation path of the scribe stress.

[0031] In some embodiments, the width of the passivation layer slot 104 can be selected in the range of 0.1 to 10 microns (e.g. 2 microns) depending on the specific chip design, the type of dicing process (e.g. mechanical dicing, laser dicing) and the stress level that can be tolerated. This range provides flexibility in design, allowing the designer to optimize the balance between stress relief and layout area according to the actual situation. Smaller width can be more space-efficient, while larger width can provide stronger stress buffering capability.

[0032] In some embodiments, both the first safety distance and the second safety distance can be set to 0.1 to 10 microns (e.g. 2 microns). The purpose of setting these two safety distances is to protect important structures on both sides of the slot. Specifically, the first safety distance (between the passivation layer slot 104 and the sealing ring 101) ensures that the etching process of the slot and the lateral stress during dicing do not damage the sealing ring 101, ensuring its structural integrity; the second safety distance (between the passivation layer slot 104 and the dicing lane 102) protects the structures (such as test keys) that may exist in the dicing lane 102 region itself, and ensures that the dicing tool can accurately cut along the predetermined path, while avoiding interference of the slot structure with the dicing process.

[0033] In other embodiments, the first safety distance and the second safety distance can also be adjusted in the range of 0.1 to 10 microns depending on the process accuracy, layout density requirements and reliability requirements. Again, this range provides flexibility in design, allowing more detailed optimization of the layout under the premise of ensuring safety.

[0034] Through the above structural design, especially the definition of the first safety distance and the second safety distance, it is ensured that the formation process of the passivation layer slot 104 and its existence will not affect the structural integrity of the sealing ring 101 and the structures in the dicing lane 102 region.

[0035] In some embodiments, the structures in the dicing lane 102 region can specifically include test keys. Test keys are key structures used to detect electrical parameters during the manufacturing process and must maintain their integrity and normal function. The safety distance design of the present application fully considers the protection of these sensitive structures adjacent to the dicing lane 102.

[0036] The semiconductor structure proposed by the present application is not limited to a specific wafer size and has good universality. In some embodiments, the semiconductor structure can be located on an 8-inch semiconductor wafer or a 12-inch semiconductor wafer, covering the current mainstream wafer size specifications.

[0037] In summary, the core advantage of the structure of the present application lies in the application of the slotting 104 of the passivation layer, which plays a key role in releasing or buffering the dicing stress when the dicing path 102 is diced, like setting a buffer area on the stress propagation path, thereby effectively preventing the stress wave from being transmitted from the dicing path 102 to the inside of the chip in large quantities, especially protecting the sealing ring 101 which is adjacent to the dicing path 102 and is crucial to the reliability of the chip. Compared with the structure in which the traditional dicing path 102 is directly connected to the sealing ring 101, the present application can significantly reduce or even avoid the common defects such as edge collapse and cracks at the edge of the chip caused by excessive dicing stress by adding such a simple slotting structure, thereby directly improving the yield of dicing. More importantly, it ensures the long-term structural stability and functional reliability of the chip in subsequent processes such as dicing and packaging and in terminal applications.

[0038] It should be noted that the diagrams provided in the embodiments only illustrate the basic concept of the present application in a schematic manner, and only show the components related to the present application in the diagrams, not the number, shape and size of the components when actually implemented. The actual implementation of each component may be arbitrarily changed in shape, number and proportion, and the layout pattern of the components may be more complex.

[0039] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical idea disclosed by the present application should be covered by the claims of the present application.

Claims

1. A structure for improving the reliability of wafer dicing, characterized by, The chip region and a scribe lane adjacent to the chip region; a seal ring located within the chip region and adjacent to the scribe lane; a passivation layer covering at least a portion of the chip region and extending towards the scribe lane; and a passivation layer slot formed in the passivation layer, the passivation layer slot being located between the seal ring and the scribe lane; wherein a first safety distance is defined between the passivation layer slot and the seal ring, and a second safety distance is defined between the passivation layer slot and the scribe lane. The width of the passivation layer slot is 0.1 to 10 microns. The width of the passivation layer slot is 2 microns.

2. The structure for improving wafer dicing reliability according to claim 1, wherein: The first safety distance and the second safety distance are each 0.1 microns to 10 microns.

3. The structure for improving wafer dicing reliability according to claim 1, wherein: The first safety distance and the second safety distance are each 2 microns.

4. The structure for improving wafer dicing reliability according to claim 1, wherein: The first safety distance and the second safety distance ensure that the formation of the passivation layer slot does not affect the structural integrity of the seal ring and the structures within the scribe lane region.

5. The structure for improving wafer dicing reliability according to claim 1, wherein: The structures within the scribe lane region include test keys.

6. The structure for improving wafer dicing reliability according to claim 1, wherein: The structures are located on an 8-inch semiconductor wafer or a 12-inch semiconductor wafer.

7. The structure for improving wafer dicing reliability according to claim 1, wherein: The passivation layer slot is used to release or buffer the scribe stress when scribing the scribe lane, so as to prevent the stress from being transmitted to the seal ring.

8. The structure for improving wafer dicing reliability according to claim 1, wherein: ​ 9. The structure for improving wafer dicing reliability according to claim 1, wherein: ​

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