Hardware overcurrent protection design circuit of motor controller

Abstract

The invention relates to the technical field of electronic circuit design, and discloses a hardware overcurrent protection design circuit of a motor controller, which comprises a driving signal input module comprising a three-phase independent half-bridge driving chip and a three-phase bridge arm N-channel MOS (Metal Oxide Semiconductor) tube, a current detection module consisting of a three-phase sampling branch, two N-channel MOS tubes connected in series in each phase and a sampling resistor, a sampling signal is amplified by the operational amplifier, the voltage comparison module comprises a first comparator and a second comparator, the logic control module comprises an AND gate and a seventh N-channel MOS tube, and the power supply control module comprises a P-channel MOS tube. According to the hardware overcurrent protection design circuit of the motor controller, the overcurrent protection value of the phase line load current is designed through hardware, and when the actual load reaches the threshold value, the hardware immediately responds to disconnect the power supply of the three-phase independent half-bridge driving chip of the controller, so that continuous output overload is avoided, and the reliability of the motor controller is improved. And overload or overvoltage damage of three-phase power bridge circuit components is caused.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuit design, in particular to a hardware overcurrent protection design circuit of a motor controller. BACKGROUND

[0002] A brushless direct current (BLDC) motor is a type of electric motor that uses brushless motor technology, also known as a brushless DC motor or permanent magnet synchronous motor. Compared with traditional DC motors, BLDC motors do not need to use carbon brushes and commutators to achieve current commutation, but use electronic commutators (also known as controllers) to control the direction and size of the current. BLDC motors have many advantages, including high efficiency, high power density, high speed range, low noise, and long service life, etc. They are widely used in many fields, such as automobiles, aerospace, home appliances, industrial automation, and robots, etc.

[0003] The existing BLDC or PMSM motor, when running, the software samples the phase line load current to determine whether it is overloaded, and then performs software signal shutdown output. The software processing time of this overload period is relatively long, and the three-phase power bridge circuit components are overloaded or damaged by overvoltage before the software can be turned off, which cannot meet the use requirements. Therefore, a hardware overcurrent protection design circuit of a motor controller is needed to solve the above problems. SUMMARY

[0004] (I) Technical problems solved

[0005] In view of the defects of the prior art, the present application provides a hardware overcurrent protection design circuit of a motor controller, which has the advantages of fast response speed, etc. The problem that the software processing time of the overload period is relatively long when the existing BLDC or PMSM motor is running is solved.

[0006] (II) Technical solutions

[0007] The technical solutions of the present application to solve the above technical problems are as follows: a hardware overcurrent protection design circuit of a motor controller, comprising:

[0008] A drive signal input module: including a three-phase independent half-bridge drive chip and a three-phase bridge arm N-channel MOS tube, the input end of the three-phase independent half-bridge drive chip is connected with the motor control output signal of the MCU, and the output end is connected with the gate of the three-phase bridge arm N-channel MOS tube;

[0009] A current detection module: composed of three-phase sampling branches, each phase includes two N-channel MOS tubes and a sampling resistor connected in series, and the sampling signal is amplified by an operational amplifier;

[0010] Voltage comparison module: including first comparator and second comparator, connect reference voltage VREF_H and VREF_L respectively;

[0011] Logic control module: including AND gate and seventh N channel MOS tube, for integrating comparator output and MCU enable signal;

[0012] Power supply control module: including P channel MOS tube, for controlling the VCC power supply of three-phase independent half-bridge driving chip;

[0013] Motor connection module: including VS1, VS2, VS3, connect the winding coil of motor respectively.

[0014] The beneficial effects of the application are:

[0015] The hardware overcurrent protection design circuit of the motor controller, through the hardware design of the phase line load current overcurrent protection value, when the actual load reaches this threshold, the hardware immediately responds to disconnect the power supply of the three-phase independent half-bridge driving chip of the controller, avoids continuous output overload, causes three-phase power bridge circuit components overload or overvoltage damage, has higher practicability and reliability, through reasonable selection and combination, can meet the overcurrent protection requirements of motor controller in different application scenarios.

[0016] On the basis of the above technical scheme, the application can also be improved as follows.

[0017] Further, in the voltage comparison module, VREF_H is set as a forward overcurrent protection threshold, and VREF_L is set as a reverse overcurrent protection threshold, wherein the first operational amplifier lifts the three-phase current signal by a 2.5V bias voltage, and the first comparator detects the forward overcurrent signal, and the second comparator detects the reverse overcurrent signal, forming a bidirectional current protection mechanism.

[0018] Further, in the voltage comparison module, the reference voltages VREF_H and VREF_L are obtained by setting resistance voltage division, for setting the overcurrent protection threshold.

[0019] Further, the logic control module further includes an eighth resistor, the source electrode of the seventh N channel MOS tube is connected to GND, and the drain electrode is connected to the gate electrode of the P channel MOS tube through the eighth resistor, for controlling the gate voltage of the P channel MOS tube, thereby controlling the conduction and cutoff thereof.

[0020] Further, in the power supply control module, the source electrode of the P channel MOS tube is connected to VCC, and the drain electrode is connected to the power supply pin VCC of the three-phase independent half-bridge driving chip, for controlling the power supply state of the three-phase independent half-bridge driving chip, realizing the cut-off of power supply in hardware. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 Structure design block diagram for the present application;

[0022] Figure 2 Signal transmission principle diagram for the first embodiment of the present application;

[0023] Figure 3 Signal transmission principle diagram for the second embodiment of the present application. DETAILED DESCRIPTION

[0024] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0025] In the present application

[0026] Embodiment one: by Figure 2 A hardware overcurrent protection design circuit of a motor controller is given, and the present application comprises a driving signal input module, a current detection module, a voltage comparison module, a logic control module, a power supply control module and a motor connection module. The driving signal input module comprises a three-phase independent half-bridge driving chip and three-phase bridge arm N-channel MOS tubes. The input ends HIN1, HIN2, HIN3, LIN1, LIN2 and LIN3 of the three-phase independent half-bridge driving chip are respectively connected to the motor control output signals of an MCU. The output ends HO1, HO2, HO3, LO1, LO2 and LO3 of the three-phase independent half-bridge driving chip are respectively connected to the gates of the HO1, HO2, HO3, LO1, LO2 and LO3 of the three-phase bridge arm N-channel MOS tubes.

[0027] The current detection module comprises a first N-channel MOS tube, a second N-channel MOS tube, a third N-channel MOS tube, a fourth N-channel MOS tube, a fifth N-channel MOS tube, a sixth N-channel MOS tube, an operational amplifier, a second capacitor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, sampling resistors: a fifth resistor, a sixth resistor, and a seventh resistor; the source of the first N-channel MOS tube is connected to the drain of the fourth N-channel MOS tube; the source of the fourth N-channel MOS tube is connected to the first pin of the fifth resistor; the second pin of the fifth resistor is connected to GND; the source of the second N-channel MOS tube is connected to the drain of the fifth N-channel MOS tube; the source of the fifth N-channel MOS tube is connected to the first pin of the sixth resistor; the second pin of the sixth resistor is connected to GND; the source of the third N-channel MOS tube is connected to the drain of the sixth N-channel MOS tube; the source of the sixth N-channel MOS tube is connected to the first pin of the seventh resistor; the second pin of the seventh resistor is connected to GND; the drain of the first N-channel MOS, the drain of the second N-channel MOS tube, and the drain of the third N-channel MOS tube are connected together to VBUS; the first pin of the second capacitor is connected to the first pin of the fifth resistor and the first pin of the thirteenth resistor; the second pin of the second capacitor is connected to GND and the first pin of the eleventh resistor; the second pin of the thirteenth resistor is connected to the second pin of the fourteenth resistor and the third pin positive input end of the operational amplifier; the first pin of the fourteenth resistor is connected to 2.5V; the second pin of the eleventh resistor is connected to the first pin of the twelfth resistor and the fourth pin negative input end of the operational amplifier; the second pin of the twelfth resistor is connected to the first pin of the third resistor and the first pin output end of the operational amplifier; the second pin of the operational amplifier is connected to 5V; and the fifth pin of the operational amplifier is connected to GND.

[0028] The sampling resistor is a milliohm alloy resistor, with a resistance tolerance of ≤±1% and a power rating of ≥2W.

[0029] The voltage comparison module includes a first comparator, a second comparator, a first resistor, a second resistor, a third resistor, a first capacitor, a third capacitor, a fifteenth resistor, a sixteenth resistor and a seventeenth resistor, the second pin of the twelfth resistor is connected with the first pin of the seventeenth resistor, the second pin of the third resistor is connected with the first pin of the first capacitor and the fourth pin negative input end of the first comparator, the second pin of the first capacitor is connected with GND, the third pin positive input end of the first comparator is connected with the first pin of the first resistor and the second pin of the second resistor, the first pin of the second resistor is connected with VREF_H, the second pin of the first resistor is connected with the first pin output end of the first comparator, the first pin output end of the second comparator and the first pin input end of the AND gate and the second pin of the fifteenth resistor, the second pin of the seventeenth resistor is connected with the first pin of the third capacitor and the third pin positive input end of the second comparator, the second pin of the third capacitor is connected with GND, the fourth pin negative input end of the second comparator is connected with the first pin of the fifteenth resistor and the second pin of the sixteenth resistor, the first pin of the sixteenth resistor is connected with VREF_L signal, the second pin of the second comparator is connected with GND, and the fifth pin of the second comparator is connected with 5V.

[0030] The logic control module and the power supply module include an AND gate, a seventh N-channel MOS tube, an eighth resistor, a ninth resistor and a P-channel MOS tube, the second pin input end of the AND gate is connected with the MCU_CONTROL signal, the power supply pin of the AND gate is connected with 5V, the negative pin of the AND gate is connected with GND, the output end pin of the AND gate is connected with the gate of the seventh N-channel MOS tube and the first pin of the tenth resistor, the second pin of the tenth resistor is connected with GND and the source of the seventh N-channel MOS tube, the drain of the seventh N-channel MOS tube is connected with the second pin of the eighth resistor, the first pin of the eighth resistor is connected with the second pin of the ninth resistor and the gate of the P-channel MOS tube, the source of the P-channel MOS tube is connected with the first pin of the ninth resistor and the VCC signal, and the drain of the P-channel MOS is connected with the power supply pin VCC of the three-phase independent half-bridge drive.

[0031] The motor connection module includes VS1, VS2 and VS3, which are connected with the winding coils of the motor respectively.

[0032] In the voltage comparison module, VREF_H is set as a positive overcurrent protection threshold value, and VREF_L is set as a reverse overcurrent protection threshold value, wherein the first operational amplifier lifts the three-phase current signal through a 2.5V bias voltage, and then the first comparator detects the positive overcurrent signal and the second comparator detects the reverse overcurrent signal, thereby forming a bidirectional current protection mechanism.

[0033] In the voltage comparison module, the reference voltages VREF_H and VREF_L are obtained by setting resistance voltage division, and are used for setting the overcurrent protection threshold value.

[0034] The source of the seventh N-channel MOS is connected to GND, and the drain is connected to the gate of the P-channel MOS through the eighth resistor, which is used to control the gate voltage of the P-channel MOS, thereby controlling its conduction and cutoff.

[0035] The source of the P-channel MOS is connected to VCC, and the drain is connected to the power supply pin VCC of the three-phase independent half-bridge driving chip, which is used to control the power supply state of the three-phase independent half-bridge driving chip, realizing the hardware cut-off power supply.

[0036] Component model name: AND gate: SN74LVC1G08DBVR, first comparator: TLV3201AIDBVR, second comparator: TLV3201AIDBVR, operational amplifier: LMV321RIYLT, three-phase independent half-bridge driving chip: LN4317SR-G, first, second, third, fourth, fifth, and sixth N-channel MOS: JMSL040SAGQ-13, seventh N-channel MOS: CJ2310, P-channel MOS: DMPH6250S-7, power resistor: BVS-M-R0005-1.0.

[0037] 1. When the motor is running under load, the current of each phase winding of the motor is connected to GND through the power resistor to form a loop, at this time the load current of each phase can be sampled and calculated through the power resistor to obtain the actual phase line load current, when the current flows through the fifth resistor and is amplified by the operational amplifier, it is compared with the set overcurrent protection voltage value VREF_H / VREF_L, when the output value of the operational amplifier is greater than VREF_H or less than VREF_L, the comparator outputs low to the AND gate, and according to the logic characteristics of the AND gate, the AND gate outputs low to the gate of the seventh N-channel MOS at this time, the second pin of the AND gate inputs the MCU_CONTROL signal which can be controlled by the MCU, and the normal working state is high, when the gate of the seventh N-channel MOS is low, the MOS is in the closed state, because the gate level of the N-channel MOS does not reach the threshold value of the open MOS, so the drain of the seventh N-channel MOS cannot be connected to the source GND, so the eighth resistor and the ninth resistor cannot divide the gate signal of the P-channel MOS, so the gate voltage of the P-channel MOS is equal to the source voltage, due to the characteristics of the P-channel MOS, the P-channel MOS is in the closed state, so it cannot supply power to the power supply pin of the three-phase independent half-bridge driving chip, at this time the hardware cut-off power supply is completed;

[0038] 2. When the output value of the operational amplifier is less than VREF_H and greater than VREF_L, the comparator outputs a high level to the AND gate, and according to the logic characteristics of the AND gate, the AND gate outputs a high level to the gate of the seventh N-channel MOS transistor, and the MCU can control the MCU_CONTROL signal input to the second pin of the AND gate, and the normal working state is high level, when the gate of the seventh N-channel MOS transistor is high level, the MOS is in an open state, and since the gate level of the N-channel MOS transistor reaches the threshold value of the open MOS, the drain and source of the seventh N-channel MOS are connected to GND, so the eighth resistor and the ninth resistor divide the voltage signal at the gate of the P-channel MOS transistor, and the gate voltage of the P-channel MOS transistor is lower than the source voltage, and since the P-channel MOS transistor has the characteristics, the P-channel MOS transistor is in an open state, and thus the power supply pin of the three-phase independent half-bridge driving chip is normally powered.

[0039] Specifically, referring to the accompanying drawings Figure 1 The load current sampling signal of the BLDC motor during operation is output through a first signal operational amplifier, compared with a set protection threshold value to output a second signal, output a logic level through a third signal of an AND gate chip, and the logic level controls the opening or closing of the MOS transistor to realize the power supply control of the driving chip.

[0040] Embodiment two: the Figure 3The negative terminal of the Load is connected to the first terminal pin of the fifth resistor, the first pin of the second capacitor is connected to the first pin of the fifth resistor and the second pin of the Load and the first pin of the sixth resistor, the second pin of the second capacitor is connected to GND and the second pin of the fifth resistor and the first pin of the seventh resistor, the second pin of the sixth resistor is connected to the second pin of the fourth resistor and the positive input terminal of the third pin of the operational amplifier, the first pin of the fourth resistor is connected to 2.5V, the second pin of the seventh resistor is connected to the first pin of the eleventh resistor and the negative input terminal of the fourth pin of the operational amplifier, the second pin of the eleventh resistor is connected to the output terminal of the first pin of the operational amplifier and the first pin of the third resistor, the second pin of the operational amplifier is connected to 5V, the fifth pin of the operational amplifier is connected to GND, the second pin of the third resistor is connected to the first pin of the first capacitor and the negative input terminal of the fourth pin of the first comparator, the second pin of the first capacitor is connected to GND, the positive input terminal of the third pin of the first comparator is connected to the first pin of the first resistor and the second pin of the second resistor, the first pin of the second resistor is connected to VREF, the second pin of the first resistor is connected to the output terminal of the first pin of the first comparator and the input terminal of the first pin of the AND gate, the input terminal of the second pin of the AND gate is connected to the MCU_CONTROL signal, the power supply pin of the AND gate is connected to 5V, the negative pin of the AND gate is connected to GND, the output terminal pin of the AND gate is connected to the gate of the first N-channel MOS and the first pin of the tenth resistor, the second pin of the tenth resistor is connected to GND and the source of the first N-channel MOS, the drain of the first N-channel MOS is connected to the second pin of the eighth resistor, the first pin of the eighth resistor is connected to the second pin of the ninth resistor and the gate of the P-channel MOS, the source of the P-channel MOS is connected to the first pin of the ninth resistor and the VBAT+ signal, the drain of the first P-channel MOS is connected to the positive terminal of the Load.

[0041] Component model name: AND gate: SN74LVC1G08DBVR, first comparator: TLV3201AIDBVR, operational amplifier: LMV321RIYLT, first N-channel MOS: CJ2310, P-channel MOS: SP010P09GHTO; power resistor: BVS-M-R0005-1.0.

[0042] 1. Load current is connected to GND through power resistance to form a loop, at this time the actual load current can be calculated by sampling the load current through the power resistance, when the current flows through the fifth resistance and is amplified by the operational amplifier, it is compared with the set overcurrent protection voltage value VREF, when the output value of the operational amplifier is greater than VREF, the comparator outputs low level to the AND gate, and according to the logic characteristics of the AND gate, the AND gate outputs low level to the gate of the seventh N-channel MOS at this time, the MCU_CONTROL signal input to the second pin of the AND gate can be controlled by the MCU, and the normal working state is high level, when the gate of the first N-channel MOS is low level, the MOS is in the closed state, because the gate level of the N-channel MOS does not reach the threshold value of the open MOS, the drain of the seventh N-channel MOS cannot be connected to the source GND, so the eighth resistance and the ninth resistance cannot divide the gate signal of the P-channel MOS, and the gate voltage value of the P-channel MOS is equal to the source voltage value, because of the characteristics of the P-channel MOS, the P-channel MOS is in the closed state, so it cannot supply power to the rear-end load, at this time the hardware power supply is cut off;

[0043] 2. When the output value of the operational amplifier is less than VREF, the comparator outputs high level to the AND gate, and according to the logic characteristics of the AND gate, the AND gate outputs high level to the gate of the first N-channel MOS at this time, the MCU_CONTROL signal input to the second pin of the AND gate can be controlled by the MCU, and the normal working state is high level, when the gate of the first N-channel MOS is high level, the MOS is in the open state, because the gate level of the N-channel MOS reaches the threshold value of the open MOS, the drain of the seventh N-channel MOS is connected to the source GND, so the eighth resistance and the ninth resistance divide the gate signal of the P-channel MOS, so the gate voltage value of the P-channel MOS is lower than the source voltage value, because of the characteristics of the P-channel MOS, the P-channel MOS is in the open state, so it can normally supply power to the rear-end load.

[0044] The multi-phase current sampling and double threshold protection design of embodiment one provides higher flexibility and reliability for complex motor control systems, and the simplified design of embodiment two provides a feasible solution for low-cost and low-complexity application scenarios, both of which have good compatibility and scalability in technology, and can be combined or optimized according to actual needs, the hardware overcurrent protection circuit structure of the present application is simple, low in cost and easy to integrate into existing motor control systems, its fast response characteristics can effectively protect the motor from overcurrent damage, and has high practical value.

[0045] It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting; it is not intended to exclude myriad other embodiments of the present application that other inventors can develop based on the same general inventive concepts embodied by the described embodiments. That is, although the present application is described in terms of particular embodiments and implementations, it is to be understood that the terminology used is for the purpose of descriptive clarity and that it is intended to be limited only by the words recited in the appended claims. The scope of the present application shall be limited only by the claims.

[0046] While the embodiments of the application have been shown and described herein, it is to be understood that the application is not limited to these embodiments. Rather, numerous modifications are possible without departing from the spirit and scope of the present application as delineated by the claims and their equivalents.

Claims

1. A hardware overcurrent protection design circuit of a motor controller, characterized in that, The application relates to a three-phase independent half-bridge drive chip and a three-phase bridge arm N-channel MOS tube, an input end of the three-phase independent half-bridge drive chip is connected with a motor control output signal of an MCU, and an output end of the three-phase independent half-bridge drive chip is connected with a gate of the three-phase bridge arm N-channel MOS tube. The current detection module is composed of three-phase sampling branches, each phase comprises two N-channel MOS tubes and a sampling resistor in series connection, and a sampling signal is amplified through an operational amplifier. The voltage comparison module comprises a first comparator and a second comparator, and is connected with reference voltages VREF_H and VREF_L respectively. The logic control module comprises an AND gate and a seventh N-channel MOS tube, and is used for integrating the comparator output and the MCU enabling signal. The power supply control module comprises a P-channel MOS tube, and is used for controlling the VCC power supply on-off of the three-phase independent half-bridge drive chip. The motor connection module comprises VS1, VS2 and VS3, and is connected with winding coils of a motor respectively. In the voltage comparison module, the VREF_H is set as a forward overcurrent protection threshold value, the VREF_L is set as a reverse overcurrent protection threshold value, a first operational amplifier lifts the three-phase current signal through a 2.5V bias voltage, the first comparator detects the forward overcurrent signal, the second comparator detects the reverse overcurrent signal, and a bidirectional current protection mechanism is formed.

2. The hardware overcurrent protection design circuit of a motor controller according to claim 1, wherein: In the voltage comparison module, the reference voltages VREF_H and VREF_L are obtained through resistance voltage division, and are used for setting the overcurrent protection threshold value.

3. The hardware overcurrent protection design circuit of a motor controller according to claim 1, wherein: The logic control module further comprises an eighth resistor, a source of the seventh N-channel MOS tube is connected with GND, a drain is connected with a gate of the P-channel MOS tube through the eighth resistor, and the gate voltage of the P-channel MOS tube is controlled, so that the conduction and cut-off of the P-channel MOS tube are controlled.

4. The hardware overcurrent protection design circuit of a motor controller according to claim 1, wherein: In the power supply control module, a source of the P-channel MOS tube is connected with VCC, a drain is connected with a power supply pin VCC of the three-phase independent half-bridge drive chip, the power supply state of the three-phase independent half-bridge drive chip is controlled, and the power supply is cut off on the hardware.

5. The hardware overcurrent protection design circuit of a motor controller according to claim 1, wherein: ​

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