Differential signal generator and method of calibrating the same

Abstract

The application provides a differential signal generator and a calibration method thereof. The differential signal generator comprises a control processing unit configured to obtain a common-mode bias voltage setting value and a differential-mode bias voltage setting value, determine a common-mode bias voltage code word according to a first mapping relationship, determine a differential-mode bias voltage code word according to a second mapping relationship, and output the common-mode bias voltage code word and the differential-mode bias voltage code word to an output amplification unit; a waveform generation unit connected to the output amplification unit and configured to provide a positive-end alternating-current signal and a negative-end alternating-current signal for the output amplification unit under the control of the control processing unit; and the output amplification unit configured to obtain a positive-end bias intermediate voltage and a negative-end bias intermediate voltage according to the common-mode bias voltage code word and the differential-mode bias voltage code word, and output a positive-end output signal and a negative-end output signal, thereby solving the problem that the current differential signal generator cannot adjust common-mode bias output voltage and differential-mode bias output voltage.

Description

Technical Field

[0001] This application relates to the field of instrument technology, and in particular to a differential signal generator and its calibration method. Background Technology

[0002] A signal generator is an electronic measuring instrument that can generate various frequencies, amplitudes, and waveforms according to user needs. For example, it can be used to generate clock signals, modulation signals, or simulate various test signals. It is often used to evaluate whether electronic circuits and equipment are operating normally or to optimize their performance. Differential signals are an important signal output form of signal generators. Differential signals have advantages such as strong anti-interference ability, effective suppression of electromagnetic interference, improved signal-to-noise ratio, and suppression of even harmonics. They are widely used in the electronics field. For example, common LVDS, LVPECL, and USB 3.0 are all differential signal forms. The input and output terminals of high-speed ADCs (analog-to-digital converters), DACs (digital-to-analog converters), and VGAs basically use differential ports.

[0003] When a signal generator outputs a differential signal and is DC coupled to the device under test (DUT), the signal generator typically needs to provide an output bias voltage signal to meet the requirements of the DUT. For example, high-performance ADCs usually require the input common-mode voltage to be within a certain range; otherwise, the ADC will experience a reduction in the dynamic range of the input signal and severe distortion. When the input and output biases of a fully differential op-amp deviate from the center of the power rail, harmonic and bandwidth performance may deteriorate. For the output port of a differential signal generator, the bias voltage includes both the output common-mode bias and the output differential-mode bias. Different DUTs have different requirements for the bias voltage. Therefore, the common-mode bias output voltage and differential-mode bias output voltage of the differential signal generator need to be adjustable within a certain range and meet certain accuracy requirements, which is precisely the capability currently lacking in differential signal generators. Summary of the Invention

[0004] In view of the above problems, this application provides a differential signal generator and its calibration method, which has the function of adjustable common-mode bias output voltage and differential-mode bias output voltage.

[0005] Firstly, the following technical solution is provided through an embodiment:

[0006] A differential signal generator includes a control processing unit and a waveform generation unit and an output amplification unit connected to the control processing unit. The control processing unit acquires a common-mode bias voltage setpoint and a differential-mode bias voltage setpoint, determines a common-mode bias voltage codeword according to a first mapping relationship, determines a differential-mode bias voltage codeword according to a second mapping relationship, and outputs the common-mode bias voltage codeword and the differential-mode bias voltage codeword to the output amplification unit. The first mapping relationship is the mapping relationship between the common-mode bias voltage codeword and the common-mode bias voltage setpoint and the differential-mode bias voltage setpoint; the second mapping relationship is the mapping relationship between the common-mode bias voltage codeword and the common-mode bias voltage setpoint and the differential-mode bias voltage setpoint. The mapping relationship between the differential bias voltage codeword and the common bias voltage setting value and the differential bias voltage setting value; the waveform generation unit is connected to the output amplification unit and is used to provide the output amplification unit with a positive terminal AC signal and a negative terminal AC signal under the control of the control processing unit; the output amplification unit is used to obtain the positive terminal bias intermediate voltage and the negative terminal bias intermediate voltage according to the common mode bias voltage codeword and the differential mode bias voltage codeword, and output a positive terminal output signal according to the positive terminal AC signal and the positive terminal bias intermediate voltage, and output a negative terminal output signal according to the negative terminal AC signal and the negative terminal bias intermediate voltage.

[0007] In some embodiments, the first mapping relationship is: DAC _code_cm = a 1 ×V cm_set + a 2 ×V diff_set + a 3 The second mapping relationship is: DAC _code_diff = b 1 ×V cm_set + b 2 ×V diff_set + b 3 ;in, DAC _code_cm The common-mode bias voltage codeword, DAC _code_diff The differential bias voltage codeword, V cm_set The common-mode bias voltage setting value, V diff_set The differential bias voltage setting value, a 1 , a2 and a 3 For coefficient terms, b 1 , b 2 and b 3 This is the coefficient term.

[0008] In some embodiments, the output amplification unit includes a first radio frequency (RF) amplifier, a second RF amplifier, and a bias voltage circuit. The input terminal of the first RF amplifier is connected to the output terminal of the waveform generation unit, and is used to amplify and output the positive AC signal. The input terminal of the second RF amplifier is connected to the output terminal of the waveform generation unit, and is used to amplify and output the negative AC signal. The input terminal of the bias voltage circuit is connected to the control processing unit to obtain the common-mode bias voltage codeword and the differential-mode bias voltage codeword. The bias voltage circuit includes a first bias output terminal and a second bias output terminal. The first bias output terminal is connected to the output terminal of the first RF amplifier, and the second bias output terminal is connected to the output terminal of the second RF amplifier. The bias voltage circuit is used to determine the positive bias intermediate voltage and the negative bias intermediate voltage based on the common-mode bias voltage codeword and the differential-mode bias voltage codeword. The positive bias intermediate voltage is superimposed on the output terminal of the first RF amplifier through the first bias output terminal to obtain the positive output signal, and the negative bias intermediate voltage is superimposed on the output terminal of the second RF amplifier through the second bias output terminal to obtain the negative output signal.

[0009] In some embodiments, the bias voltage circuit includes a bias digital-to-analog converter (DAC), a first operational amplifier (op-amp) sub-circuit, and a second operational amplifier (op-amp) sub-circuit; the input terminal of the bias DAC is connected to the output terminal of the control processing unit, and the output terminal of the bias DAC is connected to the input terminals of the first and second op-amp sub-circuits, respectively; the bias DAC is used to convert the common-mode bias voltage codeword into a common-mode bias analog voltage and output it to the first and second op-amp sub-circuits, and to convert the differential-mode bias voltage codeword into a differential-mode bias analog voltage and output it to the first op-amp sub-circuit; The output terminal of the first operational amplifier sub-circuit is connected to the input terminal of the second operational amplifier sub-circuit and the first bias output terminal. The first operational amplifier sub-circuit is used to obtain the positive terminal bias intermediate voltage based on the common-mode bias analog voltage and the differential-mode bias analog voltage, and output the positive terminal bias intermediate voltage to the first bias output terminal and the second operational amplifier sub-circuit. The output terminal of the second operational amplifier sub-circuit is connected to the second bias output terminal, and is used to obtain the negative terminal bias intermediate voltage based on the positive terminal bias intermediate voltage and the common-mode bias analog voltage, and output the negative terminal bias intermediate voltage to the second bias output terminal.

[0010] In some embodiments, the first operational amplifier sub-circuit includes a first resistor, a second resistor, a third resistor, and a first operational amplifier; the non-inverting input of the first operational amplifier is connected to the output of the bias digital-to-analog converter through the first resistor to obtain the differential bias analog voltage, the inverting input of the first operational amplifier is connected to the output of the bias digital-to-analog converter through the second resistor to obtain the common-mode bias analog voltage, the output of the first operational amplifier is connected to the first bias output and the input of the second operational amplifier sub-circuit, for obtaining the positive bias intermediate voltage based on the common-mode bias analog voltage and the differential bias analog voltage, and outputting the positive bias intermediate voltage to the first bias output and the second operational amplifier sub-circuit; one end of the third resistor is connected to the inverting input of the first operational amplifier, and the other end is connected to the output of the first operational amplifier.

[0011] In some embodiments, the second operational amplifier sub-circuit includes a fourth resistor, a fifth resistor, a sixth resistor, and a second operational amplifier; the non-inverting input terminal of the second operational amplifier is grounded, and the inverting input terminal of the second operational amplifier is connected to the output terminal of the bias digital-to-analog converter through the fourth resistor and to the output terminal of the first operational amplifier sub-circuit through the fifth resistor, so as to obtain the superposition voltage of the common-mode bias analog voltage and the positive terminal bias intermediate voltage; the output terminal of the second operational amplifier is connected to the second bias output terminal, for outputting the negative terminal bias intermediate voltage according to the superposition voltage; one end of the sixth resistor is connected to the inverting input terminal of the second operational amplifier, and the other end is connected to the output terminal of the second operational amplifier.

[0012] In some embodiments, the output amplification unit further includes a first 2-to-1 switch, a second 2-to-1 switch, a first output stage amplifier, a third 2-to-1 switch, a fourth 2-to-1 switch, a second output stage amplifier, a positive output terminal, and a negative output terminal; the input terminal of the first 2-to-1 switch is connected to the output terminal of the first RF amplifier, the first output terminal of the first 2-to-1 switch is connected to the input terminal of the first output stage amplifier, the output terminal of the first output stage amplifier is connected to the first input terminal of the second 2-to-1 switch, the second output terminal of the first 2-to-1 switch is connected to the second input terminal of the second 2-to-1 switch, and the output terminal of the second 2-to-1 switch is connected to the positive output terminal; the first 2-to-1 switch and the second 2-to-1 switch are configured to directly connect the output terminal of the first RF amplifier and the positive output terminal. Alternatively, the output terminal of the first RF amplifier, the first output stage amplifier, and the positive output terminal can be connected; the input terminal of the third 2-to-1 switch is connected to the output terminal of the second RF amplifier, the first output terminal of the third 2-to-1 switch is connected to the input terminal of the second output stage amplifier, the output terminal of the second output stage amplifier is connected to the first input terminal of the fourth 2-to-1 switch, the second output terminal of the third 2-to-1 switch is connected to the second input terminal of the fourth 2-to-1 switch, and the output terminal of the fourth 2-to-1 switch is connected to the output terminal of the output amplification unit; the third 2-to-1 switch and the fourth 2-to-1 switch are configured to directly connect the output terminal of the second RF amplifier and the negative output terminal, or connect the output terminal of the second RF amplifier, the second output stage amplifier, and the negative output terminal.

[0013] In some embodiments, the differential signal generator further includes an output attenuation unit, and the waveform generation unit is connected to the output amplification unit through the output attenuation unit; the output attenuation unit is used to filter the positive terminal AC signal and the negative terminal AC signal, and attenuate the positive terminal AC signal to the input signal range of the first RF amplifier before outputting it to the first RF amplifier, and attenuate the negative terminal AC signal to the input signal range of the second RF amplifier before outputting it to the second RF amplifier.

[0014] In some embodiments, the differential signal generator further includes an output control unit, which includes a fifth 2-to-1 switch, a sixth 2-to-1 switch, a P differential output terminal, and an N differential output terminal. The output amplification unit includes a positive output terminal and a negative output terminal. The P differential output terminal is connected to the positive output terminal through the fifth 2-to-1 switch and is used to output or disable the output of the positive terminal signal under the control of the fifth 2-to-1 switch. The N differential output terminal is connected to the negative output terminal through the sixth 2-to-1 switch and is used to output or disable the output of the negative terminal signal under the control of the sixth 2-to-1 switch.

[0015] Secondly, based on the same inventive concept, the following technical solution is provided through an embodiment:

[0016] A calibration method is applied to a differential signal generator provided in a first aspect embodiment. The calibration method includes: acquiring at least three sets of common-mode bias voltage codewords and differential-mode bias voltage codewords; sequentially inputting each set of common-mode bias voltage codewords and differential-mode bias voltage codewords into an output amplification unit via a control processing unit; measuring the positive terminal bias output voltage and the negative terminal bias output voltage output by the output amplification unit; calculating the common-mode bias output voltage and the differential-mode bias output voltage based on the positive terminal bias output voltage and the negative terminal bias output voltage; using the common-mode bias output voltage as a common-mode bias voltage setpoint and the differential-mode bias output voltage as a differential-mode bias voltage setpoint; and calibrating a first mapping relationship and a second mapping relationship based on the at least three sets of common-mode bias voltage codewords, differential-mode bias voltage codewords, common-mode bias voltage setpoints, and differential-mode bias voltage setpoints.

[0017] According to one of the technical solutions in the above embodiments, the following beneficial effects or advantages are achieved:

[0018] This application provides a differential signal generator that can receive user-set common-mode bias voltage and differential-mode bias voltage settings. It calculates common-mode bias voltage codewords and differential-mode bias voltage codewords using pre-prepared first and second mapping relationships. Then, it obtains the positive and negative terminal bias intermediate voltages based on these codewords. These are then superimposed onto the positive and negative AC signals, respectively, to generate a positive terminal output signal containing the common-mode bias output voltage and a negative terminal output signal containing the differential-mode bias output voltage. Therefore, the differential signal generator provided by this application supports user adjustment of the common-mode bias voltage and differential-mode bias voltage settings. By obtaining the corresponding common-mode bias voltage codewords and differential-mode bias voltage codewords through pre-prepared or calibrated first and second mapping relationships, it achieves the function of adjusting the positive and negative terminal bias intermediate voltages, thereby adjusting the common-mode and differential-mode bias output voltages and improving the output accuracy of the bias voltage.

[0019] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0020] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings; in the drawings…

[0021] Figure 1 A frame diagram of a differential signal generator according to an embodiment of this application is shown.

[0022] Figure 2 A detailed block diagram of a differential signal generator according to one embodiment of this application is shown.

[0023] Figure 3 A schematic diagram showing the structure and connection relationship of an output amplification unit according to an embodiment of this application is provided.

[0024] Figure 4 A schematic diagram of the bias voltage circuit according to one embodiment of this application is shown.

[0025] Figure 5 A schematic diagram of the circuit structure of a bias voltage circuit according to an embodiment of this application is shown.

[0026] Figure 6A schematic flowchart of a calibration method according to an embodiment of this application is shown.

[0027] Explanation of reference numerals in the attached figures: 10, Control processing unit; 20, Waveform generation unit; 21, Waveform digital-to-analog converter; 30, Output amplification unit; 31, First RF amplifier; 32, Second RF amplifier; 33, Bias voltage circuit; Op, First bias output terminal; On, Second bias output terminal; Ro_P, First output resistor; Ro_N, Second output resistor; 331, Bias digital-to-analog converter; 332, First operational amplifier sub-circuit; 333, Second operational amplifier sub-circuit; R1, First resistor; R2, Second resistor; R3, Third resistor; U1, First operational amplifier; R4, Fourth resistor; R5, Fifth resistor; R6, Sixth resistor. 34. First 2-to-1 switch; 35. First output stage amplifier; 36. Second 2-to-1 switch; 37. Third 2-to-1 switch; 38. Second output stage amplifier; 39. Fourth 2-to-1 switch; O1. Positive output terminal; O2. Negative output terminal; 40. Output attenuation unit; 41. First filter; 42. Second filter; 43. First attenuator; 44. Second attenuator; 50. Output control unit; 51. Fifth 2-to-1 switch; 52. Sixth 2-to-1 switch; 53. P differential output terminal; 54. N differential output terminal; 60. Input unit; 70. Display unit; 80. Storage unit. Detailed Implementation

[0028] The embodiments of this application will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of this application. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0029] The accompanying drawings illustrate various structural schematics according to embodiments of this application. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0030] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms "an," "a," or "the," etc., do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms "comprising," "including," etc., mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. The terms "connected," "linked," etc., are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Above," "below," "left," "right," etc., are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0031] The following is a comparison of some Chinese terms and their corresponding English abbreviations involved in the embodiments of this application.

[0032] V p_out The positive terminal (P terminal) outputs a signal.

[0033] V n_out The negative terminal (N terminal) outputs the signal.

[0034] V cm_out Common-mode bias output voltage.

[0035] V diff_out Differential bias output voltage.

[0036] V cm_set Common-mode bias voltage setting value.

[0037] V diff_set Differential bias voltage setting value.

[0038] V cm_dac Common-mode bias analog voltage.

[0039] V diff_dac Differential bias analog voltage.

[0040] DAC _code_cm Common-mode bias voltage codeword.

[0041] DAC _code_diff Differential bias voltage codeword.

[0042] V p_ac Positive terminal (P terminal) AC signal.

[0043] V n_ac The negative terminal (N terminal) is the AC signal.

[0044] V p_offset0 The positive terminal is biased with the intermediate voltage.

[0045] V n_offset0 The negative terminal is biased with the intermediate voltage.

[0046] V p_offset_out The positive terminal (P terminal) biases the output voltage.

[0047] V n_offset_out The negative terminal (N terminal) biases the output voltage.

[0048] Most existing signal generators are single-port outputs, which cannot meet the testing requirements of differential signal interfaces. The few signal generators on the market with differential output terminals typically have an output bias voltage accuracy of around ±(2%×set value+10mV), failing to achieve the ±(1%×set value+2mV) accuracy level of single-port signal sources. Furthermore, existing differential signal generators usually only focus on the common-mode bias output voltage in their output bias function, neglecting the differential-mode bias output voltage adjustment function, or the adjustable range is relatively small, only around ±20mV, which cannot meet the needs of practical applications.

[0049] For example, one current approach is to provide a method for implementing a differential signal generator. However, this differential signal generator has a relatively simple function and a bandwidth of only about 10 MHz. More importantly, it does not mention the adjustment function of the output common-mode bias and output differential-mode bias, which cannot meet most of the testing needs in the field of electronic measurement.

[0050] To address the aforementioned issues, this application provides a structure or implementation method for a differential signal generator with independently adjustable common-mode and differential-mode output bias voltages. It also analyzes the potential causes of low output bias accuracy in the differential signal generator and provides corresponding calibration schemes to improve the accuracy of the output bias voltage without increasing hardware costs.

[0051] Firstly, regarding the issue that the common-mode bias output voltage and differential-mode bias output voltage can be adjusted within a certain range, in one optional embodiment, please refer to... Figure 1 The provided differential signal generator includes a control processing unit 10, a waveform generation unit 20, and an output amplification unit 30 connected to the control processing unit 10; the control processing unit 10 is used to acquire the common-mode bias voltage setting value V. cm_set Sum and difference mode bias voltage setting value V diff_set And determine the common-mode bias voltage codeword DAC according to the first mapping relationship. _code_cm The differential bias voltage codeword DAC is determined based on the second mapping relationship. _code_diff DAC with common-mode bias voltage codeword_code_cm Sum and difference mode bias voltage codeword DAC _code_diff Output to output amplifier unit 30; the first mapping relationship is common-mode bias voltage codeword DAC _code_cm With common-mode bias voltage setting value V cm_set Differential bias voltage setting value V diff_set The mapping relationship between them, the second mapping relationship is the differential bias voltage codeword DAC _code_diff With common-mode bias voltage setting value V cm_set Differential bias voltage setting value V diff_set The mapping relationship between them; the waveform generation unit 20 is connected to the output amplification unit 30, and is used to provide the positive terminal AC signal V to the output amplification unit 30 under the control of the control processing unit 10. p_ac AC signal V at the negative terminal n_ac Output amplifier unit 30 is used for codeword DAC based on common-mode bias voltage. _code_cm Sum and difference mode bias voltage codeword DAC _code_diff The positive terminal biased intermediate voltage V is obtained p_offset0 and the negative terminal bias intermediate voltage V n_offset0 And according to the positive terminal AC signal V p_ac and the positive terminal bias intermediate voltage V p_offset0 The positive terminal outputs a signal, based on the negative terminal AC signal V. n_ac and the negative terminal bias intermediate voltage V n_offset0 Output signal at the negative terminal.

[0052] Specifically, the output signal of the differential signal generator can be divided into two parts. One part is the AC component provided by the waveform generation unit 20 and amplified by the output amplification unit 30, namely the positive terminal AC signal V. p_ac AC signal V at the negative terminal n_ac Secondly, the DC bias section provided by the output amplification unit 30, namely the positive terminal bias intermediate voltage V. p_offset0 and the negative terminal bias intermediate voltage V n_offset0 By biasing the positive terminal with an intermediate voltage V p_offset0 Superimposed on the positive terminal AC signal V p_ac The positive terminal output signal V is obtained p_out The negative terminal is biased with the intermediate voltage V. n_offset0 Superimposed on the negative terminal AC signal V n_ac Obtain the negative terminal output signal V n_out .

[0053] During the aforementioned signal output process, the control processing unit 10 is used, on the one hand, to configure and monitor other units, such as the waveform generation unit 20 and the output amplification unit 30, and on the other hand, to set the common-mode bias voltage V based on user input or other sources. cm_set Sum and difference mode bias voltage setting value Vcm_diff The common-mode bias voltage codeword (DAC) is converted into the corresponding digital code through the first and second mapping relationships, respectively. _code_cm Sum and difference mode bias voltage codeword DAC _code_diff These codewords are then provided to the output amplification unit 30.

[0054] The waveform generation unit 20, under the monitoring of the control and processing unit 10, generates differential signal waveforms. Its main responsibility is to generate wideband differential AC signals, specifically the positive terminal AC signal V. p_ac AC signal V at the negative terminal n_ac And output to output amplifier unit 30, positive terminal AC signal V p_ac AC signal V at the negative terminal n_ac These are a pair of strictly correlated core signals that jointly construct the differential AC signal. They correspond to the peak values ​​of the AC signal at the positive terminal (P terminal) and negative terminal (N terminal) of the differential signal, respectively, and possess the key characteristics of "equal amplitude and opposite phase." The V signal output by waveform generation unit 20... p_ac and V n_ac Normally, it only contains AC components and will not generate bias at the output, or in some cases it generates a fixed bias that can be eliminated through subsequent calibration steps.

[0055] Under the monitoring of the control processing unit 10, the output amplification unit 30 outputs the signal according to the input signal: positive terminal AC signal V. p_ac Common-mode bias voltage codeword DAC _code_cm Negative terminal AC signal V n_ac Sum and difference mode bias voltage codeword DAC _code_diff Output positive terminal output signal V p_out and negative terminal output signal V n_out The positive terminal output signal V can be used. p_out The DC bias portion is denoted as the positive terminal bias output voltage V. p_offset_out The negative terminal output signal V n_out The DC bias portion is denoted as the negative terminal bias output voltage V. n_offset_out .

[0056] The output amplification unit 30 may have a signal amplification function to increase the bandwidth of the output signal, for example, it may further amplify the AC signal V. p_ac and V n_ac Then bias the positive terminal with the intermediate voltage V. p_offset0 Superimposed on the amplified positive terminal AC signal V p_ac The initial positive terminal output signal V is obtained. p_out The negative terminal is biased with the intermediate voltage V. n_offset0 The AC signal V superimposed on the amplified negative terminal n_ac The initial negative terminal output signal V is obtained.n_out The output amplifier unit 30 can directly output V. p_out and V n_out Alternatively, it can be further amplified before output. Without considering further gain and zero-bias changes in the output signal caused by the output amplification unit 30, and with the output terminal of the differential signal generator either floating or connected to a high-resistance load, V p_offset_out With V p_offset0 Same, V n_offset_out With V n_offset0 Similarly, if we consider gain variation and zero bias variation, then V n_offset_out With V n_offset0 Different, V n_offset_out With V n_offset0 different.

[0057] Based on the DC bias component in the output signal: V p_offset_out and V n_offset_out The differential signal generator can output a common-mode bias output voltage V. cm_out Sum and difference mode bias output voltage V diff_out According to the definition of a differential signal, the common-mode bias output voltage V of the differential signal generator is... cm_out Sum and difference mode bias output voltage V diff_out The following formula should be satisfied:

[0058] V cm_out =(V p_offset_out +V n_offset_out ) / twenty one)

[0059] V diff_out =V p_offset_out –V n_offset_out (2).

[0060] Under ideal conditions or with accurate calibration, the common-mode bias output voltage V of the differential signal generator is... cm_out It should be consistent with the common-mode bias voltage setting value V set by the user or input. cm_set To maintain consistency, the differential bias output voltage V diff_out It should be consistent with the user-set or input differential bias voltage setting value V. diff_set To maintain consistency, the first mapping relationship, as a pre-determined mathematical transformation relationship stored in the control processing unit 10, can be regarded as both a common-mode bias voltage codeword DAC. _code_cm With common-mode bias voltage setting value V cm_set Differential bias voltage setting value V diff_set The mapping relationship between them can also be regarded as a common-mode bias voltage codeword DAC. _code_cm With common-mode bias output voltage V cm_out Differential bias output voltage V diff_outThe mapping relationship between the two is as follows; the second mapping relationship is similar.

[0061] The first and second mapping relationships can be constructed and adjusted during the calibration phase of the differential signal generator, using the user-input common-mode bias voltage setting V as much as possible. cm_set The common-mode bias output voltage V of the differential signal generator cm_out To maintain consistency, the differential bias voltage setting value V diff_set The differential bias output voltage V of the differential signal generator diff_out To maintain consistency and minimize the error between the two; it is understandable that the mathematical expressions corresponding to the first and second mapping relationships may have different forms depending on the application environment or requirements.

[0062] As can be seen, the differential signal generator provided in this application can receive the common-mode bias voltage setting value and the differential-mode bias voltage setting value set by the user. It calculates the common-mode bias voltage codeword and the differential-mode bias voltage codeword through a pre-prepared first mapping relationship and a second mapping relationship. Then, based on the codeword, it obtains the positive terminal bias intermediate voltage and the negative terminal bias intermediate voltage, respectively, and superimposes them onto the positive terminal AC signal and the negative terminal AC signal, thus generating a positive terminal output signal containing the common-mode bias output voltage and a negative terminal output signal containing the differential-mode bias output voltage. Therefore, the differential signal generator provided in this application can support users in obtaining the corresponding common-mode bias voltage codeword (DAC) by adjusting the common-mode bias voltage setting value and the differential-mode bias voltage setting value through a pre-prepared or calibrated first mapping relationship and a second mapping relationship. _code_cm Sum and difference mode bias voltage codeword DAC _code_diff This allows for adjustment of the positive terminal bias intermediate voltage V. p_offset0 and the negative terminal bias intermediate voltage V n_offset0 This enables the adjustment of common-mode bias output voltage and differential-mode bias output voltage, while also improving the output accuracy of the bias voltage. The first and second mapping relationships are also continuously adjusted according to different application scenarios and requirements to further improve the adjustment accuracy of the bias voltage.

[0063] It should be noted that the solution in this application focuses on the regulation of DC bias voltage. Therefore, the main consideration in the solution introduction is the impact of the structure and function of each unit on the DC bias section.

[0064] In some embodiments, the first mapping relationship can be a common-mode bias voltage codeword DAC. _code_cm With common-mode bias voltage setting value V cm_set Differential bias voltage setting value V diff_set The binary polynomial relationship between them, the second mapping relationship can be the differential bias voltage codeword DAC. _code_diff With common-mode bias voltage setting value Vdiff_set Differential bias voltage setting value V diff_set The bivariate polynomial relationship between the two variables, as verified by theoretical derivation and test results in the following text, shows that the first and second mapping relationships satisfying this mathematical relationship can effectively output a bias output voltage that matches the user-input bias voltage setting, and can also achieve a common-mode bias output voltage V. cm_out Differential bias voltage setting value V diff_set The two can be adjusted independently without affecting each other, and the requirement for consistency of the bias circuits at both ends of the differential signal generator is eliminated, further improving the adjustment accuracy.

[0065] In some embodiments, the common-mode bias voltage codeword DAC _code_cm Sum and difference mode bias voltage codeword DAC _code_diff The bivariate polynomial relation has the following form:

[0066] DAC _code_cm = a 1 ×V cm_set + a 2 ×V diff_set + a 3 (3)

[0067] DAC _code_diff = b 1 ×V cm_set + b 2 ×V diff_set + b 3 (4)

[0068] in, a 1 , a 2 and a 3 For coefficient terms, b 1 , b 2 and b 3 The coefficient term can be determined through pre-calibration.

[0069] Without needing to align the positive terminal AC signal V p_ac AC signal V at the negative terminal n_acIn some embodiments, when performing signal filtering and conditioning, the output of the waveform generation unit 20 can be directly connected to the input of the output amplification unit 30; if filtering and conditioning are required, please refer to [the relevant documentation] in some embodiments. Figure 2 The differential signal generator also includes an output attenuation unit 40, and the waveform generation unit 20 is connected to the output amplification unit 30 through the output attenuation unit 40; the output attenuation unit 40 is used to attenuate the differential AC signal: the positive terminal AC signal V p_ac AC signal V at the negative terminal n_ac Conditioning and filtering are performed, and the differential AC signal is attenuated to a suitable input signal range for the output amplification unit 30 to prevent it from entering saturation. In some embodiments, the output amplification unit 30 may include a multi-stage amplifier that can be switched by an electronic switch, and the output attenuation unit 40 can switch to different levels. In conjunction with the output amplification unit 30, a larger dynamic range of differential signals can be achieved.

[0070] In some embodiments, please refer to Figure 2 The differential signal generator also includes an output control unit 50, which is connected to the output terminal of the output amplifier unit 30 and is responsible for controlling the switching of the signal link and providing protection for the signal link.

[0071] In some embodiments, please refer to Figure 2 The differential signal generator also includes an input unit 60 and a display unit 70, which provide users with various input / output interactive functions under the monitoring of the control processing unit 10.

[0072] In some embodiments, please refer to Figure 2 The differential signal generator also includes a storage unit 80, which can be used to store various types of data and configuration information, and can work with the control processing unit 10 to complete the configuration and monitoring of other units.

[0073] All the above units can establish a communication connection with the control processing unit 10, and realize their respective functions under the configuration and monitoring of the control processing unit 10. Regarding the common-mode bias output and differential-mode bias output of the differential signal generator, the key points are mainly concentrated in two aspects: one is the common-mode bias voltage codeword DAC output by the control processing unit 10. _code_cm Sum and difference mode bias voltage codeword DAC _code_diff On the other hand, the output includes the positive terminal biased output voltage V. p_offset_out The positive terminal output signal V p_out and including the negative-terminal biased output voltage V n_offset_out The negative terminal output signal V n_out Output amplification unit 30 for output signals.

[0074] In some embodiments, the output amplification unit 30 includes a first radio frequency amplifier and a second radio frequency amplifier. The input terminal of the first radio frequency amplifier is connected to the output terminal of the waveform generation unit 20, and is used to amplify and output the positive AC signal V. p_ac The input of the second RF amplifier is connected to the output of the waveform generation unit 20, and is used to amplify and output the negative AC signal V. n_ac .

[0075] AC signal V at the positive terminal p_ac AC signal V at the negative terminal n_ac When conditioning and filtering are not required, the first and second RF amplifiers can be directly connected to the waveform generation unit 20, while the positive terminal AC signal V... p_ac AC signal V at the negative terminal n_ac For conditioning and filtering, please refer to [link / reference]. Figure 3 The input terminal of the first RF amplifier 31 can be connected to the output terminal of the waveform generation unit 20 through the output attenuation unit 40, and the input terminal of the second RF amplifier 32 can be connected to the output terminal of the waveform generation unit 20 through the output attenuation unit 40. The output attenuation unit 40 includes a first filter 41, a second filter 42, a first attenuator 43, and a second attenuator 44. The input terminal of the first filter 41 is connected to the waveform digital-to-analog converter 21 of the waveform generation unit 20, and its output terminal is connected to the input terminal of the first attenuator 43. The output terminal of the first attenuator 43 is connected to the input terminal of the first RF amplifier 31. The input terminal of the second filter 42 is connected to the waveform digital-to-analog converter 21, and its output terminal is connected to the input terminal of the second attenuator 44. The output terminal of the second attenuator 44 is connected to the input terminal of the second RF amplifier 32.

[0076] The waveform digital-to-analog converter 21, or waveform DAC for short, is mainly responsible for generating wideband differential AC signals: positive terminal AC signal V p_ac AC signal V at the negative terminal n_ac It has two output terminals, one of which is used to output the positive AC signal V. p_ac The positive terminal AC signal V is filtered out by the first filter 41. p_ac The image frequency and out-of-band spurious signals are then input to the first attenuator 43, and the other output is used to output the negative AC signal V. n_ac The negative terminal AC signal V is filtered out by the second filter 42. n_ac The image frequency and out-of-band spurious signals are input to the second attenuator 44. The first attenuator 43 and the second attenuator 44 are responsible for switching between different levels, that is, achieving a larger dynamic range, and attenuating the signal to a range suitable for the input signals of the first RF amplifier 31 and the second RF amplifier 32, preventing the RF amplifier from entering saturation. The first RF amplifier 31 and the second RF amplifier 32 are respectively used to amplify their respective differential AC signals and increase the signal bandwidth.

[0077] In some embodiments, please refer to Figure 3 The output amplification unit 30 also includes a bias voltage circuit 33, the input of which is connected to the control processing unit 10 to obtain a common-mode bias voltage codeword DAC. _code_cm Sum and difference mode bias voltage codeword DAC _code_diff The bias voltage circuit 33 includes a first bias output terminal and a second bias output terminal. Figure 3 (Not shown) The first bias output terminal is connected to the output terminal of the first RF amplifier 31, and the second bias output terminal is connected to the output terminal of the second RF amplifier 32; the bias voltage circuit 33 is used to determine the codeword DAC based on the common-mode bias voltage. _code_cm Sum and difference mode bias voltage codeword DAC _code_diff Determine the positive terminal bias intermediate voltage V p_offset0 and the negative terminal bias intermediate voltage V n_offset0 The positive terminal is biased by the intermediate voltage V through the first bias output terminal. p_offset0 The positive output signal V is obtained by superimposing it onto the output terminal of the first RF amplifier 31. p_out The negative terminal is biased to the intermediate voltage V through the second bias output terminal. n_offset0 The negative output signal V is obtained by superimposing it onto the output of the second RF amplifier 32. n_out .

[0078] For the differential signal generator in this embodiment, the DC bias portion of its output signal (including output common mode and output differential mode) is generated by the bias voltage circuit 33. The bias voltage circuit 33 processes the received common mode bias voltage codeword and differential mode bias voltage codeword through circuit operations and outputs: positive terminal bias intermediate voltage V. p_offset0 and the negative terminal bias intermediate voltage V n_offset0 The initial positive and negative output signals can be obtained by superimposing them onto the output terminals of the first RF amplifier 31 and the second RF amplifier 32, respectively.

[0079] The output amplification unit 30 can directly output the initial positive terminal output signal and the negative terminal output voltage as the final output signal, or it can further amplify them before outputting. To achieve selective amplification of the output signal, in some embodiments, please refer to... Figure 3The output amplification unit 30 further includes a first two-way switch 34, a second two-way switch 36, a first output stage amplifier 35, a third two-way switch 37, a fourth two-way switch 39, a second output stage amplifier 38, a positive output terminal O1, and a negative output terminal O2. The input terminal of the first two-way switch 34 is connected to the output terminal of the first RF amplifier 31, the first output terminal of the first two-way switch 34 is connected to the input terminal of the first output stage amplifier 35, the output terminal of the first output stage amplifier 35 is connected to the first input terminal of the second two-way switch 36, the second output terminal of the first two-way switch 34 is connected to the second input terminal of the second two-way switch 36, and the output terminal of the second two-way switch 36 is connected to the positive output terminal O1. The first two-way switch 34 and the second two-way switch 36 are configured to directly connect the output terminal of the first RF amplifier 31 and the positive output terminal O2. The output terminal O1 is connected to the output terminal of the first RF amplifier 31, the first output stage amplifier 35, and the positive output terminal O1; the input terminal of the third two-way switch 37 is connected to the output terminal of the second RF amplifier 32, the first output terminal of the third two-way switch 37 is connected to the input terminal of the second output stage amplifier 38, the output terminal of the second output stage amplifier 38 is connected to the first input terminal of the fourth two-way switch 39, the second output terminal of the third two-way switch 37 is connected to the second input terminal of the fourth two-way switch 39, and the output terminal of the fourth two-way switch 39 is connected to the output terminal of the output amplification unit 30; the third two-way switch 37 and the fourth two-way switch 39 are configured to directly connect the output terminal of the second RF amplifier 32 and the negative output terminal O2, or connect the output terminal of the second RF amplifier 32, the second output stage amplifier 38, and the negative output terminal O2.

[0080] Based on the circuit design described above, when the user desires a higher output signal power and bias voltage, and can tolerate some degradation in bandwidth, harmonics, and noise, the two-to-one switch can be switched to the output stage amplifier. This means the signal paths of the first two-to-one switch 34, the first output stage amplifier 35, and the second two-to-one switch 36 are activated to further amplify the positive terminal output signal V. p_out And to further amplify the negative terminal output signal V by connecting the third two-to-one switch 37, the second output stage amplifier 38, and the fourth two-to-one switch 39. n_out .

[0081] When users want the output signal to have better high-frequency performance, including higher bandwidth, lower noise floor and better harmonic performance, they can bypass the output stage amplifier. That is, the first two-to-one switch 34 and the second two-to-one switch 36 are directly turned on, and the third two-to-one switch 37 and the fourth two-to-one switch 39 are directly turned on, so that the output signal is no longer further amplified by the output stage amplifier.

[0082] Therefore, the output amplification unit 30 includes multiple stages (at least two stages) of amplifiers. The first stage amplifier is a radio frequency amplifier used to amplify AC signals, and the second stage amplifier is an output stage amplifier that can be used selectively. The output stage amplifier provides the function of further amplifying the output signal. The output stage amplifier is switched with a two-to-one switch to adapt to different needs and achieve a larger signal dynamic range.

[0083] In some embodiments, please refer to Figure 3 The output control unit 50 includes a fifth 2-to-1 switch 51, a sixth 2-to-1 switch 52, a P differential output terminal 53, and an N differential output terminal 54. The P differential output terminal 53 is connected to the positive output terminal O1 through the fifth 2-to-1 switch 51, and is used to output or disable the positive output signal V under the control of the fifth 2-to-1 switch 51. p_out The N differential output terminal 54 is connected to the negative output terminal O2 via a sixth 2-to-1 switch 52, and is used to output or disable the negative output signal V under the control of the sixth 2-to-1 switch 52. n_out .

[0084] Specifically, the fifth 2-to-1 switch 51 and the sixth 2-to-1 switch 52 of the output control unit 50 are responsible for turning the P differential output terminal 53 and the N differential output terminal 54 on and off, respectively, which controls the output state of the control signal. The reason for using 2-to-1 switches is that when no external signal output is needed, the 2-to-1 switches can be used to switch to the internal load of the differential signal generator to absorb power and avoid external radiation. The on / off control of the fifth 2-to-1 switch 51 and the sixth 2-to-1 switch 52 can be monitored and implemented by the control processing unit 10.

[0085] All of the above two-way switches can be electronic switches.

[0086] In some embodiments, the structure of the bias voltage circuit 33 is as follows: Figure 4 As shown, it includes a bias digital-to-analog converter 331, a first operational amplifier sub-circuit 332, and a second operational amplifier sub-circuit 333. The input terminal of the bias digital-to-analog converter 331 is connected to the output terminal of the control processing unit 10, and the output terminal of the bias digital-to-analog converter 331 is connected to the input terminals of the first operational amplifier sub-circuit 332 and the second operational amplifier sub-circuit 333, respectively. The bias digital-to-analog converter 331 is used to convert the common-mode bias voltage codeword into a DAC. _code_cm Convert to common-mode bias analog voltage V cm_dac The output is then fed to the first operational amplifier sub-circuit 332 and the second operational amplifier sub-circuit 333, and the differential bias voltage codeword DAC is also used. _code_diff Converted to differential bias analog voltage V diff_dacThe output is then sent to the first operational amplifier sub-circuit 332; the output terminal of the first operational amplifier sub-circuit 332 is connected to the input terminal of the second operational amplifier sub-circuit 333 and the first bias output terminal Op. The first operational amplifier sub-circuit 332 is used to adjust the common-mode bias analog voltage V. cm_dac Sum and difference mode bias analog voltage V diff_dac The positive terminal biased intermediate voltage V is obtained p_offset0 And bias the positive terminal with the intermediate voltage V p_offset0 The output is connected to the first bias output terminal Op and the second operational amplifier sub-circuit 333; the output terminal of the second operational amplifier sub-circuit 333 is connected to the second bias output terminal On, and is used to bias the intermediate voltage V based on the positive terminal. p_offset0 and common-mode bias analog voltage V cm_dac Obtain the negative terminal bias intermediate voltage V n_offset0 And bias the negative terminal with the intermediate voltage V n_offset0 Output to the second bias output terminal On.

[0087] Specifically, the CPU in the control processing unit 10 converts the codeword: DAC _code_cm and DAC _code_diff The output is sent to the bias voltage circuit 33, which is responsible for generating the bias intermediate voltage across the differential link: positive terminal bias intermediate voltage V. p_offset0 and the negative terminal bias intermediate voltage V n_offset0 The bias digital-to-analog converter 331, or bias DAC for short, is used to convert the input digital bias voltage codeword into a corresponding bias analog voltage and then output it to the corresponding operational amplifier sub-circuit; the common-mode bias analog voltage V cm_dac Sum and difference mode bias analog voltage V diff_dac After the first operational amplifier sub-circuit 332 and the second operational amplifier sub-circuit 333 are superimposed and driven to enhance the voltage, the positive terminal bias intermediate voltage V is obtained. p_offset0 and the negative terminal bias intermediate voltage V n_offset0 Then, the bias intermediate voltage is superimposed onto the corresponding RF amplifier through the corresponding bias output terminal to obtain the positive terminal output signal V. p_out and negative terminal output signal V n_out .

[0088] In some embodiments, please refer to Figure 3The first bias output terminal Op is connected to the output terminal of the first RF amplifier 31 through the first output resistor Ro_P, and the second bias output terminal On is connected to the output terminal of the second RF amplifier 32 through the second output resistor Ro_N. The first output resistor Ro_P and the second output resistor Ro_N are used to realize the single-ended output impedance and differential output impedance of the differential signal generator. The resistance values ​​of the first output resistor Ro_P and the second output resistor Ro_N are set according to actual needs. For example, both are 50±1 ohms to realize a single-ended output impedance of 50 ohms and a differential output impedance of 100 ohms.

[0089] The first operational amplifier sub-circuit 332 and the second operational amplifier sub-circuit 333, as a circuit structure for signal superposition and drive enhancement, can employ operational amplifier circuits; in some embodiments, please refer to... Figure 5 The first operational amplifier sub-circuit 332 includes a first resistor R1, a second resistor R2, a third resistor R3, and a first operational amplifier U1; the non-inverting input of the first operational amplifier U1 is connected to the output of the bias digital-to-analog converter 331 through the first resistor R1 to obtain the differential bias analog voltage V. diff_dac The inverting input of the first operational amplifier U1 is connected to the output of the bias digital-to-analog converter 331 through the second resistor R2 to obtain the common-mode bias analog voltage V. cm_dac The output of the first operational amplifier U1 is connected to the first bias output Op and the input of the second operational amplifier sub-circuit 333, and is used to adjust the common-mode bias analog voltage V. cm_dac Sum and difference mode bias analog voltage V diff_dac The positive terminal biased intermediate voltage V is obtained p_offset0 The positive terminal is biased by the intermediate voltage V p_offset0 The output is connected to the first bias output terminal Op and the second operational amplifier sub-circuit 333; one end of the third resistor R3 is connected to the inverting input terminal of the first operational amplifier U1, and the other end is connected to the output terminal of the first operational amplifier U1.

[0090] The first operational amplifier U1, together with the first resistor R1, the second resistor R2, and the third resistor R3, forms a mixing / conditioning circuit for differential and common-mode signals. The first operational amplifier U1 uses a "differential amplification + common-mode superposition" method to condition the common-mode bias analog voltage V. cm_dac Sum and difference mode bias analog voltage V diff_dac After weighted processing, the output positive terminal biased intermediate voltage V is obtained. p_offset0 .

[0091] In some embodiments, please refer to Figure 5The second operational amplifier sub-circuit 333 includes a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and a second operational amplifier U2. The non-inverting input of the second operational amplifier U2 is grounded, and the inverting input of the second operational amplifier U2 is connected to the output of the bias digital-to-analog converter 331 through the fourth resistor R4 and to the output of the first operational amplifier sub-circuit 332 through the fifth resistor R5 to obtain a common-mode bias analog voltage V. cm_dac With the positive terminal biased intermediate voltage V p_offset0 The superimposed voltage is used to output a negative bias intermediate voltage V based on the superimposed voltage. The output terminal of the second operational amplifier U2 is connected to the second bias output terminal On. n_offset0 One end of the sixth resistor R6 is connected to the inverting input of the second operational amplifier U2, and the other end is connected to the output of the second operational amplifier U2.

[0092] The second operational amplifier U2, in conjunction with the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6 (feedback resistor), provides common-mode bias to the analog voltage V. cm_dac The positive bias intermediate voltage V of the first operational amplifier sub-circuit 332 output. p_offset0 The superimposed signals are divided and amplified by feedback, where the common-mode bias analog voltage V cm_dac The output signal of the first operational amplifier U1 is: positive terminal biased by the intermediate voltage V, which is input to the inverting input terminal of the second operational amplifier U2 through the fourth resistor R4. p_offset0 The signal is input to the inverting input of the second operational amplifier U2 through the fifth resistor R5. The two signals are superimposed at the inverting input and together serve as the input signal for the second operational amplifier U2, participating in the subsequent feedback amplification process. The output is biased by an intermediate voltage V at the negative terminal. n_offset0 .

[0093] The above embodiments describe the hardware composition of a differential signal generator. In the following embodiments, we will use... Figure 3 and Figure 5 Taking a differential signal generator as an example, the complete process of bias voltage generation is introduced as follows.

[0094] 1) The user sets the common-mode bias voltage setting value V through the input unit 60 according to the expected common-mode and differential-mode output bias voltages. cm_set Sum and difference mode bias voltage setting value V diff_set .

[0095] 2) The control processing unit 10 transmits V via the processor CPU. cm_set and V diff_set Substituting the first and second mapping relationships obtained beforehand or after calibration, we obtain the corresponding common-mode bias voltage codeword DAC. _code_cm Sum and difference mode bias voltage codeword DAC _code_diffIt is then transmitted to the bias digital-to-analog converter 331 (bias DAC).

[0096] 3) The bias digital-to-analog converter 331 adjusts the input codeword: DAC _code_cm and DAC _code_diff This is converted into the corresponding common-mode bias analog voltage V. cm_dac Sum and difference mode bias analog voltage V diff_dac .

[0097] 4) Analog voltage V cm_dac and V diff_dac After being superimposed and driven by the first operational amplifier U1 and the second operational amplifier U2, a positive bias intermediate voltage V is generated. p_offset0 and the negative terminal bias intermediate voltage V n_offset0 The signals are superimposed on the outputs of the first RF amplifier 31 at the P terminal and the second RF amplifier 32 at the N terminal, respectively, to obtain the initial positive output signal V. p_out and negative terminal output signal V n_out .

[0098] 5) Due to insertion loss in the two-to-one switch and gain and zero bias in the output amplifier, changes in gain and zero bias will occur during the superposition of the voltage at the RF amplifier output. Ultimately, this change is reflected at the P differential output terminal 53 of the differential signal generator using V. p_offset_out This indicates the measured V p_out The positive terminal biased output voltage is used at the N differential output terminal 54 with V. n_offset_out This indicates the measured V n_out The negative terminal biased output voltage.

[0099] 6) According to V p_offset_out and V n_offset_out Define the common-mode bias output voltage V of the signal generator. cm_out Sum and difference mode bias output voltage V diff_out For details, see equations (1) and (2).

[0100] Through the circuit design of the differential signal generator described above, the user can set V cm_set and V diff_set The value is used to achieve the common-mode bias output voltage V of the differential signal generator. cm_out Sum and difference mode bias output voltage V diff_out The adjustment and control of the common-mode bias voltage and differential-mode bias voltage should, under ideal conditions, be consistent with the user setting, or within a certain accuracy range, i.e., V. cm_out =V cm_set V diff_out =V diff_set .

[0101] To achieve this, a quantitative relationship between the common-mode bias output voltage, the differential-mode bias output voltage, and the DAC codeword can be obtained through calibration, namely V cm_out and V diff_out With DAC _code_cm and DAC_ code_diff The mapping relationship between them, in V cm_out Replace with V cm_set After obtaining the first mapping relationship, V diff_out Replace with V diff_set The second mapping relationship is then obtained, and its calibration principle and calibration method are described in the second aspect embodiment.

[0102] The differential signal generator provided in the first aspect embodiment has the following advantages:

[0103] 1) It has the function of independently adjusting the common-mode bias output voltage and the differential-mode bias output voltage, so that they no longer affect each other, and at the same time improves the output accuracy of the bias voltage and enhances the user experience.

[0104] 2) Through the various components and the above-mentioned bias voltage generation process, a differential signal generator with a bandwidth of about 2.6GHz, a wide signal dynamic range, output bias voltage, and a single-ended output impedance of 50 ohms (the resistance values ​​of the first output resistor Ro_P and the second output resistor Ro_N) can be provided.

[0105] 3) It does not increase the cost and complexity of hardware design.

[0106] As described in the first aspect of the embodiment, the first mapping relationship and the second mapping relationship can be constructed and adjusted through calibration. However, current calibration methods for output bias voltage are commonly used for calibrating the bias output voltage of single-port output signal sources, and cannot be directly applied to differential signal generators. The main reason is that the two definitions of bias output voltage are inconsistent. The output bias of a differential signal generator includes both common-mode and differential-mode output levels, not just the bias output voltage of a single port. Secondly, there is a difference in gain between the two ends of the differential link, which will cause the same DC voltage to generate common-mode and differential-mode components after passing through the two ends of the differential link. The algorithm needs to be modified to address this issue. If this point is ignored, the calibrated common-mode bias output voltage and differential-mode bias output voltage will interfere with each other, reducing calibration accuracy and user experience.

[0107] Solving the above problems involves two aspects: firstly, constructing a reasonable first and second mapping relationship; and secondly, providing a corresponding calibration method. Therefore, in the second aspect, based on the same inventive concept, a calibration method is provided, applied to the differential signal generator provided in the first aspect embodiment. Please refer to [link to relevant documentation]. Figure 6The calibration method includes steps S601 to S603, as detailed below:

[0108] S601: Obtain at least three sets of common-mode bias voltage codewords and differential-mode bias voltage codewords.

[0109] S602: The control processing unit sequentially inputs each set of common-mode bias voltage codewords and differential-mode bias voltage codewords into the output amplification unit, measures the positive terminal bias output voltage and negative terminal bias output voltage of the output amplification unit, and calculates the common-mode bias output voltage and differential-mode bias output voltage based on the positive terminal bias output voltage and negative terminal bias output voltage.

[0110] S603: Using the common-mode bias output voltage as the common-mode bias voltage setting value and the differential-mode bias output voltage as the differential-mode bias voltage setting value, calibrate the first mapping relationship and the second mapping relationship based on at least three sets of common-mode bias voltage codewords, differential-mode bias voltage codewords, common-mode bias voltage setting values, and differential-mode bias voltage setting values.

[0111] In some embodiments, during calibration, the waveform output unit can be controlled to output a differential AC signal: V p_ac and V n_ac Zeroing the voltage to simplify the entire calibration process and facilitate the measurement of the positive bias output voltage V p_offset_out and negative terminal biased output voltage V n_offset_out .

[0112] The calibration principle of the above scheme is as follows.

[0113] When the bias digital-to-analog converter 331 operates in the linear region, the following relationship exists between the bias analog voltage and the bias voltage codeword:

[0114] V cm_dac = k1 x DAC _code_cm + d1 (5)

[0115] V diff_dac = k1 x DAC _code_diff + d1 (6)

[0116] In the above formula, k1 represents the gain relationship between the input codeword and the output voltage of the bias DAC, and d1 represents the zero bias of the bias DAC.

[0117] When the first operational amplifier U1 and the second operational amplifier U2 are operating in the linear region, the output of the bias voltage circuit 33 satisfies:

[0118] V p_offset0 =k5 x V cm_dac + k6 x V diff_dac (7)

[0119] V n_offset0 = k7 x V cm_dac + k8 x V diff_dac (8)

[0120] Where k5 and k6, k7 and k8 represent the coefficients of the first operational amplifier sub-circuit 332 at the positive terminal (P) and the second operational amplifier sub-circuit 333 at the negative terminal (N), respectively. Figure 5 The resistance values ​​of R2 to R6 in the equation are determined by the following relationship.

[0121] k 5 =- R3 / R2 (9)

[0122] k 6 =( R3 + R2 ) / R2 (10)

[0123] k 7 =- R3 / R2× (- R6 / R5 )– R6 / R4 (11)

[0124] k 8 =(( R3 + R2 ) / R2 ) × (- R6 / R5 (12)

[0125] The resistance values ​​of R1~R6 are set according to actual needs. Based on the definitions of common-mode bias output voltage and mode bias output voltage, when setting the resistance values ​​of R1~R6, k5=k7, k 6= -k8 is sufficient.

[0126] When other components, such as the output stage amplifier and the 2-to-1 switch, are all operating in the linear region, the relationship between the bias output voltage and the bias intermediate voltage satisfies:

[0127] V p_offset_out = k3 x V p_offset0 +d3 (13)

[0128] V n_offset_out = k4 x V n_offset0 + d4 (14)

[0129] k3 and d3 represent the intermediate voltage V of the positive terminal bias, respectively. p_offset0 The gain variation coefficient and zero bias variation coefficient generated during the process of reaching the P differential output terminal 53 (P port) of the differential signal generator; similarly, k4 and d4 represent the negative terminal bias intermediate voltage V, respectively. p_offset0 The gain variation coefficient and zero bias variation coefficient generated during the process of reaching the N differential output terminal 54 (N port) of the differential signal generator.

[0130] In some embodiments, according to the product design, the resistance values ​​of the first resistor R1 to the sixth resistor R6 are respectively: R1=R2=R3=R5=R6=10kΩ, R4=5kΩ. Therefore, we can derive k5=k7=-1, k6=2, k8=-2, and equations (7) and (8) are:

[0131] V p_offset0 = -V cm_dac +2 ×V diff_dac (15)

[0132] V n_offset0 = -V cm_dac -2 ×V diff_dac (16).

[0133] For the sake of simplicity, the following calculations will be performed based on equations (15) and (16).

[0134] Further calculations of equations (13) and (14) yield:

[0135] V p_offset_out = k3 x V p_offset0 + d3

[0136] = (-k1 x k3) x DAC _code_cm +(2 x k1 x k3) x DAC _code_diff +(k3 x d1 + d3) (17)

[0137] V n_offset_out = k4 x Vn_offset0 + d4

[0138] = (-k1 x k4) x DAC _code_cm -(2 x k1 x k4) x DAC _code_diff +(-3 x k4 x d1 + d4) (18).

[0139] Substituting equations (17) and (18) into equations (1) and (2), we get:

[0140] V cm_out =( V p_offset_out + V n_offset_out ) / 2

[0141] = ((-k1) x (k3 + k4) x DAC _code_cm + 2 x k1 x (k3 - k4) x DAC _code_diff ) / 2 + (d3 + d4 + k3 x d1 - 3 x k4 x d1) / 2

[0142] = A1 x DAC _code_cm + A2 x DAC _code_diff + A3 (19)

[0143] V diff_out = V p_offset_out -V n_offset_out

[0144] = ((-k1) x (k3 - k4) x DAC _code_cm + 2 x k1 x (k3 + k4) x DAC _code_diff ) / 1 + (d3 - d4 + k3 x d1 + 3 x k4 x d1) / 1

[0145] = B1 x DAC _code_cm + B2 x DAC _code_diff + B3 (20)

[0146] in:

[0147] A1 = (-k1) x (k3 + k4) / 2

[0148] A2 = k1 x (k3 - k4)

[0149] A3 = (d3 + d4 + k3 x d1 - 3 x k4 x d1) / 2

[0150] B1 = (-k1) x (k3 - k4)

[0151] B2 = 2 x k1 x (k3 + k4)

[0152] B3 = d3 - d4 + k3 x d1 + 3 x k4 x d1 .

[0153] Ideally, the output resistors, 2-to-1 electronic switches, and output stage amplifiers used on both the positive (P) and negative (N) terminals are identical. The insertion losses of the electronic switches are all the same, and the gains of the output stage amplifiers are identical, meaning k3 = k4. Substituting these values ​​into the equation, we get A2 = B1 = 0, which means:

[0154] V cm_out = A1 x DAC _code_cm +A3 (twenty one)

[0155] V diff_out = B2 x DAC _code_diff +B3 (twenty two).

[0156] That is, under ideal conditions, the common-mode bias output voltage V of the differential signal generator cm_out Only common-mode bias voltage codeword DAC _code_cm The differential bias output voltage V exhibits a linear relationship. diff_out Only differential bias voltage codeword DAC _code_diff They exhibit a linear relationship and are independent of each other.

[0157] However, in reality, differences between the devices at both ends of a differential link are unavoidable. For example, Figure 3 The 50-ohm first output resistor Ro_P and second output resistor Ro_N typically have large packages due to their high power consumption, and they also need to meet high-frequency performance requirements. Resistors that meet these requirements usually have low accuracy; for example, the accuracy of 50-ohm RF resistors provided by a certain company on the market is usually only ±2% or even ±5%. In addition, there will be differences in the insertion loss of the two-to-one electronic switch and the gain of the output stage amplifier; therefore, k3≠k4, and thus A2≠0, B1≠0; therefore, the following two equations are more consistent with the actual circuit model.

[0158] V cm_out = A1 x DAC _code_cm + A2 x DAC _code_diff +A3 (twenty three)

[0159] Vdiff_out = B1 x DAC _code_cm + B2 x DAC _code_diff +B3 (twenty four).

[0160] This means that when the link gains at the P and N terminals are inconsistent, the common-mode bias voltage codeword DAC is set. _code_cm This will generate a portion of differential-mode voltage at the output; the set differential-mode bias voltage codeword DAC _code_diff This will generate a portion of common-mode voltage at the output. If this is ignored, and calibration is performed based on equations (21) and (22), it is very likely that the output common-mode bias and output differential-mode bias will interfere with each other, for example, when adjusting V. cm_set At that time, not only was it impossible to achieve V cm_out ≈V cm_set It can also lead to V diff_out It is also changing, meaning that the output common mode and output differential mode cannot be adjusted independently.

[0161] Since A1, A2, A3, B1, B2, and B3 are all constants, equations (23) and (24) can be transformed by a simple linear transformation to obtain:

[0162] DAC _code_cm =a 1 ×V cm_out +a 2 ×V diff_out +a 3 (25)

[0163] DAC _code_diff =b 1 ×V cm_out +b 2 ×V diff_out +b 3 (26).

[0164] in a 1 、a 2 、a 3 、b 1 、b 2 、b 3These are unknown constants, and the calibration process is the process of solving for these unknown constants; after calibration, the user sets the common-mode bias voltage setting value V through the UI of the input unit 60. cm_set Sum and difference mode bias voltage setting value V diff_set The CPU of the control processing unit 10 will V cm_set Substituting V into equations (25) and (26) cm_out V diff_set Substituting V into equations (25) and (26) diff_out That is, the common-mode bias voltage codeword DAC is calculated through the first mapping relationship shown in equation (3). _code_cm The differential bias voltage codeword DAC is calculated using the second mapping relationship shown in equation (4). _code_diff The bias digital-to-analog converter 331, which transmits the voltage to the bias voltage circuit 33, can generate the expected common-mode bias output voltage V after processing by the bias voltage circuit 33. cm_out Sum and difference mode bias output voltage V diff_out .

[0165] As discussed above regarding the calibration principle, the purpose of calibration is to obtain the mapping relationship between the DAC codeword and the output common-mode and output differential-mode biases, i.e., the DAC... _code_cm With V cm_out V diff_out The polynomial relationship between them, DAC _code_diff With V cm_out V diff_out The polynomial relationship between them is obtained by solving equations (25) and (26). After solving the constant terms in equations (25) and (26), the first mapping relationship and the second mapping relationship are obtained simultaneously.

[0166] The equipment required for calibration includes a multimeter and a computer. Set the output of waveform generation unit 20 to zero, so the multimeter can be used to directly measure the bias voltage V at the differential output terminals (i.e., P and N terminals). p_offset_out and V n_offset_out The computer is used to calculate the corresponding common-mode bias output voltage V. cm_out Sum and difference mode bias output voltage V diff_out It also controls the signal source and multimeter to achieve automated calibration.

[0167] For polynomial relations of the form (25) and (26), solve for the constant term. a 1 、a 2 、a 3 、b 1 、b 2、b 3 At least three sets of data are required, therefore the calibration steps are as follows.

[0168] 1) Set the signal source to be tested, and set the first set of bias voltage DAC codewords: DAC _code_cm1 and DAC _code_diff1 The bias output voltage V at the P differential output terminal 53 was measured using a multimeter. p_offset_out1 The bias output voltage V of the N differential output terminal 54 n_offset_out1 Based on this, the common-mode bias output voltage V is calculated. cm_out1 Sum and difference mode bias output voltage V diff_out1 The first set of test data (DAC) was obtained. _code_cm1 DAC _code_diff1 V cm_out1 , and V diff_out1 ).

[0169] 2) Set the signal source to be tested, and set the second set of bias voltage DAC codewords: DAC _code_cm2 and DAC _code_diff2 Repeat step 1) to obtain the second set of test data (DAC). _code_cm2 DAC _code_diff2 V cm_out2 , and V diff_out2 ).

[0170] 3) Set the signal source to be tested, and set the third set of bias voltage DAC codewords: DAC _code_cm3 and DAC _code_diff3 Repeat step 1) to obtain the third set of test data (DAC). _code_cm3 DAC _code_diff3 V cm_out3 , and V diff_out3 ).

[0171] 4) Substitute the above three sets of test data into equations (25) and (26) to solve. a 1 ~a 3 ,b 1 ~b 3 Simultaneously, we obtain equation (3) corresponding to the first mapping relationship and equation (4) corresponding to the second mapping relationship.

[0172] 5) Save the function expression after calibration.

[0173] The calibration process is now complete. Following the steps outlined above, the V mentioned earlier can be achieved. cm_set ≈V cm_out V diff_set ≈V diff_outThat is, the set value of the bias voltage is basically the same as the actual output value. Therefore, the control processing unit 10 only needs to adjust the bias voltage according to the user-set V. cm_set and V diff_set The corresponding DAC is calculated using the first and second mapping relationships. _code_cm and DAC _code_diff This will generate the expected output common-mode bias and output differential-mode bias.

[0174] The test was performed using a calibrated differential signal generator, by setting multiple different V... cm_set and V diff_set Measure the output voltage V at the link output port. p_out and V n_out Considering that the AC component can be set to zero during measurement, therefore V p_out and V n_out This actually corresponds to the DC bias output voltage: V p_offset_out and V n_offset_out Based on this, the common-mode bias output voltage V is calculated. cm_out Sum and difference mode bias output voltage V diff_out Then, based on the deviation between the set value and the actual value, the accuracy of the bias output voltage is obtained.

[0175] Table 1: Test data after calibration.

[0176] Test No. V cm_set / mV]]> V diff_set / mV]]> V p_out / mV]]> V n_out / mV]]> V cm_out / mV]]> V diff_out / mV]]> 1 2000 0 2000 2000 2000 0 2 1000 0 999.97 999.99 999.98 -0.02 3 100 0 100 100 100 0 4 10 0 10.01 10 10.005 0.01 5 0 0 0.00619 0.00070864 0.00344932 0.00548136 6 -10 0 -9.99 -10 -9.995 0.01 7 -100 0 -99.99 -100 -99.995 0.01 8 -1000 0 -999.96 -999.98 -999.97 0.02 9 -2000 0 -2000 -2000 -2000 0 10 0 2000 1000 -1000 0 2000 11 0 1000 500 -500 0 1000 12 0 100 50.01 -50 0.005 100.01 13 0 10 5.01 -5 0.005 10.01 15 0 -10 -4.99 5 0.005 -9.99 16 0 -100 -49.99 50 0.005 -99.99 17 0 -1000 -499.99 500 0.005 -999.99 18 0 -2000 -999.99 1000 0.005 -1999.99

[0177] As shown in Table 1, the differential signal generator and calibration method provided in this application can improve the accuracy of the common-mode bias output voltage and the differential-mode bias output voltage to ±(1%×set value+3mV); at the same time, it enables users to adjust the common-mode bias voltage setting value V cm_set At that time, the differential bias output voltage V diff_out Basically unchanged; adjusting the differential bias voltage setting value V diff_set At that time, the common-mode bias output voltage V cm_out The basic structure remains unchanged, meaning that the common-mode bias output voltage V is achieved. cm_out Sum and difference mode bias output voltage V diff_out Each can be adjusted independently without affecting the others.

[0178] In summary, the solution provided by this application through one or more embodiments has the following advantages:

[0179] The differential signal generator and corresponding calibration method provided in this application fully verify that due to the link gain difference between the two ends of the differential link, the DAC... _code_cm and V cm_out V diff_out Both exhibit a linear relationship, DAC _code_diff and Vcm_out V diff_out The results show a linear relationship and explain why current differential signal generators have low output bias voltage accuracy, as well as the possible reasons why "adjusting the common-mode voltage will cause changes in the output differential-mode voltage, and adjusting the differential-mode voltage will cause changes in the output common-mode voltage, affecting the user experience." A differential signal generator that can solve this problem and a calibration method suitable for the output bias of differential signal generators are proposed.

[0180] The differential signal generator and corresponding calibration method provided in this application, under the premise of fully considering the differences at both ends of the differential link, construct a polynomial relationship between the common-mode bias voltage codeword obtained according to the user settings and the common-mode bias output voltage and the differential-mode bias output voltage, and the polynomial relationship between the differential-mode bias voltage codeword and the common-mode bias output voltage and the differential-mode bias output voltage, so as to realize the independent adjustment of the output common-mode voltage and the output differential-mode voltage without affecting each other, and improve the adjustment accuracy.

[0181] The calibration method for the differential signal generator provided in this application has the advantage of being easy to implement. It eliminates the requirement for high consistency of the bias circuits at both ends of the differential circuit, such as the electronic switches of the P and N links and the output stage amplifier. It also reduces the requirements for devices and the difficulty of hardware design. Under this premise, the accuracy of the final output bias voltage can reach about ±(1%+3mV), which is significantly better than the existing product specifications on the market: ±(2%+10mV).

[0182] From the user's perspective, the differential signal generator provided in this application allows for independent adjustment of the output common-mode bias and output differential-mode bias, preventing them from affecting each other, and improving accuracy, thereby enhancing the user experience.

[0183] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0184] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A differential signal generator, characterized in that, It includes a control processing unit, a waveform generation unit, and an output amplification unit connected to the control processing unit; The control processing unit is used to acquire the common-mode bias voltage setting value and the differential-mode bias voltage setting value, determine the common-mode bias voltage codeword according to the first mapping relationship, determine the differential-mode bias voltage codeword according to the second mapping relationship, and output the common-mode bias voltage codeword and the differential-mode bias voltage codeword to the output amplification unit. The first mapping relationship is the mapping relationship between the common-mode bias voltage codeword and the common-mode bias voltage setting value and the differential-mode bias voltage setting value; the second mapping relationship is the mapping relationship between the differential-mode bias voltage codeword and the common-mode bias voltage setting value and the differential-mode bias voltage setting value. The waveform generation unit is connected to the output amplification unit and is used to provide positive AC signal and negative AC signal to the output amplification unit under the control of the control processing unit. The output amplification unit is used to obtain the positive terminal bias intermediate voltage and the negative terminal bias intermediate voltage according to the common-mode bias voltage codeword and the differential-mode bias voltage codeword, and output the positive terminal output signal according to the positive terminal AC signal and the positive terminal bias intermediate voltage, and output the negative terminal output signal according to the negative terminal AC signal and the negative terminal bias intermediate voltage.

2. The differential signal generator as described in claim 1, characterized in that, The first mapping relationship is: DAC _code_cm = a 1 ×V cm_set + a 2 ×V diff_set + a 3 ； The second mapping relationship is: DAC _code_diff = b 1 ×V cm_set + b 2 ×V diff_set + b 3 ； in, DAC _code_cm The common-mode bias voltage codeword, DAC _code_diff The differential bias voltage codeword, V cm_set The common-mode bias voltage setting value, V diff_set The differential bias voltage setting value, a 1 , a 2 and a 3 For coefficient terms, b 1 , b 2 and b 3 This is the coefficient term.

3. The differential signal generator as described in claim 1, characterized in that, The output amplification unit includes a first radio frequency amplifier, a second radio frequency amplifier, and a bias voltage circuit. The input terminal of the first radio frequency amplifier is connected to the output terminal of the waveform generation unit, and is used to amplify and output the positive AC signal. The input terminal of the second radio frequency amplifier is connected to the output terminal of the waveform generation unit, and is used to amplify and output the negative AC signal. The input terminal of the bias voltage circuit is connected to the control processing unit to obtain the common-mode bias voltage codeword and the differential-mode bias voltage codeword. The bias voltage circuit includes a first bias output terminal and a second bias output terminal. The first bias output terminal is connected to the output terminal of the first RF amplifier, and the second bias output terminal is connected to the output terminal of the second RF amplifier. The bias voltage circuit is used to determine the positive terminal bias intermediate voltage and the negative terminal bias intermediate voltage according to the common-mode bias voltage codeword and the differential-mode bias voltage codeword. The positive terminal bias intermediate voltage is superimposed on the output terminal of the first RF amplifier through the first bias output terminal to obtain the positive terminal output signal, and the negative terminal bias intermediate voltage is superimposed on the output terminal of the second RF amplifier through the second bias output terminal to obtain the negative terminal output signal.

4. The differential signal generator as described in claim 3, characterized in that, The bias voltage circuit includes a bias digital-to-analog converter, a first operational amplifier sub-circuit, and a second operational amplifier sub-circuit. The input terminal of the bias digital-to-analog converter is connected to the output terminal of the control processing unit, and the output terminal of the bias digital-to-analog converter is connected to the input terminals of the first operational amplifier sub-circuit and the second operational amplifier sub-circuit, respectively. The bias digital-to-analog converter is used to convert the common-mode bias voltage codeword into a common-mode bias analog voltage and output it to the first operational amplifier sub-circuit and the second operational amplifier sub-circuit, and to convert the differential-mode bias voltage codeword into a differential-mode bias analog voltage and output it to the first operational amplifier sub-circuit. The output terminal of the first operational amplifier sub-circuit is connected to the input terminal of the second operational amplifier sub-circuit and the first bias output terminal. The first operational amplifier sub-circuit is used to obtain the positive terminal bias intermediate voltage based on the common-mode bias analog voltage and the differential-mode bias analog voltage, and output the positive terminal bias intermediate voltage to the first bias output terminal and the second operational amplifier sub-circuit. The output terminal of the second operational amplifier sub-circuit is connected to the second bias output terminal, and is used to obtain the negative bias intermediate voltage based on the positive bias intermediate voltage and the common-mode bias analog voltage, and output the negative bias intermediate voltage to the second bias output terminal.

5. The differential signal generator as described in claim 4, characterized in that, The first operational amplifier sub-circuit includes a first resistor, a second resistor, a third resistor, and a first operational amplifier; The non-inverting input of the first operational amplifier is connected to the output of the bias digital-to-analog converter through the first resistor to obtain the differential bias analog voltage. The inverting input of the first operational amplifier is connected to the output of the bias digital-to-analog converter through the second resistor to obtain the common-mode bias analog voltage. The output of the first operational amplifier is connected to the first bias output and the input of the second operational amplifier sub-circuit. This is used to obtain the positive bias intermediate voltage based on the common-mode bias analog voltage and the differential bias analog voltage, and output the positive bias intermediate voltage to the first bias output and the second operational amplifier sub-circuit. One end of the third resistor is connected to the inverting input terminal of the first operational amplifier, and the other end is connected to the output terminal of the first operational amplifier.

6. The differential signal generator as described in claim 4, characterized in that, The second operational amplifier sub-circuit includes a fourth resistor, a fifth resistor, a sixth resistor, and a second operational amplifier; The non-inverting input of the second operational amplifier is grounded, and the inverting input of the second operational amplifier is connected to the output of the bias digital-to-analog converter through the fourth resistor and to the output of the first operational amplifier sub-circuit through the fifth resistor, so as to obtain the superposition voltage of the common-mode bias analog voltage and the positive terminal bias intermediate voltage. The output of the second operational amplifier is connected to the second bias output, and is used to output the negative terminal bias intermediate voltage according to the superposition voltage. One end of the sixth resistor is connected to the inverting input terminal of the second operational amplifier, and the other end is connected to the output terminal of the second operational amplifier.

7. The differential signal generator as described in claim 3, characterized in that, The output amplification unit further includes a first two-to-one switch, a second two-to-one switch, a first output stage amplifier, a third two-to-one switch, a fourth two-to-one switch, a second output stage amplifier, a positive output terminal, and a negative output terminal; The input terminal of the first two-way switch is connected to the output terminal of the first RF amplifier, the first output terminal of the first two-way switch is connected to the input terminal of the first output stage amplifier, the output terminal of the first output stage amplifier is connected to the first input terminal of the second two-way switch, the second output terminal of the first two-way switch is connected to the second input terminal of the second two-way switch, and the output terminal of the second two-way switch is connected to the positive output terminal; the first two-way switch and the second two-way switch are configured to directly connect the output terminal of the first RF amplifier and the positive output terminal, or connect the output terminal of the first RF amplifier, the first output stage amplifier, and the positive output terminal; The input terminal of the third 2-to-1 switch is connected to the output terminal of the second RF amplifier. The first output terminal of the third 2-to-1 switch is connected to the input terminal of the second output stage amplifier. The output terminal of the second output stage amplifier is connected to the first input terminal of the fourth 2-to-1 switch. The second output terminal of the third 2-to-1 switch is connected to the second input terminal of the fourth 2-to-1 switch. The output terminal of the fourth 2-to-1 switch is connected to the output terminal of the output amplification unit. The third 2-to-1 switch and the fourth 2-to-1 switch are configured to directly connect the output terminal of the second RF amplifier and the negative output terminal, or connect the output terminal of the second RF amplifier, the second output stage amplifier, and the negative output terminal.

8. The differential signal generator as described in claim 3, characterized in that, It also includes an output attenuation unit, through which the waveform generation unit is connected to the output amplification unit; The output attenuation unit is used to filter the positive AC signal and the negative AC signal, attenuate the positive AC signal to the input signal range of the first RF amplifier and then output it to the first RF amplifier, and attenuate the negative AC signal to the input signal range of the second RF amplifier and then output it to the second RF amplifier.

9. The differential signal generator as described in claim 1, characterized in that, It also includes an output control unit, which includes a fifth 2-to-1 switch, a sixth 2-to-1 switch, a P differential output terminal and an N differential output terminal, and the output amplification unit includes a positive output terminal and a negative output terminal; The P differential output terminal is connected to the positive output terminal through the fifth two-to-one switch, and is used to output or disable the output signal of the positive terminal under the control of the fifth two-to-one switch. The N differential output terminal is connected to the negative output terminal through the sixth 2-to-1 switch, and is used to output or disable the output signal of the negative terminal under the control of the sixth 2-to-1 switch.

10. A calibration method, characterized in that, The calibration method, applied to the differential signal generator as described in any one of claims 1 to 9, comprises: Obtain at least three sets of common-mode bias voltage codewords and differential-mode bias voltage codewords; The control processing unit sequentially inputs each set of common-mode bias voltage codewords and differential-mode bias voltage codewords into the output amplification unit, measures the positive terminal bias output voltage and negative terminal bias output voltage output by the output amplification unit, and calculates the common-mode bias output voltage and differential-mode bias output voltage based on the positive terminal bias output voltage and negative terminal bias output voltage. The common-mode bias output voltage is used as the common-mode bias voltage setting value, and the differential-mode bias output voltage is used as the differential-mode bias voltage setting value. Based on at least three sets of common-mode bias voltage codewords, differential-mode bias voltage codewords, common-mode bias voltage setting values, and differential-mode bias voltage setting values, the first mapping relationship and the second mapping relationship are calibrated.

Images