System and method for driving a hybrid switch

Abstract

The invention relates to a system and method for driving a hybrid switch. A switching system includes a hybrid switch and a control circuit. The hybrid switch includes an IGBT and a MOSFET. The control circuit includes an input terminal configured to receive a disconnect command. The control circuit also includes an IGBT drive circuit configured to turn off the IGBT in response to expiration of a first delay period, the first delay period starting in response to the turn-off command. Further, the control circuit includes a MOSFET driving circuit configured to: increase a gate-to-source voltage of the MOSFET from a first voltage level to a second voltage level in response to a turn-off command; driving the MOSFET at a second voltage level for a second delay period, the second delay period starting in response to the off command and being longer than the first delay period; and turning off the MOFET in response to expiration of the second delay period.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to hybrid switches, and in particular to control schemes for driving hybrid switches. BACKGROUND

[0002] Power electronics can be used to control the conversion and distribution of power. For example, a switching power converter can be used to generate a direct current (“DC”) voltage from an alternating current (“AC”) voltage by switching current through a magnetic element, such as an inductor. Conversely, an inverter can be used to convert a DC voltage to an AC voltage. In these and other forms of power electronics, power switches can be used to control the conversion and flow of power through a power conversion system and to electronic circuits powered by the device.

[0003] A hybrid switch can be used as a power switch in a power conversion system to improve conduction losses over a wide current range. A hybrid switch can include a high-power metal-oxide-semiconductor field-effect transistor (“MOSFET”) coupled in parallel with an insulated-gate bipolar transistor (“IGBT”). The forward voltage drop of a power MOSFET is generally linear with current. On the other hand, an IGBT generally has a diode-like forward voltage drop characteristic due to the internal junction of the IGBT. Thus, when combined in a hybrid switch, the MOSFET can dominate at low currents and the IGBT can dominate at higher currents. As a result, the hybrid device can improve conduction losses over a wide current range compared to a power MOSFET or IGBT alone. However, the inventors of embodiments of the present disclosure have recognized that a hybrid switch can incur higher switching losses than, for example, a power MOSFET alone. The inventors of embodiments of the present disclosure have recognized that such higher switching losses can negatively impact the overall efficiency of a power conversion system. Embodiments of the present disclosure can address one or more of these challenges. BRIEF DESCRIPTION OF DRAWINGS

[0004] A more complete understanding of embodiments of the application can be obtained by reference to the following description in connection with the accompanying drawings, in which like

[0005] Figure 1 A schematic diagram of a hybrid switch system according to embodiments of the present disclosure is shown.

[0006] Figure 2 A timing diagram of waveforms received and generated by a delay generator according to embodiments of the present disclosure is shown.

[0007] Figure 3 A timing diagram of waveforms for controlling a hybrid switch according to embodiments of the present disclosure is shown.

[0008] Figure 4A method for controlling a hybrid switch according to embodiments of the disclosure is shown. DETAILED DESCRIPTION

[0009] The details of one or more implementations are set forth in the accompanying description and drawings. Other features will be apparent from the description, the drawings, and from the claims.

[0010] Figure 1 A schematic diagram of a hybrid switch system 100 according to embodiments of the disclosure is shown. The hybrid switch system 100 can be implemented in any suitable manner according to the operations described in this disclosure. The hybrid switch system 100 can include a hybrid switch 110 and a control circuit 120. The control circuit 120 can provide control signals for turning on and off the hybrid switch 110.

[0011] As Figure 1 shown, the hybrid switch 110 can be coupled between a load 180 and ground GND, and can draw a load current I LOAD In some embodiments, the load 180 can represent a magnetic element of a switching power converter, such as an inductor or transformer. While Figure 1 An exemplary embodiment of the hybrid switch 110 used as a low-side switch coupled between the load 180 and ground GND is shown, the hybrid switch 110 can also be used as a high-side switch, for example, coupled between a high-side voltage supply rail and the load 180. Furthermore, in some embodiments, different instances of the hybrid switch system 100 including the hybrid switch 110 can respectively implement a high-side switch and a low-side switch coupled to a load. For example, in a power conversion system using a half-bridge topology to drive a magnetic element, a first instance of the hybrid switch system 100 can be used for the high-side switch of the half-bridge, and a second instance of the hybrid switch system 100 can be used for the low-side switch of the half-bridge.

[0012] The hybrid switch 110 can include a MOSFET gate input 101, an IGBT gate input 103, a MOSFET 111, and an IGBT 113. In some embodiments, the MOSFET 111 can be a silicon carbide ("SiC") MOSFET formed on a silicon carbide substrate. The MOSFET 111 can also be implemented in other semiconductor technologies, including wide bandgap semiconductor technologies such as gallium arsenide ("GaN"). In some embodiments, the IGBT can be a silicon IGBT formed on a silicon substrate. The IGBT can also be implemented in other semiconductor technologies, such as SiC. The conduction path of the MOSFET 111 can be coupled in parallel to the conduction path of the IGBT 113. For example, the MOSFET 111 can have a gate coupled to the MOSFET gate input 101, a drain coupled to a first conducting terminal 116, and a source coupled to a second conducting terminal 117. The IGBT can have a gate coupled to the IGBT gate input 103, a collector coupled to the first conducting terminal 116, and an emitter coupled to the second conducting terminal 117.

[0013] The hybrid switch 110 can also include a diode 112 and a diode 114. The respective anodes of the diode 112 and the diode 114 can be coupled to the second conducting terminal 117, and the respective cathodes of the diode 112 and the diode 114 can be coupled to the first conducting terminal 116. In some embodiments, the diode 112 can be implemented by an internal body diode of the MOSFET 111. The diode 114 can be implemented separately from the diode 112, including in embodiments in which the diode 112 is an internal body diode of the MOSFET 111. Thus, when the hybrid switch 110 experiences a reverse current, the diode 114 can protect the MOSFET 111 from all of the reverse current conducted through the diode 112.

[0014] The control circuit 120 can include an input terminal 121, a delay generator 130, a hybrid drive circuit 140, a MOSFET drive output 151, and an IGBT drive output 153. The control circuit 120 can be implemented in any suitable manner in accordance with the operations described in this disclosure. The control circuit 120 can be configured to receive a PWM signal at the input terminal 121. The PWM signal can command the control circuit 120 to turn on and off the hybrid switch 110. For example, a rising edge of the PWM signal can serve as a turn-on command, and a falling edge of the PWM signal can serve as a turn-off command, or vice versa. The control circuit 120 can repeatedly turn on and off the hybrid switch 110 in accordance with the pulse width and frequency of the PWM signal. Although the example embodiments described herein involve a PWM signal, the signal received at the input terminal 121 and the downstream control signals generated by the control circuit 120 can take any suitable form to repeatedly turn on and off the hybrid switch 110. For example, the control circuit 120 can receive a pulse frequency modulation (“PFM”) signal at the input terminal 121, or a clock signal with fixed or varying on-time and frequency.

[0015] Based on the PWM signal or other command signal received at the input terminal 121, the control circuit 120 can provide a first drive signal DRIVE MOS at the MOSFET drive output 151 for driving the MOSFET 111, and can provide a second drive signal DRIVE IGBT at the IGBT drive output 153 for driving the IGBT 113. As explained in detail below, the timing of the DRIVE MOS signal and the DRIVE IGBT signal can be controlled to minimize switching losses incurred when switching the hybrid switch 110 from an on state to an off state.

[0016] In some embodiments, the components of the hybrid switch system 100 can be implemented on multiple semiconductor dies and co-packaged in a single multi-chip integrated circuit package. For example, in some embodiments, the control circuit 120, the MOSFET 111, and the IGBT 113 can each be implemented on separate semiconductor dies and co-packaged in a multi-chip integrated circuit package. In other embodiments, the control circuit 120 can be implemented on the same semiconductor die as one of the MOSFET 111 or the IGBT 113 and co-packaged with the other of the MOSFET 111 or the IGBT 113 in a multi-chip integrated circuit package. In other example embodiments, the control circuit 120, the MOSFET 111, and the IGBT 113 can be implemented in separate integrated circuit packages.

[0017] As Figure 1As shown, control circuit 120 can include a delay generator 130. Delay generator 130 can be implemented in any suitable manner in accordance with the operations described in this disclosure. Delay generator 130 can include a delay circuit 131, a delay circuit 132, and a logic gate 133.

[0018] Delay circuit 131 and delay circuit 132 can be configured to receive the PWM signal from input terminal 121. As described above, in some embodiments, the rising edge of the PWM received at input terminal 121 can be used as a turn-on command, while the falling edge of the PWM signal can be used as a turn-off command. Delay circuit 131 and delay circuit 132 can apply a first delay and a second delay, respectively, to the turn-off command received at input terminal 121. For example, delay circuit 131 can apply a first delay to the falling edge of the PWM signal and generate an IGBT control signal PWM-IGBT for controlling IGBT 113. The first delay can be, for example, 5 ns, 10 ns, 15 ns, 30 ns, or more. Delay circuit 132 can apply a second delay to the falling edge of the PWM signal and generate a MOSFET control signal PWM-MOS for controlling MOSFET 111. In some embodiments, the second delay generated by delay circuit 132 can be greater than the first delay generated by delay circuit 131. For example, the second delay generated by delay circuit 132 can be 20 ns, 30 ns, 40 ns, 50 ns, or more greater than the first delay generated by delay circuit 131.

[0019] Logic gate 133 can include a first input coupled to receive the PWM signal from input terminal 121 and a second input coupled to receive the MOSFET control signal PWM-MOS from delay circuit 132. As Figure 1 As shown, logic gate 133 can be implemented as a logic AND gate with inversion at the first input for receiving the PWM signal. Logic gate 133 can generate a “selection” signal and can provide the “selection” signal to hybrid drive circuit 140. As described in further detail below, MOSFET drive circuit 141 within hybrid drive circuit 140 can receive the “selection” signal at a selection terminal and can be configured to select one of two voltages for driving the gate of MOSFET 111 during the turn-on state of MOSFET 111 and when switching hybrid switch 110 from the turn-on state to the turn-off state.

[0020] Figure 2 A timing diagram showing the waveforms received and generated by delay generator 130 in accordance with embodiments of the present disclosure is shown. Figure 2 A timing diagram showing the waveforms received and generated by delay generator 130 in accordance with embodiments of the present disclosure is shown. Figure 1The described PWM-IGBT signal, PWM-MOS signal, and "select" signal are responsive to the timing of a PWM signal received at input terminal 121 of control circuit 120. A falling edge and / or a sustained logic low of the PWM signal can represent a command for the drive hybrid switch 110 to be in an off state, where the hybrid switch is non-conducting, albeit with a small leakage current or reverse current. A rising edge and / or a sustained logic high of the PWM signal can represent a command for the drive hybrid switch 110 to be in a conductive on state, where the hybrid switch 110 can conduct current from the first conducting terminal 116 to the second conducting terminal 117. Thus, a transition of the PWM signal from logic low to logic high can be a command to change the hybrid switch 110 from the off state to the on state. And a transition of the PWM signal from logic high to logic low can be a command to change the hybrid switch 110 from the on state to the off state. In some embodiments, the logic low level can be 0 V, and the logic high level can be 1.5 V, 1.8 V, 3.3 V, 5.0 V, or any other voltage level suitable for use as a logic high level for a low voltage control circuit.

[0021] At time tl, the PWM signal received at input terminal 121 can rise from a logic low level to a logic high level. In response to the rising edge of the PWM signal at time tl, the IGBT control signal PWM-IGBT and the MOSFET control signal PWM-MOS can likewise rise from a logic low level to a logic high level.

[0022] At time t2, the PWM signal can fall from a logic high level to a logic low level. In response to the falling edge of the PWM signal, the delay circuit 131 can impose a first delay to the falling edge of the IGBT control signal PWM-IGBT. Thus, as shown in Figure 2 the PWM-IGBT can fall from a logic high level to a logic low level at time t3. The time difference between the falling edge of the PWM-IGBT at time t3 and the falling edge of the PWM at time t2 can represent the first delay period generated by the delay circuit 131.

[0023] In response to the falling edge of the PWM signal, the delay circuit 132 can impose a second delay to the falling edge of the MOSFET control signal PWM-MOS. Thus, as shown in Figure 2 the PWM-MOS can fall from a logic high level to a logic low level at time t4. The time difference between the falling edge of the PWM-MOS at time t4 and the falling edge of the PWM at time t2 can represent the second delay period generated by the delay circuit 132. The second delay period from the falling edge of the PWM to the falling edge of the PWM-MOS can be greater than the first delay period from the falling edge of the PWM to the falling edge of the PWM-IGBT.

[0024] AsFigure 2 As shown, the "select" signal can be set to a logic high level during a second delay period from time t2 to time t4. As described above, the second delay period represents the time between the falling edge of the PWM signal and the falling edge of the PWM-MOS. As described in further detail below, the MOSFET drive circuit 141 within the hybrid drive circuit 140 can receive the "select" signal at the select terminal and use the "select" signal to select one of two voltages for driving the gate of the MOSFET 111 during the on state of the MOSFET 111 and during the transition of the hybrid switch 110 from the on state to the off state.

[0025] The hybrid drive circuit 140 can be implemented in any suitable manner in accordance with the operations described in this disclosure. Referring back to Figure 1 , the hybrid drive circuit 140 can include a MOSFET drive circuit 141 and an IGBT drive circuit 143.

[0026] The MOSFET drive circuit 141 can be configured to receive the PWM-MOS and generate an output signal DRIVE MOS for driving the MOSFET 111. For example, the MOSFET drive circuit 141 can include a level shifter that can level shift the logic low or logic high level of the PWM-MOS to generate the output signal DRIVE MOS with a voltage sufficient to turn the MOSFET 111 on and off at a desired level. In response to a logic low level on the PWM-MOS, the MOSFET drive circuit 141 can apply a gate-to-source voltage of, for example, -5V to drive the MOSFET 111 in the off state. And in response to a logic high level on the PWM-MOS, the MOSFET drive circuit 141 can apply one of two potential positive gate-to-source voltages to the MOSFET 111 to drive the MOSFET 111 in the on state. For example, during the on state of the MOSFET 111, the MOSFET drive circuit 141 can select one of the two voltages for driving the MOSFET 111 based on the "select" signal received at the select terminal. As described in further detail below with reference to Figure 3 , the MOSFET drive circuit 141 can be configured to select a first gate-to-source voltage, for example, a first voltage level at +15V, during the on time of the hybrid switch 110. The MOSFET drive circuit 141 can also be configured to select a second gate-to-source voltage, for example, a second voltage level at +20V, during a second delay period from the falling edge of the PWM signal at time t2 to the falling edge of the PWM-MOS at time t4.

[0027] The IGBT drive circuit 143 can be configured to receive the PWM-IGBT and generate an output signal DRIVE for driving the IGBT 113 IGBT . For example, the IGBT drive circuit 143 can include a voltage level shifter that can level shift a logic low or logic high level of the PWM-IGBT to generate the output signal DRIVE IGBT having a voltage sufficient to turn the IGBT 113 on and off at a desired level. In response to a logic low level on the PWM-IGBT, the IGBT drive circuit 143 can apply a gate-to-emitter voltage of, for example, -5V to the IGBT 113 to drive the IGBT 113 in an off state. And in response to a logic high level on the PWM-IGBT, the IGBT drive circuit 143 can apply a gate-to-emitter voltage of, for example, a third voltage level at +18V to the IGBT 113 to drive the IGBT 113 in an on state. As described in further detail below, the third voltage level of, for example, +18V that can be used to drive the IGBT 113 during the on-time of the hybrid switch 110 can be greater than a first voltage level of, for example, +15V that can be used to drive the MOSFET 111 during the on-time of the hybrid switch 110.

[0028] Figure 3 A timing diagram of waveforms for controlling the hybrid switch 110 is shown in accordance with an embodiment of the disclosure. Times tl, t2, t3, and t4 are shown in Figure 3 to coincide with corresponding times tl, t2, t3, and t4 in Figure 2 .

[0029] Prior to time tl, the hybrid switch 110 can be driven in an off state with a gate-to-emitter voltage V GE_IGBT of, for example, -5V for the IGBT 113, and a gate-to-source voltage V GS_MOS of, for example, -5V for the MOSFET 111. At time tl, the control circuit 120 can receive a drive command to turn on the hybrid switch 110. Accordingly, at time tl, the hybrid switch 110 can transition to an on state with a gate-to-emitter voltage V GE_IGBT of, for example, +18V for the IGBT 113, and a gate-to-source voltage V GS_MOS of, for example, +15V for the MOSFET 111.

[0030] As shown in Figure 3 , a current I IGBT through the IGBT 113 and a current I MOSmay increase in response to IGBT 113 and MOSFET 111 being driven in the on state. In some embodiments, IGBT 113 and MOSFET 111 can be configured such that 70-80% of load current I LOAD is conducted through IGBT 113 during the on state of hybrid switch 110. For example, in some embodiments, IGBT 113 and MOSFET 111 can be configured such that 70-80% of load current I LOAD is conducted through IGBT 113, and the remaining 20-30% of load current I LOAD is conducted through MOSFET 111 during the on state of hybrid switch 110. To provide such current distribution, the die area of IGBT 113 can be greater than the die area of MOSFET 111. The distribution of current between IGBT 113 and MOSFET 111 can also be controlled by the respective voltages used to drive the gates of IGBT 113 and MOSFET 111. In some embodiments, IGBT 113 can be driven with a gate-to-emitter voltage that is greater than the gate-to-source voltage of MOSFET 111 during the on time of hybrid switch 110 between time tl and time t2. For example, as shown in FIG. 1C, IGBT 113 can be driven with a gate-to-emitter voltage level of +18V, and MOSFET 111 can be driven with a gate-to-source voltage level of +15V during the on time between time tl and time t2. Figure 3

[0031] Hybrid switch 110 can transition from the on state to the off state between times t2 and t4. The transition schemes disclosed herein can utilize a variety of techniques to reduce switching losses associated with switching hybrid switch 110 from the on state to the off state. For example, by keeping MOSFET 111 on during the transition of IGBT 113 from the on state to the off state, and thereby keeping the voltage at the collector of IGBT 113 low, the switching losses associated with turning off IGBT 113 can be reduced. Thus, by keeping MOSFET 111 in the on state during the transition of IGBT 113 to the off state, the switching losses associated with turning off IGBT 113 can be reduced.

[0032] Load current I LOAD from IGBT 113 to MOSFET 111 can be referred to as commutation. However, when MOSFET 111 is driven at its nominal on state gate-to-source voltage (e.g., +15V), the rate (dl MOS / dt) at which I MOS can be increased can be less than the rate (dl IGBT / dt) at which I​IGBT / dt). Thus, as Figure 3 shown at time t3 in FIG. 1 IB, the voltage V 116 at the first conduction terminal 116 coupled to the drain of the MOSFET 111 and the collector of the IGBT 113 can spike. The increased voltage at the collector of the IGBT 113 can thus result in switching losses associated with turning off the IGBT 113. However, as described below, the control circuit 120 can drive the gate of the MOSFET 111 in a manner that reduces this voltage spike during the transition of the hybrid switch 110 from the on state to the off state, and thus reduces the associated switching losses.

[0033] Driving the gate of the MOSFET 111 with an increased voltage during the transition of the IGBT 113 from the on state to the off state can further reduce the switching losses associated with turning off the IGBT 113. As described above with reference to Figure 1 , the load 180 can be an inductive element, such as a winding of an inductor or transformer. The commutation mismatch between the IGBT 113 and the MOSFET 111 attempts to change the load current I LOAD . However, due to the inductive load, the load current I LOAD may not immediately change when the IGBT turns off. In order to keep the current constant in the inductive load, the voltage across the load must increase, resulting in a voltage potential change.

[0034] To improve the commutation of current from the IGBT 113 to the MOSFET 111 when the IGBT 113 turns off, the control circuit 120 can first increase the gate-to-source voltage applied to the MOSFET 111. The increased gate-to-source voltage applied to the MOSFET 111 can increase the rate at which the current I MOS through the MOSFET 111 is able to increase (dl MOS / dt). Thus, the voltage spike at time t3 can be reduced, as well as the associated switching losses incurred by turning off the IGBT 113.

[0035] Referring back to Figure 1 and Figure 2 , at time t2, the control circuit 120 can receive a command to turn off the hybrid switch 110 in the form of a falling edge of a PWM signal. In response to the turn-off command at time t2, the control circuit 120 can increase the gate-to-source voltage applied to the MOSFET 111 from a first voltage level to a second voltage level. As Figure 3 shown, the gate-to-source voltage V GS_MOSThe first voltage level can increase from, for example, +15V to a second voltage level of, for example, +20V. After the first delay, as measured from time t2 to time t3, the gate-to-emitter voltage V GE_IGBT is driven low to turn off the IGBT 113. With the higher gate-to-source voltage applied to the MOSFET 111 during the transition of the IGBT 113 from the on state to the off state, the commutation of the current from the IGBT 113 to the MOSFET 111 beginning at time t3 can be improved. As a result, the voltage spike at the collector of the IGBT 113 and the switching losses associated with turning off the IGBT 113 can be reduced. Subsequently, after the second delay, as measured from time t2 to time t4, the gate-to-source voltage V GS_MOS is driven low to turn off the MOSFET 111. When the MOSFET 111 reaches the off state, the process for transitioning the hybrid switch 110 as a whole from the on state to the off state can be complete.

[0036] Figure 4 Operation of an exemplary method 400 for controlling a hybrid switch in accordance with an embodiment of the disclosure is shown. The method 400 can be performed by any suitable mechanism, such as the control circuit 120. The method 400 can be performed with fewer or more steps than shown. Moreover, steps of the method 400 can be omitted, repeated, performed in parallel, performed in a different order than shown, or recursively. Unless otherwise noted, one or more steps of the method 400, although shown in order, can be performed simultaneously or in a reordered manner. Figure 4 Figure 4

[0037] At step 402, a turn-on command for a hybrid switch can be received. For example, as described above with reference to Figure 1 and Figure 2 The control circuit 120 can be capable of receiving the turn-on command in the form of a rising edge of a PWM signal received at the input terminal 121.

[0038] At step 404, the IGBT of the hybrid switch can be driven to be in an IGBT-on state in response to the turn-on command. For example, the hybrid switch 110 can include the IGBT 113. In response to the turn-on command, the control circuit 120 can drive the IGBT 113 by driving the gate-to-emitter voltage V GE_IGBT The IGBT 113 can thus drive the current I IGBT ​​from its collector to its emitter. For the purposes of the present disclosure, the on and off states of the IGBT 113 can be referred to as an IGBT on state or an IGBT off state to distinguish from the on and off states of the MOSFET 111.

[0039] At step 406, the MOSFET of the hybrid switch can be driven into a first MOSFET on state in response to a turn-on command. For example, the hybrid switch can include the MOSFET 111. In response to the turn-on command, the control circuit 120 can drive the MOSFET 111 by applying a gate-to-source voltage V GS_MOS The MOSFET 111 is driven to drive the MOSFET 111 into the first on state. The MOSFET 111 can thus conduct current I MOS from its drain to its source. For the purposes of the present disclosure, the on and off states of the MOSFET 111 can be referred to as a MOSFET on state or a MOSFET off state to distinguish from the on and off states of the IGBT 113.

[0040] At step 408, a turn-off command for the hybrid switch can be received. For example, as described above with reference to Figure 1 and Figure 2 The control circuit 120 can be capable of receiving the turn-off command in the form of a falling edge of a PWM signal received at the input terminal 121.

[0041] At step 410, the MOSFET of the hybrid switch can be driven into a second MOSFET on state in response to the turn-off command. For example, in response to the turn-off command, the control circuit 120 can drive the MOSFET 111 by applying a gate-to-source voltage V GS_MOS The MOSFET 111 is driven to drive the MOSFET 111 into the second on state. As Figure 3 shown, from time t2 to time t4, the control circuit 120 can drive the MOSFET 111 by applying a gate-to-source voltage V GS_MOS The MOSFET 111 is driven to drive the MOSFET 111 into the second on state. As compared to when it is driven into the first on state with a gate-to-source voltage V GS_MOS The MOSFET 111 is driven to drive the MOSFET 111 into the second on state. As compared to when it is driven into the first on state with a gate-to-source voltage V GS_MOS The MOSFET 111 is more conductive when it is driven into the second on state with a gate-to-source voltage V

[0042] As described above with reference to Figure 1 and Figure 2As described, the falling edge of the PWM signal at time t2 can represent a turn-off command. In response to the turn-off command, the delay generator 130 of the control circuit 120 can generate a first signal PWM-IGBT with a first delay and can generate a second signal PWM-MOS with a second delay. The delay generator 130 can also generate a “select” signal based on the second signal PWM-MOS and the PWM signal. For example, as shown in Figure 2 response to the turn-off command, the “select” signal can transition from a logic low level to a logic high level at time t2. Referring back to Figure 1 , the MOSFET drive circuit 141 can select between on states based on the PWM-MOS signal and the “select” signal. For example, when the second signal PWM-MOS is in a logic high state, the MOSFET drive circuit 141 can select between a first MOSFET on state with a gate-to-source voltage V GS_MOS of +15V and a second MOSFET on state with a gate-to-source voltage V GS_MOS of +20V based on the “select” signal. For example, the “select” signal can transition from a logic low level to a logic high level at time t2 in response to the turn-off command, and the MOSFET drive circuit can in turn select the second on state with a gate-to-source voltage V GS_MOS of +20V. Thus, the MOSFET drive circuit 141 can select between the first MOSFET on state and the second MOSFET on state based at least in part on the turn-off command at the falling edges of the PWM signal and the second signal PWM-MOS.

[0043] At step 412, the IGBT can be driven into the IGBT non-on state after the first delay period that started in response to the turn-off command. For example, in response to the falling edge of the PWM signal received at the input terminal 121, the delay circuit 131 can generate the IGBT control signal PWM-IGBT with a first delay relative to the falling edge of the PWM signal. Upon expiration of the first delay period that started at the falling edge of the PWM signal, the PWM-IGBT can transition from a logic high state to a logic low state, indicating to the IGBT drive circuit 143 to apply a gate-to-emitter voltage of, for example, -5V to the IGBT 113 to drive the IGBT 113 into the non-on, off state. As shown in Figure 2 the first delay period can start at the falling edge of the PWM signal at time t2 and expire at the falling edge of the PWM-IGBT at time t3. And as shown in Figure 2 and Figure 3As shown, the first delay period can expire at time t3, at which time the IGBT drive circuit 143 can apply a gate-to-emitter voltage of, for example, -5V to the IGBT 113 to drive the IGBT 113 into a non-conducting off state.

[0044] At step 414, the MOSFET can be driven into a non-conducting state after a second delay period, which begins in response to the off command and lasts longer than the first delay period. For example, in response to a falling edge of the PWM signal received at the input terminal 121, the delay circuit 132 can generate a MOSFET control signal PWM-MOS having a second delay relative to the falling edge of the PWM signal. Upon expiration of the second delay period beginning at the falling edge of the PWM signal, PWM-MOS can transition from a logic high state to a logic low state, indicating to the MOSFET drive circuit 141 to apply a gate-to-source voltage of, for example, -5V to the MOSFET 111 to drive the MOSFET 111 into a non-conducting off state. As Figure 2 As shown, the second delay period can begin at time t2 with a falling edge of the PWM signal and expire at time t4 with a falling edge of the PWM-MOS signal. The second delay period from the falling edge of PWM to the falling edge of PWM-MOS can thus be greater than the first delay period from the falling edge of PWM to the falling edge of PWM-IGBT. And as Figure 2 and Figure 3 As shown, the second delay period can expire at time t4, at which time the MOSFET drive circuit 141 can apply a gate-to-source voltage of, for example, -5V to the MOSFET 111 to drive the MOSFET 111 into a non-conducting off state.

[0045] While examples have been described above, other modifications and changes will be apparent to those of ordinary skill in the art from the disclosure. The descriptions above of various embodiments illustrate principles of the application. Many variations and modifications will be readily apparent to those skilled in the art from the disclosure. The scope of the claims is intended to cover all such variations and modifications.

Claims

1. A switching system comprising: a hybrid switch comprising: an insulated gate bipolar transistor (IGBT); and a metal oxide semiconductor field effect transistor (MOSFET); and a control circuit comprising: an input terminal configured to receive a turn-off command; an IGBT drive circuit configured to turn off the IGBT in response to expiration of a first delay period, the first delay period starting in response to the turn-off command; and a MOSFET drive circuit configured to: increase a gate-to-source voltage of the MOSFET from a first voltage level to a second voltage level in response to the turn-off command; drive the MOSFET at the second voltage level for a second delay period, the second delay period starting in response to the turn-off command and being longer than the first delay period; and turn off the MOSFET in response to expiration of the second delay period.

2. The switching system of claim 1, wherein the MOSFET comprises a silicon carbide MOSFET.

3. The switching system of claim 1, wherein the IGBT comprises a silicon IGBT.

4. The switching system of claim 1, wherein the IGBT has a larger die area than the MOSFET.

5. The switching system of claim 1, wherein: the input terminal is further configured to receive a turn-on command; the MOSFET drive circuit is further configured to drive the gate-to-source voltage of the MOSFET at the first voltage level in response to the turn-on command; and the IGBT drive circuit is further configured to drive a gate-to-emitter voltage of the IGBT at a third voltage level in response to the turn-on command, the third voltage level being greater than the first voltage level of the gate-to-source voltage of the MOSFET.

6. The switching system of claim 1, wherein the control circuit further comprises: a first delay circuit configured to generate a first signal having a first delay corresponding to the first delay period in response to the turn-off command; and a second delay circuit configured to generate a second signal having a second delay corresponding to the second delay period in response to the turn-off command.

7. The switching system of claim 1, wherein the IGBT, the MOSFET, and the control circuit are co-packaged in a multi-chip integrated circuit package.

8. The switching system of claim 1, wherein the MOSFET drive circuit further comprises a select terminal and is configured to select one of two voltages for driving a gate of the MOSFET during a turn-on state of the MOSFET based on a select signal received at the select terminal during the turn-on state of the MOSFET.

9. A hybrid switching system comprising: a hybrid switch comprising: an insulated gate bipolar transistor (IGBT); and a metal oxide semiconductor field effect transistor (MOSFET); and a control circuit comprising: an input terminal configured to receive a turn-off command; an IGBT drive circuit configured to turn off the IGBT in response to expiration of a first delay period, the first delay period starting in response to the turn-off command; and a MOSFET drive circuit configured to: increase a gate-to-source voltage of the MOSFET from a first voltage level to a second voltage level in response to the turn-off command; drive the MOSFET at the second voltage level for a second delay period, the second delay period starting in response to the turn-off command and being longer than the first delay period; and turn off the MOSFET in response to expiration of the second delay period. an insulated gate bipolar transistor (IGBT); a metal oxide semiconductor field effect transistor (MOSFET); and a control circuit, the control circuit comprising: an input terminal configured to receive an off command; a delay generator configured to generate an IGBT control signal having a first delay and to generate a MOSFET control signal having a second delay in response to the off command; an IGBT drive circuit configured to turn off the IGBT in response to the IGBT control signal having the first delay; and a MOSFET drive circuit configured to increase a gate-to-source voltage applied to the MOSFET in response to the off command and subsequently to turn off the MOSFET in response to the MOSFET control signal having the second delay.

10. The hybrid switch system of claim 9, wherein the MOSFET comprises a silicon carbide MOSFET.

11. The hybrid switch system of claim 9, wherein the IGBT comprises a silicon IGBT.

12. The hybrid switch system of claim 9, wherein the IGBT has a larger die area than the MOSFET.

13. The hybrid switch system of claim 9, wherein: the input terminal is further configured to receive an on command; the MOSFET drive circuit is further configured to drive the gate-to-source voltage of the MOSFET at a first voltage level in response to the on command and at a second voltage level higher than the first voltage level in response to the off command; and the IGBT drive circuit is further configured to drive a gate-to-emitter voltage of the IGBT at a third voltage level in response to the on command, the third voltage level being greater than the first voltage level of the gate-to-source voltage of the MOSFET.

14. The hybrid switch system of claim 9, wherein the MOSFET drive circuit further comprises a select terminal and is configured to select one of two voltages for driving a gate of the MOSFET during an on state of the MOSFET based on a select signal received at the select terminal during the on state of the MOSFET.

15. A method for controlling a hybrid switch, the method comprising: receiving an on command for the hybrid switch; driving an insulated gate bipolar transistor (IGBT) of the hybrid switch into an IGBT on state in response to the on command; driving a metal oxide semiconductor field effect transistor (MOSFET) of the hybrid switch into a first MOSFET on state in response to the on command; receiving an off command for the hybrid switch; driving the IGBT of the hybrid switch into an IGBT off state in response to the off command; and driving the MOSFET of the hybrid switch into a second MOSFET off state in response to the off command. driving the MOSFET into a second MOSFET-on state in response to the turn-off command, wherein the MOSFET is more conductive in the second MOSFET-on state than in the first MOSFET-on state; driving the IGBT into an IGBT-off state after a first delay period, the first delay period starting in response to the turn-off command; and driving the MOSFET into a MOSFET-off state after a second delay period, the second delay period starting in response to the turn-off command and lasting longer than the first delay period.

16. The method for controlling a hybrid switch of claim 15, wherein: driving the MOSFET into the first MOSFET-on state includes applying a first gate-to-source voltage to the MOSFET; and driving the MOSFET into the second MOSFET-on state includes applying a second gate-to-source voltage to the MOSFET that is greater than the first gate-to-source voltage.

17. The method for controlling a hybrid switch of claim 15, wherein: driving the MOSFET into the first MOSFET-on state includes applying a first gate-to-source voltage to the MOSFET; and driving the IGBT into the IGBT-on state includes applying a first gate-to-emitter voltage to the IGBT that is greater than the first gate-to-source voltage applied to the MOSFET.

18. The method for controlling a hybrid switch of claim 15, wherein the IGBT is more conductive in the IGBT-on state than the MOSFET is in the first MOSFET-on state.

19. The method for controlling a hybrid switch of claim 15, the method further comprising: generating a first signal having a first delay corresponding to the first delay period in response to the turn-off command; and generating a second signal having a second delay corresponding to the second delay period in response to the turn-off command.

20. The method for controlling a hybrid switch of claim 19, the method further comprising selecting between the first MOSFET-on state and the second MOSFET-on state based at least in part on the turn-off command and the second signal.

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