Mass production test system based on JESD204B interface analog-to-digital converter

Abstract

The invention provides a mass production test system for an analog-to-digital converter based on a JESD204B interface, and the system comprises a to-be-tested chip which is provided with the JESD204B interface; the automatic test equipment is in communication connection with the JESD204B interface of the chip to be tested; the signal generator is used for providing an analog input signal and a clock for the chip to be tested and providing a reference clock for the automatic test equipment; wherein the automatic test equipment controls the to-be-tested chip to output a fixed waveform signal, so that the automatic test equipment performs sampling edge alignment based on the fixed waveform signal so as to capture output data of the JESD204B interface for analysis, application layer data is obtained, and a test result is determined based on the application layer data. The test efficiency can be effectively improved, and the complexity of a test architecture is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of analog-to-digital converter testing, and in particular to a mass production testing system for analog-to-digital converters based on JESD204B interface. BACKGROUND

[0002] With the large-scale application of high-speed analog-to-digital converters supporting JESD204B protocol, the requirements for mass production testing solutions for JESD204B high-speed analog-to-digital converters are also increasing. Most of the existing mass production testing solutions for JESD204B analog-to-digital converters rely on the GTH resources of FPGAs or special ASIC chips to parse protocol data, and there are problems such as complex testing hardware architecture, insufficient testing parameter coverage, inflexible algorithm configuration, and high testing cost. SUMMARY

[0003] In view of the above problems existing in the prior art, the present application provides a mass production testing system for analog-to-digital converters based on JESD204B interface, which mainly solves the problems of low testing parameter coverage, long testing time, low testing efficiency and dependence on high-speed digital devices supporting JESD204B in the testing process of the existing mass production testing solutions.

[0004] To achieve the above object and other objects, the technical scheme adopted by the present application is as follows.

[0005] The present application provides a mass production testing system for analog-to-digital converters based on JESD204B interface, which comprises: a to-be-tested chip having a JESD204B interface; an automatic testing device in communication connection with the JESD204B interface of the to-be-tested chip; and a signal generator for providing an analog input signal and a clock for the to-be-tested chip, and providing a reference clock for the automatic testing device; wherein the automatic testing device controls the to-be-tested chip to output a fixed waveform signal, so that the automatic testing device performs sampling edge alignment based on the fixed waveform signal, captures output data of the JESD204B interface for analysis, obtains application layer data, and determines a testing result based on the application layer data.

[0006] In an embodiment of the present application, the automatic testing device is further configured to test an eye diagram, a rise and fall time, and a CML level according to the fixed waveform signal.

[0007] In an embodiment of the present application, the automatic testing device is further configured to supply power to the to-be-tested chip.

[0008] In an embodiment of the present application, the automatic testing device is further configured to align according to an eye diagram of the fixed waveform signal to determine a sampling edge, and complete sampling edge alignment so that the automatic testing device is synchronized with the clock of the to-be-tested chip.

[0009] In an embodiment of the present application, the automatic test equipment is further configured to re-perform the sampling edge alignment after each time the rate of the fixed waveform signal or the clock setting of the automatic test equipment is changed, so as to perform the test of the chip under test after the sampling edge alignment.

[0010] In an embodiment of the present application, the automatic test equipment sends a synchronization control signal to make the chip under test output the fixed waveform signal, wherein the fixed waveform signal is a repeated K28.5 code.

[0011] In an embodiment of the present application, the chip under test outputs the fixed waveform signal when the synchronization control signal is pulled low, wherein the low pulse width duration of the synchronization control signal is at least greater than two multi-frame periods.

[0012] In an embodiment of the present application, the automatic test equipment is further configured to determine that the synchronization is successful when at least four continuous and error-free K28.5 codes are captured, and then pull the synchronization control signal high.

[0013] In an embodiment of the present application, the automatic test equipment is further configured to read test configuration parameters of the chip under test, wherein the test configuration parameters include the number of transmission lines of each link, the number of data converters of each device, the number of bytes contained in each frame clock period, the number of samples transmitted by each converter per frame, whether to perform 8-bit to 10-bit encoding, whether the encoding is scrambled, and whether to take the complement code; and the application layer data is obtained by splicing according to the test configuration parameters.

[0014] As described above, the present application has the following beneficial effects.

[0015] The present application uses mainstream automatic test equipment to build a high-speed analog-to-digital converter mass production test system supporting the JESD204B protocol, and can realize comprehensive and efficient testing of JESD204B interface analog-to-digital converters. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 The figure is a test system architecture diagram in an embodiment of the present application.

[0017] Figure 2 The figure is a K28.5 code waveform diagram captured after the eye center alignment of the JESD204B output signal in an embodiment of the present application.

[0018] Figure 3 The figure is an eye diagram of the JESD204B output signal tested by the test system in an embodiment of the present application.

[0019] Figure 4Figure 8 is a diagram of an eye width and eye height test result of a JESD204B output signal in an embodiment of the present application.

[0020] Figure 5 Figure 9 is a flowchart of a JESD204B offline data analysis in an embodiment of the present application.

[0021] Figure 6 Figure 10 is a flowchart of a multi-thread test calling in an embodiment of the present application.

[0022] Figure 7 Figure 11 is a 10b data waveform diagram collected by a test system in an embodiment of the present application.

[0023] Figure 8 Figure 12 is a CGS part data diagram analyzed from collected data by a test system in an embodiment of the present application.

[0024] Figure 9 Figure 13 is an ILAS part data diagram analyzed from collected data by a test system in an embodiment of the present application.

[0025] Figure 10 Figure 14 is an 8b user data diagram on lan0 and lan1 after data decoding and descrambling by a test system in an embodiment of the present application.

[0026] Figure 11 Figure 15 is a time domain waveform diagram after data splicing by a test system in an embodiment of the present application.

[0027] Figure 12 Figure 16 is a frequency domain waveform diagram after data splicing by a test system in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The present application is described herein with reference to specific embodiments thereof, which are illustrated in the attached drawings. The following detailed description of the application is presented in the context of these drawings, like reference numerals in the drawings denote like or similar elements for the sake of clarity and ease of understanding. It should be noted that the following examples and features of the examples can be combined with each other, without conflicts, unless it is clearly stated otherwise.

[0029] It should be noted that the diagrams provided in the following examples are merely schematic representations of the basic concepts of the present application, and thus the diagrams only show the components related to the present application, rather than the number, shape and size of the components when actually implemented. The actual implementation of each component can be a random change in shape, number and proportion, and the layout of the components can be more complex.

[0030] Reference is made to Figure 1 , Figure 1The figure is a schematic diagram of a production test system based on a JESD204B interface analog-to-digital converter in an embodiment of the present application. The production test system comprises: a chip under test, the chip under test having a JESD204B interface; an automatic test equipment, which is communicatively connected with the JESD204B interface of the chip under test; and a signal generator, which is configured to provide an analog input signal and a clock for the chip under test, and to provide a reference clock for the automatic test equipment. The automatic test equipment controls the chip under test to output a fixed waveform signal, so that the automatic test equipment performs sampling edge alignment based on the fixed waveform signal, captures output data of the JESD204B interface, obtains application layer data, and determines a test result based on the application layer data. Specifically, the chip under test is a high-speed analog-to-digital converter chip having a JESD204B interface. The automatic test equipment (ATE) can be an advanced ATE device having high-precision and high-stability transceiving capability, and the high-speed digital board card of the ATE can have a transmission rate of up to 16 Gbps, which can meet the test requirements of the JESD204B high-speed signal. In the production test process, the signal generator provides an analog signal and a clock for the chip under test, and provides a reference clock for the ATE, so as to ensure the clock synchronization between the signal generator and the ATE. The automatic test equipment can be connected with a terminal, and can output test data and data captured in the test process to the terminal for analysis. The display interface of the terminal can display corresponding data, such as an eye diagram and a waveform diagram. The terminal can be a computer terminal or other terminal having data processing and display functions, and the specific terminal can be selected and adjusted according to actual application requirements. The data analysis process can also be completed in the automatic test equipment.

[0031] In an embodiment, the chip under test can be powered by the automatic test equipment. Specifically, the power supply pin of the chip under test is connected with a channel of a power supply board card of the ATE, the JESD204B data pin is connected with a channel of a high-speed digital board card, and other pins are connected with channels of ordinary digital board cards.

[0032] In an embodiment, the integrity of the high-speed signal should be ensured in the entire hardware design, and signal attenuation and interference should be reduced. Factors affecting the integrity of the high-speed signal mainly include the following aspects: 1. reflection caused by impedance mismatch of signal lines; 2. crosstalk on adjacent signal lines caused by electromagnetic effect when a signal passes through a signal line; and 3. delay caused by too long signal lines. Therefore, in the test system, a high-speed board material (≥8 GHz) should be selected for PCB design, the layout and wiring of the chip under test should be designed to reduce the length of the high-speed signal lines, the layer design should consider reducing the density and direction of the signal lines to reduce crosstalk, the clock signal and the high-speed signal differential pair should be processed to be equal in length, the power supply lines and ground lines should be processed in layers and away from the high-speed signal.

[0033] In an embodiment, the automatic test equipment is further configured to test the eye diagram, rise and fall time, and CML level of the fixed waveform signal. The eye height, eye width, rise and fall time, and CML level of the JESD204B output signal can be tested. The sampling edge alignment needs to be performed before the test. The automatic test equipment aligns the sampling edge according to the eye diagram of the fixed waveform signal to determine the sampling edge, and completes the sampling edge alignment, so that the automatic test equipment is synchronized with the clock of the chip to be tested. Specifically, the clock alignment of the JESD204B signal is a key step to ensure the correctness and synchronization of the JESD204B data transmission. The selected ATE does not have CDR technology, and cannot restore the sampling clock in the data stream, but can use the Embedded Timming Search API of the ATE to align the eye center of the JESD204B output signal to determine the sampling edge of the output signal, and use the acquisition vector of the K28.5 code to replace the CDR (Clock Data Recovery). When using the Embedded Timming Search to find the signal edge, the fixed waveform needs to be sent by the device to be tested. In the embodiment of the application, the SYNC (synchronization control signal) specified in the JESD204B is fixed to low to make the device under test in the CGS state, and continuously send the K28.5 code. After the eye center and offset alignment is completed, the waveform captured by the ATE is as follows Figure 2 .

[0034] After the sampling edge alignment is completed, the signal integrity test can be performed to test the eye width and eye height, and the rise and fall time and CML level of the JESD204B output signal. After the fixed waveform is sent by the device to be tested, the shmoo tool of the ATE can be used to test the eye diagram of the JESD204B output signal as follows Figure 3 . The Fast Adjuset function of the ATE is used to test the eye width and eye height, and the rise and fall time and CML level of the JESD204B output signal as follows Figure 4 .

[0035] In an embodiment, the physical layer of the device to be tested can be tested first. The main purpose of the physical layer test is to verify the performance of the physical layer of the interface, including clock recovery, signal integrity, jitter, and noise, to ensure that the data can be accurately and reliably transmitted between the sending end and the receiving end. In an embodiment, the sampling edge alignment must be performed before the physical layer test and the subsequent converter performance test, and the rate of the JESD204B output signal of the device to be tested and the timing setting of the ATE cannot be changed. If the above settings are changed, the sampling edge alignment needs to be performed again.

[0036] In an embodiment, the automatic test equipment of the present application uses a synchronous control signal (SYNC) to send a fixed high-low-high (where the low pulse duration is greater than two multi-frame periods) to capture the entire JESD204B output data, and then offline parses the data. The CGS stage is the first important stage in the JESD204B link establishment process. After the ATE pulls down the SYNC signal, the DUT is controlled to send repeated K28.5 codes, and the low pulse duration of the SYNC is at least greater than two multi-frame periods to ensure that the ATE can capture at least four consecutive K28.5 characters without error to consider the synchronization successful. After the synchronization is successful, the ATE pulls up the SYNC signal to start the ILAS stage. The ILAS usually consists of four multi-frames, the first multi-frame data starts with K28.0 code and ends with K28.3 code, the second multi-frame data starts with K28.0 code, followed by K28.4 code and link configuration parameters, and ends with K28.3 code, and the third and fourth multi-frame data starts with K28.0 code and ends with K28.3 code. The data in the CSG and ILAS parts are all unscrambled 10b data, and the captured 10b data finds the positions of the first K code and R code, and the front is the data of the CGS part, and the 128 10b data after it is the data of the ILAS part.

[0037] In the JESD204B protocol, an 8b / 10b encoding method is used, and the test system needs to decode the captured data stream to 10b / 8b, which is the inverse process of 8b / 10b encoding. 10b encoding can represent 1024 data, and 8b encoding can only represent 256 data, so in the process of 10b to 8b, multiple 10b data may correspond to one 8b data, and errors may occur, so the number of errors needs to be recorded in the decoding process to judge the accuracy of the data, and whether the data is a K code.

[0038] In the JESD204B protocol, in order to reduce electromagnetic interference in data transmission and enhance the independence of data, a data randomization process is added in the transmission process, that is, scrambling, and the scrambling polynomial is 1+X^14+X^15. If the JESD204B transmission signal is scrambled, the test system needs to descramble the received data to restore the original data. The descrambling principle is as follows: the x-2 data is denoted as A, the x-1 data is denoted as B, and the x data is denoted as C. 8-bit A, B, and C are combined into a 24-bit data S, where A is the MSB and C is the LSB. Regenerate 8-bit final data D, where D[i] = S[i]^S[i+14]^S[i+15]. At this time, the MSB and LSB of the data D are inverted, and the data D after inversion is the descrambled data. If the chip output data contains frame alignment control information (FACI), it needs to be removed from the 8b data after descrambling.

[0039] The data after the above processing is spliced according to the configuration of the LMFS of the chip to obtain the application layer data. The LMFS parameter configuration defines the structure and rate of data transmission. L represents the number of transmission lines of each link; M represents the number of data converters of each device; F represents the number of bytes contained in each frame clock cycle; and S represents the number of samples transmitted by each converter per frame. The above configurations can be read or calculated through chip configuration. Taking L=4, M=1, F=1, S=2, and N=14 as an example, that is, one 14-bit data converter, four lanes, two sample quantities transmitted by each converter per frame, and one byte per frame, the data splicing process is as follows. Two sample quantities S1 and S2 are transmitted by one converter per frame, wherein Oct0 of S1 is transmitted by lane0, Oct1 is transmitted by lane1, Oct0 of S2 is transmitted by lane2, and Oct1 is transmitted by lane3. A total of 16 bits of data are transmitted, and the low 2 bits are CS bits, which need to be removed during data splicing. Therefore, the high 8 bits of S1 are composed of Oct1 of lane0, and the low 6 bits of S1 are composed of the high 6 bits of lane1. S2 is spliced in the same way. The spliced S1 and S2 are sequentially spliced to obtain the final data. If the application layer data is a complement, the complement data also needs to be converted.

[0040] In an embodiment, the automatic test equipment is further configured to read test configuration parameters of the chip under test, wherein the test configuration parameters include the number of transmission lines of each link, the number of data converters of each device, the number of bytes contained in each frame clock cycle, the number of samples transmitted by each converter per frame, whether 8-bit to 10-bit encoding is performed, whether the encoding is scrambled, and whether the complement is taken. The application layer data is obtained by splicing data according to the test configuration parameters. The LMFS parameter configuration is crucial to the stability and transmission efficiency of the JESD204B link. In the JESD240B protocol, synchronization and alignment between multiple frames can be achieved through different LMFS configurations, and errors and losses in the data transmission process are avoided. By adjusting the values of L, M, F, and S, the data transmission rate and efficiency can be adjusted. Therefore, during the chip mass production test process, the test under different LMFS configurations is particularly important for improving the chip test coverage, ensuring product stability, and quality reliability.

[0041] The reuse of test algorithms under different LMFS configurations can simplify the code of the test system, improve the test efficiency, and enable the test system to be reused in more JESD204B mass production test systems.

[0042] Based on the fast vector production technology provided by the ATE, the algorithm reuse of the LMFS can be achieved through the following three steps:

[0043] 1. Using fast vector production technology to quickly generate SPI test vectors, read the parameter configuration of chip LMFS, in addition to reading LMFS parameters, also need to read whether to perform 8b10 encoding, whether to scramble, whether to take the code, whether there is FACI configuration information, and store them in the global variable structure config;

[0044] 2. According to the parameter configuration of LMFS, calculate the required data depth of grabbing, confirm the test depth of test vector and dynamically change the size of grabbing data vector, and execute the test vector;

[0045] 3. Change the JESD204B parameters in the code of the algorithm related to protocol parsing and user layer data splicing to the variables in the structure config, and pass config into the algorithm code, and parse the grabbed data according to the parameters of LMFS to obtain the final application layer data.

[0046] In the chip mass production test system, in addition to the test coverage, its test cost, especially the test time cost, is also very important, so shortening the test time is particularly important. In the test process of high-precision ADC of 16 bits or more JESD204B, especially multi-channel ADC, because the test data volume is large (T bit level), the single-chip test time can reach several minutes, which seriously affects the production test efficiency of the chip.

[0047] In view of the above problems, in the data analysis processing of the host computer, the multi-core processing capability of the host computer is used, the multi-threading technology is used to process the analysis of multi-lane data in parallel, and the analysis process is carried out in the background, while the ATE carries out other test items test, and the test results are output after all the tests are completed. Using the background processing method of multi-threading, the production test time of high-precision JESD204B can be shortened by more than 80%, which greatly improves the test efficiency. The multi-threading test flow is as follows Figure 6 .

[0048] The specific test process is: after the test system is powered on, the chip to be tested is configured as the expected mode, and the clock signal and the analog input signal are provided to the chip to be tested through the signal generator. The analog signal is output by the SERDES pin after analog-to-digital conversion, the ATE collects the 10b waveform as shown in Figure 7 , the CGS part of the analyzed data is as shown in Figure 8 , the ILAS part of the analyzed data is as shown in Figure 9 , the 8b user data on lan0 and lan1 after decoding and descrambling is as shown in Figure 10 , then the time domain waveform is obtained through data splicing Figure 11 , and finally the frequency domain graph is obtained through Fourier transform Figure 12 .

[0049] After repeated tests, the dynamic parameters such as SNR and SFDR of the analog-to-digital converter can reach the values in the device manual under different frequency points and different configurations, the test results are stable, the test efficiency is high, the test coverage is complete, and the test ability of the test system for the high-speed JESD204B analog-to-digital converter is effectively verified.

[0050] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical idea disclosed by the present application should be covered by the claims of the present application.

Claims

1. A production test system for JESD204B interface based analog-to-digital converters, characterized in that, The system comprises: a chip under test, which has a JESD204B interface; an automatic test equipment, which is communicatively connected with the JESD204B interface of the chip under test; a signal generator, which is configured to provide an analog input signal and a clock for the chip under test, and provide a reference clock for the automatic test equipment; wherein the automatic test equipment controls the chip under test to output a fixed waveform signal, so that the automatic test equipment performs sampling edge alignment based on the fixed waveform signal, captures output data of the JESD204B interface to obtain application layer data, and determines a test result based on the application layer data.

2. The JESD204B interface-based analog-to-digital converter production test system of claim 1, wherein, The automatic test equipment is further configured to test an eye diagram, a rise and fall time, and a CML level of the fixed waveform signal.

3. The JESD204B interface-based analog-to-digital converter production test system of claim 1, wherein, The automatic test equipment is further configured to supply power for the chip under test.

4. The JESD204B interface-based analog-to-digital converter production test system of claim 1, wherein, The automatic test equipment is further configured to perform alignment according to an eye diagram of the fixed waveform signal to determine a sampling edge, and complete sampling edge alignment so that the automatic test equipment is synchronized with the clock of the chip under test.

5. The JESD204B interface-based analog-to-digital converter production test system of claim 1, wherein, The automatic test equipment is further configured to re-perform sampling edge alignment after changing a rate of the fixed waveform signal or a clock setting of the automatic test equipment each time, and perform a test of the chip under test after the sampling edge alignment.

6. The JESD204B interface-based analog-to-digital converter production test system of claim 4, wherein, The automatic test equipment sends a synchronization control signal to make the chip under test output the fixed waveform signal, wherein the fixed waveform signal is a repeated K28.5 code.

7. The JESD204B interface-based analog-to-digital converter production test system of claim 6, wherein, The chip under test outputs the fixed waveform signal when the synchronization control signal is pulled low, wherein a low pulse width duration of the synchronization control signal is at least greater than two multi-frame periods.

8. The JESD204B interface-based analog-to-digital converter production test system of claim 7, wherein, The automatic test equipment is further configured to determine synchronization success when at least four continuous and error-free K28.5 codes are captured, and pull up the synchronization control signal.

9. The JESD204B interface-based analog-to-digital converter production test system of claim 7, wherein, The automatic test equipment is further configured to read test configuration parameters of the chip under test, wherein the test configuration parameters include a number of transmission lines of each link, a number of data converters of each device, a number of bytes contained in each frame clock period, a number of samples transmitted by each converter per frame, whether 8-bit to 10-bit encoding is performed, whether encoding is scrambled, and whether a complement code is taken; and perform data splicing to obtain the application layer data according to the test configuration parameters.

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