Downconversion serialization output network for high-speed time domain interleaving analog-to-digital converter test

Abstract

The invention relates to a down-conversion serialization output network for testing a high-speed time domain interleaving analog-to-digital converter, which is characterized in that a clock down-conversion module accesses M single-channel sampling clock signals and performs down-conversion processing to obtain M down-conversion clock signals, and the M down-conversion clock signals are transmitted to a clock serialization module and a latch module; the clock serialization module is used for carrying out serialization processing on the M underclocking clock signals to obtain a high-frequency interleaving clock signal and transmitting the high-frequency interleaving clock signal to the output serialization module; the latch module responds to the M underclocking clock signals, performs underclocking latching on M groups of quantized codes input into the M underclocking clock signals, and outputs M groups of underclocking quantized codes of the current period; and the output serialization module accesses the clock serialization signals generated by the clock serialization module in the serialization processing process and the high-frequency interleaving clock signals, and the output serialization module responds to the multiple clock serialization signals and serializes the M groups of underclocking quantized codes to obtain a synthesized quantized code. The device can meet high-speed ADC test requirements.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuits, and particularly relates to a frequency-reducing serialization output network for high-speed time-domain interleaved analog-to-digital converter testing. BACKGROUND

[0002] Since the advent of digital signal processing systems, analog-to-digital converters (ADCs) have been one of the key electronic components in electronic devices that interact with the real world. The scale of time-domain interleaved ADCs is getting larger and larger, and the sampling rate of the ADC has reached 72GS / s in the latest research. However, high-speed output signals cannot be directly processed during the ADC testing process, so the output of the ADC is generally serialized and frequency-reduced in the circuit before being output. The traditional serialization and frequency-reduction structure adopts a logic structure of serialization first and then frequency-reduction. However, as the number of interleaved channels increases, both the serialization and frequency-reduction processes face increasingly serious problems. The serialization process is realized by logic gates, and the high-frequency output signal imposes strict requirements on the delay of the logic gate. The delay is limited by the process, and even if additional power consumption and area are paid, it may not meet the requirements. High sampling rate means high frequency reduction rate at the output, i.e. large-scale frequency reduction circuit. At this time, the delay of the frequency reduction circuit will also be a problem, which may cause frequency reduction rate errors, or even output state uncertainty. Moreover, the traditional serialization and frequency-reduction structure itself cannot distinguish the outputs of each channel, and additional flag bits need to be added to the output, which not only increases the size of the output network, but also is not conducive to directly observing the output of a single channel.

[0003] In short, the existing serialization and frequency-reduction structure cannot meet the requirements of ADC testing. SUMMARY

[0004] In order to solve the above problems in the prior art, the present application provides a frequency-reducing serialization output network for high-speed time-domain interleaved analog-to-digital converter testing. The technical problem to be solved by the present application is solved by the following technical scheme:

[0005] The application provides a frequency reduction serialization output network for high-speed time domain interleaving analog-to-digital converter (ADC) testing, comprising a clock frequency reduction module, a clock serialization module, a latch module and an output serialization module; wherein: M input ends of the clock frequency reduction module are connected to one single-channel sampling clock signal with a frequency of fs respectively, for performing frequency reduction processing on the M single-channel sampling clock signals to obtain M frequency reduction clock signals with a frequency of fs / N, the M frequency reduction clock signals are transmitted to M input ends of the clock serialization module and M control ends of the latch module, and M is a positive integer; the clock serialization module is used for performing serialization processing on the M frequency reduction clock signals to obtain a high-frequency interleaving clock signal with a frequency of (M / N)·fs and transmitting the high-frequency interleaving clock signal to the output serialization module; the latch module is used for performing frequency reduction latching on M groups of quantization codes input thereto in response to the M frequency reduction clock signals and outputting M groups of frequency reduction quantization codes of a current period; a control end of the output serialization module is connected to clock serialization signals generated in the serialization processing process of the clock serialization module and the high-frequency interleaving clock signal, M input ends are connected to the M groups of frequency reduction quantization codes, and the output serialization module is used for performing serialization processing on the M groups of frequency reduction quantization codes in response to the multiple clock serialization signals to obtain a synthetic quantization code with a frequency of (M / N)·fs.

[0006] Compared with the prior art, the application has the following beneficial effects:

[0007] In view of the problem that the existing serialization frequency reduction structure cannot meet the ADC testing requirements, the application provides a frequency reduction serialization output network for high-speed time domain interleaving ADC testing, which realizes the key functions in high-speed time domain interleaving ADC testing through the synergistic optimization of four modules (clock frequency reduction, latch, clock serialization and output serialization), that is, M parallel high-frequency clock signals and quantization codes are respectively frequency-reduced to fs / N, after hierarchical serialization synthesis with strict phase alignment, a lossless single high-frequency interleaving clock and data stream are output, the output signal complexity is significantly reduced while the original signal phase relationship and data integrity are ensured, hardware-level redundancy support is provided for multi-channel independent testing, and finally a high-precision, high-flexibility and low-jitter high-speed ADC testing solution is achieved. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a structural composition schematic diagram of the frequency reduction serialization output network for high-speed time domain interleaving ADC testing provided by the application;

[0009] Figure 2 is a structural composition schematic diagram of the clock frequency reduction module;

[0010] Figure 3is a circuit connection schematic diagram of a clock frequency reduction circuit DECI provided by an embodiment of the present application;

[0011] Figure 4 is a circuit connection schematic diagram of a first clock frequency reduction start circuit DECI_START1 provided by an embodiment of the present application;

[0012] Figure 5 is a circuit connection schematic diagram of a second clock frequency reduction start circuit DECI_START2 provided by an embodiment of the present application;

[0013] Figure 6 is a circuit connection schematic diagram of a DIV-N module provided by an embodiment of the present application;

[0014] Figure 7 is a waveform change schematic diagram before and after a swallowing module works provided by an embodiment of the present application;

[0015] Figure 8 is a waveform change schematic diagram before and after a clock frequency reduction module works provided by an embodiment of the present application;

[0016] Figure 9 is a circuit connection schematic diagram of a clock serialization module provided by an embodiment of the present application. DETAILED DESCRIPTION

[0017] The present application will be further described below in connection with specific embodiments, but the embodiments of the present application are not limited thereto.

[0018] In the description of the present application, the terms "first", "second", "third" and the like are used only to describe and distinguish one feature from another, and are not necessarily used to describe a relative importance or to implicitly indicate the number of the indicated technical features. Therefore, a feature defined with "first", "second", "third" or the like can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0019] In the description of the present application, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms is not necessarily directed to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in the present specification.

[0020] Although the application is described herein with reference to various embodiments, one skilled in the art will understand that other changes in the described embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from an inspection of the drawings, the disclosure, and the appended claims. The word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single processor or other unit can fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

[0021] A clock frequency reduction module for a high-speed time-domain interleaved analog-to-digital converter test is provided.

[0022] Figure 1 is a structural composition diagram of the clock frequency reduction module provided by the embodiment of the application. As shown in the figure, Figure 1 the clock frequency reduction module comprises (M-2) clock frequency reduction circuits DECI which are the same in structure; the (M-2) clock frequency reduction circuits are divided into two groups, i.e., a first group of (M-2) / 2 clock frequency reduction circuits DECI1 and a second group of (M-2) / 2 clock frequency reduction circuits DECI2, and the first group of clock frequency reduction circuits DECI1 and the second group of clock frequency reduction circuits DECI2 are connected in series.

[0023] First, the specific components of each structure are described. It should be noted that in the drawings, a D flip-flop is simply referred to as a DFF in the figure.

[0024] Figure 2 is a structural composition diagram of the clock frequency reduction module provided by the embodiment of the application. As shown in the figure, Figure 2 the clock frequency reduction module comprises (M-2) clock frequency reduction circuits DECI which are the same in structure; the (M-2) clock frequency reduction circuits are divided into two groups, i.e., a first group of (M-2) / 2 clock frequency reduction circuits DECI1 and a second group of (M-2) / 2 clock frequency reduction circuits DECI2, and the first group of clock frequency reduction circuits DECI1 and the second group of clock frequency reduction circuits DECI2 are connected in series. Figure 2The clock frequency reduction channel of odd number sequence is composed of clock frequency reduction circuits of odd number sequence, and the clock frequency reduction channel of even number sequence is composed of clock frequency reduction circuits of even number sequence.

[0025] The clock frequency reduction circuit of the highest number sequence in the clock frequency reduction channel of odd number sequence is connected with the first clock frequency reduction starting circuit DECI_START1, and the clock frequency reduction circuit of the highest number sequence in the clock frequency reduction channel of even number sequence is connected with the second clock frequency reduction starting circuit DECI_START2.

[0026] Specifically, Figure 3 is a circuit connection schematic diagram of the clock frequency reduction circuit DECI provided by the embodiment of the application, Figure 4 is a circuit connection schematic diagram of the first clock frequency reduction starting circuit DECI_START1 provided by the embodiment of the application, Figure 5 is a circuit connection schematic diagram of the second clock frequency reduction starting circuit DECI_START2 provided by the embodiment of the application, Figure 6 is a circuit connection schematic diagram of the DIV-N module provided by the embodiment of the application. It should be noted that the same label in the figure means the same connection end.

[0027] As Figure 3 shown, the i-th clock frequency reduction circuit comprises a first frequency division delay circuit, a first D flip-flop, a second D flip-flop and a first DIV-N module; the RST ends of the first D flip-flop and the second D flip-flop are connected with an external signal PWRD i ; i is less than or equal to (M-2); wherein: the first input end of the first frequency division delay circuit and the input end of the first DIV-N module are connected with a single-channel sampling clock signal CLK i , the second input end is connected with the first output end of the adjacent clock frequency reduction circuit to receive a starting signal START i+1 generated by the i+1-th clock frequency reduction circuit, the output end of the first frequency division delay circuit is connected with the CLK end of the first D flip-flop and the CLK end of the second D flip-flop respectively; the D end of the first D flip-flop is connected with a power supply VDD, and the Q end is connected with the D end of the second D flip-flop; the Q end of the second D flip-flop is connected with the RST end of the first DIV-N module, and the output end of the first DIV-N module outputs a clock signal CLK i _DIV; the Q end of the second D flip-flop is also used to generate a starting signal STARTi .

[0028] like Figure 5 As shown, the second clock frequency reduction start-up circuit includes: a third D flip-flop, a fourth flip-flop, and a second DIV-N module; the RST terminals of both the third and fourth flip-flops are connected to the external signal PWRD. M Wherein: the D terminal of the third D flip-flop is connected to the power supply VDD, the Q terminal is connected to the D terminal of the fourth flip-flop, and the RST terminals of both the third and fourth D flip-flops are connected to the external signal PWRD. M The Q input of the fourth flip-flop is connected to the RST input of the second DIV-N module, and the output of the second DIV-N module outputs a down-frequency clock signal CLK. M _DIV; The Q output of the fourth D flip-flop is also used to generate a start signal START to activate the clock down-conversion circuit with the highest sequence number in the even-numbered clock down-conversion channel. M .

[0029] like Figure 4 As shown, the first clock frequency reduction start-up circuit includes: a second frequency divider delay circuit, a fifth D flip-flop, a sixth D flip-flop, a seventh D flip-flop, an eighth D flip-flop, and a third DIV-N module; the RST terminal of each D flip-flop is connected to an external signal PWRD. M-1 Specifically: the D terminals of the fifth and seventh D flip-flops are both connected to the power supply VDD; the D terminal of the sixth D flip-flop is connected to the Q terminal of the fifth D flip-flop; and the D terminal of the eighth D flip-flop is connected to the Q terminal of the seventh D flip-flop. The CLK terminals of the fifth and seventh D flip-flops are both connected to a single-channel sampling clock signal CLK. M-1 The Q terminal of the sixth D flip-flop is connected to the RST terminal of the second frequency divider / delay circuit, and the input of the second frequency divider / delay circuit is connected to the single-channel sampling clock signal CLK. M-1 The output terminals are connected to the CLK terminals of the seventh and eighth D flip-flops, respectively. The Q terminal of the eighth D flip-flop is connected to the RST terminal of the third DIV-N module. The input terminal of the third DIV-N module is connected to the single-channel sampling clock signal CLK. M-1 The output terminal outputs a down-frequency clock signal CLK. M-1 _DIV; The Q input of the eighth D flip-flop is also used to generate a start signal START to activate the clock down-conversion circuit with the highest sequence number in the odd-sequence clock down-conversion channel. M-1 .

[0030] like Figure 6 As shown, Figure 3 to Figure 5The DIV-N module structures involved in the method are all the same, that is, all the DIV-N module structures are the same, each DIV-N module comprises a main frequency divider, a pre-frequency divider and a swallowing module; the pre-frequency divider is configured to perform initial frequency division processing on an access single-channel sampling clock signal to generate a preliminary reduced frequency clock signal; the main frequency divider is configured to perform secondary frequency division on the preliminary reduced frequency clock signal to generate a reduced frequency clock signal; and the swallowing module is configured to synchronously monitor a counter state of the main frequency divider, and forcibly reset to zero when the counter state of the main frequency divider reaches a preset value, so as to dynamically cut off the frequency division period of the entire DIV-N module, thereby adjusting the comprehensive frequency division ratio of the main frequency divider and the pre-frequency divider.

[0031] Here, the pre-frequency divider comprises S1 cascaded D flip-flops; the main frequency divider comprises S2 cascaded D flip-flops; and the swallowing module comprises an AND gate, a D flip-flop DFFa and a D flip-flop DFFb; wherein: the CLK end of each D flip-flop in the pre-frequency divider is connected to an access single-channel sampling clock signal, the RST end of the first (S1-1) flip-flop in the pre-frequency divider is connected to an external reset signal; the D end of the first D flip-flop in the pre-frequency divider and the QB end of the S1th D flip-flop are connected; the RST end of the S1th D flip-flop in the pre-frequency divider is connected to the Q end of the D flip-flop DFFb in the swallowing module; the Q end of the first D flip-flop in the pre-frequency divider is also connected to the CLK end of each D flip-flop in the main frequency divider; the D end of the first D flip-flop in the main frequency divider and the QB end of the S2th D flip-flop are connected; the RST end of each D flip-flop in the main frequency divider is connected to a reset signal; the Q end of the S2th D flip-flop in the main frequency divider outputs a reduced frequency clock signal; the QB end of the first D flip-flop in the main frequency divider is connected to one input end of the AND gate in the swallowing module and outputs a T1B signal, and the QB end of the second D flip-flop in the main frequency divider is connected to the other input end of the AND gate in the swallowing module and outputs a TS2B signal; the output end of the AND gate is connected to the RST end of the D flip-flop DFFa, the CLK end of the D flip-flop DFFa is connected to a signal F(S1-j)B, the D end of the D flip-flop DFFa is connected to a power supply VDD, the QB end is connected to the RST end of the D flip-flop DFFb, the CLK end of the D flip-flop DFFb is connected to a signal F(S1-1)B, and the D end of the D flip-flop DFFb is connected to the power supply VDD.

[0032] Here, the swallowing module achieves the requirement by adjusting the frequency division multiple of the pre-frequency divider. The pre-frequency divider and the main frequency divider are respectively composed of S1 and S2 D flip-flops, and the frequency division multiple that can be achieved is 4·S1·S2-j (j=2, 3, …, S1-1). The working process of the DIV-N module will be described in combination with an example. Specifically, Figure 7is a waveform change schematic diagram before and after the swallowing module provided by the embodiment of the application. It is assumed that the pre-frequency divider stage number S1=3 (3-stage D flip-flop), the main frequency divider stage number S2=2 (2-stage D flip-flop), the swallowing adjustment value j=2, the target frequency division ratio N=4xS1xS2-j=4x3x2-2=22, and the input clock Fin period Ts=1 ns. In the initial state, the RST end of all D flip-flops is at the low level, and the output is zero; after a period of time, the RST end is at the high level, and the reset ends. Fin (single-channel sampling clock) is connected to the CLK end of each D flip-flop of the pre-frequency divider. First, the 3-stage D flip-flop of the pre-frequency divider processes the normal frequency division ratio 2xS1=6, and outputs F1=Fin / 6 (period 6 ns); the F1 signal is sent to the CLK end of each flip-flop of the main frequency divider. Subsequently, the main frequency divider processes, and the swallowing module monitors the main frequency divider, and generates a valid pulse with a pulse width of S1xTs=3 ns when T1B and TS2B are high at the same time (occur once every 4xS1xS2=24 Fin periods). When the valid pulse is effective, the D flip-flop DFFa is reset, and the F(S1-j)B signal is connected, F(S1-j)B=F(3-2)B=F1B. When the rising edge of F1B arrives, DFFa samples, so that the Q end is 1 and the QB end is 0. The QB end of DFFa is 0, which pulls down the RST end of DFFb, forcing DFFb to reset, RST_R=0, that is, the last stage of the pre-frequency divider is reset, forcing the output FS1 to flip 2 Fin periods in advance, and the current frequency division period is shortened to 2xS1-j=6-2=4 (instead of the normal 6). At the same time, the valid signal is quickly pulled down after FS1 flips, and the QB end of DFFa outputs a high level. When the rising edge of F2B arrives, DFFb samples VDD and flips RST_R, so that the last stage of the pre-frequency divider is reset. The main frequency divider receives 4xS2=8 F1 pulses in the complete period (originally 4xS1xS2=24 Fin periods), and due to the swallowing action, the actual consumption is 24-j=22 Fin periods to complete a Tout period -> achieve 22 frequency division.

[0033] The three-step mechanism of swallowing window monitoring -> pre-frequency divider dynamic reset -> anti-interference timing recovery realizes accurate control of the frequency division ratio (j value control) in the ultra-low delay path, and provides a high-flexible programmable clock frequency reduction core module for high-speed TI-ADC testing.

[0034] The working principle of the clock frequency reduction module is described in the form of examples.

[0035] When the system starts, the reset signal PWRD i(i = 1, 2, ..., M) synchronously acts on all clock down-frequency circuits and their corresponding startup circuits, forcing all D flip-flops and DIV-N module counters to zero, clearing their internal states, and providing initial conditions for down-frequency operation; after the reset, the first clock down-frequency startup circuit DECI_START1 (channel M-1) and the second clock down-frequency startup circuit DECI_START2 (channel M) respectively operate on the single-channel sampling clock CLK M-1 and CLK M Activated under control, each generating a start signal START. M-1 and START M This triggers the reverse start chain of the odd-even downclocking channel. Specifically, the odd-channel clock downclocking channel starts with START. M-1 Start the highest sequence channel M-1, and then trigger the odd-numbered channels M-3, M-5, ... in sequence; the even-numbered clock channels are downclocked starting with START. M Channel M is activated, and channels M-2, M-4, ... are triggered sequentially in even-numbered order. The activation interval between adjacent channels is (M-1) / M times the single-channel clock period Ts (e.g., when M=8, the interval is 7Ts / 8), which is significantly better than the Ts / M interval for sequential activation, avoiding timing conflicts in high-speed multi-channel operation. Each activated clock frequency down-division circuit DECI receives the previous stage activation signal and the sampling clock CLK of this channel through a frequency division and delay circuit. i A synchronization enable signal is generated by two D flip-flops to unlock the first DIV-N module from CLK. i Frequency division, outputting a down-frequency clock CLK with a duty cycle of approximately 1 / 2MHz. i _DIV, simultaneously generating the next-level start signal START. i The low-sequence-number channel is driven. The odd / even channels are internally aligned in phase using a first frequency divider and delay circuit; the phase difference between the odd and even sequence clock down-frequency channels is calibrated using a second frequency divider and delay circuit to ensure that the M down-frequency clocks strictly meet the interleaving phase requirements. Combined with the DIV-N module, the frequency division period can be flexibly controlled, resulting in a simple design that effectively meets the requirements of different down-frequency circuits. This is achieved through an independent reset signal PWRD. i The frequency reduction circuit of channel i can be reset independently to stop it from outputting CLK. i The _DIV channel is disabled, while the other channels continue to operate. Because the clock serialization module is implemented using pure OR logic, the failure of a single channel does not affect the interleaved output of other channels. Channel selective shielding can be achieved without additional flag bits, greatly simplifying the ADC single-channel testing process.

[0036] Figure 8 This is a schematic diagram showing the waveform changes before and after the clock down-frequency module provided in this embodiment of the invention operates. For example... Figure 8 As shown, Figure 8 (a) in the diagram is a waveform diagram of a single-channel sampling clock signal.Figure 8 The waveform diagram of the (b) in the figure is a waveform diagram of a downclock signal. It can be seen from the two figures that the downclock retains the phase interleaving characteristics of the original clock completely under the premise of frequency reduction, and the clock quality is optimized through dynamic frequency control, thereby providing a processable clock signal for high-speed TI-ADC testing.

[0037] Figure 9 The figure is a schematic diagram of the circuit connection of the clock serialization module and the output serialization module provided by the embodiment of the application. As shown in the figure, Figure 9 The clock serialization module comprises: log4M stages of four-input OR gates connected in series, wherein the kth stage of four-input OR gate comprises independent OR gates, two inverters are arranged at the output end of each OR gate in each stage of four-input OR gate as a buffer to enhance the driving of the next stage; k is a stage number, k≥1; wherein the input end of the first stage of four-input OR gate is connected to M downclock signals, every 4 downclock signals drive 1 OR gate, and the output end outputs The kth stage of four-input OR gate receives the clock serialization signals output by the k-1th stage of four-input OR gate, and outputs The last stage of four-input OR gate collects the multiple clock serialization signals output by the previous stage of four-input OR gate, and outputs an interleaved clock signal.

[0038] The output serialization module comprises: log4M stages of MUX groups connected in series, wherein the kth stage of MUX group comprises independent four-to-one MUX devices; the M input ends of the first stage of MUX group are connected to M groups of downclock quantization codes, every 4 groups of downclock quantization codes drive 1 four-to-one MUX device, and the first stage of MUX group outputs The kth stage of MUX group receives the group signals output by the k-1th stage of MUX group, and outputs The last stage of MUX group collects the multiple group signals output by the previous stage of MUX group, and outputs a synthetic quantization code.

[0039] Correspondingly, the latch module comprises: M groups of independent D flip-flops, the Q end of each group of D flip-flops is connected with one input end of the first stage of MUX group, and the CLK end is connected with one output end of the clock downclock module.

[0040] In order to solve the problem that the existing serialization frequency reduction structure is difficult to meet the ADC test requirement, the embodiment of the present application provides a frequency reduction serialization output network for high-speed time domain interleaving analog-digital converter test, through the four-stage module (clock frequency reduction, latch, clock serialization and output serialization) of cooperative optimization, the key function in the high-speed time domain interleaving ADC test is realized: the M parallel high-frequency clock signals and the quantization code are respectively reduced to fs / N, after the hierarchical serialization synthesis of phase strict alignment, the lossless single high-frequency interleaving clock and data stream are output, while the original signal phase relationship and data integrity are ensured, the output signal complexity is significantly reduced, the hardware level redundancy support is provided for the multi-channel independent test, and finally the high-precision, high-flexibility high-speed ADC test solution is achieved.

[0041] The above is the further detailed description of the present application in combination with the specific preferred embodiments, and the specific implementation of the present application cannot be limited to these descriptions. For the ordinary skilled in the art to which the present application belongs, some simple deductions or replacements can be made without departing from the concept of the present application, and all of them shall be regarded as falling within the protection scope of the present application.

Claims

1. A derating serializing output network for high-speed time-interleaved analog-to-digital converter testing, comprising: The clock frequency reduction module, the clock serialization module, the latch module and the output serialization module are included. M input ends of the clock frequency reduction module are connected to single-channel sampling clock signals with a frequency of fs respectively, for performing frequency reduction processing on the M single-channel sampling clock signals to obtain M frequency-reduced clock signals with a frequency of fs / N, the M frequency-reduced clock signals are transmitted to M input ends of the clock serialization module and M control ends of the latch module, and M is a positive integer; The clock serialization module is configured to serialize the M frequency-reduced clock signals to obtain a high-frequency interleaving clock signal with a frequency of (M / N)fs and transmit the high-frequency interleaving clock signal to the output serialization module; The latch module is configured to perform frequency reduction latching on M quantization codes input thereto in response to the M frequency-reduced clock signals and output M groups of frequency-reduced quantization codes of a current period; A control end of the output serialization module is connected to clock serialization signals generated by the clock serialization module during serialization processing and the high-frequency interleaving clock signal, and M input ends of the output serialization module are connected to the M groups of frequency-reduced quantization codes, and the output serialization module is configured to serialize the M groups of frequency-reduced quantization codes in response to the clock serialization signals to obtain a group of synthetic quantization codes with a frequency of (M / N)fs. The clock frequency reduction module includes (M-2) clock frequency reduction circuits with the same structure; 2. The reduced-rate serializing output network for high-speed time-interleaved analog-to-digital converter testing of claim 1, wherein, The (M-2) clock frequency reduction circuits are divided into an odd-numbered clock frequency reduction channel composed of clock frequency reduction circuits with odd serial numbers and an even-numbered clock frequency reduction channel composed of clock frequency reduction circuits with even serial numbers; The highest-numbered clock frequency reduction circuit in the odd-numbered clock frequency reduction channel is connected to a first clock frequency reduction start circuit, the highest-numbered clock frequency reduction circuit in the even-numbered clock frequency reduction channel is connected to a second clock frequency reduction start circuit, and the first clock frequency reduction start circuit and the second clock frequency reduction start circuit are configured to be started synchronously. The clock frequency reduction circuits in the odd-numbered clock frequency reduction channel and the even-numbered clock frequency reduction channel are started in order from the highest-numbered clock frequency reduction circuit to the lowest-numbered clock frequency reduction circuit. All DIV-N modules have the same structure, and each DIV-N module includes a main frequency divider, a pre-frequency divider and a swallowing module.

3. The reduced-rate serializing output network for high-speed time-interleaved analog-to-digital converter testing of claim 2, wherein, The i-th clock frequency reduction circuit comprises: a first frequency division delay circuit, a first D flip-flop, a second D flip-flop and a first DIV-N module; the RST end of the first D flip-flop and the second D flip-flop are connected to an external signal PWRD i ; i is less than or equal to (M-2); wherein: The first input end of the first frequency division delay circuit and the input end of the first DIV-N module are connected to a single-channel sampling clock signal CLK i The second input end is connected to the first output end of the adjacent clock frequency reduction circuit to receive a start signal START generated by the i+1th clock frequency reduction circuit i+1 The output end of the first frequency division delay circuit is connected to the CLK end of the first D flip-flop and the CLK end of the second D flip-flop respectively; the D end of the first D flip-flop is connected to the power supply VDD, and the Q end is connected to the D end of the second D flip-flop; the Q end of the second D flip-flop is connected to the RST end of the first DIV-N module, and the output end of the first DIV-N module outputs a frequency-reduced clock signal CLK i _DIV; The Q terminal of the second D flip-flop is also used to generate a start signal START for starting the i-1th clock frequency reduction circuit i .

4. The reduced-rate serializing output network for high-speed time-interleaved analog-to-digital converter testing of claim 2, wherein, The second clock frequency reduction starting circuit comprises a third D flip-flop, a fourth flip-flop and a second DIV-N module; the RST end of the third D flip-flop and the fourth flip-flop are connected to an external signal PWRD M ; wherein: The D end of the third D flip-flop is connected to a power supply VDD, the Q end is connected to the D end of the fourth flip-flop, and the RST ends of the third D flip-flop and the fourth flip-flop are connected to the external signal PWRD M ; the Q end of the fourth flip-flop is connected to the RST end of the second DIV-N module, and the output end of the second DIV-N module outputs a frequency-reduced clock signal CLK M _DIV; The Q terminal of the fourth D flip-flop is also used to generate a start signal START for starting the clock frequency reduction circuit with the highest sequence number in the even sequence clock frequency reduction channel M .

5. The reduced-rate serializing output network for high-speed time-interleaved analog-to-digital converter testing of claim 2, wherein, The first clock frequency reduction starting circuit comprises a second frequency division delay circuit, a fifth D flip-flop, a sixth D flip-flop, a seventh D flip-flop, an eighth D flip-flop and a third DIV-N module; the RST end of each D flip-flop is connected to an external signal PWRD M-1 ; wherein: The D terminal of the fifth D flip-flop and the D terminal of the seventh D flip-flop are connected to a power supply VDD, the D terminal of the sixth D flip-flop is connected to the Q terminal of the fifth D flip-flop, and the D terminal of the eighth D flip-flop is connected to the Q terminal of the seventh D flip-flop; the CLK terminal of the fifth D flip-flop and the CLK terminal of the seventh D flip-flop are connected to a single-channel sampling clock signal CLK M-1 ​ The Q end of the sixth D flip-flop is connected with the RST end of the second frequency division delay circuit, the input end of the second frequency division delay circuit is connected with the single-channel sampling clock signal CLK M-1 , the output end is connected with the CLK end of the seventh D flip-flop and the CLK end of the eighth D flip-flop respectively, the Q end of the eighth D flip-flop is connected with the RST end of the third DIV-N module, the input end of the third DIV-N module is connected with the single-channel sampling clock signal CLK M-1 , and the output end outputs a frequency-reduced clock signal CLK M-1 _DIV. The Q terminal of the eighth D flip-flop is also used to generate a start signal START for starting the clock frequency reduction circuit with the highest serial number in the odd-numbered serial clock frequency reduction channel M-1 .

6. The reduced-rate serializing output network for high-speed time-interleaved analog-to-digital converter testing of any of claims 3-5, wherein, The pre-frequency divider is configured to perform initial frequency division processing on a single-channel sampling clock signal to generate a preliminary frequency-reduced clock signal. The main frequency divider is configured to perform secondary frequency division on the preliminary frequency-reduced clock signal to generate a frequency-reduced clock signal. The swallowing module is configured to synchronously monitor a counter state of the main frequency divider, forcibly reset the counter state when the counter state of the main frequency divider reaches a preset value, dynamically cut off a frequency division period of the entire DIV-N module, and thus adjust a comprehensive frequency division ratio of the main frequency divider and the pre-frequency divider. The pre-frequency divider includes S1 cascaded D flip-flops, the main frequency divider includes S2 cascaded D flip-flops, and the swallowing module includes an AND gate, a D flip-flop DFFa and a D flip-flop DFFb.

7. The reduced-rate serializing output network for high-speed time-interleaved analog-to-digital converter testing of claim 6, wherein, ​ The CLK end of each D flip-flop in the pre-divider is connected to a single-channel sampling clock signal, and the RST end of the first (S1-1) flip-flop in the pre-divider is connected to an external reset signal; the D end of the first D flip-flop in the pre-divider is connected to the QB end of the S1th D flip-flop; and the RST end of the S1th D flip-flop in the pre-divider is connected to the Q end of the D flip-flop DFFb in the swallowing module. The Q end of the first D flip-flop in the pre-divider is also connected to the CLK end of each D flip-flop in the main divider; the D end of the first D flip-flop in the main divider is connected to the QB end of the S2th D flip-flop; the RST end of each D flip-flop in the main divider is connected to the reset signal; and the Q end of the S2th D flip-flop in the main divider outputs a reduced clock signal. The QB end of the first D flip-flop in the main divider is connected to one input end of the AND gate in the swallowing module and outputs a T1B signal; the QB end of the second D flip-flop in the main divider is connected to the other input end of the AND gate in the swallowing module and outputs a TS2B signal; the output end of the AND gate is connected to the RST end of the D flip-flop DFFa; the CLK end of the D flip-flop DFFa is connected to the signal F(S1-j)B; the D end of the D flip-flop DFFa is connected to the power supply VDD; the QB end of the D flip-flop DFFa is connected to the RST end of the D flip-flop DFFb; the CLK end of the D flip-flop DFFb is connected to the signal F(S1-1)B; and the D end of the D flip-flop DFFb is connected to the power supply VDD.

8. The reduced-rate serializing output network for high-speed time-interleaved analog-to-digital converter testing of claim 1, wherein, The clock serialization module comprises: log4M levels of four-input OR gates connected in series one after another, wherein one independent OR gate is contained in the kth level of four-input OR gate, and an inverter is arranged at the 4 input ends and the output end of each OR gate in each level of four-input OR gate; k is a level serial number, k>=1; The input end of the first-stage four-input OR gate is connected with M downclock signals, every 4 downclock signals drive 1 OR gate, and the output is the kth-stage four-input OR gate receives the output of the (k-1)th-stage four-input OR gate and outputs the last-stage four-input OR gate collects the outputs of the previous-stage four-input OR gates and outputs the interleaved clock signal.

9. The reduced-rate serializing output network for high-speed time-interleaved analog-to-digital converter testing of claim 8, wherein, The output serialization module includes log4M stages of MUX groups, wherein the kth stage of MUX groups includes four independent 1-in-4 MUX devices; The M inputs of the first-stage MUX group are connected to the M groups of down-quantized codes, every 4 groups of down-quantized codes drive a 4-to-1 MUX device, and the output is a group signal, the kth-stage MUX group receives the (k-1)th-stage MUX group output group signal, and outputs a group signal; the last-stage MUX group collects the multiple group signals output by the previous-stage MUX groups, and outputs the synthetic quantized code.

10. The reduced-rate serializing output network for high-speed time-interleaved analog-to-digital converter testing of claim 9, wherein, The latch module comprises M groups of independent D flip-flops, the Q end of each group of D flip-flops is connected to one input end of the first-level MUX group, and the CLK end is connected to one output end of the clock frequency reduction module.

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