Coding method, decoding method and communication device

Abstract

The invention provides a coding method, a decoding method and a communication device. According to the method, information bits are selected in two stages, T information bits are selected in the first stage, K-T information bits are selected in the second stage, the method is beneficial to accurately selecting the bit with the highest reliability as the information bit, the coding and decoding performance (such as error correction performance) can be improved, and then the communication performance can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of wireless communication, and in particular to an encoding method, a decoding method and a communication device. BACKGROUND

[0002] Polar code is the first encoding scheme that can be strictly proved to "reach" the Shannon channel capacity, and has the advantages of good decoding performance and low complexity. Polar code has been determined by the 3rd generation partnership project (3GPP) to be the control channel encoding scheme for the enhanced mobile broadband (eMBB) scenario.

[0003] Suppose the encoding length of the Polar code is N (where N is an integer power of 2), the encoding length is E, and the length of the information bit sequence to be encoded is K, that is, the information bit sequence to be encoded includes K bits, and K is an integer greater than 1 and less than E. For Polar code supporting rate matching, in the case of shortening or puncturing rate matching method, the process of determining K information bits by the sending end device is as follows: first, pre-freeze N-E bit positions in N bit positions that need to be rate matched (which can be referred to as rate matching bit pre-freezing); then, sort the reliabilities of the remaining E bit positions, and select the K bit positions with the highest reliabilities from the E bit positions as information bit positions, and the K information bit positions are used to carry the K bits in the information bit sequence to be encoded.

[0004] After determining the K information bit positions, the sending end device encodes the information bit sequence to be encoded according to the K information bit positions, obtains a coded bit sequence with a length of N, then performs rate matching on the coded bit sequence with a length of N according to the N-E bit positions that need to be rate matched, that is, puncturing or shortening N-E bit positions, obtains a coded bit sequence with a length of E, and then sends the coded bit sequence with a length of E to the receiving end device.

[0005] The above method has the following problems: due to the introduction of rate matching bit positions, the reliability sorting of information bit positions may change, that is, before rate matching, the selected K information bit positions are the K bit positions with the highest reliabilities, and after rate matching, the reliabilities of some or some of the K information bit positions may decrease, resulting in that the previously selected K information bit positions are not the optimal K information bit positions after rate matching, thereby causing the performance of the constructed Polar code to decrease, and further affecting the communication quality. SUMMARY

[0006] Embodiments of the present application provide an encoding method, a decoding method and a communication device to improve communication quality.

[0007] In a first aspect, the embodiments of the present application provide an encoding method, which can be executed by a first device. In the present application, the first device can refer to the first device itself (for example, a terminal device or a network device), a component (for example, a communication module, a processor, a circuit, a chip or a chip system) in the first device, or a logic module or software capable of realizing all or part of the functions of the first device. The method comprises the following steps: obtaining an information bit sequence to be encoded, the information bit sequence comprising K bits, K being an integer greater than 1; determining a first information bit position set according to a first bit position set and a first reliability sequence of a polar code; wherein the first bit position set is used to indicate the bit positions in the first reliability sequence that are frozen when the first information bit position set is determined, the first reliability sequence is used to indicate the order of the reliability degrees of the bit positions in the polar code, and the first information bit position set is used to indicate T bit positions, the T bit positions being used to carry T bits in the K bits, T being a positive integer; determining a second information bit position set according to a second bit position set and the first reliability sequence; wherein the second bit position set is used to indicate the bit positions in the first reliability sequence that are frozen when the second information bit position set is determined, and the second information bit position set is used to indicate K-T bit positions, the K-T bit positions being used to carry K-T bits in the K bits other than the T bits; and performing polar code encoding on the information bit sequence according to the first information bit position set and the second information bit position set to obtain an encoded bit sequence.

[0008] The first bit position set is also referred to as a first frozen bit position set or a first pre-frozen bit position set. The second bit position set is also referred to as a second frozen bit position set or a second pre-frozen bit position set.

[0009] The K bits in the information bit sequence can all be payload bits, or can comprise payload bits and check bits.

[0010] The above scheme selects information bit positions in two stages, wherein T information bit positions are selected in the first stage, and K-T information bit positions are selected in the second stage. This method helps to accurately select the bit positions with the highest reliability as information bit positions, and can improve the encoding and decoding performance (for example, error correction performance), thereby improving the communication performance.

[0011] In a second aspect, an embodiment of the present application provides a decoding method, which can be executed by a second device. Unless specifically stated, the "second device" in the present application can refer to the second device itself (for example, a terminal device or a network device), a component (for example, a communication module, a processor, a circuit, a chip, or a chip system) in the second device, or a logic module or software capable of realizing all or part of the functions of the second device. The method comprises: obtaining an encoded bit sequence, the encoded bit sequence comprising an information bit sequence, the information bit sequence comprising K bits, K being an integer greater than 1; determining a first information bit position set according to a first bit position set and a first reliability sequence of a polar code; wherein the first bit position set is used to indicate the bit positions in the first reliability sequence that are frozen when determining the first information bit position set, the first reliability sequence is used to indicate the order of reliability of the bit positions in the polar code, and the first information bit position set is used to indicate T bit positions, the T bit positions being used to carry T bits in the K bits, T being a positive integer; determining a second information bit position set according to a second bit position set and the first reliability sequence; wherein the second bit position set is used to indicate the bit positions in the first reliability sequence that are frozen when determining the second information bit position set, and the second information bit position set is used to indicate K-T bit positions, the K-T bit positions being used to carry K-T bits in the K bits other than the T bits; and performing polar code decoding on the encoded bit sequence according to the first information bit position set and the second information bit position set to obtain the information bit sequence.

[0012] The above scheme selects information bit positions in two stages, wherein T information bit positions are selected in the first stage, and K-T information bit positions are selected in the second stage. This method helps to accurately select the bit positions with the highest reliability as information bit positions, and can improve the encoding and decoding performance (for example, error correction performance), thereby helping to improve the communication performance.

[0013] Based on the first aspect or the second aspect, any one or more of the following implementation methods can be provided:

[0014] In a possible implementation method, the first bit position set is used to indicate the punctured or shortened bit positions.

[0015] In a possible implementation method, the first bit position set is the same as a rate matching position set, and the rate matching position set is used to indicate the punctured or shortened bit positions.

[0016] In a possible implementation method, wherein, represents the upward rounding.

[0017] In a possible implementation, T is related to one or more of K, E, R or N; wherein E represents a length of the coded bit sequence, R represents a code rate and R=K / E, and N represents a coding length of the polar code.

[0018] The above scheme flexibly configures the size of T, which helps to select reliable bit positions as information bit positions, thereby improving coding and decoding performance, and further improving communication performance.

[0019] In a possible implementation, T increases as K increases.

[0020] The above scheme flexibly configures the size of T, which helps to select reliable bit positions as information bit positions, thereby improving coding and decoding performance, and further improving communication performance.

[0021] In a possible implementation, T increases as R increases.

[0022] The above scheme flexibly configures the size of T, which helps to select reliable bit positions as information bit positions, thereby improving coding and decoding performance, and further improving communication performance.

[0023] In a possible implementation, when E / N is greater than or equal to Z0, T increases as E / N increases; when E / N is less than Z0 and greater than or equal to Z1, T does not change with the change of E / N; when E / N is less than Z1, T decreases as E / N increases; wherein Z0 and Z1 are both greater than 0 and less than 1, and Z0 is greater than Z1.

[0024] The above scheme flexibly configures the size of T, which helps to select reliable bit positions as information bit positions, thereby improving coding and decoding performance, and further improving communication performance.

[0025] In a possible implementation, when 9 / 16<=E / N, when 17 / 32<=E / N<9 / 16, when E / N<17 / 32, wherein, indicates rounding up.

[0026] In a possible implementation, the code rate R is less than or equal to 7 / 8.

[0027] In a possible implementation, the first bit position set includes a rate matching position set, and the number of bit positions in the first bit position set is greater than the number of bit positions in the rate matching position set, the rate matching position set being used to indicate punctured or shortened bit positions.

[0028] In a possible implementation, the first set of bit positions is a proper subset of the second set of bit positions.

[0029] In a possible implementation, T is related to one or more of K, E or N; where E represents the length of the coded bit sequence, and N represents the coding length of the polar code.

[0030] The above scheme flexibly configures the size of T, which helps to select reliable bit positions as information bit positions, thereby improving coding and decoding performance, and further improving communication performance.

[0031] In a possible implementation, the T increases with the increase of the K.

[0032] The above scheme flexibly configures the size of T, which helps to select reliable bit positions as information bit positions, thereby improving coding and decoding performance, and further improving communication performance.

[0033] In a possible implementation, the T increases with the increase of the E / N.

[0034] The above scheme flexibly configures the size of T, which helps to select reliable bit positions as information bit positions, thereby improving coding and decoding performance, and further improving communication performance.

[0035] In a possible implementation, when 3 / 4 <= E / N, when 5 / 8 <= E / N < 3 / 4, when E / N < 5 / 8, wherein, represents upward rounding.

[0036] In a possible implementation, the bit positions in the first set of bit positions are consecutive bit positions in a natural order bit sequence, the natural order bit sequence is composed of consecutive N bit positions sorted in ascending order, and N represents the coding length of the polar code.

[0037] In a possible implementation, the first set of information bit positions has no intersection with the second set of information bit positions, and the reliability of the bit positions in the second set of information bit positions is lower than the reliability of the bit positions in the first set of information bit positions.

[0038] In a possible implementation, the serial numbers of the bit positions in the second set of information bit positions are all greater than or equal to N / 2, where N represents the coding length of the polar code.

[0039] In a possible implementation, the bit positions in the second set of bit positions are consecutive bit positions in a natural order bit sequence, the natural order bit sequence being composed of consecutive N bit positions sorted in ascending order, and N representing the encoding length of the polar code.

[0040] In a possible implementation, the second set of bit positions is composed of the first N / 2 bit positions in the natural order bit sequence.

[0041] In a possible implementation, the number of bit positions in the first set of bit positions increases as N increases and decreases as E increases, where N represents the encoding length of the polar code and E represents the length of the encoding bit sequence.

[0042] In a possible implementation, the T bit positions are T bit positions with the highest reliability in a second reliability sequence, the second reliability sequence being composed of bit positions in the first reliability sequence other than the first set of bit positions.

[0043] In a possible implementation, the K-T bit positions are K-T bit positions with the highest reliability in a third reliability sequence other than the first set of information bit positions, the third reliability sequence being composed of bit positions in the first reliability sequence other than the second set of bit positions.

[0044] In a third aspect, an embodiment of the present application provides a communication apparatus, which has the function of implementing any implementation method of the first aspect. The function can be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions.

[0045] In a fourth aspect, an embodiment of the present application provides a communication apparatus, which has the function of implementing any implementation method of the second aspect. The function can be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions.

[0046] In a fifth aspect, an embodiment of the present application provides a communication apparatus, which includes units or means for performing each step of any implementation method of the first aspect to the second aspect.

[0047] In a sixth aspect, an embodiment of the present application provides a communication apparatus, which includes a processor and an interface circuit, the processor being configured to communicate with other apparatuses through the interface circuit and to perform any implementation method of the first aspect to the second aspect. The processor includes one or more.

[0048] Optionally, the communication apparatus can further comprise a memory for storing computer instructions, the memory being coupled to the processor, and the processor executes the computer instructions stored in the memory to cause the apparatus to perform any of the implementation methods of the first aspect to the second aspect.

[0049] In a seventh aspect, the embodiments of the present application further provide a computer program product, which comprises computer programs or instructions, and when the computer programs or instructions are run on the communication apparatus, any of the implementation methods of the first aspect to the second aspect are performed.

[0050] In an eighth aspect, the embodiments of the present application further provide a computer readable storage medium, which stores instructions, and when the instructions are run on the communication apparatus, any of the implementation methods of the first aspect to the second aspect are performed.

[0051] In a ninth aspect, the embodiments of the present application provide a chip (or chip system), which comprises a processor, the processor being coupled to a memory, and the memory stores computer programs; the processor is used to invoke part or all of the computer programs in the memory, so that any of the implementation methods of the first aspect to the second aspect are performed.

[0052] In a tenth aspect, the embodiments of the present application provide a communication system, which comprises a first device for performing any of the implementation methods of the first aspect, and a second device for performing any of the implementation methods of the second aspect. BRIEF DESCRIPTION OF DRAWINGS

[0053] Figure 1 A schematic diagram of an architecture of a communication system to which embodiments of the present application are applied;

[0054] Figure 2 A schematic diagram of a coding and decoding procedure provided by the embodiments of the present application;

[0055] Figure 3 An 8x8 polar transform matrix provided by the embodiments of the present application;

[0056] FIG. 4(a) is a schematic diagram of a coding method provided by the embodiments of the present application;

[0057] FIG. 4(b) is a schematic diagram of a decoding method provided by the embodiments of the present application;

[0058] Figure 5 A schematic diagram of another coding method provided by the embodiments of the present application;

[0059] Figure 6 A schematic diagram of another coding method provided by the embodiments of the present application;

[0060] Figure 7 A flowchart of another encoding method provided for an embodiment of the present application is shown in FIG. 6.

[0061] Figure 8 A structural diagram of a communication device provided for an embodiment of the present application is shown in FIG. 7.

[0062] Figure 9 A structural diagram of another communication device provided for an embodiment of the present application is shown in FIG. 8.

[0063] Figure 10 A structural diagram of another communication device provided for an embodiment of the present application is shown in FIG. 9.

[0064] Figure 11 A structural diagram of a chip system provided for an embodiment of the present application is shown in FIG. 10.

[0065] Figure 12 A structural diagram of another chip system provided for an embodiment of the present application is shown in FIG. 11. DETAILED DESCRIPTION

[0066] The technical solutions of the embodiments of the present application can be applied to various communication systems, such as a long term evolution (LTE) system, a 5th generation (5G) mobile communication system (such as a new radio (NR) system), and the like. The technical solutions provided by the present application can also be applied to future communication systems, such as a 6th generation (6G) mobile communication system, and the like. The communication system can also be a Bluetooth communication system, a wireless local area network (WLAN) communication system, a wireless fidelity (WiFi) communication system, an internet of things (IoT) communication system, and the like.

[0067] Figure 1 A structural diagram of a communication system to which an embodiment of the present application is applied is shown in FIG. 12. The communication system includes a network device and a terminal device, wherein, Figure 1 In the embodiment, the number of network devices is 1, and the number of terminal devices is 2 (i.e., terminal device A and terminal device B). When the network device is a sending end, the terminal device A or the terminal device B is a receiving end. When the terminal device A or the terminal device B is a sending end, the network device is a receiving end.

[0068] The terminal device can be widely applied to various scenarios, for example, device-to-device (D2D), vehicle to everything (V2X) communication, machine-type communication (MTC), internet of things (IoT), virtual reality, augmented reality, industrial control, automatic driving, remote medical treatment, smart power grid, smart furniture, smart office, smart wear, smart transportation, smart city, etc. The terminal device can be a mobile phone, a tablet computer, a computer with wireless transceiving function, a wearable device, a vehicle, a drone, a helicopter, an airplane, a ship, a robot, a mechanical arm, a smart home device, a vehicle-mounted terminal, an IoT terminal, a wearable device, etc. Embodiments of the present application do not limit specific technologies and specific device forms adopted by the terminal device.

[0069] The network device can also be referred to as an access network (AN) device, or a radio access network (RAN) device. It can be a base station, an evolved NodeB (eNodeB), a transmitter and receiver point (TRP), an integrated access and backhauling (IAB) node, a next generation NodeB (gNB) in a 5th generation (5G) mobile communication system, a base station in a 6G mobile communication system, a base station in other future mobile communication systems, or an access node in a WiFi system, a home base station (for example, a home evolved nodeB, or home nodeB (HNB)), an access point (AP) in a wireless fidelity (WIFI) system, a wireless relay node, a wireless backhaul node, etc. It can also be a module or unit that completes part of the functions of a base station, for example, it can be a central unit (CU), or a distributed unit (DU). The CU here completes the functions of the radio resource control protocol and the packet data convergence protocol (PDCP) of the base station, and can also complete the function of the service data adaptation protocol (SDAP); the DU completes the functions of the radio link control layer and the medium access control (MAC) layer of the base station, and can also complete the functions of part of the physical layer or the entire physical layer. For specific descriptions of the above-mentioned various protocol layers, reference can be made to the relevant technical specifications of 3GPP. The network device can also be a non-terrestrial base station, such as a low earth orbit (LEO) / very low earth orbit (VLEO) satellite, a high-attitude platform station (HAPS), and can also be a terminal that undertakes the function of a network device in V2X, D2D, and machine to machine (M2M) communication, etc.

[0070] In the embodiments of the present application, the functions of the network device can also be performed by a module (such as a chip) in the network device, or can be performed by a control subsystem containing the functions of the network device. The control subsystem containing the functions of the network device herein can be a control center in application scenarios such as smart grids, industrial control, intelligent transportation, and smart cities. The functions of the terminal device can also be performed by a module (such as a chip or a modem) in the terminal device, or can be performed by a device containing the functions of the terminal device.

[0071] Still taking the communication system shown in Figure 1 FIG. 1 as an example, in order to ensure the reliability of communication between devices, information can be processed by encoding and decoding, which can be processed by referring to the encoding and decoding process shown in Figure 2 FIG. 2. The source of the sending end outputs modulation symbols in sequence after joint source channel encoding and modulation. The receiving end obtains the sink in sequence after demodulation and joint source channel decoding based on the modulation symbols received. The receiving end can obtain useful information based on the sink.

[0072] In order to facilitate understanding of those skilled in the art, some terms in the embodiments of the present application are explained below.

[0073] I. Polar code

[0074] Polar code is the first encoding scheme that can be strictly proved to "reach" the Shannon channel capacity, and has the advantages of good decoding performance and low complexity. At present, polar code has been determined by 3GPP to be the encoding scheme of the control channel in the eMBB scenario.

[0075] II. Polar code encoding

[0076] Polar code is a linear block code, where the polar transformation matrix is G N , the polar transformation matrix can also be denoted as G, and the polar transformation matrix can also be called an encoding matrix or a generator matrix. The encoding process is where is a binary row vector, that is, a binary sequence, with a length of N, and N is the code length of the polar code; G N is an N×N matrix, and can be defined as the Kronecker product of log2N matrices F2. Among them

[0077] In the encoding process of the polar code, Some of the bits are used to carry information, the bits used to carry information are called information bits, the part of the bits used to carry information forms a set of information bits, the set of bit indices of these bits is denoted as A; another part of the bits is set to a fixed value agreed by the receiving end and the sending end in advance, which is called a set of fixed bits or a set of frozen bits, and the set of bit indices thereof is the complement of A c . The encoding process of the polar code is equivalent to: Here, G N (A) is a submatrix obtained by the rows corresponding to the bit indices in the set A in G N . G N (A C ) is a submatrix obtained by the rows corresponding to the bit indices in the set A N in G c . μ A is the set of information bits in , the number of which is K; is the set of frozen bits in , the number of which is (N-K), which is a known bit. These frozen bits are usually set to 0, but as long as the receiving end and the sending end agree in advance, the frozen bits can be set arbitrarily. The encoding output of the polar code can be simplified as: Here μ A is the set of information bits in , μ A is a row vector of length K, that is, |A|=K, |A| represents the number of elements in the set A, K is the information block size, or K is the number of information bits, or K is the size of the information bit set, G N (A) is a submatrix obtained by the rows corresponding to the bit indices in the set A in the matrix G N . G N (A) is a K*N matrix.

[0078] The construction process of the polar code, that is, the selection process of the set A, determines the performance of the polar code. The construction process of the polar code is usually that, according to the code length N, N polarized channels corresponding to the N rows of the polarized transformation matrix are determined, the channel reliabilities of the polarized channels are calculated, the bit indices of the first K polarized channels with higher channel reliabilities are taken as the elements of the set A, and the bit indices of the remaining (N-K) polarized channels are taken as the elements of the set A c of frozen bits. The set A determines the positions of the information bits, and the set A c determines the positions of the frozen bits.

[0079] Figure 3An 8x8 polar transformation matrix is shown, Figure 3 An example of a specific encoding process is shown, where the left side can be understood as the to-be-encoded side, the bits on the left side are denoted by u, the right side can be understood as the encoding side (or code word side), the bits on the right side are denoted by x, and the process from left to right is the encoding process of the sending end on the to-be-encoded bit sequence. The to-be-encoded information bits are represented by the sequence u(0, 0, 0, 0, 0, 0, 1, 1), and after the polar transformation matrix, the encoded bits are represented by the sequence x(0, 1, 0, 1, 0, 1, 0, 1). Mapping x into modulation symbols can be transmitted on the channel W. Among them, the bit corresponding to the high channel reliability is used to map the information bit, and the bit corresponding to the low channel reliability is used to map the frozen bit. For example Figure 3 As shown in the middle, {u0, u1, u2, u4} are frozen bit positions, and {u3, u5, u6, u7} are information bit positions.

[0080] Referring to Figure 3 In the encoding process, the two adjacent columns are an encoding layer, and the left column of bits is the input bit of the encoding layer, and the right column of bits is the output bit of the encoding layer. For example, in the leftmost encoding layer, the input bit sequence is (0, 0, 0, 0, 0, 0, 1, 1), and the output bit sequence is (0, 0, 0, 0, 0, 0, 0, 1). The operator symbol "XOR" in the middle of the encoding layer represents the XOR operation. Specifically, "XOR" represents a one-time XOR operation between the bit in the row of "XOR" and the bit in the row of "XOR", and the bit on the right side of "XOR" is the operation result. For example, in the leftmost encoding layer, the first input bit (value 0) and the second input bit (value 0) perform "XOR" operation to obtain the first output bit (value 0).

[0081] The construction process of the Polar code achieves two goals: 1) When the Polar code is a non-encoding length, determine the rate matching method; wherein the encoding length is an integer power of 2 (for example, 2 n ), and the non-encoding length is a non-integer power of 2. 2) Based on the reliability sequence, determine the information bit position and the frozen bit position. The following will be introduced respectively.

[0082] 1) Rate matching. In actual application, the length of the Polar code required may be a non-encoding length, at which time some bits in the Polar code need to be removed for not being transmitted, and this process is usually called rate matching. The following further illustrates the rate matching method in three cases.

[0083] ​​​​​​①Puncture: "Puncture" refers to directly puncturing some positions of the Polar code of the encoding length and not transmitting, and an arbitrary length of Polar code encoding bit sequence is generated by this method. At the decoding side, since there is no information amount corresponding to the position of "puncture", the log likelihood ratio (LLR) of the corresponding bit is set to 0.

[0084] ②Shorten: "Shorten" is another common rate matching method, which is to design the Polar code so that some positions in the encoding bit sequence are fixed values, so they also do not need to be transmitted. At the decoding side, since the position corresponding to "shorten" is equivalent to the known (usually 0) at the receiving end, the LLR of the corresponding bit is set to infinity.

[0085] ③Repetition: "Repetition" refers to transmitting part of the code word bits repeatedly to obtain a longer Polar code encoding bit sequence.

[0086] 2) Determination of information bit and frozen bit. The bit with higher reliability is set as information bit (data), and the bit with lower reliability is set as frozen bit. In 5G NR, the reliability sequence is used to determine the frozen bit and information bit of the Polar code. Taking a Polar code with a length of 8 as an example, assuming that the reliability sequence is [01243567], the reliability of the bit from high to low is bit 7, bit 6, bit 5, bit 3, bit 4, bit 2, bit 1, and bit 0. When constructing a Polar code with an encoding length of 8 and an information length of 4, bit 7, bit 6, bit 5, and bit 3 are selected from the back to the front as information bits, that is, {u7, u6, u5, u3} are set as information bits, and {u4, u2, u1, u0} are set as frozen bits.

[0087] Assuming that the encoding length of the Polar code is N (where N is an integer power of 2), the code length after rate matching is E (where E is less than N), and the length of the information bit sequence to be encoded is K, that is, the information bit sequence to be encoded includes K bits, K is an integer greater than 1 and K is less than E. For the Polar code supporting rate matching, the process of determining the K information bits at the sending end device is as follows: first, pre-freezing N-E bits of the N bits that need to be rate matched (which can be referred to as rate matching bit pre-freezing); then, sorting the reliabilities of the remaining E bits, and selecting the K bits with the highest reliability from the E bits as information bits, and the K information bits are used to carry the K bits in the information bit to be encoded.

[0088] After the K information bits are determined, the sending device encodes the information bit sequence to be encoded according to the K information bits, to obtain a coded bit sequence with a length of N, and then performs rate matching on the coded bit sequence with a length of N, that is, puncturing or shortening N-E bits, to obtain a coded bit sequence with a length of E, and then sends the coded bit sequence with a length of E to the receiving device.

[0089] The above method has the following problems: due to the introduction of the rate matching bits, the reliability order of the information bits may change, that is, before the rate matching is performed, the K information bits selected are the K bits with the highest reliability, and after the rate matching is performed, the reliability of one or more bits in the K information bits may decrease, so that the K information bits selected before are not the optimal K information bits after the rate matching, thereby causing the performance of the Polar code constructed to decrease, and further affecting the communication quality.

[0090] To solve the problem, the present application provides corresponding embodiments, which are described below.

[0091] FIG. 4(a) is a flowchart of an encoding method provided by an embodiment of the present application. The method is performed by a first device. Unless otherwise specified, the "first device" in the present application can refer to the first device itself (for example, a terminal device or a network device), a component (for example, a communication module, a processor, a circuit, a chip, or a chip system) in the first device, or a logic module or software capable of realizing all or part of the functions of the first device.

[0092] The method includes the following steps:

[0093] Step 401a, the first device obtains an information bit sequence to be encoded.

[0094] The information bit sequence includes K bits, and K is an integer greater than 1. The K bits in the information bit sequence can all be payload bits, or can include payload bits and check bits.

[0095] Step 402a, the first device determines a first information bit position set according to the first bit position set and a first reliability sequence of the Polar code.

[0096] The first bit position set is used to indicate the frozen bits in the first reliability sequence when the first information bit position set is determined, the first reliability sequence is used to indicate the order of the reliability of the bits in the Polar code, and the first information bit position set is used to indicate T bits, and the T bits are used to carry T bits in the K bits of the information bit sequence, and T is a positive integer.

[0097] The first bit position set is also referred to as a first frozen bit position set or a first pre-frozen bit position set.

[0098] As an implementation method, the step 402a specifically includes: determining, by the first device, a second reliability sequence according to the first bit position set and the first reliability sequence of the polar code, the second reliability sequence being composed of bit positions in the first reliability sequence except for the first bit position set. Then, the first device selects T bit positions with the highest reliability from the second reliability sequence to form a first information bit position set, that is, the T bit positions in the first information bit position set are the T bit positions with the highest reliability in the second reliability sequence.

[0099] Two different implementation methods of the first bit position set are introduced below.

[0100] Implementation method one: the first bit position set is used to indicate punctured or shortened bit positions.

[0101] It can be understood that the first bit position set is a rate matching position set, or it can be understood that the first bit position set is the same as the rate matching position set, and the rate matching position set is used to indicate punctured or shortened bit positions.

[0102] For this implementation method one, two different determination methods of the number T of bit positions in the first information bit position set are introduced below.

[0103] Method 1: the size of T is preconfigured. For example, the size of T is preconfigured as 2. wherein, represents rounding up.

[0104] Method 2: T is related to one or more of K, E, R or N. That is, the first device determines the size of T according to one or more of K, E, R or N. Wherein, E represents the length of the coded bit sequence after encoding, that is, the code length after rate matching. R represents the code rate and R=K / E. N represents the encoding length of the polar code.

[0105] For example, T increases with the increase of K.

[0106] For example, T increases with the increase of R.

[0107] For example, when E / N is greater than or equal to Z0, T increases with the increase of E / N; when E / N is less than Z0 and greater than or equal to Z1, T does not change with the change of E / N; when E / N is less than Z1, T decreases with the increase of E / N. Wherein, Z0 and Z1 are both greater than 0 and less than 1, and Z0 is greater than Z1. For example, Z0 is set as 9 / 16, Z1 is set as 17 / 32, and when 9 / 16 <= E / N, T = 1; when 17 / 32 <= E / N < 9 / 16, T = 1; and when E / N < 17 / 32, T = 0. when 17 / 32 <= E / N < 9 / 16, T = 1; and when E / N < 17 / 32, T = 0. wherein, represents the upward rounding. It should be noted that the case of “equal to” above can also be divided in other ways, which is not limited in the present application. For example, when E / N is greater than Z0, T increases with the increase of E / N; when E / N is less than or equal to Z0 and greater than Z1, T does not change with the change of E / N; and when E / N is less than or equal to Z1, T decreases with the increase of E / N.

[0108] In the second implementation method, the first bit position set contains a rate matching position set, and the number of bit positions in the first bit position set is greater than the number of bit positions in the rate matching position set, and the rate matching position set is used to indicate the punctured or shortened bit positions.

[0109] For the second implementation method, the number of bit positions contained in the first information bit position set T is related to one or more of K, E or N. That is, the first device determines the size of T according to one or more of K, E or N. Wherein, E represents the length of the encoded bit sequence after encoding, that is, the code length after rate matching. N represents the encoding length of the polar code.

[0110] For example, T increases with the increase of K.

[0111] For example, T increases with the increase of E / N.

[0112] For example, when 3 / 4 <= E / N, T = 1; when 5 / 8 <= E / N < 3 / 4, T = 1; and when E / N < 5 / 8, T = 0. when 5 / 8 <= E / N < 3 / 4, T = 1; and when E / N < 5 / 8, T = 0. wherein, represents the upward rounding.

[0113] For the second implementation method, exemplarily, the bit positions in the first bit position set are consecutive bit positions in a natural order bit sequence, the natural order bit sequence is composed of consecutive N bit positions sorted from small to large, and the natural order bit sequence is [0, 1, 2, 3, 4, 5, …, N-1]. For example, the bit positions in the first bit position set are [0, 1, 2, 3, 4, 5, …, 31], where N is greater than or equal to 32.

[0114] For the second implementation method, exemplarily, the number of bit positions in the first bit position set increases as N increases and decreases as E increases.

[0115] In step 403a, the first device determines a second information bit position set according to the second bit position set and the first reliability sequence.

[0116] The second bit position set is used to indicate the bit positions in the first reliability sequence that are frozen when the second information bit position set is determined, and the second information bit position set is used to indicate K-T bit positions that are used to carry K-T bits in the information bit sequence to be encoded, except for T bits. That is, the information bit sequence to be encoded contains K bits, T bits in the K bits are carried by the T bit positions included in the first information bit position set, and the other K-T bits in the K bits are carried by the K-T bit positions included in the second information bit position set.

[0117] The second bit position set is also referred to as a second frozen bit position set or a second pre-frozen bit position set.

[0118] As an implementation method, the step 403a specifically includes: the first device determines a third reliability sequence according to the first bit position set and the first reliability sequence of the polar code, the third reliability sequence is composed of bit positions in the first reliability sequence except for the second bit position set. Then, the first device selects K-T bit positions with the highest reliability from the third reliability sequence except for the first information bit position set to constitute the second information bit position set, that is, the K-T bit positions in the second information bit position set are K-T bit positions with the highest reliability in the second reliability sequence except for the first information bit position set.

[0119] As an implementation method, the first bit position set is a proper subset of the second bit position set.

[0120] As an implementation method, the first information bit position set and the second information bit position set have no intersection, and the reliability of the bit positions in the second information bit position set is lower than the reliability of the bit positions in the first information bit position set, that is, the reliability of the K-T bit positions in the second information bit position set is lower than the reliability of the T bit positions in the first information bit position set.

[0121] As an implementation method, the serial numbers of the bit positions in the second information bit position set are all greater than or equal to N / 2, where N represents the encoding length of the polar code.

[0122] As an implementation method, the bit positions in the second bit position set are continuous multiple bit positions in a natural order bit sequence, the natural order bit sequence is composed of continuous N bit positions sorted in ascending order, and N represents the encoding length of the polar code. Specifically, the second bit position set can be composed of the first N / 2 bit positions in the natural order bit sequence. The natural order bit sequence is composed of continuous N bit positions sorted in ascending order, and the natural order bit sequence is [0, 1, 2, 3, 4, 5, …, N-1].

[0123] Step 404a, the first device polar code encodes the information bit sequence according to the first information bit position set and the second information bit position set to obtain an encoded bit sequence.

[0124] The above scheme selects information bit positions in two stages, where T information bit positions are selected in the first stage, and K-T information bit positions are selected in the second stage. This method helps to accurately select the bit positions with the highest reliability as information bit positions, which can improve the encoding and decoding performance (such as error correction performance), and further helps to improve the communication performance.

[0125] As an implementation method, when the code rate R is less than or equal to 7 / 8, the information bit position set is selected according to the method of the embodiment of FIG. 4(a). When the code rate R is greater than 7 / 8, the information bit position set is selected according to the prior art method, that is, K bit positions with the highest reliability are selected from the first reliability sequence to form the information bit position set, and there is no need to select information bit positions in two steps.

[0126] As an implementation method, after the above step 404a, the first device can send the encoded bit sequence to the second device. The second device can be a terminal device, a network device, a module (such as a chip or a chip system) in a terminal device, a module (such as a chip or a chip system) in a network device, or other types of devices.

[0127] FIG. 4(b) is a flowchart of a decoding method according to an embodiment of the present application. The method is performed by a second device. Unless otherwise specified, the "second device" in the present application can refer to the second device itself (e.g., a terminal device or a network device), a component (e.g., a communication module, a processor, a circuit, a chip, or a chip system) in the second device, or a logic module or software that can implement all or part of the functions of the second device.

[0128] The method includes the following steps.

[0129] In step 401b, the second device acquires a sequence of symbols to be decoded.

[0130] The sequence of symbols to be decoded corresponds to a sequence of coded bits, and the sequence of coded bits includes a sequence of information bits, which includes K bits, where K is an integer greater than 1. The K bits included in the sequence of information bits can all be payload bits, or can include payload bits and check bits.

[0131] In one implementation, the second device acquires the sequence of symbols to be decoded. Specifically, the second device can receive a physical signal over the air interface, and acquire the sequence of symbols to be decoded by analyzing the physical signal. Alternatively, the second device can acquire the sequence of symbols to be decoded from the local device through an internal interface.

[0132] In step 402b, the second device determines a first set of information bit positions based on the first set of bit positions and a first reliability sequence of the polar code.

[0133] The first set of bit positions is used to indicate the bit positions in the first reliability sequence that are frozen when determining the first set of information bit positions. The first reliability sequence is used to indicate the order of reliability of the bit positions in the polar code. The first set of information bit positions is used to indicate T bit positions, which are used to carry T bits of the K bits included in the sequence of information bits, where T is a positive integer.

[0134] In step 403b, the second device determines a second set of information bit positions based on the second set of bit positions and the first reliability sequence.

[0135] The second set of bit positions is used to indicate the bit positions in the first reliability sequence that are frozen when determining the second set of information bit positions. The second set of information bit positions is used to indicate K-T bit positions, which are used to carry K-T bits of the K bits included in the sequence of information bits, in addition to the T bits.

[0136] The steps 402b to 403b are the same as the steps 402a to 403a in the embodiment of FIG. 4(a), and the implementation methods can be referred to the foregoing description.

[0137] At step 404b, the second device performs polar code decoding on the to-be-decoded symbol sequence according to the first set of information bit positions and the second set of information bit positions, to obtain the sequence of information bits.

[0138] The above scheme selects information bit positions in two stages, where T information bit positions are selected in the first stage, and K-T information bit positions are selected in the second stage. This method helps to accurately select the bit positions with the highest reliability as information bit positions, and can improve the encoding and decoding performance (e.g., error correction performance), thereby helping to improve the communication performance.

[0139] The embodiment of FIG. 4(a) and the embodiment of FIG. 4(b) can be implemented independently or in combination. In the case of combined implementation, after step 404a, the first device can send the sequence of encoded bits to the second device, and the second device receives the physical signal generated based on the sequence of encoded bits, parses the physical signal, and obtains the to-be-decoded symbol sequence corresponding to the sequence of encoded bits sent by the first device. Then, the second device decodes the to-be-decoded symbol sequence to obtain the sequence of information bits containing K bits by the embodiment of FIG. 4(b).

[0140] The encoding method in the embodiment of FIG. 4(a) will be described below in conjunction with specific embodiments. The following embodiments are specific examples of the embodiment of FIG. 4(a). Figures 5 to 7 The embodiment of FIG. 4(a) is a specific example of the embodiment of FIG. 4(a).

[0141] Figure 5 A flowchart of an encoding method according to an embodiment of the present application is shown. The method includes the following steps:

[0142] At step 501, the first device determines the encoding length (denoted as N).

[0143] The specific implementation method of the first device for determining the encoding length N is not limited. By way of example, two different implementation methods are given below.

[0144] Method 1: Simplified calculation method

[0145] The encoding length N is the smallest integer power of 2 that is greater than or equal to the code length E after rate matching. For example, if E = 252, then N = 256. For example, if E = 5, then N = 8.

[0146] Method 2: NR calculation method

[0147] 1. Calculate n1. If K / E < 9 / 16 and E < (1+1 / 8)*N0 / 2, then Otherwise,

[0148] wherein K is the bit quantity of the information bit sequence to be encoded, E is the code length after rate matching, also referred to as the code length after rate matching, and the size of the code length after rate matching E is determined by factors such as the available resource size and the bit quantity K of the information bit sequence to be encoded.

[0149] wherein N0 is the smallest 2 integer power greater than or equal to the code length after rate matching E. For example, E = 252, then N0 = 256. For example, E = 5, then N0 = 8.

[0150] ②Calculate n2. Wherein n2 = floor (N0 / K) * K. R min represents the minimum code rate supported, R min = 1 / 8. represents the upward rounding.

[0151] ③Calculate n. Wherein n = max{min{n1, n2, n max}, n min}, wherein the minimum code length is the maximum code length is n min = 5, n max = 10, and n max = 5.

[0152] ④Determine the code length N according to n, wherein N = 2 n .

[0153] Step 502, the first device determines the rate matching method and the rate matching position set (denoted by Q) according to the bit quantity of the information bit sequence, the code length after rate matching, and the code length.

[0154] The process of determining the rate matching method is as follows: when E > N, the rate matching method is selected as repetition; when E <= N and K / E <= 7 / 16, the rate matching method is selected as puncturing; and when E <= N and K / E > 7 / 16, the rate matching method is selected as shortening.

[0155] Wherein the ratio of K to E (i.e. K / E) is referred to as the code rate R, that is, the code rate R = K / E.

[0156] Exemplarily, the process of determining the rate matching position set Q is specifically: dividing 0, 1, 2, …, N-1 into 32 sub-blocks, then performing sub-block interleaving to obtain a bit sub-channel sequence number vector after interleaving, and the specific implementation method of the sub-block interleaving is not limited in the present application. Taking N=64 as an example, the bit sub-channel sequence number vector after interleaving is [0, 1, 2, 3, 4, 5, 8, 9, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 32, 33, 18, 19, 34, 35, 20, 21, 36, 37, 22, 23, 38, 39, 24, 25, 40, 41, 26, 27, 42, 43, 28, 29, 44, 45, 30, 31, 46, 47, 48, 49, 50, 51, 52, 53, 56, 57, 54, 55, 58, 59, 60, 61, 62, 63]. Wherein, when the rate matching method is shortening, the first device selects N-E positions from the back to the front of the bit sub-channel sequence number vector after interleaving as the rate matching position set Q; when the rate matching method is puncturing, the first device selects N-E positions from the front to the back of the bit sub-channel sequence number vector after interleaving as the rate matching position set Q.

[0157] The rate matching position set Q here is a specific example of the first bit position set in the embodiment of FIG. 4(a).

[0158] Step 503, the first device determines a first information bit position set (denoted as T) according to the reliability sequence S of the polar code and the rate matching position set. Wherein, the number T of bits contained in the first information bit position set is pre-configured.

[0159] Firstly, the first device removes the rate matching position set Q from the reliability sequence S to obtain a reliability sequence S1, and the length of S1 is equal to E. Taking N=64 and E=42 as an example, assuming that the reliability sequence S is [0, 1, 2, 4, 8, 16, 32, 3, 5, 9, 6, 17, 10, 18, 12, 33, 20, 34, 24, 36, 7, 11, 40, 19, 13, 48, 14, 21, 35, 26, 37, 25, 22, 38, 41, 28, 42, 49, 44, 50, 15, 52, 23, 56, 27, 39, 29, 43, 30, 45, 51, 46, 53, 54, 57, 58, 60, 31, 47, 55, 59, 61, 62, 63], when the rate matching method is puncturing and the rate matching position set Q is [0, 1, 2, 3, 4, 5, 8, 9, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 32, 33, 18, 19], the reliability sequence S1 is [20, 34, 24, 36, 40, 48, 21, 35, 26, 37, 25, 22, 38, 41, 28, 42, 49, 44, 50, 52, 23, 56, 27, 39, 29, 43, 30, 45, 51, 46, 53, 54, 57, 58, 60, 31, 47, 55, 59, 61, 62, 63].

[0160] Then, the first device determines a first information bit position set and that is, the number of bit positions in the first information bit position set is equal to T. Exemplarily, or or and so on. wherein, represents rounding up, represents a set of bit positions in the reliability sequence S1, and Q represents the rate matching position set, represents a result of removing Q from . Exemplarily, the first device reads T bit positions from the reliability sequence S1 from back to front to form the first information bit position set Taking the above example, assuming that K=18, thus

[0161] The first information bit position set is also called a first information position set, a first information bit position set, or a first information bit set, and is used to indicate bit positions carrying information.

[0162] The reliability sequence S here is a specific example of the first reliability sequence in the embodiment of Figure 4(a), and the reliability sequence S1 here is a specific example of the second reliability sequence in the embodiment of Figure 4(a).

[0163] Step 504: The first device determines the set of pre-frozen bit positions (using the code length and encoding length after rate matching) based on the code length and encoding length after rate matching. express).

[0164] The set of pre-frozen bit positions includes one or more pre-frozen bit positions.

[0165] In one implementation method, in In the case of, when Take the first few bits from the natural order bit sequence [0, 1, 2, ..., N-1] One bit is used as a pre-frozen bit, when The first N / 2 bits of the natural order bit sequence [0, 1, 2, ..., N-1] are used as pre-frozen bits. Here, the natural order bit sequence [0, 1, 2, ..., N-1] refers to the sequence where the bit numbers are consecutive and ordered in ascending order. The advantage of this configuration method is that its performance is relatively stable under various code lengths and code rates. Assuming N = 64 and E = 42, since... Therefore, the first 32 bits in the natural order bit sequence [0, 1, 2, ..., 63] can be used as the pre-frozen bits, that is, the set of pre-frozen bit positions. [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31].

[0166] In another implementation method, in In the case of, when Take the first few bits from the natural order bit sequence [0, 1, 2, ..., N-1] One bit is used as a pre-frozen bit, when The first 9N / 16 bits of the natural order bit sequence [0, 1, 2, ..., N-1] are used as pre-frozen bits. The advantage of this configuration method is that it has better performance with short code lengths.

[0167] In another implementation method, in In this case, the first N / 2 bits of the natural order bit sequence [0, 1, 2, ..., N-1] are used as pre-frozen bits. The advantage of this configuration method is that it is relatively simple to configure.

[0168] In another implementation method, in In the case of, when Take the first few bits from the natural order bit sequence [0, 1, 2, ..., N-1] One bit is used as a pre-frozen bit, when The first N / 2 bits of the natural order bit sequence [0, 1, 2, ..., N-1] are used as pre-frozen bits. The advantage of this configuration method is that it provides better performance at high bit rates.

[0169] The set of pre-frozen bit positions here This is a specific example of the second pre-frozen bit position set in the embodiment of Figure 4(a).

[0170] Step 505: The first device determines the second information bit position set (using the reliability sequence S, the rate matching position set, the pre-frozen bit position set, and the first information bit position set) based on the reliability sequence S, the rate matching position set, the pre-frozen bit position set, and the first information bit position set. express).

[0171] First, the first device removes the rate-matching position set Q and the pre-frozen bit position set from the reliability sequence S. We obtain the reliability sequence S2, where the length of S2 is less than or equal to E. Continuing with the previous example, i.e., N = 64, E = 42, and assuming a pre-frozen bit location set... Given the sequence [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], the reliability sequence S2 is [34, 36, 40, 48, 35, 37, 38, 41, 42, 49, 44, 50, 52, 56, 39, 43, 45, 51, 46, 53, 54, 57, 58, 60, 47, 55, 59, 61, 62, 63], where the length of S2 is 30.

[0172] Next, the first device, based on the reliability sequence S2 and the first information bit position set... Determine the set of second information bit positions in, and in, Let S represent the set of bits in the reliability sequence S1, and Q represent the set of rate matching positions. Represents the set of pre-frozen bit positions. Represents the set of positions of the first information bits. Indicates from Remove Q from the middle and The obtained result. Exemplarily, the first device reads out K-T bits not belonging to the first information bit position set from the reliability sequence S2 from back to front in succession to form a second information bit position set Next to the above example, that is, N=64, E=42, K=18, and T=17, K-T=1, thus The second information bit position set is also called a second information position set, a second information bit set, or a second information bit set, and is used to indicate bits carrying information.

[0173] The reliability sequence S2 here is a specific example of the third reliability sequence in the embodiment of FIG. 4(a).

[0174] Step 506, the first device determines a third information bit position set (denoted as S3) according to the first information bit position set and the second information bit position set.

[0175] Wherein, Next to the above example, that is, N=64, E=42,

[0176] Thus,

[0177] Step 507, the first device performs polar code encoding on the information bit sequence to be encoded according to the third information bit position set to obtain an encoded bit sequence.

[0178] Wherein, the length of the information bit sequence is K, and the code length after rate matching is E.

[0179] Specifically, the first device first performs polar code encoding on the information bit sequence according to the third information bit position set S3 to obtain an encoded bit sequence with a length of N, and then performs rate matching on the encoded bit sequence with a length of N according to the rate matching position set Q to remove N-E bits from the encoded bit sequence with a length of N to obtain an encoded bit sequence with a length of E. The above scheme selects information bits in two stages, wherein T information bits are selected in the first stage, and K-T information bits are selected in the second stage, which helps to accurately select bits with the highest reliability as information bits, improves decoding performance (for example, error correction performance), and further helps to improve communication performance. And the above scheme supports sub-block interleaving and natural order rate matching, is widely applicable, and further improves communication performance.

[0180]

[0181] ​​​The following is combined with Figure 5 The specific examples given in the embodiments illustrate Figure 5 The beneficial effects brought about by the embodiments. Regarding Figure 5 The specific example given in the embodiment, if following the existing technical method, involves directly selecting K (i.e., 18) bits with the highest reliability from the reliability sequence S1 to form the information bit position set, namely [29, 43, 30, 45, 51, 46, 53, 54, 57, 58, 60, 31, 47, 55, 59, 61, 62, 63]. However, according to the present invention... Figure 5 In the method of the embodiment, the final determined set of information bit positions (i.e., the third set of information bit positions) is [39, 43, 30, 45, 51, 46, 53, 54, 57, 58, 60, 31, 47, 55, 59, 61, 62, 63]. It can be seen that the difference between the two is that the prior art uses bit 29 as one of the K bits with the highest reliability, while the present invention uses bit 39 as one of the K bits with the highest reliability. In practical applications, due to the influence of rate matching on reliability ranking, the reliability of bit 39 is actually higher than that of bit 29. Therefore, the method of the present invention can accurately select the bit with the highest reliability as the information bit, which can improve encoding and decoding performance (e.g., error correction performance), thereby helping to improve communication performance.

[0182] Figure 6 This is a flowchart illustrating an encoding method provided in an embodiment of this application. The method includes the following steps:

[0183] Step 601: The first device determines the encoding length (denoted by N).

[0184] The specific implementation method for determining the coding length N in this application is not limited. For example, the coding length N is the smallest integer power of 2 greater than or equal to the rate-matched code length E. For instance, if E = 252, then N = 256. Or, if E = 5, then N = 8.

[0185] Step 602: The first device determines the rate matching method and the rate matching position set (denoted by Q) based on the number of bits in the information bit sequence, the code length after rate matching, and the encoding length.

[0186] The process of determining the rate matching method is as follows: when E>N, the rate matching method is repetition; when E<=N and K / E<=7 / 16, the rate matching method is punching; when E<=N and K / E>7 / 16, the rate matching method is shortening.

[0187] The ratio of K to E (i.e., K / E) is also called the bitrate R, that is, bitrate R = K / E.

[0188] The process of determining the rate matching position set Q is as follows: when the rate matching method is shortening, the first device selects N-E positions from the natural order bit sequence [0, 1, 2, …, N-1] from back to front as the rate matching position set Q; when the rate matching method is puncturing, the first device selects N-E positions from the natural order bit sequence [0, 1, 2, …, N-1] from front to back as the rate matching position set Q.

[0189] When the rate matching method is shortening, the following steps 603-607 are performed after step 602.

[0190] The rate matching position set Q here is a specific example of the first bit position set in the embodiment of FIG. 4(a).

[0191] Step 603: The first device determines a first information bit position set (denoted as T) according to the reliability sequence S of the polar code and the rate matching position set. The number of bits contained in the first information bit position set T is related to one or more of E, K, R or N.

[0192] First, the first device removes the rate matching position set Q from the reliability sequence S to obtain a reliability sequence S1, and the length of S1 is equal to E. Taking N=64 and E=42 as an example, assuming that the reliability sequence S is [0, 1, 2, 4, 8, 16, 32, 3, 5, 9, 6, 17, 10, 18, 12, 33, 20, 34, 24, 36, 7, 11, 40, 19, 13, 48, 14, 21, 35, 26, 37, 25, 22, 38, 41, 28, 42, 49, 44, 50, 15, 52, 23, 56, 27, 39, 29, 43, 30, 45, 51, 46, 53, 54, 57, 58, 60, 31, 47, 55, 59, 61, 62, 63], when the rate matching method is shortening and the rate matching position set Q is [42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63], then S1=[0, 1, 2, 4, 8, 16, 32, 3, 5, 9, 6, 17, 10, 18, 12, 33, 20, 34, 24, 36, 7, 11, 40, 19, 13, 14, 21, 35, 26, 37, 25, 22, 38, 41, 28, 15, 23, 27, 39, 29, 30, 31].

[0193] Then, the first device determines a first information bit position set T according to the reliability sequence S1. And wherein, denotes a set of bit positions in the reliability sequence S1, Q denotes a set of rate matching positions, denotes a result of removing Q from . The number of bit positions in the first information bit position set is equal to T. Exemplarily, the first device reads T bit positions from the reliability sequence S1 from back to front successively to form the first information bit position set

[0194] wherein the size of T is related to one or more of E, K, R or N.

[0195] For example, when E / N is greater than or equal to Z0, T increases with the increase of E / N; when E / N is less than Z0 and greater than or equal to Z1, T does not change with the change of E / N; when E / N is less than Z1, T decreases with the increase of E / N; wherein Z0 and Z1 are both greater than 0 and less than 1, and Z0 is greater than Z1. The value of Z is related to E and N, and the value of Z is between 0 and 1. It should be noted that the value of Z is not limited to 2 values (i.e. Z0 and Z1), but can be 3 values or even more, which is essentially a kind of interval division method. When the number of values of Z is 2, it means to divide into 3 intervals, when the number of values of Z is 3, it means to divide into 4 intervals, and so on.

[0196] The following Table 1 gives a specific example.

[0197] Table 1

[0198]

[0199] Referring to Table 1, taking Z0 = 9 / 16 and Z1 = 17 / 32 as an example, the relationship between T and E / N is shown. Wherein, when 9 / 16 <= E / N, when 17 / 32 <= E / N < 9 / 16, when E / N < 17 / 32, wherein, denotes rounding up, and R = K / E.

[0200] Continuing the foregoing example, N = 64, E = 42, K = 21, and T = 20, then

[0201] The first information bit position set is also called a first information position set, a first information bit position set or a first information bit set, and the first information bit position set is used to indicate the bit positions carrying information.

[0202] The reliability sequence S here is a specific example of the first reliability sequence in the embodiment of FIG. 4(a), and the reliability sequence S1 here is a specific example of the second reliability sequence in the embodiment of FIG. 4(a).

[0203] At step 604, the first device determines a pre-frozen bit position set (denoted as ) according to the code length after rate matching and the coding length.

[0204] The pre-frozen bit position set includes one or more pre-frozen bits.

[0205] For example, the first device takes the first N / 2 bits in the natural order bit sequence [0, 1, 2, …, N-1] as the pre-frozen bits.

[0206] Taking N=64 and E=42 as an example, we have

[0207] The pre-frozen bit position set is a specific example of the second pre-frozen bit position set in the embodiment of FIG. 4(a).

[0208] At step 605, the first device determines a second information bit position set (denoted as ) according to the reliability sequence S, the rate matching position set, the pre-frozen bit position set, and the first information bit position set.

[0209] First, the first device removes the rate matching position set Q and the pre-frozen bit position set from the reliability sequence S to obtain a reliability sequence S2, where the length of S2 is less than or equal to E. Taking the aforementioned example, i.e., N=64 and E=42, we have the pre-frozen bit position set [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], and the reliability sequence S2 is [32, 33, 34, 36, 40, 35, 37, 38, 41, 39].

[0210] Next, the first device determines the second information bit position set according to the reliability sequence S2 and the first information bit position set where and where denotes a set of bits in the reliability sequence S1, Q denotes the rate matching position set, denotes a pre-frozen bit position set, denotes a first information bit position set, denotes a result of removing Q, from and Exemplarily, the first device reads out K-T bits not belonging to the first information bit position set from the reliability sequence S2 from back to front successively, to form a second information bit position set Taking the above example, i.e. N=64, E=42, K=21, T=20, then K-T=1, therefore

[0211] The second information bit position set is also called a second information position set, a second information bit set or a second information bit set, and the second information bit position set is used to indicate a bit carrying information.

[0212] The reliability sequence S2 here is a specific example of the third reliability sequence in the embodiment of FIG. 4(a).

[0213] Step 606, the first device determines a third information bit position set (denoted by ) according to the first information bit position set and the second information bit position set.

[0214] wherein, Taking the above example, i.e. N=64, E=42, then

[0215] Step 607, the first device performs polar code encoding on the information bit sequence to be encoded according to the third information bit position set, to obtain an encoded bit sequence.

[0216] wherein, the length of the information bit sequence is K, and the length of the encoded bit sequence is E.

[0217] Specifically, the first device performs polar code encoding on the information bit sequence according to the third information bit position set to obtain an encoded bit sequence with a length of N, and then the first device performs rate matching on the encoded bit sequence with a length of N according to the rate matching position set Q, removes N-E bits from the encoded bit sequence with a length of N, to obtain an encoded bit sequence with a length of E.

[0218] As an implementation method, if R >= 7 / 8, T is set to K, and the first information bit position set determined in the above step 603 is It contains K bits, therefore the first device will set the first information bit position. As the final set of information bit positions, steps 604 to 606 are no longer required after step 603, and step 607 is modified to: the first device determines the first set of information bit positions. The information bit sequence to be encoded is polar-coded to obtain the encoded bit sequence. If R < 7 / 8, then after step 603, the above steps 604 to 607 are continued, and Table 1 above also applies to the scenario where R < 7 / 8.

[0219] The above scheme selects information bits in two stages, which helps to accurately select the bits with the highest reliability as information bits, improving encoding and decoding performance (such as error correction performance), and thus contributing to improved communication performance. Furthermore, this scheme does not require sub-block interleaving, thus reducing complexity.

[0220] The following is combined with Figure 6 The specific examples given in the embodiments illustrate Figure 6 The beneficial effects brought about by the embodiments. Regarding Figure 6 The specific example given in the embodiment, if following the existing technical method, involves directly selecting K (i.e., 21) bits with the highest reliability from the reliability sequence S1 to form the information bit position set, namely [11, 40, 19, 13, 14, 21, 35, 26, 37, 25, 22, 38, 41, 28, 15, 23, 27, 39, 29, 30, 31]. However, according to the present invention... Figure 6 In the method of the embodiment, the final determined set of information bit positions (i.e., the third set of information bit positions) is [36, 40, 19, 13, 14, 21, 35, 26, 37, 25, 22, 38, 41, 28, 15, 23, 27, 39, 29, 30, 31]. It can be seen that the difference between the two is that the prior art uses bit 11 as one of the K bits with the highest reliability, while the present invention uses bit 36 ​​as one of the K bits with the highest reliability. In practical applications, due to the influence of rate matching on reliability ranking, the reliability of bit 36 ​​is actually higher than that of bit 11. Therefore, the method of the present invention can accurately select the bit with the highest reliability as the information bit, which can improve encoding and decoding performance (e.g., error correction performance), thereby helping to improve communication performance.

[0221] Figure 7 This is a flowchart illustrating an encoding method provided in an embodiment of this application. The method includes the following steps:

[0222] Step 701: The first device determines the encoding length (denoted by N).

[0223] The embodiment of the present application does not limit the specific implementation method of the encoding length N. Exemplarily, the encoding length N is the smallest integer power of 2 greater than or equal to the code length E after rate matching. For example, E = 252, and N = 256. For another example, E = 5, and N = 8.

[0224] In step 702, the first device determines a rate matching method and a rate matching position set (denoted as Q) according to the bit quantity of the information bit sequence, the code length after rate matching, and the encoding length.

[0225] The process of determining the rate matching method is specifically as follows: when E > N, the rate matching method is selected as repetition; when E <= N and K / E <= 7 / 16, the rate matching method is selected as puncturing; and when E <= N and K / E > 7 / 16, the rate matching method is selected as shortening.

[0226] The ratio of K to E (i.e., K / E) is also referred to as a code rate R, that is, the code rate R = K / E.

[0227] The process of determining the rate matching position set Q is specifically as follows: when the rate matching method is shortening, the first device selects N-E positions from the back to the front in the natural order bit sequence [0, 1, 2, …, N-1] as the rate matching position set Q; and when the rate matching method is puncturing, the first device selects N-E positions from the front to the back in the natural order bit sequence [0, 1, 2, …, N-1] as the rate matching position set Q.

[0228] When the rate matching method is puncturing, the following steps 703-707 are performed after step 702.

[0229] In step 703, the first device determines a first information bit position set (denoted as ) according to the reliability sequence S of the polar code and a first pre-frozen bit position set (denoted as ).

[0230] The first pre-frozen bit position set includes one or more pre-frozen bit positions.

[0231] The rate matching position set Q is a proper subset of the first pre-frozen bit position set In addition to the bit positions in the rate matching position set Q, the first pre-frozen bit position set also includes other bit positions. As an implementation method, when N <= 256, the first device takes the first N-E bit positions in the natural order bit sequence [0, 1, 2, …, N-1] as the first pre-frozen bit position set; and when N > 256, the first device takes the first N-E bit positions in the natural order bit sequence [0, 1, 2, …, N-1] as the first pre-frozen bit position set.

[0232] As an implementation method, when N <= 256, the first device takes the first N-E bit positions in the natural order bit sequence [0, 1, 2, …, N-1] as the first pre-frozen bit position set; and when N > 256, the first device takes the first N-E bit positions in the natural order bit sequence [0, 1, 2, …, N-1] as the first pre-frozen bit position set.​​​ As the first set of pre-frozen bit positions For example, N = 64, E = 42,

[0233] For example, the specific implementation process of step 703 is as follows:

[0234] First, the first device removes the first pre-frozen bit position set from the reliability sequence S. A reliability sequence S1 is obtained, the length of which is less than or equal to E. Taking N=64 and E=42 as an example, assuming the reliability sequence S is [0, 1, 2, 4, 8, 16, 32, 3, 5, 9, 6, 17, 10, 18, 12, 33, 20, 34, 24, 36, 7, 11, 40, 19, 13, 48, 14, 21, 35, 26, 37, 25, 22, 38, 41, 28, 42, 49, 44, 50, 15, 52, 23, 56, 27, 39, 29, 43, 30, 45, 51, 46, 53, 54, 57, 58, 60, 31, 47, 55, 59, 61, 62, 63], when the rate matching method is puncturing, and the first pre-frozen bit position set... Given [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26], then S1 = [32, 33, 34, 36, 40, 48, 35, 37, 38, 41, 28, 42, 49, 44, 50, 52, 56, 27, 39, 29, 43, 30, 45, 51, 46, 53, 54, 57, 58, 60, 31, 47, 55, 59, 61, 62, 63].

[0235] Then, the first device determines the first information bit position set according to the reliability sequence S1. and in, This represents the set of bits in the reliability sequence S1. This represents the set of the first pre-frozen bit positions. Indicates from Remove from The result obtained. First information bit position set. The number of bits in the sequence is equal to T. For example, the first device reads T bits consecutively from the reliability sequence S1 from the end to the beginning, forming the first information bit position set.

[0236] For example, the size of T is related to E, K, and N.

[0237] The following Table 2 gives a specific example.

[0238] Table 2

[0239]

[0240] Referring to Table 2, the relationship between T and E / N is shown. Wherein, when 3 / 4 <= E / N, then when 5 / 8 <= E / N < 3 / 4, then when E / N < 5 / 8, then wherein, represents the upward rounding.

[0241] Exemplarily, when N = 64, E = 42, K = 18, T = 15,

[0242] The first information bit position set is also referred to as a first information position set, a first information bit set or a first information bit set, which is used to indicate the bit carrying information.

[0243] The first pre-frozen bit position set herein is a specific example of the first bit position set in the embodiment of FIG. 4(a).

[0244] The reliability sequence S herein is a specific example of the first reliability sequence in the embodiment of FIG. 4(a), and the reliability sequence S1 herein is a specific example of the second reliability sequence in the embodiment of FIG. 4(a).

[0245] In step 704, the first device determines a second pre-frozen bit position set (denoted as ) according to the code length after rate matching and the coding length.

[0246] The second pre-frozen bit position set includes one or more pre-frozen bits.

[0247] Exemplarily, the first device takes the first N / 2 bits in the natural order bit sequence [0, 1, 2, …, N-1] as pre-frozen bits.

[0248] Taking N = 64 and E = 42 as an example, then

[0249] In the embodiment of the present application, the first pre-frozen bit position set is a proper subset of the second pre-frozen bit position set , that is, the second pre-frozen bit position set In addition to the bits in the first pre-frozen bit position set , other bits are also included.

[0250] The second pre-frozen bit position set here is a specific example of the second bit position set in the embodiment of FIG. 4(a).

[0251] At step 705, the first device determines a second information bit position set (denoted as ) according to the reliability sequence S, the second pre-frozen bit position set and the first information bit position set.

[0252] First, the first device removes the second pre-frozen bit position set from the reliability sequence S to obtain a reliability sequence S2, where the length of S2 is less than or equal to E. In the foregoing example, i.e., N = 64 and E = 42, the pre-frozen bit position set is [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], and the reliability sequence S2 is [32, 33, 34, 36, 40, 48, 35, 37, 38, 41, 42, 49, 44, 50, 52, 56, 39, 43, 45, 51, 46, 53, 54, 57, 58, 60, 47, 55, 59, 61, 62, 63].

[0253] Next, the first device determines the second information bit position set according to the reliability sequence S2 and the first information bit position set wherein and wherein denotes a set of bits in the reliability sequence S1, denotes the second pre-frozen bit position set, denotes the first information bit position set, denotes a result of removing and from . Exemplarily, the first device reads out K-T bits not belonging to the first information bit position set from the reliability sequence S2 from back to front and in succession to form the second information bit position set In the foregoing example, i.e., N = 64, E = 42, K = 18 and T = 15, K-T = 3, and thus

[0254] The second information bit position set is also called the second information position set, the second information bit set, or the second information bit set. The second information bit position set is used to indicate the bits that carry information.

[0255] Step 706: The first device determines the third information bit position set (using the first information bit position set and the second information bit position set) based on the first information bit position set and the second information bit position set. express).

[0256] in, Taking the aforementioned example, that is, N=64, E=42, but

[0257] Step 707: The first device performs polar code encoding on the information bit sequence to be encoded according to the third information bit position set to obtain the encoded bit sequence.

[0258] The length of the information bit sequence is K, and the length of the encoded bit sequence is E.

[0259] Specifically, the first device first determines the location of the third information bit set. The information bit sequence is polar-coded to obtain a coded bit sequence of length N. Then, the first device performs rate matching on the coded bit sequence of length N according to the rate matching position set Q, and removes NE bits from the coded bit sequence of length N to obtain a coded bit sequence of length E.

[0260] The above scheme selects information bits in two stages, which helps to accurately select the bits with the highest reliability as information bits, improving encoding and decoding performance (such as error correction performance), and thus contributing to improved communication performance. Furthermore, this scheme does not require sub-block interleaving, thus reducing complexity.

[0261] The following is combined Figure 7 The specific examples given in the embodiments illustrate Figure 7 The beneficial effects brought about by the embodiments. Regarding Figure 7 The specific example given in the embodiment, if following the existing technical method, involves directly selecting K (i.e., 18) bits with the highest reliability from the reliability sequence S1 to form the information bit position set, namely [29, 43, 30, 45, 51, 46, 53, 54, 57, 58, 60, 31, 47, 55, 59, 61, 62, 63]. However, according to the present invention... Figure 7The final determined information bit position set (i.e. the third information bit position set) of the method of the embodiment is [56, 39, 43, 45, 51, 46, 53, 54, 57, 58, 60, 31, 47, 55, 59, 61, 62, 63]. It can be seen that the difference between the two is that the prior art takes bit positions 29 and 30 as one of the K bit positions with the highest reliability, while the present application takes bit positions 39 and 56 as one of the K bit positions with the highest reliability. In actual application, due to the influence of rate matching on reliability ranking, the reliability of bit positions [39, 56] is actually higher than that of bit positions [29, 30], so by the method of the present application, the bit positions with the highest reliability can be accurately selected as information bit positions, and the coding and decoding performance (such as error correction performance) can be improved, thereby helping to improve the communication performance.

[0262] It can be understood that, in order to implement the functions in the above embodiments, the first device or the second device comprises a corresponding hardware structure and / or software module for performing each function. Those skilled in the art should easily realize that, in combination with the units and method steps of the examples described in the embodiments disclosed in the present application, the present application can be realized in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed in the form of hardware or computer software driving hardware depends on the specific application scenario and design constraints of the technical solution.

[0263] In the following, the communication device provided by the embodiments of the present application will be described in combination with Figures 8 to 12 The communication device provided by the embodiments of the present application will be described in detail. The embodiments of the present application can divide the functional modules of the communication device according to the above method examples, for example, each functional module can be divided according to each function, or two or more functions can be integrated in one processing module. The above integrated module can be realized in the form of hardware, or in the form of a software functional module, or a combination of software and hardware. The division of modules in the embodiments of the present application is illustrative, and is only a logical functional division. When actually implemented, another division mode can be used. The following will be described taking the example of dividing each functional module according to each function.

[0264] Figure 8 The structure schematic diagram of the possible communication device provided by the embodiments of the present application is shown. These communication devices can be used to realize the functions of the first device or the second device in the above method embodiments, and thus can also realize the beneficial effects possessed by the above method embodiments. In the embodiments of the present application, the communication device can be the first device or the second device.

[0265] Figure 8 The communication device 800 shown comprises a processing unit 810 and a transceiver unit 820. The communication device 800 is used to realize the functions of the first device or the second device in the above method embodiments.

[0266] When the communication apparatus 800 is configured to implement the functions of the first device in the above method embodiments, the processing unit 810 is configured to obtain an information bit sequence to be encoded, the information bit sequence comprising K bits, K being an integer greater than 1; determine a first information bit position set according to a first bit position set and a first reliability sequence of a polar code; wherein the first bit position set is used to indicate the bit positions in the first reliability sequence that are frozen when determining the first information bit position set, the first reliability sequence is used to indicate the ordering of the reliabilities of the bit positions in the polar code, and the first information bit position set is used to indicate T bit positions, the T bit positions being used to carry T bits in the K bits, T being a positive integer; determine a second information bit position set according to a second bit position set and the first reliability sequence; wherein the second bit position set is used to indicate the bit positions in the first reliability sequence that are frozen when determining the second information bit position set, and the second information bit position set is used to indicate K-T bit positions, the K-T bit positions being used to carry K-T bits in the K bits other than the T bits; and perform polar code encoding on the information bit sequence according to the first information bit position set and the second information bit position set to obtain an encoded bit sequence. The transceiver 820 is configured to transmit the encoded bit sequence.

[0267] In a possible implementation, the first bit position set is used to indicate punctured or shortened bit positions.

[0268] In a possible implementation, the first bit position set is the same as a rate matching position set, and the rate matching position set is used to indicate punctured or shortened bit positions.

[0269] In a possible implementation, wherein, represents rounding up.

[0270] In a possible implementation, T is related to one or more of K, E, R or N; wherein E represents the length of the encoded bit sequence, R represents the code rate and R = K / E, and N represents the encoding length of the polar code.

[0271] In a possible implementation, T increases as K increases.

[0272] In a possible implementation, T increases as R increases.

[0273] In a possible implementation, when E / N is greater than or equal to Z0, the T increases as the E / N increases; when E / N is less than Z0 and greater than or equal to Z1, the T does not change as the E / N changes; when E / N is less than Z1, the T decreases as the E / N increases; wherein Z0 and Z1 are both greater than 0 and less than 1, and Z0 is greater than Z1.

[0274] In a possible implementation, when 9 / 16<=E / N, when 17 / 32<=E / N<9 / 16, when E / N<17 / 32, wherein, denotes rounding up.

[0275] In a possible implementation, the code rate R is less than or equal to 7 / 8.

[0276] In a possible implementation, the first bit position set includes a rate matching position set, and the number of bit positions in the first bit position set is greater than the number of bit positions in the rate matching position set, the rate matching position set being used to indicate punctured or shortened bit positions.

[0277] In a possible implementation, the first bit position set is a proper subset of the second bit position set.

[0278] In a possible implementation, the T is related to one or more of K, E, or N; wherein E represents the length of the coded bit sequence, and N represents the encoding length of the polar code.

[0279] In a possible implementation, the T increases as the K increases.

[0280] In a possible implementation, the T increases as the E / N increases.

[0281] In a possible implementation, when 3 / 4<=E / N, when 5 / 8<=E / N<3 / 4, when E / N<5 / 8, wherein, denotes rounding up.

[0282] In a possible implementation, the bit positions in the first bit position set are consecutive bit positions in a natural order bit sequence, the natural order bit sequence being composed of consecutive N bit positions sorted in ascending order, and the N representing the encoding length of the polar code.

[0283] In a possible implementation, the first set of information bit positions has no intersection with the second set of information bit positions, and the reliability of a bit in the second set of information bit positions is lower than the reliability of a bit in the first set of information bit positions.

[0284] In a possible implementation, the serial numbers of the bits in the second set of information bit positions are all greater than or equal to N / 2, where N represents the encoding length of the polar code.

[0285] In a possible implementation, the bits in the second set of bit positions are consecutive bits in a natural order bit sequence, and the natural order bit sequence is composed of consecutive N bits sorted in ascending order, where N represents the encoding length of the polar code.

[0286] In a possible implementation, the second set of bit positions is composed of the first N / 2 bits in the natural order bit sequence.

[0287] In a possible implementation, the number of bits in the first set of bit positions increases as N increases and decreases as E increases, where N represents the encoding length of the polar code, and E represents the length of the encoded bit sequence.

[0288] In a possible implementation, the T bits are the T bits with the highest reliability in a second reliability sequence, and the second reliability sequence is composed of bits in the first reliability sequence except for the bits in the first set of bit positions.

[0289] In a possible implementation, the K-T bits are the K-T bits with the highest reliability in a third reliability sequence except for the bits in the first set of information bit positions, and the third reliability sequence is composed of bits in the first reliability sequence except for the bits in the second set of bit positions.

[0290] When the communication apparatus 800 is configured to implement the functions of the second device in the above method embodiments, the transceiver 820 is configured to obtain an encoded bit sequence, the encoded bit sequence comprising an information bit sequence, the information bit sequence comprising K bits, K being an integer greater than 1; the processing unit 810 is configured to determine a first information bit position set according to a first bit position set and a first reliability sequence of a polar code; the first bit position set is used to indicate the bit positions in the first reliability sequence that are frozen when determining the first information bit position set, the first reliability sequence is used to indicate the ordering of the reliabilities of the bit positions in the polar code, and the first information bit position set is used to indicate T bit positions, the T bit positions being used to carry T bits in the K bits, T being a positive integer; determine a second information bit position set according to a second bit position set and the first reliability sequence; the second bit position set is used to indicate the bit positions in the first reliability sequence that are frozen when determining the second information bit position set, and the second information bit position set is used to indicate K-T bit positions, the K-T bit positions being used to carry K-T bits in the K bits other than the T bits; and polar decode the encoded bit sequence according to the first information bit position set and the second information bit position set to obtain the information bit sequence.

[0291] In a possible implementation, the first bit position set is used to indicate punctured or shortened bit positions.

[0292] In a possible implementation, the first bit position set is the same as a rate matching position set, and the rate matching position set is used to indicate punctured or shortened bit positions.

[0293] In a possible implementation, wherein, represents rounding up.

[0294] In a possible implementation, T is related to one or more of K, E, R or N; E represents the length of the encoded bit sequence, R represents the code rate and R = K / E, and N represents the encoding length of the polar code.

[0295] In a possible implementation, T increases as K increases.

[0296] In a possible implementation, T increases as R increases.

[0297] In a possible implementation, when E / N is greater than or equal to Z0, the T increases as the E / N increases; when E / N is less than Z0 and greater than or equal to Z1, the T does not change as the E / N changes; when E / N is less than Z1, the T decreases as the E / N increases; wherein Z0 and Z1 are both greater than 0 and less than 1, and Z0 is greater than Z1.

[0298] In a possible implementation, when 9 / 16<=E / N, when 17 / 32<=E / N<9 / 16, when E / N<17 / 32, wherein, denotes rounding up.

[0299] In a possible implementation, the code rate R is less than or equal to 7 / 8.

[0300] In a possible implementation, the first bit position set includes a rate matching position set, and the number of bit positions in the first bit position set is greater than the number of bit positions in the rate matching position set, the rate matching position set being used to indicate punctured or shortened bit positions.

[0301] In a possible implementation, the first bit position set is a proper subset of the second bit position set.

[0302] In a possible implementation, the T is related to one or more of K, E, or N; wherein E represents the length of the coded bit sequence, and N represents the code length of the polar code.

[0303] In a possible implementation, the T increases as the K increases.

[0304] In a possible implementation, the T increases as the E / N increases.

[0305] In a possible implementation, when 3 / 4<=E / N, when 5 / 8<=E / N<3 / 4, when E / N<5 / 8, wherein, denotes rounding up.

[0306] In a possible implementation, the bit positions in the first bit position set are consecutive bit positions in a natural order bit sequence, the natural order bit sequence being composed of consecutive N bit positions sorted in ascending order, the N representing the code length of the polar code.

[0307] In a possible implementation, the first set of information bit positions has no intersection with the second set of information bit positions, and the reliability of the bit positions in the second set of information bit positions is lower than the reliability of the bit positions in the first set of information bit positions.

[0308] In a possible implementation, the serial numbers of the bit positions in the second set of information bit positions are all greater than or equal to N / 2, where N represents the encoding length of the polar code.

[0309] In a possible implementation, the bit positions in the second set of bit positions are consecutive bit positions in a natural order bit sequence, and the natural order bit sequence is composed of consecutive N bit positions sorted in ascending order, where N represents the encoding length of the polar code.

[0310] In a possible implementation, the second set of bit positions is composed of the first N / 2 bit positions in the natural order bit sequence.

[0311] In a possible implementation, the number of bit positions in the first set of bit positions increases as N increases and decreases as E increases, where N represents the encoding length of the polar code and E represents the length of the encoding bit sequence.

[0312] In a possible implementation, the T bit positions are the T bit positions with the highest reliability in a second reliability sequence, and the second reliability sequence is composed of the bit positions in the first reliability sequence except the bit positions in the first set of bit positions.

[0313] In a possible implementation, the K-T bit positions are the K-T bit positions with the highest reliability in a third reliability sequence except the bit positions in the first set of information bit positions, and the third reliability sequence is composed of the bit positions in the first reliability sequence except the bit positions in the second set of bit positions.

[0314] For more details of the processing unit 810 and the transceiver unit 820, refer to the relevant description in the above method embodiments, which will not be repeated here.

[0315] Figure 9 FIG. 1 is an exemplary block diagram of a communication apparatus according to an embodiment of the present application. For example, the communication apparatus 10 can include a chip system 110, a memory 120, a bus 130, a power management module 140, or a transceiver 150, and the like.

[0316] The chip system 110 can be an integrated circuit chip and has the processing capability of signals. In the implementation process, each step of the above method can be completed by the integrated logic circuit of hardware or the instruction in the form of software in the chip system 110.

[0317] By way of example and not limitation, the chip system 110 can include a circuit or chip responsible for processing of signals (e.g., a modem chip, also known as a baseband chip, or a system on chip (SoC) chip or system in package (SIP) chip containing a modem core).

[0318] Optionally, the chip system 110 can also be provided with a memory (e.g., a cache) for storing instructions and data. In some embodiments, the memory in the chip system 110 is a cache memory. The memory can hold instructions or data that the chip system 110 has just used or recycled. If the chip system 110 needs to use the instructions or data again, it can be directly called from the memory. This avoids repeated access and reduces the waiting time of the chip system 110, thus improving the efficiency of the system.

[0319] In some embodiments, the chip system 110 can include one or more interfaces. The interfaces can include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a SIM interface, and / or a USB interface, etc.

[0320] The memory 120 can include a random access memory (RAM) and a read-only memory (ROM). The memory 120 can store computer-readable computer-executable code including instructions that, when executed, cause the processor to perform various functions described herein.

[0321] Optionally, the code can include instructions executable by a processor to implement aspects of the embodiments of the application. The code can be stored in a non-transitory computer-readable medium such as system memory or other type of memory. In some cases, the code can not directly executable by the processor 110 but can cause a computer (e.g., when compiled and executed) to perform functions described herein. In some cases, the memory 120 can include, among other things, a basic I / O system, which can control basic hardware or software operations, such as interaction with peripheral components or devices.

[0322] By way of example, the chip system 110 performs various functional applications and data processing of the communication device 10 by running instructions stored in the memory 120. For example, when the communication device 10 performs file transmission with other devices (which can also be terminal devices or network devices), the chip system 110 of the communication device 10 can invoke computer executable program codes stored in the memory 120 to implement the encoding method or decoding method provided by the embodiments of the application.

[0323] In addition, the memory 120 can be integrated in the above-mentioned chip system 110, or independent of the chip system 110.

[0324] The bus 130 can be a universal serial bus (USB) for supporting mutual communication between various parts in the communication device 10.

[0325] The power management module 140 is configured to receive charging input from a charger. Optionally, the power management module 140 can supply power to the communication device 10 (e.g., a battery module of the communication device 10) while charging the communication device 10. By way of example and not limitation, the power management module 140 can also supply power to devices other than the communication device 10.

[0326] The transceiver 150 can communicate bi-directionally with one or more antennas, wired or wireless links, for example. The transceiver 150 can represent a wireless transceiver and can communicate bi-directionally with another wireless transceiver, for example. The transceiver 150 can also include a modem to modulate the packets and to provide the modulated packets to the antennas for transmission, and to demodulate packets received from the antennas. The transceiver 150 can include a transmitter and a receiver, where the transmitter is configured to transmit signals and the receiver is configured to receive signals.

[0327] In some cases, the wireless device can include a single antenna. However, in some cases the device can have more than one antenna, which can be capable of concurrently transmitting and / or receiving multiple signals, and Figure 9The antennas 1 and 2 shown in FIG. 1 can be capable of transmitting or receiving multiple wireless transmissions simultaneously. Exemplarily, the antennas 1 and 2 are used for transmitting and receiving electromagnetic wave signals. Each of the antennas in the communication device 10 can be used to cover a single or multiple communication frequency bands. Different antennas can also be multiplexed to improve the utilization of the antennas. For example, the antenna 1 can be multiplexed as a diversity antenna for a wireless local area network. In some other embodiments, the antennas can be used in combination with a tuning switch. The communication device 10 can transmit files to other devices through a wireless communication function.

[0328] In one design, the communication device 10 can correspond to the first device in the method embodiments above. The device 10 can implement the steps or procedures performed by the first device in the method embodiments above, where the transceiver 150 can be used to perform the transceiving-related operations of the first device in the method embodiments above, and the chip system 110 can be used to perform the processing-related operations of the first device in the method embodiments above.

[0329] In another design, the communication device 10 can correspond to the second device in the method embodiments above. The device 10 can implement the steps or procedures performed by the second device in the method embodiments above, where the transceiver 150 can be used to perform the transceiving-related operations of the second device in the method embodiments above, and the chip system 110 can be used to perform the processing-related operations of the second device in the method embodiments above.

[0330] In this design, the communication device 10 can include modules such as the short-range communication module 164, the sensor 161, the display 162, or the camera 163 shown in FIG. 1. Figure 9

[0331] The short-range communication module 164 can include modules that support short-range communication, such as WI-FI, Bluetooth, etc.

[0332] The sensor 161 can include a pressure sensor, a gyroscope sensor, a barometric pressure sensor, a magnetic sensor, an acceleration sensor, a distance sensor, a proximity light sensor, a fingerprint sensor, a temperature sensor, a touch sensor, an ambient light sensor, a bone conduction sensor, etc.

[0333] ​Display 162 is used to display images, videos, etc. The display includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a Miniled LED, a MicroLED, a Micro-OLED, a quantum dot light-emitting diode (QLED), etc. For example, in this embodiment, the display can be used to display the interface required by the communication device 10. Exemplarily, the communication device 10 implements display functions through a GPU, a display, and an application processor. The GPU is a microprocessor for image processing, connected to the display and the application processor. The GPU performs mathematical and geometric calculations for graphics rendering. The chip system 110 may include one or more GPUs that execute program instructions to generate or modify display information.

[0334] Camera 163 is used to acquire images, videos, etc.

[0335] Understandable, Figure 9 The structure shown does not constitute a specific limitation on the communication device 10. In some embodiments, the communication device 10 may also include a structure that is more... Figure 9 This could mean having more or fewer components, combining some components, separating some components, or having different component arrangements. Or, Figure 9 Some of the components shown can be implemented in hardware, software, or a combination of software and hardware; the communication device 10 can be in... Figure 9 The components were added or removed based on the given structure.

[0336] Figure 10 This is a schematic block diagram of a communication device provided in an embodiment of this application. The communication device 20 may include a baseband unit 210, which can communicate with external devices via a cellular radio frequency (RF) transceiver 220 (e.g., if the communication device 20 is a terminal device, the baseband unit 210 can communicate with network devices via the cellular RF transceiver 220; or, if the communication device 20 is a network device, the baseband unit 210 can communicate with terminal devices and / or core network devices via the cellular RF transceiver 220).

[0337] The baseband unit 210 can include a computer-readable medium / memory. The baseband unit 210 is responsible for general processing, including the execution of software stored on the computer-readable medium / memory. The software, when executed by the baseband unit 210, causes the baseband unit 210 to perform the various functions described supra. The computer-readable medium / memory can also be used for storing data that is manipulated by the baseband unit 210 when executing software.

[0338] The baseband unit 210 further includes a reception unit 201, a management unit 202 and a transmission unit 203. The management unit 202 includes the one or more Figure 10 sub-units shown in FIG. 2. The units within the management unit 201 can be stored in a computer-readable medium / memory and / or be configured as hardware within the baseband unit 210. Among them, the reception unit 201 and the transmission unit 203 can be referred to as a transceiver unit.

[0339] Figure 11 is a schematic block diagram of a chip system provided by an embodiment of the present application. Among them, the chip system 30 includes but is not limited to a modem chip, also known as a baseband chip, or a system on chip (SoC) chip or a system in package (SIP) chip containing a modem core.

[0340] The chip system (or also referred to as a processing system) includes a processor 310, a memory 320, and an input / output interface 330.

[0341] Among them, the processor 310 can be a processing circuit (including at least one processor, such as processor 311 and processor 312 shown in FIG. 3, etc.) in the chip system. The processor 310 can be coupled to the memory 320 to call instructions in the memory 320, so that the chip system can implement the methods and functions of various embodiments of the present application. The input / output interface 330 can be an input / output circuit in the chip system, which outputs the information processed by the chip system or inputs the data or signaling information to be processed by the chip system for processing. Figure 11

[0342] As a kind of scheme, the chip system is used to implement the operation executed by the first device or the second device in each method embodiment described above.

[0343] ​For example, the processor 310 is configured to implement the processing-related operations performed by the first device or the second device in the above method embodiments, which can be specifically referred to the descriptions in the foregoing embodiments; the input / output interface 330 is configured to implement the sending and / or receiving-related operations performed by the first device or the second device in the above method embodiments, which can be specifically referred to the descriptions in the foregoing embodiments.

[0344] Figure 12 is a schematic block diagram of a chip system provided by the embodiments of the present application. The chip system 40 (or also can be referred to as a processing system) includes an input / output interface 410 and a logic circuit 420. Wherein, the input / output interface 410 can be an input / output circuit in the chip system, and is configured to output the information processed by the chip system, or input the data or signaling information to be processed into the chip system for processing, which can be specifically referred to the descriptions in the foregoing embodiments; the logic circuit 420 is configured to perform the communication method described above, which can be specifically referred to the descriptions in the foregoing embodiments.

[0345] As a solution, the chip system is configured to implement the operations performed by the first device or the second device in the above various method embodiments.

[0346] For example, the logic circuit 420 is configured to implement the processing-related operations performed by the first device or the second device in the above method embodiments; the input / output interface 410 is configured to implement the sending and / or receiving-related operations performed by the first device or the second device in the above method embodiments.

[0347] The embodiments of the present application also provide a computer readable storage medium, which has stored thereon computer instructions for implementing the method performed by the first device and / or the second device in the above various method embodiments.

[0348] For example, the computer program is executed by a computer, so that the computer can implement the method performed by the first device and / or the second device in the above method embodiments.

[0349] The embodiments of the present application also provide a computer program product, which contains instructions, and the instructions are executed by a computer to implement the method performed by the first device and / or the second device in the above various method embodiments.

[0350] The embodiments of the present application also provide a communication system, which includes the first device and the second device described above.

[0351] The explanations and beneficial effects of the related contents in any of the above-provided devices can refer to the corresponding method embodiments provided above, and will not be repeated here.

[0352] The steps of the methods in the embodiments of the present application can be implemented by hardware, or by a processor executing software instructions. The software instructions can be composed of one or more software modules. The software modules can be stored in any type of non-transitory computer-readable medium or memory, such as a random access memory (RAM), a flash memory, a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), registers, a hard disk, a floppy disk, a compact disc read-only memory (CD-ROM) or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. Of course, the storage medium can be a component of the processor. Suitable processors include, by way of example, both general and special purpose microprocessors. Suitable processors also include both general and special purpose microprocessors. The processor runs a software program to control the processor to implement processes described herein. Alternately, hardware exclusive of a processor, such as an integrated circuit, can be used to implement processes described herein. In fact, the software and / or hardware can be designed to implement processes described herein.

[0353] In the embodiments described above, all or some of the steps can be implemented by software, hardware, firmware or any combination thereof. When implemented in software, one or more computer programs can be used to perform the steps. A computer program can be stored in a non-transitory computer-readable medium, such as a computer program product, an integrated circuit, a soft disk, a compact flash, a compact disc read-only memory (CD-ROM), and so on. The computer program product can be distributed over a network, for example, and can be stored on a computer system, which can be used to execute the computer program. A computer system can include one or more computers, servers, or servers in a data center, and so on.

[0354] In various embodiments of the present application, the terms and / or descriptions among different embodiments are consistent and can be referred to each other if there is no special description and logical conflict, and the technical features among different embodiments can be combined to form new embodiments according to their inherent logical relationship.

[0355] In the present application, "at least one" means one or more, and "multiple" means two or more. The association relationship of "and / or" between the associated objects indicates that there can be three kinds of relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. In the character description of the present application, the character " / " generally represents that the associated objects before and after it are in an "or" relationship; in the formula of the present application, the character " / " represents that the associated objects before and after it are in a "division" relationship.

[0356] It can be understood that various numbers involved in the embodiments of the present application are only distinguished for the convenience of description, and are not used to limit the scope of the embodiments of the present application. The size of the serial number of the above processes does not mean the execution order, and the execution order of the processes should be determined according to their functions and inherent logic.

Claims

1. An encoding method characterized by comprising: The method comprises: obtaining an information bit sequence to be encoded, the information bit sequence comprising K bits, K being an integer greater than 1; determining a first information bit position set according to a first bit position set and a first reliability sequence of a polar code; wherein the first bit position set is used to indicate bit positions in the first reliability sequence that are frozen when determining the first information bit position set, the first reliability sequence is used to indicate an order of reliability degrees of bit positions in the polar code, and the first information bit position set is used to indicate T bit positions, the T bit positions being used to carry T bits in the K bits, T being a positive integer; determining a second information bit position set according to a second bit position set and the first reliability sequence; wherein the second bit position set is used to indicate bit positions in the first reliability sequence that are frozen when determining the second information bit position set, and the second information bit position set is used to indicate K-T bit positions, the K-T bit positions being used to carry K-T bits in the K bits other than the T bits; performing polar code encoding on the information bit sequence according to the first information bit position set and the second information bit position set, to obtain an encoded bit sequence.

2. A decoding method, comprising: The method comprises: obtaining an encoded bit sequence, the encoded bit sequence comprising an information bit sequence, the information bit sequence comprising K bits, K being an integer greater than 1; determining a first information bit position set according to a first bit position set and a first reliability sequence of a polar code; wherein the first bit position set is used to indicate bit positions in the first reliability sequence that are frozen when determining the first information bit position set, the first reliability sequence is used to indicate an order of reliability degrees of bit positions in the polar code, and the first information bit position set is used to indicate T bit positions, the T bit positions being used to carry T bits in the K bits, T being a positive integer; determining a second information bit position set according to a second bit position set and the first reliability sequence; wherein the second bit position set is used to indicate bit positions in the first reliability sequence that are frozen when determining the second information bit position set, and the second information bit position set is used to indicate K-T bit positions, the K-T bit positions being used to carry K-T bits in the K bits other than the T bits; performing polar code decoding on the encoded bit sequence according to the first information bit position set and the second information bit position set, to obtain the information bit sequence.

3. The method of claim 1 or 2, wherein, The first bit position set is used to indicate punctured or shortened bit positions.

4. The method of claim 3, wherein, wherein denotes the ceiling function.

5. The method of claim 3, wherein, T is related to one or more of K, E, R, or N; wherein E represents a length of the encoded bit sequence, R represents a code rate and R = K / E, and N represents a code length of the polar code.

6. The method of claim 5, wherein When 9 / 16 <= E / N, when 17 / 32 <= E / N < 9 / 16, When E / N < 17 / 32, wherein denotes the ceiling function.

7. The method of any one of claims 1 to 6, wherein, the code rate R is less than or equal to 7 / 8.

8. The method of claim 1 or 2, wherein, The first bit position set comprises a rate matching position set, and a number of bit positions in the first bit position set is greater than a number of bit positions in the rate matching position set, the rate matching position set being used to indicate punctured or shortened bit positions.

9. The method of claim 8, wherein, The first bit position set is a proper subset of the second bit position set.

10. The method of claim 8 or 9, wherein, T is related to one or more of K, E, or N; wherein E represents a length of the encoded bit sequence, and N represents a code length of the polar code.

11. The method of claim 10, wherein, When 3 / 4 <= E / N, When 5 / 8 <= E / N < 3 / 4, When E / N < 5 / 8, wherein denotes the ceiling function.

12. The method of any one of claims 8 to 11, wherein, The bit positions in the first bit position set are consecutive bit positions in a natural order bit sequence, the natural order bit sequence being composed of consecutive N bit positions sorted from small to large, the N representing a code length of the polar code.

13. The method of any one of claims 1 to 12, wherein, The first information bit position set has no intersection with the second information bit position set, and a reliability of bit positions in the second information bit position set is lower than a reliability of bit positions in the first information bit position set.

14. The method of any one of claims 1 to 13, wherein, The bit positions in the second information bit position set all have a serial number greater than or equal to N / 2, wherein N represents a code length of the polar code.

15. The method of any one of claims 1 to 14, wherein, The bit positions in the second bit position set are consecutive bit positions in a natural order bit sequence, the natural order bit sequence being composed of consecutive N bit positions sorted from small to large, the N representing a code length of the polar code.

16. The method of claim 15, wherein, The second bit position set is composed of the first N / 2 bit positions in the natural order bit sequence.

17. The method of any one of claims 1 to 16, wherein, The T bit positions are T bit positions with the highest reliability in a second reliability sequence, the second reliability sequence being composed of bit positions in the first reliability sequence other than the first bit position set.

18. The method of any one of claims 1 to 17, wherein, The K-T bit positions are K-T bit positions with the highest reliability in a third reliability sequence other than the first information bit position set, the third reliability sequence being composed of bit positions in the first reliability sequence other than the second bit position set.

19. A communications device, characterized by The apparatus comprises a processor and an interface circuit, the processor being configured to communicate with other devices through the interface circuit, and perform the method of any one of claims 1, 3-18, or perform the method of any one of claims 2-18.

20. A computer program product, characterised in that, The computer program product comprises instructions that, when executed on a processor, cause the processor to perform the method of any one of claims 1, 3-18, or perform the method of any one of claims 2-18.

21. A computer-readable storage medium, characterized in that, The storage medium stores a computer program or instructions, which, when executed by a communication device, implement the method of any one of claims 1, 3-18, or implement the method of any one of claims 2-18.

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