Summing circuit, operational circuit, circuit for executing hash algorithm and related device

Abstract

The invention relates to a summing circuit, an operational circuit, a circuit for executing a hash algorithm and a related device. The summing circuit has first and second inputs, each input being correspondingly divided to include first to Nth portions in order from low to high, N being an integer greater than 1. The summing circuit comprises a carry logic module used for calculating one or more carry bits, and each carry bit corresponds to a carry bit generated by adding a corresponding part of the first input and a corresponding part of the second input; the first register module and the second register module are respectively used for storing first to (N-1)-th parts of the first input and the second input; the third register module is used for storing the one or more carry bits; a first summation logic module for summing the Nth portions of the first and second inputs to produce an intermediate sum; and the fourth register module is used for storing the intermediate sum. And the second summation logic module is used for summing the first to (N-1) th parts of the first and second inputs, the intermediate sum and the one or more carry bits.

Description

TECHNICAL FIELD

[0001] The present disclosure generally relates to an addition circuit, an operation circuit, a circuit for performing a hash algorithm, a computing chip and a computing device. BACKGROUND

[0002] A hash algorithm is an algorithm that takes variable-length data as input and produces a fixed-length hash value as output, and its essence is to refine information. Since 1993, the U.S. Institute of Standards and Technology has designed and published multiple versions of the Secure Hash Algorithm (SHA), and SHA-256 is one of the secure hash algorithms with a hash length of 256 bits. SUMMARY

[0003] According to a first aspect of the present disclosure, an addition circuit is provided for calculating the sum of a first number and a second number, the addition circuit having a first input representing the first number and a second input representing the second number and having an output representing the sum of the first number and the second number, each of the first input and the second input being divided into 1st to Nth parts corresponding to each other, N being an integer greater than 1, the 1st to Nth parts representing the partial bits of the input in turn from low to high, the addition circuit comprising: a carry logic module configured to calculate one or more carries, each of the one or more carries corresponding to a carry generated by adding a corresponding one of the first input and a corresponding part of the second input; a first register module configured to store the 1st to N-1th parts of the first input; a second register module configured to store the 1st to N-1th parts of the second input; a third register module coupled to the carry logic module and configured to store the one or more carries; a first summing logic module configured to sum the Nth part of the first input and the Nth part of the second input, thereby generating an intermediate sum; a fourth register module coupled to the first summing logic module and configured to store the intermediate sum; and a second summing logic module coupled to the first to fourth register modules and configured to sum the 1st to N-1th parts of the first input, the 1st to N-1th parts of the second input, the intermediate sum and the one or more carries, wherein the sum output by the second summing logic module represents the partial bits of the output in turn from low to high.

[0004] In some embodiments, the carry logic module is configured to calculate the one or more carries using look-ahead carry logic.

[0005] In some embodiments, the first summing logic module is implemented as a ripple-carry adder.

[0006] In some embodiments, the second summing logic module is implemented as a plurality of ripple-carry adders in parallel.

[0007] In some embodiments, N is an integer greater than 2, and wherein: the carry logic module is configured to compute N-2 carries, an i-th carry of the N-2 carries corresponding to a carry resulting from adding an i-th portion of the first input and an i-th portion of the second input, i = 1,..., N-2; the first register module and the second register module each include 1st through (N-1)th cells, and the second sum logic module includes 1st through (N-1)th adders; a j-th cell of the first register module is configured to store a j-th portion of the first input, a j-th cell of the second register module is configured to store a j-th portion of the second input, and a j-th adder of the second sum logic module is coupled to the j-th cell of the first register module and the j-th cell of the second register module, j = 1,..., N-1; a 1st adder of the second sum logic module is configured to sum the 1st portion of the first input and the 1st portion of the second input; and an (N-1)th adder of the second sum logic module is further coupled to the third register module and the fourth register module and is configured to sum the (N-1)th portion of the first input, the (N-1)th portion of the second input, the intermediate sum, and an (N-2)th carry of the N-2 carries.

[0008] In some embodiments, N is an integer greater than 3, and wherein a k-th adder of the second sum logic module is further coupled to the third register module and is configured to sum the k-th portion of the first input, the k-th portion of the second input, and a (k-1)th carry of the N-2 carries, k = 2,..., N-2.

[0009] In some embodiments, each of the 1st through (N-2)th portions of each of the first input and the second input has a first number of bits, and the (N-1)th through Nth portions of the input collectively have a second number of bits, the second number of bits being equal to the first number of bits.

[0010] In some embodiments, the carry logic module includes: a preprocessor configured to perform an exclusive-OR operation and an AND operation on each bit of the 1st through (N-2)th portions of the first input and a corresponding bit of the 1st through (N-2)th portions of the second input, respectively, in parallel, thereby generating a corresponding carry signal and a generate signal; and a carry generator configured to generate the N-2 carries using the carry signals and the generate signals generated by the preprocessor.

[0011] In some embodiments, the carry logic module is configured to compute N-1 carries, an i-th carry of the N-1 carries corresponding to a carry resulting from adding an i-th portion of the first input and an i-th portion of the second input, i = 1, …, N-1; the first register module and the second register module each include 1st to (N-1)th cells, and the second sum logic module includes 1st to Nth adders; a j-th cell of the first register module is configured to store a j-th portion of the first input, a j-th cell of the second register module is configured to store a j-th portion of the second input, and a j-th adder of the second sum logic module is coupled to the j-th cell of the first register module and the j-th cell of the second register module, j = 1, …, N-1; a 1st adder of the second sum logic module is configured to sum the 1st portion of the first input and the 1st portion of the second input; and an Nth adder of the second sum logic module is further coupled to a third register module and a fourth register module, and is configured to sum an intermediate sum and an (N-1)th carry of the N-1 carries.

[0012] In some embodiments, N is an integer greater than 2, and wherein a k-th adder of the second sum logic module is further coupled to the third register module and is configured to sum the k-th portion of the first input, the k-th portion of the second input, and a (k-1)th carry of the N-1 carries, k = 2, …, N-1.

[0013] In some embodiments, each portion of each of the first input and the second input has the same number of bits.

[0014] In some embodiments, the carry logic module includes: a preprocessor configured to perform an exclusive-OR operation and an AND operation on each bit of the 1st to (N-1)th portions of the first input and a corresponding bit of the 1st to (N-1)th portions of the second input, respectively, in parallel, thereby generating a corresponding carry signal and a generate signal; and a carry generator configured to generate the N-1 carries using the carry signals and the generate signals generated by the preprocessor.

[0015] In some embodiments, the carry generator includes a parallel prefix network.

[0016] According to a second aspect of the present disclosure, there is provided an arithmetic circuit, comprising: a sum module including an adder circuit according to any embodiment of the first aspect of the present disclosure; and a first arithmetic module coupled to the sum module to provide a first input and a second input of the adder circuit.

[0017] In some embodiments, the arithmetic circuit includes a plurality of arithmetic stages, each of the plurality of arithmetic stages includes a respective register module, and the plurality of arithmetic stages includes a first arithmetic stage and a second arithmetic stage immediately following the first arithmetic stage, the second arithmetic stage further includes the first to fourth register modules of the adder circuit, a first arithmetic module is arranged between the first arithmetic stage and the second arithmetic stage and is coupled to the first respective register module of the first arithmetic stage, the first arithmetic module is configured to operate on data from the first respective register module to produce the first input and the second input of the adder circuit, and the carry logic module and the first sum logic module of the adder circuit are arranged between the first arithmetic stage and the second arithmetic stage.

[0018] In some embodiments, the plurality of arithmetic stages further includes a third arithmetic stage immediately following the second arithmetic stage, a third respective register module of the third arithmetic stage is coupled to the sum module to receive the output of the adder circuit, and a second sum logic module of the adder circuit is arranged between the second arithmetic stage and the third arithmetic stage.

[0019] In some embodiments, the arithmetic circuit further includes: a second arithmetic module arranged between the second arithmetic stage and the third arithmetic stage and coupled to the second respective register module of the second arithmetic stage, the second arithmetic module is configured to operate on data from the second respective register module.

[0020] In some embodiments, the sum module is a first sum module, the adder circuit is a first adder circuit, and the arithmetic circuit further includes: a second sum module including a second adder circuit, the second adder circuit is the adder circuit according to any of the embodiments of the first aspect of the present disclosure, wherein the third arithmetic stage further includes the first to fourth register modules of the second adder circuit, the second arithmetic module is coupled to the second sum module to provide the first input and the second input of the second adder circuit, and is configured to operate on data from the second respective register module to produce the first input and the second input of the second adder circuit, and the carry logic module and the first sum logic module of the second adder circuit are arranged between the second arithmetic stage and the third arithmetic stage.

[0021] According to a third aspect of the present disclosure, there is provided a circuit for performing a hash algorithm, comprising: an input configured to receive data; and an operation configured to calculate a hash value based on the received data, and comprising a plurality of operation stages arranged in a pipeline structure, wherein: the plurality of operation stages comprises a first operation stage and a second operation stage immediately following the first operation stage, each of the first operation stage and the second operation stage comprises a 0th extension register module to a 15th extension register module configured to store 0th extension data to 15th extension data of the operation stage respectively, the 15th extension register module comprises a first sum register submodule, a second sum register submodule, a first carry register submodule and a second carry register submodule, the circuit further comprises a first extension data operation module arranged between the first operation stage and the second operation stage, the first extension data operation module comprises a first submodule, a second submodule and a third submodule, the first submodule is configured to calculate an initial sum and an initial carry based on the 0th extension data of the first operation stage and based on at least two of the 1st extension data, the 9th extension data and the 14th extension data of the first operation stage, each of the initial sum and the initial carry is divided into 1st to Nth parts corresponding to each other to include, N is an integer greater than 2, the 1st to Nth parts sequentially represent partial bits of each of them from low to high, wherein the 1st to N-1th parts of the initial sum are stored in the first sum register submodule of the 15th extension register module of the second operation stage, and the 1st to N-1th parts of the initial carry are stored in the first carry register submodule of the 15th extension register module of the second operation stage, the second submodule is configured to calculate N-2 carries, the i-th carry of the N-2 carries corresponds to a carry generated by adding the i-th part of the initial sum and the i-th part of the initial carry, i = 1, …, N-2, the N-2 carries are stored in the second carry register submodule of the 15th extension register module of the second operation stage, and the third submodule is configured to sum the Nth part of the initial sum and the Nth part of the initial carry, thereby generating an intermediate sum, the intermediate sum is stored in the second sum register submodule of the 15th extension register module of the second operation stage.

[0022] In some embodiments, the plurality of operation stages further comprises a third operation stage immediately following the second operation stage, the third operation stage comprising a 14th extension register module configured to store the 14th extension data of the operation stage, and wherein the circuit further comprises a second extension data operation module arranged between the second operation stage and the third operation stage, the second extension data operation module comprising a fourth sub-module, the fourth sub-module comprising 1st to N-1st adders, wherein the 1st adder is configured to sum the 1st part of the initial summand and the 1st part of the initial carry, wherein the N-1st adder is configured to sum the N-1st part of the initial summand, the N-1st part of the initial carry, the intermediate summand and the N-2nd carry of the N-2 carries, and wherein the N-1 sums outputted by the 1st to N-1st adders are stored in the 14th extension register module of the third operation stage.

[0023] In some embodiments, N is an integer greater than 3, wherein the kth adder of the fourth sub-module is configured to sum the kth part of the initial summand, the kth part of the initial carry and the k-1th carry of the N-2 carries, k = 2, …, N-2.

[0024] According to a fourth aspect of the present disclosure, there is provided a circuit for performing a hash algorithm, comprising: an input configured to receive data; and an operation configured to calculate a hash value based on the received data, and comprising a plurality of operation stages arranged in a pipeline structure, wherein: the plurality of operation stages comprises a first operation stage and a second operation stage immediately following the first operation stage, each of the first operation stage and the second operation stage comprises a 0th extension register module to a 15th extension register module configured to store 0th extension data to 15th extension data of the operation stage respectively, the 15th extension register module comprises a first sum register submodule, a second sum register submodule, a first carry register submodule and a second carry register submodule, the circuit further comprises a first extension data operation module arranged between the first operation stage and the second operation stage, the first extension data operation module comprises a first submodule, a second submodule and a third submodule, the first submodule is configured to calculate an initial sum and an initial carry based on the 0th extension data of the first operation stage and based on at least two of the 1st extension data, the 9th extension data and the 14th extension data of the first operation stage, each of the initial sum and the initial carry is divided into 1st to Nth parts corresponding to each other to include, N is an integer greater than 1, the 1st to Nth parts sequentially represent partial bits of each of them from low to high, wherein the 1st to N-1th parts of the initial sum are stored in the first sum register submodule of the 15th extension register module of the second operation stage, and the 1st to N-1th parts of the initial carry are stored in the first carry register submodule of the 15th extension register module of the second operation stage, the second submodule is configured to calculate N-1 carries, the i-th carry of the N-1 carries corresponds to a carry generated by adding the i-th part of the initial sum and the i-th part of the initial carry, i = 1, …, N-1, the N-1 carries are stored in the second carry register submodule of the 15th extension register module of the second operation stage, and the third submodule is configured to sum the Nth part of the initial sum and the Nth part of the initial carry, thereby generating an intermediate sum, the intermediate sum is stored in the second sum register submodule of the 15th extension register module of the second operation stage.

[0025] In some embodiments, the plurality of operation stages further comprises a third operation stage immediately following the second operation stage, the third operation stage comprising a 14th extension register module configured to store the 14th extension data of the operation stage, and wherein the circuit further comprises a second extension data operation module arranged between the second operation stage and the third operation stage, the second extension data operation module comprising a fourth sub-module, the fourth sub-module comprising 1st to Nth adders, wherein the 1st adder is configured to sum the 1st part of the initial summand and the 1st part of the initial carry, wherein the Nth adder is configured to sum the intermediate summand and the N-1th carry of the N-1 carries, and wherein the N summands output by the 1st to Nth adders are stored in the 14th extension register module of the third operation stage.

[0026] In some embodiments, N is an integer greater than 2, wherein the kth adder of the fourth sub-module is configured to sum the kth part of the initial summand, the kth part of the initial carry and the k-1th carry of the N-1 carries, k = 2, …, N-1.

[0027] According to a fifth aspect of the present disclosure, there is provided a computing chip comprising the circuit according to any of the first to fourth aspects of the present disclosure.

[0028] According to a sixth aspect of the present disclosure, there is provided a computing device comprising the computing chip according to the fifth aspect of the present disclosure.

[0029] Other features and advantages of the present disclosure will become more apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the attached drawings. BRIEF DESCRIPTION OF DRAWINGS

[0030] The accompanying drawings, which constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0031] The present disclosure can be understood more fully with reference to the following detailed description, taken in conjunction with the accompanying drawings, in which: Figure 1 is a schematic block diagram illustrating an operation circuit in some examples; Figure 2 is a schematic block diagram illustrating an adder circuit according to some embodiments of the present disclosure; Figure 3 is a schematic block diagram illustrating a carry logic module of an adder circuit according to some embodiments of the present disclosure; Figures 4A-4Cis a schematic block diagram illustrating a carry lookahead adder (CLA), a parallel prefix adder (PPA), and a parallel prefix network in some examples; Figure 5 is a schematic block diagram illustrating an example implementation of a carry logic module of the adder circuit of Figure 2 ; Figure 6 is a schematic block diagram illustrating an example implementation of a first sum logic module and a second sum logic module of the adder circuit of Figure 2 ; Figure 7 is a schematic block diagram illustrating an adder circuit according to further embodiments of the present disclosure; Figure 8 is a schematic block diagram illustrating a carry logic module of the adder circuit according to further embodiments of the present disclosure; Figure 9 is a schematic block diagram illustrating an example implementation of a carry logic module of the adder circuit of Figure 7 ; Figure 10 is a schematic block diagram illustrating an example implementation of a first sum logic module and a second sum logic module of the adder circuit of Figure 7 ; Figure 11 is a schematic block diagram illustrating an arithmetic circuit according to some embodiments of the present disclosure; Figure 12 is a schematic block diagram illustrating an arithmetic circuit according to further embodiments of the present disclosure; Figure 13 is a schematic block diagram illustrating an arithmetic circuit according to yet further embodiments of the present disclosure; Figure 14 is a schematic block diagram illustrating an arithmetic circuit according to still further embodiments of the present disclosure; Figure 15 is a schematic diagram illustrating an exemplary pipeline structure for performing the SHA-256 algorithm; Figure 16 is a schematic diagram illustrating a first example of an extension register module of an arithmetic stage in the pipeline structure in Figure 15 , and an extension data arithmetic module between adjacent arithmetic stages; Figure 17 is a schematic diagram illustrating a second example of an extension register module of an arithmetic stage in the pipeline structure in Figure 15 , and an extension data arithmetic module between adjacent arithmetic stages; Figure 18 is a schematic diagram illustratingFigure 15 A schematic diagram of the third example of the extended register module of the arithmetic stage and the extended data operation module between adjacent arithmetic stages in the pipeline structure; Figure 19 This is a schematic block diagram illustrating a circuit for performing a hash algorithm according to some embodiments of the present disclosure; Figure 20 This is a schematic block diagram illustrating a circuit for performing a hash algorithm according to other embodiments of the present disclosure; Figure 21 It is shown Figure 20 A schematic diagram of a first example of the extended register module of the arithmetic stage and the extended data arithmetic module between adjacent arithmetic stages in the circuit shown; Figure 22 It is shown Figure 20 A schematic diagram of a second example of the extended register module of the arithmetic stage and the extended data arithmetic module between adjacent arithmetic stages in the circuit shown, and Figure 23 It is shown Figure 22 A schematic block diagram of the extended data processing module in the diagram; Figure 24 It is shown Figure 20 A schematic diagram of the third example of the extended register module of the arithmetic stage and the extended data arithmetic module between adjacent arithmetic stages in the circuit shown, and Figure 25 It is shown Figure 24 A schematic block diagram of the extended data processing module in the diagram.

[0032] Note that in the embodiments described below, the same reference numerals are sometimes used across different figures to denote the same parts or parts having the same function, and repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0033] For ease of understanding, the positions, dimensions, and extents of the structures shown in the accompanying drawings and other materials may not represent actual positions, dimensions, and extents. Therefore, the disclosed invention is not limited to the positions, dimensions, and extents disclosed in the accompanying drawings and other materials. Furthermore, the drawings are not necessarily drawn to scale, and some features may be enlarged to show details of specific components. Detailed Implementation

[0034] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0035] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use. Those skilled in the art will understand that they are merely illustrative of exemplary ways that can be used to implement the invention, and not exhaustive.

[0036] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0037] It should be understood that, unless explicitly stated otherwise or derived from the context, when referring to a carry resulting from addition or summation, the carry usually refers to the final carry.

[0038] Figure 1 These are schematic diagrams of the operational circuit 10 in some examples. For example... Figure 1 As shown, the arithmetic circuit 10 includes a summing module 12. The summing module 12 is configured to sum a first number a and a second number b, thereby producing a sum s and a carry c. The arithmetic circuit 10 also includes an arithmetic module 11, which is coupled before the summing module 12 and configured to perform the operation to produce the first number a and the second number b. For example, the summing module 12 can be implemented as an adder (ADD), while the arithmetic module 11 can be implemented as a combinational logic circuit. Generally, an ADD can have two inputs and one output, thus reducing one operand; however, an ADD has more stages, more glitches, a larger area, and higher power consumption. Especially when the input of the ADD comes from a combinational logic circuit, the adder has high power consumption due to high glitches.

[0039] To this end, the present disclosure provides an adder circuit that can have reduced glitch, and in turn, lower power consumption. For example, such an adder circuit can be used to compute a sum of a first number and a second number. The adder circuit can have a first input representing the first number and a second input representing the second number and have an output representing the sum of the first number and the second number. Each of the first input and the second input is correspondingly partitioned into 1st to Nth portions. For example, N can be an integer greater than 1. The 1st to Nth portions of each input represent partial bits of the input in order from a lower bit to a higher bit. Such an adder circuit can include a carry logic module configured to compute one or more carries, each of the one or more carries corresponding to a carry generated by adding a respective one of the 1st to Nth portions of the first input and a corresponding one of the 1st to Nth portions of the second input; a first register module configured to store the 1st to N-1th portions of the first input; a second register module configured to store the 1st to N-1th portions of the second input; a third register module coupled to the carry logic module and configured to store the one or more carries; a first sum logic module configured to sum the Nth portion of the first input and the Nth portion of the second input, thereby generating an intermediate sum; a fourth register module coupled to the first sum logic module and configured to store the intermediate sum; and a second sum logic module coupled to the first to fourth register modules and configured to sum the 1st to N-1th portions of the first input, the 1st to N-1th portions of the second input, the intermediate sum, and the one or more carries. The sum output by the second sum logic module can represent partial bits of the output in order from a lower bit to a higher bit.

[0040] The circuits according to various embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. It should be understood that actual circuits can also include other additional components, but in order to avoid obscuring the gist of the present disclosure, these additional components are not discussed herein and are not shown in the accompanying drawings.

[0041] Figure 2 is a schematic diagram of an adder circuit 100 according to some embodiments of the present disclosure. For example, the adder circuit 100 is configured to compute a sum of a first number a and a second number b. The adder circuit 100 can have a first input representing the first number a and a second input representing the second number b and have an output representing the sum s of the first number a and the second number b. Each of the first input a and the second input b is correspondingly partitioned into 1st to Nth portions (N being an integer greater than 2) that represent partial bits of the input in order from a lower bit to a higher bit. For example, the first input a includes a 1st portion a1, a 2nd portion a2, …, an (N-1)th portion a N-1 , a Nth portion a N (i.e., a = [a N , a N-1The second input b includes part 1 b1, part 2 b2, ..., part N-1 b1. N-1 Part Nb N (That is, b = [b N , b N-1 The value of N can be determined according to specific needs, for example, it can be 3, 4, 5, 6, 7, 8, etc.

[0042] like Figure 2 As shown, the adder circuit 100 includes a first register module 102, a second register module 104, a third register module 106, a fourth register module 108, a carry logic module 112, a first summation logic module 114, and a second summation logic module 110.

[0043] The first register module 102 is configured to store the first to N-1th portions of the first input a. Specifically, the first register module 102 includes a first unit 1021, a second unit 1022, ..., an N-1th unit 102. N-1 Each unit is configured to store a corresponding portion of the first input a. For example, the j-th unit 102 of the first register module 102. j Configured to store the j-th part a of the first input a j (j=1,…,N-1).

[0044] The second register module 104 is configured to store the first to the (N-1)th portions of the second input b. Specifically, the second register module 104 includes a first unit 1041, a second unit 1042, ..., an (N-1)th unit 104. N-1 Each unit is configured to store a corresponding portion of the second input b. For example, the j-th unit 104 of the second register module 104... j Configured to store the j-th part of the second input b j (j=1,…,N-1).

[0045] Carry logic module 112 is configured to calculate N-2 carry values ​​c1, ..., c N-2 Carry-over c1, ..., c N-2 Each of the elements in the set has one bit. The carry bits are c1, ..., c1. N-2 The i-th carry c i The i-th part a corresponding to the first input a i With the i-th part of the second input b i The carry generated by the addition (i=1, ..., N-2). For example, the carry logic module 112 can receive at least the first to N-2 parts a1, ..., a2 of the first input a. N-2And at least the first to N-2th parts of the second input b, b1, ..., b N-2 Then, the carry-lookahead logic is used to calculate these N-2 carry-in c1, ..., c2. N-2 Therefore, the carry logic module 112 does not need to sum each bit of the received input, but can quickly obtain the carry at the required bit position by jumping. An exemplary implementation of the carry logic module 112 will be described in detail below with reference to the accompanying drawings.

[0046] The third register module 106 can be coupled to the carry logic module 112 and configured to store the N-2 carry c1, ..., c2. N-2 .

[0047] The first summation logic module 114 and the second summation logic module 110 are configured to cooperate in calculating the sum s of a first number a and a second number b. For example, the first summation logic module 114 may include an adder configured to add the Nth part a of the first input a. N The Nth part of the second input b N Summing, thus producing the intermediate sum s m The "intermediate sum" here refers to the sum output by the second summing logic module 110, while it is the final output sum for the adder of the first summing logic module 114. The adder of the first summing logic module 114 outputs the sum for a... N With b N Carry generated during summation can be discarded. The fourth register module 108 is coupled to the first summation logic module 114 and is configured to store the intermediate sum s. m .

[0048] The second summation logic module 110 is coupled to the first to fourth register modules 102-108 to receive the first to N-1 parts a1, ..., a1 of the first input a. N-1 The first to N-1 parts of the second input b, b1, ..., b N-1 , middle and number s m and carry c1, ..., c N-2 And sum them.

[0049] The second summation logic module 110 includes a first adder 1101, a second adder 1102, ..., an (N-1)th adder 110 N-1 The second summation logic module 110 includes the first adder 1101, the second adder 1102, ..., the (N-1)th adder 110. N-1 Each adder in the second summing logic module 110 is coupled to a corresponding unit in the first register module 102 and a corresponding unit in the second register module 104. For example, the j-th adder 110 in the second summing logic module 110... jThe jth cell 102 of the first register module 102 is coupled to the (j-1)th cell 102 of the first register module 102 and the (j+1)th cell 102 of the first register module 102. j The jth cell 104 of the second register module 104 is coupled to the (j-1)th cell 104 of the second register module 104 and the (j+1)th cell 104 of the second register module 104. j The jth cell 102 of the first register module 102 is coupled to the (j-1)th cell 102 of the first register module 102 and the (j+1)th cell 102 of the first register module 102. j The jth cell 104 of the second register module 104 is coupled to the (j-1)th cell 104 of the second register module 104 and the (j+1)th cell 104 of the second register module 104. j (j = 1, …, N-1).

[0050] The first adder 1101 of the second summation logic module 110 is configured to sum the first part a1 of the first input a and the first part b1 of the second input b, thereby generating the first sum s1. The (N-1)th adder 110 N-1 The (N-1)th adder 110 N-1 of the second summation logic module 110 is further coupled to the third register module 106 and the fourth register module 108, and is configured to sum the (N-1)th part a N-1 of the first input a, the (N-1)th part b m of the second input b, the intermediate sum s N-2 and the (N-2)th carry c N-2 of the carries c1, …, c N-1 , thereby generating the (N-1)th sum s k . In the case where N is an integer greater than 3, the kth adder 110 k of the second summation logic module 110 is further coupled to the third register module 106, thereby receiving the (k-1)th carry c N-2 of the carries c1, …, c k-1 (k = 2, …, N-2). The kth adder 110 k is configured to sum the kth part a k of the first input a, the kth part b k of the second input b, and the (k-1)th carry c k-1 , thereby generating the kth sum s k . The N-1 sums s1, s2, …, s N-1 outputted by the first to (N-1)th adders of the second summation logic module 110 represent the partial bits of the output s from low to high (i.e., s = [s N-1 , s N-2 , …, s1]).

[0051] In fact, the jth adder 110 j (j = 1, …, N-1) generates a carry c j in addition to the sum s j when summing the jth part a j of the first input a and the jth part b j of the second input b, and this carry c j needs to be provided to the (j+1)th adder 110j+1 Only then can it correctly obtain the (j+1)th part a of the first input a. j+1 The (j+1)th part of the second input b j+1 The sum of s j+1 However, carry signals often have many glitches. If we let the j-th adder be 110... j Carry c j Output to the (j+1)th adder 110 j+1 This will lead to carry c j The glitch propagates to the (j+1)th adder 110 j+1 This results in increased power consumption. In contrast, in the adder circuit taught in this disclosure, such as... Figure 2 As shown, carry c1, ..., c N-2 The carry logic module 112 calculates the value in advance and stores it in the third register module 106. The second adder 1102 to the (N-1)th adder 110 of the second summation logic module 110. N-1 The inputs all come from registers, thus enabling glitch reduction or even elimination (e.g., by fine-tuning the register clock or register drive). The second adder 1102 to the (N-1)th adder 110 of the second summing logic module 110. N-1 All have ample setup time spanning a full cycle with minimal glitches, resulting in reduced power consumption. Furthermore, the first adder 1101 of the second summing logic module 110 and the adders of the first summing logic module 114 themselves do not have carry-over from lower bits, thus exhibiting smaller glitches and lower power consumption. In the adder circuit 100, the first adder 1101 to the (N-1)th adder 110 of the second summing logic module 110... N-1 All carry-in bits generated can be discarded, and the resulting sum is directly the corresponding bits of the sum s.

[0052] Therefore, with Figure 1 In contrast, adder circuit 100 separates the summation logic circuit of the adder into a first part (e.g., first summation logic module 114) for processing the most significant bit (MSB) and a second part (e.g., second summation logic module 110) primarily for processing the least significant bit (LSB). Furthermore, it separates the carry logic circuit and the second part of the summation logic circuit. The carry logic and the first part of the summation logic can be performed in one clock cycle, with the calculated carry and the sum of the MSB stored in registers respectively. The second part of the summation logic can be performed in the next clock cycle based on input from the registers. This reduces the glitches from the carry logic circuit to the summation logic circuit. Additionally, the summation logic circuit of adder circuit 100 further breaks down a large-scale adder into N smaller-scale adders. The total area of ​​the adders in the first summation logic module 114 and the second summation logic module 110 can be less than [a certain value].Figure 1 The area of the adders of the summation module 12 is thus reduced, and a reduced power consumption can be achieved. The N-1 adders among the N smaller scale adders that are located in the second part of the summation logic circuit (e.g., the 1st adder 1101 to the N-1 adder 110 N-1 ) can be parallel, and a reduced delay and an increased processing speed can be achieved.

[0053] Taking the example that the first number a and the second number b each include 32 bits and are split into three parts (16 bits + 8 bits + 8 bits), the summation module 12 of the operation circuit 10 needs a 32-bit adder, while the second summation logic module 110 of the adder circuit 100 only needs 2 16-bit adders and the first summation logic module 114 only needs 1 8-bit adder. Generally speaking, the area of a 32-bit adder can be equivalent to the area of three 16-bit adders, and the area of a 16-bit adder can be equivalent to the area of three 8-bit adders. In addition, a carry lookahead adder (CLA) is often needed to implement a 32-bit adder with a smaller delay, but the CLA often consumes a lot of chip area. A ripple carry adder (RCA) has a much smaller area than the CLA and is comparable to a full adder (FAA), but the delay stage of a 32-bit ripple carry adder is as high as 32 stages, and the speed is too slow. However, in the adder circuit taught in the present disclosure, the 32-bit adder can be split into 2 parallel 16-bit adders and 1 8-bit adder in series before the 16-bit adders, and these parallel smaller scale adders in the second summation logic module 110 can be implemented as RCAs, so that both the speed close to the CLA and the fewer glitches, smaller area and lower power consumption can be achieved. In addition, for example, when the adder circuit 100 is applied in a pipeline structure (e.g., as described later with respect to Figures 21-25 the first part of the summation logic of each beat can be parallel with the second part of the summation logic of the last beat, and thus the smaller scale adders in the first summation logic module can also be implemented as RCAs, so that both the speed close to the CLA and the fewer glitches, smaller area and lower power consumption can be achieved.

[0054] Each of the first through fourth register modules 102-108 can, for example, be implemented as a combination of single-bit registers. The number of single-bit registers included in each register module can depend on the number of bits that the register module is to store. In some examples, each of the first to N-2 portions of each of the first input a and the second input b has a first bit, and the N-1 to N portions of that input have a total of a second bit. For example, the second bit can be equal to the first bit. This can allow the adder circuit 100' to have a smaller computational delay in some cases, such as when it is applied in a pipelined structure (e.g., as will be discussed later). Figures 21-25 (As described). In some examples, the second digit may also be greater than or less than the first digit. In some embodiments, each of the first input a and the second input b is partitioned such that the difference between the first digit and the second digit is minimized.

[0055] For example, if the total number of bits in each input from the (N-1)th part to the Nth part remains unchanged, increasing the Nth part by one bit reduces the (N-1)th part by one bit, thus affecting the (N-1)th unit 102 of the first register module 102. N-1 The (N-1)th unit 104 of the second register module 104 N-1 Each part uses one less single-bit register, while the fourth register module 108 uses one more single-bit register, thus reducing the overall number of single-bit registers by one. On the other hand, adding one bit to the Nth part also means that the first summing logic module 114, which is implemented as RCA, adds one level of delay.

[0056] In some examples, the number of bits in the (N-1)th part of each of the first inputs a and the second input b is equal to the number of bits in the Nth part of that input. Depending on the specific requirements, the number of bits in the (N-1)th part of each of the first inputs a and the second input b may also be greater than or less than the number of bits in the Nth part of that input. In some examples, the number of bits in the (N-1)th part of each of the first inputs a and the second input b is less than the number of bits in each of the first to N-2 parts of that input. In some examples, two or more parts of each of the first inputs a and the second input b may have the same or different numbers of bits.

[0057] Figure 3 The carry logic module 112 of an adder circuit 100 according to some embodiments of the present disclosure is shown. For example... Figure 3 As shown, the carry logic module 112 may include a preprocessor 1122 and a carry generator 1124. The preprocessor 1122 may be configured to process the first to N-2 portions [a] of the first input a in parallel. N-2 Each bit of [, …, a1] and the first to N-2 parts of the second input b [bN-2 The corresponding bits of [b1, ..., b1] are XORed and ANDed respectively to generate the corresponding Propogate Signal p and Generate Signal g. The carry generator 1124 can be configured to use the Propogate Signal p and Generate Signal g generated by the preprocessor 1122 to generate carry c1, ..., c2. N-2 .

[0058] In some embodiments, the carry logic module 112 can be designed based on the construction of a carry-lookahead adder (CLA) or a parallel prefix adder (PPA). For example, refer to... Figures 4A-4C , Figure 4A and Figure 4B Example constructions of a carry-lookahead adder (CLA) and a parallel prefix adder (PPA) are shown respectively. Figures 4A-4C In this context, M represents the number of bits input to the adder. Figures 4A-4C In the example, assume that the bits of the M-bit number a are represented from least significant bit to most significant bit as A1, A2, ..., A... M-1 A M Furthermore, the bits of the M-bit number b are represented sequentially from least significant bit to most significant bit as B1, B2, ..., B... M-1 B M Furthermore, the bits of the transmitted signal p are represented sequentially from least significant bit to most significant bit as P1, P2, ..., P... M-1 P M Furthermore, the bits of the generated signal g are represented sequentially from least significant bit to most significant bit as G1, G2, ..., G... M-1 G M .like Figure 4A As shown, P v =A v ⊕B v G v =A v ·B v v = 1, 2, ..., M, where ⊕ represents the XOR operation and · represents the AND operation. For example, the carry chain of the CLA (C in The carry input is equal to the initial carry C0, C out Output the carry and it equals the final carry C. M C1 to C M-1 (for carry-over) and the formula can be calculated as follows: C0=G0=C in ; C1=G1+P 1· C0; C2= G2+P2·C1= G2+P2·(G1+P1·C0)= G2+P2·G1+P2·P1·C0; ... C M = G M +P M ·C M-1 =……; S v =P v ⊕C v-1 v = 1, 2, ..., M.

[0059] To reduce the depth of the AND gate, PPA further optimizes CLA. The computational flow of PPA and CLA is largely the same, except that in calculating C... v Sufficient parallel optimization was performed. Currently, several PPA variants exist, whose main design approach is to achieve a balance in terms of adder range, circuit depth, number of node outputs, and overall routing. For example, ... Figure 4B As shown, it is comparable to Figure 4A The CLA shown implements the carry generator as a parallel prefix network. Figure 4C Three parallel prefix networks are illustrated exemplarily in the case of M=16. For a detailed discussion of PPA and parallel prefix networks, see Milad Bahadori et al.'s article entitled "A comparative study on performance and reliability of 32-bit binary adders" (https: / / doi.org / 10.1016 / j.vlsi.2015.12.002), published in Integration, Vol. 53, pp. 54-67, March 2016, which is incorporated herein by reference in its entirety.

[0060] Since the carry logic module 112 does not need to obtain the carry at each bit position, nor the sum at each bit position, it can have simplified carry logic compared to CLA and PPA, and does not require a post-processor. For example, Figure 5 Taking the first number 'a' and the second number 'b' as examples, each consisting of 32 bits and divided into three 8-bit parts and two 4-bit parts (where the carry logic module 112 calculates three carrys c1, c2, and c3), the carry logic module 112 modified based on PPA is shown. Carry input C in It can be set to 0. The first part of the first number 'a', a1 = [A8, A7, …, A1], and the second part, a2 = [A…]. 16 A 15 [, …, A9] and part 3 a3=[A 24 A 23, …, A 17 ] and the 1st part b1=[B8, B7, …, B1], the 2nd part b2=[B 16 , B 15 , …, B9] and the 3rd part b3=[B 24 , B 23 , …, B 17 ] of the 2nd number b are inputted to the preprocessor 1122 of the carry logic module 112, while the 4th part a4=[A 28 , A 27 , A 26 , A 25 ] and the 5th part a5=[A 32 , A 31 , A 30 , A 29 ] of the 1st number a and the 4th part b4=[B 28 , B 27 , B 26 , B 25 ] and the 5th part b5=[B 32 , B 31 , B 30 , B 29 ] of the 2nd number b can be processed without inputting to the carry logic module 112. Thus, Figure 5 , the preprocessor 1122 of the carry logic module 112 can reduce 8 XOR gates and 8 AND gates compared to the preprocessor of the PPA as shown in Figure 4B . In other words, the carry logic module 112 can be constructed based on a 24-bit PPA instead of a 32-bit PPA. In addition, the carry generator 1124 can obtain the intermediate carries C8 (as the 1st carry c1), C 16 (as the 2nd carry c2) and C 24 (as the 3rd carry c3) by a parallel prefix network jump without obtaining C1 to C7, C9 to C 15 , C 17 to C 23 , C 25 to C 32 and further obtaining S1 to S 32 .

[0061] Figure 6 Fig. 2 shows the first sum logic module 114 and the second sum logic module 110 of the adder circuit 100 according to some embodiments of the present disclosure. Figure 6 Continued from Figure 5For example, the first adder 1101 to the fourth adder 1104 of the second summing logic module 110 are implemented as four parallel 8-bit RCAs, and the adder of the first summing logic module 114 is implemented as a 4-bit RCA serially preceding the fourth adder 1104. The RCA can be implemented as a cascaded combination including a full adder FAA and / or a half adder (HA) HA.

[0062] like Figure 6 As shown, the first adder 1101 of the second summation logic module 110 includes a cascaded combination of a half adder HA and seven full adders FAA. Each stage of this cascaded combination receives a corresponding bit of the first part a1 = [A8, A7, …, A1] of a first number a and a corresponding bit of the first part b1 = [B8, B7, …, B1] of a second number b, and outputs the corresponding bit of the sum s1 = [S8, S7, …, S1] of the first part a1 of the first number a and the first part b1 of the second number b. Alternatively, the half adder HA can also be implemented as FAA, where the carry input of the FAA can be set to 0. The carry (e.g., C) output by each stage of this cascaded combination except the last stage is... v (v=1,2,……,7)) is input into the next level, and the carry C8 of the last level output of this cascade combination can be discarded.

[0063] The second adder 1102 of the second summing logic module 110 includes a cascaded combination of eight full adders FAA. Each stage of this cascaded combination receives the second part a2 of the first number a = [A...]. 16 A 15 The corresponding digit of [A9] and the second part of the second number b, b2 = [B 16 B 15 Output the corresponding bit of [, …, B9] and output the sum of the second part a2 of the first number a and the second part b2 of the second number b, s2=[S 16 , S 15 The corresponding bit of [, …, S9]. The first stage of this cascade combination also receives C8, which is calculated in advance by the carry logic module 112 as the first carry c1. The carry (e.g., C) output by each stage of this cascade combination except the last stage is also included. v (v=9,10,...,15) is input into the next stage, and the carry C of the last stage output of this cascade combination is... 16 It can be discarded.

[0064] The third adder 1103 of the second summing logic module 110 includes a cascaded combination of eight full adders FAA. Each stage of this cascaded combination receives the third part a3 of the first number a = [A 24 A 23, …, A 17 The corresponding digit of ] and the third part of the second number b, b3 = [B 24 B 23 , …, B 17 Output the corresponding digit of the first number a and the third part a3 of the second number b, s3=[S 24 , S 23 , …, S 17 The corresponding bit of ] is also received by the first stage of this cascaded combination, which is calculated in advance by the carry logic module 112 as the second carry c2. 16 The carry-in (e.g., C) of the output of each stage of the cascaded combination except the last stage. v (v=17,18,...,23)) is input into the next stage, and the carry C of the last stage output of this cascade combination is... 24 It can be discarded.

[0065] The first summing logic module 114 includes a cascaded combination of a half adder HA and three full adders FAA. Each stage of this cascaded combination receives the fifth part of the first number a, a5 = [A...]. 32 A 31 A 30 A 29 The corresponding digit of ] and the 5th part of the second number b, b5 = [B 32 B 31 B 30 B 29 Output the corresponding digit of the first number a, and output the middle sum s of the 5th part a5 of the first number a and the 5th part b5 of the second number b. m =[Sm 32 , Sm 31 , Sm 30 , Sm 29 The corresponding bit of ] . Alternatively, the half-adder HA can also be implemented as FAA, where the carry input of the FAA can be set to 0. The carry of the output of each stage of the cascaded combination except the last stage (e.g., C) v (v=29, 30, 31) is input into the next stage, and the carry C of the last stage output of this cascade combination is... 32 It can be discarded.

[0066] The fourth adder 1104 of the second summing logic module 110 includes a first cascade combination of four full adders FAA and a second cascade combination of four half adders HA. The first cascade combination is serially connected before the second cascade combination. Each stage of the first cascade combination receives the fourth part of the first number a, a4 = [A...]. 28 A 27 A 26 A25 ] of the corresponding bit of the second number b, and outputs the sum of the fourth part a4 of the first number a and the fourth part b4 of the second number b [S 28 , B 27 , B 26 , B 25 ] of the corresponding bit of the second number b, and outputs the sum of the fourth part a4 of the first number a and the fourth part b4 of the second number b [S 28 , S 27 , S 26 , S 25 ] of the corresponding bit of the second number b. The first stage of the first cascaded combination also receives C 24 , which is calculated by the carry logic module 112 in advance as the third carry c3. The carry output by each stage of the first cascaded combination (e.g., C v (v = 25, 26, 27)) is input to the next stage, and the carry output by the last stage of the first cascaded combination C 28 may be input to the first stage of the second cascaded combination. Each stage of the second cascaded combination receives the corresponding bit of the intermediate sum s m = [Sm 32 , Sm 31 , Sm 30 ,Sm 29 ] and outputs the corresponding bit of the sum [S 32 , S 31 , S 30 ,S 29 ] of the fifth part a5 of the first number a and the fifth part b5 of the second number b. The first stage of the second cascaded combination also receives C 28 from the first cascaded combination. The carry output by each stage of the second cascaded combination (except the last stage) is input to the next stage, and the carry output by the last stage of the second cascaded combination can be discarded. Alternatively, each of the one or more half adders HA in the second cascaded combination can also be implemented as an FAA, where the carry input of the FAA can be set to 0.

[0067] Thus, the second summation logic module 110 can directly output a 32-bit sum s = [S 32 , S 31 , …, S1] of the 32-bit first number a and the 32-bit second number b.

[0068] Figure 7 is a schematic diagram of an adder circuit 100’ according to further embodiments of the present disclosure. The adder circuit 100’ differs from the adder circuit 100 in that the carry logic module 112’ of the adder circuit 100’ further calculates a (N-1)th carry c N-1 and a (N-1)th part b N-1The carry generated by the addition corresponds to the (N-1)th carry c. N-1 Furthermore, the second summing logic module 110' further includes an Nth adder. The differences between the adder circuit 100' and the adder circuit 100 will be described below, while their similarities will not be repeated and can be referred to the preceding description.

[0069] For example, adder circuit 100' is configured to calculate the sum of a first number a and a second number b. Adder circuit 100' may have a first input representing the first number a and a second input representing the second number b, and an output representing the sum s of the first number a and the second number b. Each of the first input a and the second input b is correspondingly divided into parts 1 to N (N is an integer greater than 1), which represent the portion bits of the input sequentially from the least significant bit to the most significant bit. For example, the first input a includes part 1 a1, part 2 a2, ..., part N-1 a1. N-1 Part N a N (i.e., a=[a N , a N-1 The second input b includes part 1 b1, part 2 b2, ..., part N-1 b1. N-1 Part Nb N (That is, b = [b N ,b N-1 The value of N can be determined according to specific needs, for example, it can be 2, 3, 4, 5, 6, 7, 8, etc.

[0070] like Figure 7 As shown, the adder circuit 100' includes a first register module 102, a second register module 104, a third register module 106, a fourth register module 108, a carry logic module 112', a first summation logic module 114, and a second summation logic module 110'.

[0071] The first register module 102 is configured to store the first to N-1th portions of the first input a. The second register module 104 is configured to store the first to N-1th portions of the second input b. As previously described, the first register module 102 may have N-1 units, and the j-th unit 102 of the first register module 102... j Configured to store the j-th part a of the first input a j And the second register module 104 may have N-1 units and the j-th unit 104 of the second register module 104 j Configured to store the j-th part of the second input b j (j=1,…,N-1).

[0072] The carry logic module 112' is configured to compute N-1 carries c1,..., c N-1 Each of the carries c1,..., c N-1 has 1 bit. The i-th carry c N-1 of the carries c1,..., c i corresponds to the i-th part a i of the first input a added with the i-th part b i of the second input b (i = 1,..., N-1). For example, the carry logic module 112' can receive at least the 1st to the N-1st parts a1,..., a N-1 of the first input a and the 1st to the N-1st parts b1,..., b N-1 of the second input b and compute these N-1 carries c1,..., c N-1 using a look-ahead carry logic. In this way, the carry logic module 112' does not need to sum the inputs bit by bit, but can quickly jump to the carry at the desired bit. An exemplary implementation of the carry logic module 112' can be similar to the exemplary implementation of the carry logic module 112.

[0073] The third register module 106 can be coupled to the carry logic module 112' and configured to store the N-1 carries c1,..., c N-1 .

[0074] The first sum logic module 114 and the second sum logic module 110' are configured to cooperate to compute the sum s of the first number a and the second number b. For example, the first sum logic module 114 can include an adder configured to sum the N-th part a N of the first input a with the N-th part b N of the second input b, thereby producing an intermediate sum s m . The fourth register module 108 is coupled to the first sum logic module 114 and configured to store the intermediate sum s m .

[0075] The second sum logic module 110' is coupled to the first to fourth register modules 102-108 to receive the 1st to N-1st parts a1,..., a N-1 of the first input a, the 1st to N-1st parts b1,..., b N-1 of the second input b, the intermediate sum s m , and the carries c1,..., c N-1 and sum them.

[0076] The second sum logic module 110' includes a 1st adder 1101, a 2nd adder 1102,..., an Nth adder 110 NFor example, the j-th adder 110 of the second summation logic module 110' j Unit j 102 coupled to the first register module 102 j The j-th unit 104 of the second register module 104 j Thus, it can receive the j-th part a of the first input a. j The j-th part of the second input b j (j=1,…,N-1).

[0077] The first adder 1101 of the second summing logic module 110' is configured to sum the first part a1 of the first input a and the first part b1 of the second input b, thereby producing the first sum s1. N It is also coupled to the third register module 106 and the fourth register module 108, and is configured to handle intermediate and data s m With carry c1, ..., c N-1 The (N-1)th carry c N-1 Summing, thus producing the Nth sum s N When N is an integer greater than 2, the k-th adder 110' of the second summing logic module 110' k It is also coupled to the third register module 106, so that it can receive carry c1, ..., c N-1 The (k-1)th carry c k-1 (k=2, ..., N-1). The k-th adder 110 k Configured to the k-th part a of the first input a k The k-th part of the second input b k With carry c of the (k-1)th position k-1 Summing, thus producing the k-th sum s k The second summation logic module 110' outputs N sums s1, s2, ..., s... N The bits from least significant to most significant represent the partial bits of the output s (i.e., s = [s...]). N , s N-1 , …, s1]).

[0078] like Figure 7 As shown, carry c1, ..., c N-1 The result is calculated in advance by the carry logic module 112' and stored in the third register module 106. The second adder 1102 to the Nth adder 110 of the second summation logic module 110'. N The inputs all come from registers, thus enabling glitch reduction or even elimination (e.g., by fine-tuning the register clock or register drive). The second adder 1102 to the Nth adder 110' of the second summing logic module 110'N All have ample setup times spanning a full cycle with minimal glitches, resulting in reduced power consumption. Furthermore, the first adder 1101 of the second summing logic module 110' and the adders of the first summing logic module 114 themselves do not have carry-overs from lower bits, thus exhibiting smaller glitches and lower power consumption. In the adder circuit 100', the first adder 1101 to the Nth adder 110 of the second summing logic module 110'... N All carry-in bits generated can be discarded, and the resulting sum is directly the corresponding bits of the sum s.

[0079] Therefore, with Figure 1 In contrast, adder circuit 100' separates the summation logic circuit of the adder into a first part (e.g., first summation logic module 114) for processing the most significant bit (MSB) and a second part (e.g., second summation logic module 110') primarily for processing the least significant bit (LSB). Furthermore, it separates the carry logic circuit and the second part of the summation logic circuit. The carry logic and the first part of the summation logic can be performed in one clock cycle, with the calculated carry and the sum of the MSB stored in registers respectively. The second part of the summation logic can be performed in the next clock cycle based on input from the registers. This reduces the glitches from the carry logic circuit to the summation logic circuit. Additionally, the summation logic circuit of adder circuit 100' further breaks down a large-scale adder into N+1 smaller-scale adders. The total area of ​​the adders in the first summation logic module 114 and the second summation logic module 110' can be less than [a certain value]. Figure 1 The area of ​​the adders in the summing module 12 is reduced, thus enabling lower power consumption. Of these N+1 smaller-scale adders, N adders are located in the second part of the summing logic circuit (e.g., the first adder 1101 to the Nth adder 110 of the second summing logic module 110'). N It can operate in parallel, thereby achieving reduced latency and increased processing speed.

[0080] Taking the example of the first number a and the second number b each comprising 32 bits and being split into four parts (8 bits + 8 bits + 8 bits + 8 bits), the summation module 12 of the arithmetic circuit 10 requires a 32-bit adder, while the summation logic module of the adder circuit 100 only requires 4 8-bit adders (in the second part of the summation logic circuit) and 1 8-bit adder (in the first part of the summation logic circuit). In the adder circuit taught in the present disclosure, the 32-bit adder can be split into 4 8-bit adders in parallel and 1 8-bit adder in series before the 8-bit adders, and the smaller scale adders in the second part of the summation logic can be implemented as RCAs, so as to achieve a speed close to CLA, while having less glitch, smaller area and lower power consumption. Moreover, for example when the adder circuit 100’ is applied in a pipelined structure (e.g., as described later with respect to Figures 21-25 the first part of the summation logic of each tick can be in parallel with the second part of the summation logic of the previous tick, so the smaller scale adders in the first part of the summation logic can also be implemented as RCAs, so as to achieve a speed close to CLA, while having less glitch, smaller area and lower power consumption.

[0081] In some examples, each part of each of the first input a and the second input b has the same number of bits. This can result in the adder circuit 100’ having a smaller computation latency in some cases, for example when applied in a pipelined structure (e.g., as described later with respect to Figures 21-25 In some examples, each of the first input a and the second input b is partitioned such that the difference in the number of bits between each of its parts is as small as possible. In some examples, two or more parts of each of the first input a and the second input b can also have different numbers of bits.

[0082] Figure 8 A carry logic module 112’ of the adder circuit 100’ according to some embodiments of the present disclosure is shown. As Figure 8 shown, the carry logic module 112’ can include a pre-processor 1122’ and a carry generator 1124’. The pre-processor 1122’ can be configured to perform an XOR operation and an AND operation on each bit of the 1stto (N-1)thparts of the first input a [a N-1 , …, a1] and the corresponding bits of the 1stto (N-1)thparts of the second input b [b N-1 , …, b1] respectively in parallel, so as to generate a corresponding pass signal p and a generate signal g. The carry generator 1124’ can be configured to generate the carries c1, …, c N-1 using the pass signal p and the generate signal g generated by the pre-processor 1122’.

[0083] In some embodiments, the carry logic module 112' can be designed based on the construction of a carry lookahead adder (CLA) or a parallel prefix adder (PPA). Since the carry logic module 112' does not need to get the carry at each bit, much less the sum at each bit, it can have simplified carry logic compared to CLA and PPA, and does not need a post-processor. For example, Figure 9 Take an example where the first number a and the second number b each include 32 bits and are split into 3 8-bit parts and 2 4-bit parts (where the carry logic module 112' will compute 4 carries cl, c2, c3, c4), and show the carry logic module 112' based on a PPA retrofit. The carry-in C in may be set to 0. The 1st part al = [A8, A7,..., Al], the 2nd part a2 = [A 16 , A 15 ,..., A9], the 3rd part a3 = [A 24 , A 23 ,..., A 17 ], and the 4th part a4 = [A 28 , A 27 , A 26 , A 25 ] of the first number a and the 1st part bl = [B8, B7,..., Bl], the 2nd part b2 = [B 16 , B 15 ,..., B9], the 3rd part b3 = [B 24 , B 23 ,..., B 17 ], and the 4th part b4 = [B 28 , B 27 , B 26 , B 25 ] of the second number b are input to the pre-processor 1122' of the carry logic module 112', while the 5th part a5 = [A 32 , A 31 , A 30 , A 29 ] of the first number a and the 5th part b5 = [B 32 , B 31 , B 30 , B 29 ] of the second number b can not need to be input to the carry logic module 112' for processing. Thus, Figure 9 the pre-processor 1122' of the carry logic module 112' can be simpler than the pre-processor 1122 of the carry logic module 112 as Figure 4BThe pre-processor of the illustrated PPA can reduce 4 XOR gates and 4 AND gates. In other words, instead of constructing the carry logic module 112' based on a 32-bit PPA, the carry logic module 112' can be constructed based on a 28-bit PPA. In addition, the carry generator 1124' can obtain the intermediate carries C8(as the 1st carry cl), C 16 (as the 2nd carry c2), C 24 (as the 3rd carry c3), and C 28 (as the 4th carry c4) in a single step of the parallel prefix network, without obtaining C1to C7, C9to C 15 , C 17 to C 23 , C 25 to C 27 , C 29 to C 32 , and S1to S 32 , respectively, in further steps of the parallel prefix network.

[0084] Figure 10 The first sum logic module 114 and the second sum logic module 110' of the adder circuit 100' according to some embodiments of the present disclosure are illustrated. Figure 10 Continuing Figure 9 the example, the 1st to 5th adders 1101 to 1105 of the second sum logic module 110' are implemented as 3 parallel 8-bit RCAs and 2 parallel 4-bit RCAs, and the adder of the first sum logic module 114 is implemented as a 4-bit RCA serially preceding the 5th adder 1105. The RCAs can be implemented as cascaded combinations of full adders FAA and / or half adders HA. As Figure 10 illustrated, the configuration of the first sum logic module 114 and the 1st to 3rd adders 1101 to 1103 is similar to that in Figure 6 , which is not repeated here.

[0085] The 4th adder 1104 of the second sum logic module 110' comprises a cascaded combination of 4 full adders FAA. Each stage of the cascaded combination receives a respective one bit of the 4th part a4= [A 28 , A 27 , A 26 , A 25 ] of the first number a and a respective one bit of the 4th part b4= [B 28 , B 27 , B 26 , B 25 ] of the second number b, and outputs the sum [S 28 , S 27 , S 26 , S 25the first level of the cascaded combination also receives C 24 from the carry logic module 112' as a third carry c3. Each level of the cascaded combination, except the last level, outputs a carry (e.g., C v (v = 25, 26, 27)) to the next level, and the last level of the cascaded combination outputs a carry C 28 which can be discarded.

[0086] The fifth adder 1105 of the second summing logic module 110' includes a cascaded combination of four half-adders HA. Each level of the cascaded combination receives a respective bit of the intermediate sum s m = [Sm 32 , Sm 31 , Sm 30 , Sm 29 ] and outputs a respective bit of the sum [S 32 , S 31 , S 30 , S 29 ] of the fifth portion a5 of the first number a and the fifth portion b5 of the second number b. The first level of the cascaded combination also receives C 28 from the carry logic module 112' as a fourth carry c4. The carry outputted by each level of the cascaded combination, except the last level, is inputted to the next level, and the carry outputted by the last level of the cascaded combination can be discarded. Alternatively, each of one or more half-adders HA in the cascaded combination can also be implemented as a FAA, where the carry input of the FAA can be set to 0.

[0087] Thus, the second summing logic module 110' can directly output a 32-bit sum s = [S 32 , S 31 ,..., S1] of the 32-bit first number a and the 32-bit second number b.

[0088] Figure 11 An arithmetic circuit 200 according to some embodiments of the present disclosure is shown. As shown in Figure 11 , the arithmetic circuit 200 includes a summing module 220 and a first arithmetic module 210 coupled to the summing module 220. The summing module 220 can include the adder circuit 100, 100' of any of the preceding embodiments. The first arithmetic module 210 can provide the first and second inputs of the adder circuit 100, 100'. Figures 12-14 Several non-limiting example configurations of the arithmetic circuit 200 are shown in Figure 11 . In the example shown in Figures 12-14 , the adder circuit included by the summing module 220 is depicted as Figure 2The illustrated add circuit 100, however, is for illustrative purposes only and is not intended to be limiting.

[0089] In some examples, the arithmetic circuit 200 includes a plurality of arithmetic stages. For example, the arithmetic stages can be arranged in a pipelined structure. Each arithmetic stage can include a respective register module.

[0090] As Figure 12 illustrated, the plurality of arithmetic stages of the arithmetic circuit 200 includes a first arithmetic stage 230a and a second arithmetic stage 230b that is immediately subsequent to the first arithmetic stage 230a. The first arithmetic stage 230a includes a first respective register module 232a. The second arithmetic stage 230b includes a second respective register module 232b and also includes the first through fourth register modules 102-108 of the add circuit of the summation module 220. A first arithmetic module 210 is arranged between the first arithmetic stage 230a and the second arithmetic stage 230b and is coupled to the first respective register module 232a of the first arithmetic stage 230a. For example, the first arithmetic module 210 can be configured to operate on data from the first respective register module 232a to produce the first input and the second input of the add circuit of the summation module 220. Additionally, the carry logic module 112 and the first summation logic module 114 of the add circuit of the summation module 220 can also be arranged between the first arithmetic stage 230a and the second arithmetic stage 230b.

[0091] As Figure 13 illustrated, in some examples, the plurality of arithmetic stages of the arithmetic circuit 200 also includes a third arithmetic stage 230c that is immediately subsequent to the second arithmetic stage 230b. The third arithmetic stage 230c includes a third respective register module 232c. The third respective register module 232c of the third arithmetic stage 230c can be coupled to the summation module 220 to receive the output of the add circuit thereof. For example, the second summation logic module 110 of the add circuit of the summation module 220 can be arranged between the second arithmetic stage 230b and the third arithmetic stage 230c.

[0092] As Figure 14 illustrated, in some examples, the arithmetic circuit 200 also includes a second arithmetic module 240 arranged between the second arithmetic stage 230b and the third arithmetic stage 230c. The second arithmetic module 240 can be coupled to the second respective register module 232b of the second arithmetic stage 230b and configured to operate on data from the second respective register module 232b. For example, the second arithmetic module 240 can have the same configuration as the first arithmetic module 210.

[0093] In some examples, the arithmetic circuit 200 may also include another summing module 220', which may have the same configuration as the summing module 220. In such an example, the third arithmetic stage 230c may further include first to fourth register modules 102-108 of the summing module 220'. The second arithmetic module 240 may be coupled to the summing module 220' to provide the first and second inputs of its adder circuit. The second arithmetic module 240 may be configured to perform operations on data from the second corresponding register module 232b to generate the first and second inputs of the adder circuit of the summing module 220'. The carry logic module 112 and the first summing logic module 114 of the adder circuit of the summing module 220' may also be arranged between the second arithmetic stage 230b and the third arithmetic stage 230c.

[0094] Although not shown, the first operational stage 230a may also include the first to fourth register modules of the adder circuit of another summing module, and the second summing logic module of the adder circuit of this other summing module may also be arranged between the first operational stage 230a and the second operational stage 230b. That is, the internal configuration of each operational stage of the operational circuit 200 and the configuration between adjacent operational stages may be the same.

[0095] To present the inventive concept of this disclosure more clearly and intuitively, the SHA-256 algorithm will be briefly introduced below, and its use as a representative example of a hash algorithm will be used to describe the circuitry for executing the hash algorithm according to embodiments of this disclosure. Those skilled in the art will understand that the circuitry for executing the hash algorithm according to embodiments of this disclosure is applicable to any hash algorithm and can even be further applied to any other suitable circuitry, and is not limited to implementing the SHA-2 series algorithms such as the SHA-256 algorithm.

[0096] Figure 15 A schematic diagram of an exemplary pipeline structure for performing the SHA-256 algorithm is shown. The input to SHA-256 is a maximum length less than 2. 64 The input data is processed in 512-bit blocks, and the output is a 256-bit data digest, i.e., a hash value. To implement the SHA-256 algorithm, 64 rounds of repeated computation are required for each 512-bit data block. Therefore, a pipelined architecture with 64 computation stages can be used to process 64 sets of data in parallel. Figure 15 As shown, the pipeline architecture includes operation stages 0 to 63. Each operation stage includes eight 32-bit compressed register modules A to H for storing intermediate values ​​and sixteen 32-bit extended register modules R0 to R1 for storing extended data. 15The 0th operation stage receives the input data block, divides it into eight 32-bit data segments, stores them in compression register modules A through H, processes them, and then provides the results to the 1st operation stage. Afterward, each operation stage processes the results received from the previous stage and provides its own result to the next stage. Finally, after 64 operation stages, this pipeline structure outputs the hash result of the input data having undergone one SHA-256 algorithm operation.

[0097] The internal logic of a round of operations performed by SHA-256 at each operational level is discussed in detail below. The t-th round of operations performed at the t-th operational level is defined by the following formula (t is an integer and satisfies 0 ≤ t ≤ 63): T1 = H + Σ1(E) + Ch(E, F, G) + K t + W t ; T2 = Σ0(A) + Maj(A, B, C); H = G; G = F; F = E; E = D + T1; D = C; C = B; B = A; A = T1 + T2; (Equation 1) in: Ch(x, y, z)=(x AND y) ⊕ ((NOT x) AND z) Maj(x, y, z)= (x AND y) ⊕ (x AND z) ⊕ (y AND z) Σ0(x)=ROTR 2 (x) ⊕ ROTR 13 (x) ⊕ ROTR 22 (x) Σ1(x)=ROTR 6 (x) ⊕ ROTR 11 (x) ⊕ ROTR 25 (x) Among them, ROTR n (x) represents a circular right shift of n bits on a 32-bit variable x; W t For a 32-bit word, derived from the current 256-bit input data block; K t A 32-bit additional constant; + indicates modulo 2. 32Add; AND is a 32-bit bitwise AND operation; NOT is the negation operation; ⊕ is the XOR operation.

[0098] Next, we will describe the 32-bit word W. t How was it derived from a 512-bit data block? t It can be obtained using the following formula: For 0 ≤ t ≤ 15: W t Taken directly from the input data block; For 16 ≤ t ≤ 63: W t =σ1(W t-2 ) + W t-7 + σ0(W t-15 ) + W t-16 (Equation 2) in: σ0(x) = ROTR 7 (x) ⊕ ROTR 18 (x) ⊕ SHR 3 (x) σ1(x) = ROTR 17 (x) ⊕ ROTR 19 (x) ⊕ SHR 10 (x) Among them, ROTR n (x) represents a circular right shift of n bits on a 32-bit variable x; SHR n (x) represents shifting the 32-bit variable x to the right by n bits, filling the left side with 0s; ⊕ is the XOR operation; + is the modulo 2 operation. 32 add.

[0099] Note that the formulas for the functions Σ0(x), Σ1(x), σ0(x), and σ1(x) above are given as examples of SHA-256 for processing 32-bit data. Those skilled in the art know that in other SHA algorithms (such as SHA-512) and even other hash algorithms, these functions can be adapted to other corresponding forms to process data of other sizes (such as 64-bit data).

[0100] The following is combined with Figures 16-18 describe Figure 15 This section provides several non-restricted example configurations of the extended register modules in the arithmetic stages and the extended data operation modules between adjacent arithmetic stages within the pipelined architecture. It is understood that... Figures 16-18 Some extended register modules and extended data operation modules are depicted in gray for illustrative purposes only and are not intended to be restrictive.

[0101] Figure 16 It is shownFigure 15 Fig. 1 is a schematic diagram of a first example of an extension data operation module between an extension register module of an operation stage in a pipeline structure and a neighboring operation stage.

[0102] Reference Figure 16 , the extension data in the extension register modules R0, R1, R9 and R 14 in the tth operation stage are used to calculate the extension data to be stored in the extension register modules R0, R1, R9 and R 15 of the next operation stage. In addition, the extension data in the extension register modules R1 to R 15 can be directly shifted to the corresponding extension register modules R0 to R 14 of the next operation stage. Specifically, the 15th extension data W15 15 in the extension register module R t+1 of the t+1th operation stage is obtained by sequentially adding the 0th extension data W0 t in the extension register module R0 of the tth operation stage, the 1st extension data W1 t in the extension register module R1 of the tth operation stage after σ0 operation by a σ0 operator to obtain σ0(W1 t ), the 9th extension data W9 t in the extension register module R9 of the tth operation stage, the 14th extension data W14 14 in the extension register module R t after σ1 operation by a σ1 operator to obtain σ1(W14 t ), i.e., W15 t+1 = W0 t + σ0(W1 t ) + W9 t + σ1(W14 t ). It can be seen that the 0th extension data W0 14 , the 1st extension data W1 t , the 9th extension data W9 t , the 14th extension data W14 t in the extension register modules R0, R1, R9 and R t of the tth operation stage are used to calculate the 15th extension data W15 15 to be stored in the extension register modules R0, R1, R9 and R t+1 of the next operation stage. The number of operation logic stages that need to be experienced is as high as 4 stages, which brings significant calculation delay, limits the operation speed of the pipeline structure, and further makes it difficult to achieve a lower power performance ratio.

[0103] In this regard, the inventors of this application noted that there is a direct connection between the extended register module R0 of the (t+1)th operation level and the extended register module R1 of the tth operation level; that is, the extended data stored in the extended register module R1 of the tth operation level is directly shifted to the extended register module R0 of the (t+1)th operation level. Therefore, the inventors of this application conceived of using this direct connection between the extended register modules R0 and R1 to transfer the extended register module R0 used for calculating the (t+2)th operation level... 15 During the process of storing extended data, the portion of the extended data in the extended register module R0 of the (t+1)th operation level (i.e., the extended data in the extended register module R1 of the t-th operation level) is moved forward to the extended register module R1 used for calculating the (t+1)th operation level. 15 The process of storing the extended data is performed simultaneously and stored in the extended register module R0 of the (t+1)th operation level. In this way, the extended register module R0 used for calculating the (t+2)th operation level can be used... 15 After decomposing the process of storing the extended data, the decomposed parts are combined with the extended register module R used to calculate the (t+1)th operation level. 15 The process of storing extended data is handled in parallel. Parallel processing reduces the number of logical operation stages required to compute the extended data in each round, thereby increasing the processing speed of the circuit and the computing chip containing it, facilitating a lower power-to-computing power ratio. Specifically, the 15th extended register module R of the (t+2)th operation stage... 15 The 15th extended data W15 stored in the middle t+2 The first extended data W1 is stored in the first extended register module R1 of the t-th operation level. t The second extended data W2 is stored in the second extended register module R2 of the t-th operation level. t The 10th extended register module R of the t-th operation level 10 The 10th extended data W10 stored in the middle t and the 15th extended register module R of the t-th operation level 15 The 15th extended data W15 stored in the middle t The following relationship can be satisfied: W15 t+2 =W1 t +σ0(W2 t )+W10 t +σ1(W15 t ), where the definitions of σ0, σ1, and + are as described above.

[0104] For example, it can be based on the second extended register module R2 and the tenth extended register module R at the t-th operation level. 10 15th Extended Register Module R 15The extended data to be stored in the 0th extended register module R0 of the (t+1)th operation level is calculated based on the extended data stored in one or both of the extended register modules and the extended data stored in the 1st extended register module R1 of the t-th operation level. Alternatively, the extended data can be calculated based on the 1st extended register module R1, the 9th extended register module R9, and the 14th extended register module R0 of the t-th operation level. 14 The extended data stored in one or both of these registers, along with the extended data stored in the 0th extended register module R0 of the t-th operation level, are used to calculate the data to be stored in the 15th extended register module R of the (t+1)-th operation level. 15 Extended data within.

[0105] Figure 17 It is shown Figure 15 A schematic diagram of a second example of the extended register module of the operation stage and the extended data operation module between adjacent operation stages in the pipeline structure.

[0106] like Figure 17 As shown, the 0th extended data W0 in the 0th extended register module R0 of the (t+1)th operation stage t+1 The first extended data W1 is stored in the first extended register module R1 of the t-th operation level. t and the second extended data W2 stored in the second extended register module R2 t Obtained. Specifically, in this example, W0 t+1 =W1 t +σ0(W2 t ).

[0107] Further as Figure 17 As shown, the 15th extended register module R of the (t+1)th operation level 15 Extended data W15 in t+1 The 0th extended data W0 is stored in the 0th extended register module R0 of the t-th operation level. t The 9th extended data W9 is stored in the 9th extended register module R9. t and the 14th extended register module R 14 The 14th extended data W14 stored in the middle t Obtained. Specifically, in this example, W15 t+1 =W0 t +W9 t + σ1(W14 t ).

[0108] Further as Figure 17 As shown, the extended data stored in the i-th extended register module of the t-th operation level is directly shifted to the (i-1)-th extended register module of the (t+1)-th operation level, where 2≤i≤15 and i is an integer.

[0109] In Figure 17 the example shown, the number of operation logic stages that the final calculation for the extended data of the t+1 operation stage needs to go through is reduced to 3 stages, greatly reducing the calculation delay, so that the operation speed of the pipeline structure is greatly improved.

[0110] The extended data operation module between the t+1 operation stage and the t+2 operation stage can be the same as the extended data operation module between the t operation stage and the t+1 operation stage. Further as Figure 17 shown, the 15th extended register module R 15 of the t+2 operation stage stores the 15th extended data W15 t+2 obtained by the 0th extended data W0 t+1 stored in the 0th extended register module R0 of the t+1 operation stage, the 9th extended data W9 t+1 stored in the 9th extended register module R9, and the 14th extended data W14 14 stored in the 14th extended register module R t+1 . Specifically, in this example, W15 t+2 = W0 t+1 + W9 t+1 + σ1(W14 t+1 ) = W1 t + σ0(W2 t ) + W10 t + σ1(W15 t ).

[0111] Figure 18 is a schematic diagram showing a third example of the extended register modules of the operation stages in the pipeline structure in Figure 15 and the extended data operation modules between adjacent operation stages.

[0112] As Figure 18 shown, the 0th extended data W0 t+1 in the 0th extended register module R0 of the t+1 operation stage is obtained by the 1st extended data W1 t stored in the 1st extended register module R1 of the t operation stage and the 10th extended data W10 10 stored in the 10th extended register module R t . Specifically, in this example, W0 t+1 = W1 t + W10 t .

[0113] Further as Figure 18 shown, the 15th extended register module R 15Extended data W15 in t+1 The 0th extended data W0 is stored in the 0th extended register module R0 of the t-th operation level. t The first extended data W1 stored in the first extended register module R1 t and the 14th extended register module R 14 The 14th extended data W14 stored in the middle t Obtained. Specifically, in this example, W15 t+1 =W0 t +σ0(W1 t )+ σ1(W14 t ).

[0114] Further as Figure 18 As shown, the extended data stored in the i-th extended register module of the t-th operation level is directly shifted to the (i-1)-th extended register module of the (t+1)-th operation level, where 2≤i≤15 and i is an integer.

[0115] exist Figure 18 In the example shown, the number of computational logic stages required to finally compute the extended data for the (t+1)th operation stage is reduced to 3, which greatly reduces computational latency and significantly improves the computational speed of the pipeline structure.

[0116] The extended data operation module between the (t+1)th operation level and the (t+2)th operation level can be the same as the extended data operation module between the t-th operation level and the (t+1)th operation level. Further, as... Figure 18 As shown, the 15th extended register module R of the (t+2)th operation stage 15 Extended data W15 in t+2 The 0th extended data W0 is stored in the 0th extended register module R0 of the (t+1)th operation level. t+1 The first extended data W1 stored in the first extended register module R1 t+1 and the 14th extended register module R 14 The 14th extended data W14 stored in the middle t+1 Resulting. Specifically, in this example, W15 t+2 =W0 t+1 +σ0(W1 t+1 )+σ1(W14 t+1 )=W1 t +σ0(W2 t )+W10 t +σ1(W15 t ).

[0117] In addition, in some examples, W0 t+1 =W1 t+ σ1(W15 t ) and W15 t+1 = W0 t + σ0(W1 t )+ W9 t , so that W15 t+2 = W0 t+1 + σ0(W1 t+1 )+ W9 t+1 = W1 t + σ0(W2 t )+ W10 t + σ1(W15 t ). This can be implemented similarly to the configuration of Figures 17-18 , which is not described in more detail here.

[0118] In the configuration of Figures 16-18 , there are cases where the inputs of the adders come from combinational logic circuits. For example, Figure 16 , the inputs of the adder ADD come from the full adder FAA2, and Figure 17 , the inputs of the adder ADD1 in each of Figure 18 come from the full adder FAA. Therefore, these configurations have the problem of the arithmetic circuit shown in Figure 1 , that is, the adders have higher glitch-caused power consumption and more stage-caused delay. Therefore, these configurations can be modified according to the teachings of the present disclosure, so that a pipeline structure with reduced power consumption and delay is achieved.

[0119] Figure 19A circuit 300 for performing a hash algorithm according to some embodiments of the present disclosure is shown, where arrows indicate the direction of data transmission. The circuit 300 may include an input unit 310 and an arithmetic unit 320. The input unit 310 may be configured to receive data. The arithmetic unit 320 may be configured to calculate a hash value based on the received data. The arithmetic unit 320 may include a plurality of arithmetic stages 320-0, ..., 320-63 arranged in a pipelined structure. Each arithmetic stage may include an extended register module configured to store extended data. For example, the extended register module may be implemented as a combination of single-bit registers. It should be understood that although the arithmetic unit 320 is depicted in the figures as including 64 arithmetic stages, as mentioned above, this document only provides a non-limiting example of a circuit for performing the SHA-256 algorithm, and the circuit according to the present disclosure can actually be applied to perform any hash algorithm now known or later developed (not limited to the SHA family of algorithms), and may include any suitable number of arithmetic stages. It should also be understood that the actual circuit may have additional components (such as a compression register module), but to avoid obscuring the key points of this disclosure, these other components are not shown in the accompanying drawings and are not discussed herein. Typically, the extended data of the first operational stage 320-0 of the arithmetic unit 320 can be directly taken from the data received by the input unit 310, for example, while the extended data of each operational stage starting from operational stage 320-1 can be determined, for example, based on the extended data of the previous operational stage.

[0120] Generally, the extended register modules of each of the multiple arithmetic stages 320-0, ..., 320-63 can have the same configuration. In some cases, the extended register modules of each of the multiple arithmetic stages 320-0, ..., 320-63 can have different configurations. For example, there may be one or more arithmetic stages that have one or more fewer extended register modules than other arithmetic stages. This disclosure is not limited to any of the above situations.

[0121] like Figure 19 As shown, the multiple operation stages 320-0, ..., 320-63 include a first operation stage 320-a and a second operation stage 320-b immediately following the first operation stage 320-a. In this paper, the operation stage that comes first among two adjacent operation stages in the pipeline structure can be referred to as the first operation stage, and the operation stage that comes later among two adjacent operation stages can be referred to as the second operation stage. Note that "first" and "second" are used only for distinction and not as a limitation.

[0122] Each of the first operational level 320-a and the second operational level 320-b includes an extended register module R0 to an extended register module R15, respectively configured to store extended data from the 0th to the 15th extensions of that operational level. 1515th Extended Register Module R 15 Includes the first sum register submodule R 15s1 First carry register submodule R 15c1 The second sum register submodule R 15s2 Second base register submodule R 15c2 For example, the first sum register submodule R in circuit 300 15s1 First carry register submodule R 15c1 The second sum register submodule R 15s2 Second base register submodule R 15c2 These can correspond to the first register module 102, the second register module 104, the fourth register module 108, and the third register module 106 in the summation module 220 of the arithmetic circuit 200, respectively. Therefore, their configuration can be similar to the configuration of the first register module 102, the second register module 104, the fourth register module 108, and the third register module 106 described above, and will not be elaborated here.

[0123] Further as Figure 19 As shown, circuit 300 further includes a first extended data processing module 330-a disposed between the first operational stage 320-a and the second operational stage 320-b. The first extended data processing module 330-a includes a first submodule 331, a second submodule 332 and a third submodule 333.

[0124] The first submodule 331 of the first extended data processing module 330-a can be configured to be based on the 0th extended data W0 of the first processing level 320-a. a And based on the first extended data W1 of the first operation level 320-a a Extended Data W9, No. 9 a and the 14th extended data W14 a At least two of them are used to calculate the initial sum s0 and the initial carry c0. For example, the first submodule 331 of the first extended data operation module 330-a in circuit 300 may correspond to the first operation module 210 of operation circuit 200. The initial sum s0 and the initial carry c0 can be processed as the aforementioned first number a and second number b using the teachings of this disclosure. For example, each of the initial sum s0 and the initial carry c0 is divided into parts corresponding to each other to include the first to the Nth parts (when applying the teachings regarding the adder circuit 100, N can be an integer greater than 2; when applying the teachings regarding the adder circuit 100', N can be an integer greater than 1), which represent the part bits of each from the least significant bit to the most significant bit. For example, s0 = [s0 N ,s0 N-1 , …, s01], and c0=[c0 N, c0 N-1 ,..., c01]. The first through N-1 portions of the initial sum s0 [s0 N-1 ,..., s01] are stored in the first sum register submodule R 15c of the 15th extension register module R 15s1 of the second arithmetic stage 320-b, and the first through N-1 portions of the initial carry c0 [c0 N-1 ,..., c01] are stored in the first carry register submodule R 15c of the 15th extension register module R 15c1 of the second arithmetic stage 320-b. For example, the first sum register submodule R 15s1 and the first carry register submodule R 15c1 may each include first through N-1 cells for storing the respective portions of the initial sum s0 and the initial carry c0. In this case, the jth portion s0 j of the initial sum s0 can be stored in the jth cell of the first sum register submodule R 15 of the 15th extension register module R 15s1 of the second arithmetic stage 320-b, and the jth portion c0 j of the initial carry c0 can be stored in the jth cell of the first carry register submodule R 15 of the 15th extension register module R 15c1 of the second arithmetic stage 320-b (j = 1,..., N-1).

[0125] When applying the teachings regarding the addition circuit 100, the second submodule 332 of the first extension data operation module 330-a can be configured to compute N-2 carries c1,..., c N-2 , where the ith carry corresponds to the carry resulting from adding the ith portion s0 i of the initial sum s0 and the ith portion c0 i of the initial carry c0 (i = 1,..., N-2). Alternatively, when applying the teachings regarding the addition circuit 100', the second submodule 332 of the first extension data operation module 330-a can be configured to compute N-1 carries c1,..., c N-1 , where the ith carry corresponds to the carry resulting from adding the ith portion s0 i of the initial sum s0 and the ith portion c0 i of the initial carry c0 (i = 1,..., N-1). These pre-computed carries are stored in the second carry register submodule R 15 of the 15th extension register module R 15c2For example, the second submodule 332 of the first extended data operation module 330-a in circuit 300 can correspond to the carry logic modules 112 and 112' in the summation module 220 of operation circuit 200. Therefore, its configuration can be similar to the configuration of the carry logic modules 112 and 112' described above, and will not be elaborated here.

[0126] The third submodule 333 of the first extended data processing module 330-a can be configured to process the Nth part s0 of the initial sum s0. N The Nth part c0 of the initial carry c0 N Summing, thus producing the intermediate sum s m The middle number s m Stored in the 15th extended register module R of the second arithmetic stage 320-b 15 The second sum register submodule R 15s2 For example, the third submodule 333 of the first extended data operation module 330-a in circuit 300 can correspond to the first summing logic module 114 in the summing module 220 of operation circuit 200. Therefore, its configuration can be similar to the configuration of the first summing logic module 114 described above, and will not be elaborated here.

[0127] In some examples, such as reference Figure 20 The multiple operation levels 320-0, ..., 320-63 also include a third operation level 320-c immediately following the second operation level 320-b. The third operation level 320-c includes a 14th extended data W14 configured to store this operation level. c 14th Extended Register Module R 14 Circuit 300 also includes a second extended data processing module 330-b disposed between the second operational stage 320-b and the third operational stage 320-c. The second extended data processing module 330-b includes a fourth submodule 334.

[0128] When applying the teachings regarding the adder circuit 100, the fourth submodule 334 of the second extended data operation module 330-b may include the first to the (N-1)th adders. The first adder is configured to sum the first part s01 of the initial sum s0 with the first part c01 of the initial carry c0. The (N-1)th adder is configured to sum the (N-1)th part s0 of the initial sum s0. N-1 The (N-1)th part of the initial carry c0 N-1 , middle and number s m With the (N-2)th carry c N-2 Summation. When N is an integer greater than 3, the k-th adder is configured to sum the k-th part s0 of the initial sum s0. k The k-th part of the initial carry c0 kWith carry c of the (k-1)th position k-1 Summation (k=2, ..., N-2). For example, the fourth submodule 334 of the second extended data operation module 330-b in circuit 300 can correspond to the second summation logic module 110 in the summation module 220 of operation circuit 200. Therefore, its configuration can be similar to the configuration of the second summation logic module 110 described above, and will not be repeated here. The N-1 sums output by the first to N-1 adders of the fourth submodule 334 (which consist of the sum s of the initial sum s0 and the initial carry c0) are stored in the 14th extended register module R of the third operation stage 320-c. 14 middle.

[0129] Alternatively, when applying the teachings regarding the adder circuit 100', the fourth submodule 334 of the second extended data processing module 330-b may include first to Nth adders. The first adder is configured to sum the first portion s01 of the initial sum s0 with the first portion c01 of the initial carry c0. The Nth adder is configured to sum the intermediate sum s0... m With the (N-1)th carry c N-1 Summation. When N is an integer greater than 2, the k-th adder is configured to sum the k-th part s0 of the initial sum s0. k The k-th part of the initial carry c0 k With carry c of the (k-1)th position k-1 Summation (k=2, ..., N-1). For example, the fourth submodule 334 of the second extended data operation module 330-b in circuit 300 can correspond to the second summation logic module 110' in the summation module 220 of operation circuit 200. Therefore, its configuration can be similar to the configuration of the second summation logic module 110' described above, and will not be repeated here. The N sums output by the first to Nth adders of the fourth submodule 334 (which consist of the sum s of the initial sum s0 and the initial carry c0) are stored in the 14th extended register module R of the third operation stage 320-c. 14 middle.

[0130] Figures 21-25 The following are examples of applying the teachings of this disclosure to... Figures 16-18 Several non-restrictive example configurations are obtained by making corresponding modifications. This is understandable. Figures 21-25 The grayed-out depiction of some extended register modules and extended data operation modules is for illustrative purposes only and is not intended to be restrictive. Figures 21-25 In the example shown, each operation level can have the same configuration both internally and between adjacent operation levels.

[0131] like Figure 21As shown, the first submodule 331 of the first extended data operation module 330-a between the first operation stage 320-a and the second operation stage 320-b includes a σ0 operator, a σ1 operator, and two full adders FAA1, FAA2, and is configured to calculate an initial sum s0 and an initial carry c0 based on the 0th extended data W0 a , the 1st extended data W1 a , the 9th extended data W9 a , and the 14th extended data W14 a of the first operation stage 320-a. Each of the initial sum s0 and the initial carry c0 is partitioned correspondingly to each other to include 1st to Nth portions (N can be an integer greater than 2 when the teachings regarding the addition circuit 100 are applied; N can be an integer greater than 1 when the teachings regarding the addition circuit 100' are applied), which represent partial bits of the each from low to high. For example, s0 = [s0 N , s0 N-1 , …, s01] and c0 = [c0 N , c0 N-1 , …, c01]. The 1st to N-1th portions of the initial sum s0 are stored in the first sum register submodule R 15 of the 15th extended register module R 15s1 of the second operation stage 320-b, and the 1st to N-1th portions of the initial carry c0 are stored in the first carry register submodule R 15 of the 15th extended register module R 15c1 of the second operation stage 320-b.

[0132] The second submodule 332 of the first extended data operation module 330-a includes a carry logic module (Carry Logic Module) CLM. When the teachings regarding the addition circuit 100 are applied, the carry logic module CLM can receive at least the 1st to N-2th portions of the initial sum s0 and at least the 1st to N-2th portions of the initial carry c0, thereby generating N-2 carries c1, …, c N-2 , where the i-th carry corresponds to the carry generated by adding the i-th portion s0 i of the initial sum s0 and the i-th portion c0 i of the initial carry c0 (i = 1, …, N-2). When the teachings regarding the addition circuit 100' are applied, the carry logic module CLM can receive at least the 1st to N-1th portions of the initial sum s0 and at least the 1st to N-1th portions of the initial carry c0, thereby generating N-1 carries c1, …, c N-1 , where the i-th carry corresponds to the carry generated by adding the i-th portion s0 i of the initial sum s0 and the i-th portion c0i The carry-overs generated by the additions (i = 1,..., N - 1). These carry-overs computed by the carry logic module CLM are stored in the second carry register sub-module R 15 of the 15th extended register module R 15c2 of the second arithmetic stage 320-b.

[0133] The third sub-module 333 of the first extended data operation module 330-a includes a first sum logic module SLM1. The first sum logic module SLM1 can receive the Nth portion of the initial sum s0 and the Nth portion of the initial carry c0, thereby generating an intermediate sum s m . The intermediate sum s m is stored in the second sum register sub-module R 15 of the 15th extended register module R 15s2 of the second arithmetic stage 320-b.

[0134] The fourth sub-module 334 of the second extended data operation module 330-b between the second arithmetic stage 320-b and the third arithmetic stage 320-c includes a second sum logic module SLM2.

[0135] The second sum logic module SLM2 can receive the first to N - 1th portions of the initial sum s0 and the first to N - 1th portions of the initial carry c0, and the carries c1,..., c N-2 and the intermediate sum s m , thereby generating N - 1 sums s1,..., s N-1 , when the teachings regarding the addition circuit 100 are applied. The second sum logic module SLM2 includes first to N - 1 adders. The first adder is configured to sum the first portion s01 of the initial sum s0 and the first portion c01 of the initial carry c0, thereby generating the sum s1. The N - 1th adder is configured to sum the N - 1th portion s0 N-1 , the N - 1th portion c0 N-1 of the initial carry c0, the intermediate sum s m , and the N - 2th carry c N-2 , thereby generating the sum s N-1 . In the case where N is an integer greater than 3, the kth adder is configured to sum the kth portion s0 k of the initial sum s0, the kth portion c0 k of the initial carry c0, and the k - 1th carry c k-1 (k = 2,..., N - 2), thereby generating the sum s k . The N - 1 sums s1,..., s N-1(The sum s of the initial sum s0 and the initial carry c0) is stored in the 14th extended register module R of the third arithmetic level 320-c. 14 middle.

[0136] Alternatively, when applying the teachings regarding the adder circuit 100', the second summing logic module SLM2 can receive the first to N-1 parts of the initial sum s0 and the first to N-1 parts of the initial carry c0, as well as the carry c1, ..., c N-1 and the middle number s m This produces N sums s1, ..., s2. N The second summation logic module SLM2 includes adders 1 through N. The first adder is configured to sum the first part s01 of the initial sum s0 with the first part c01 of the initial carry c0, thereby producing a sum s1. The Nth adder is configured to sum the intermediate sums s1 and s2. m With the (N-1)th carry c N-1 Summing, thus producing the sum s N When N is an integer greater than 2, the k-th adder is configured to add the k-th part s0 of the initial sum s0. k The k-th part of the initial carry c0 k With carry c of the (k-1)th position k-1 Summing (k=2, ..., N-1) to produce the sum s k N sums s1, ..., s2 N (The sum s of the initial sum s0 and the initial carry c0) is stored in the 14th extended register module R of the third arithmetic level 320-c. 14 middle.

[0137] Therefore, the 14th extended register module R of the third arithmetic stage 320-c 14 The 14th extended data W14 stored in the middle c With the 0th extended data W0 of the first operation level 320-a a Extended Data W1 a Extended Data W9, No. 9 a and the 14th extended data W14 a The following relationship can be satisfied: W14 c =W0 a +σ0(W1 a +W9 a +σ1(W14 a ).

[0138] Figure 21 and Figure 16 In comparison, although calculating "W0" a +σ0(W1 a +W9a +σ1(W14 a This requires an extra round of processing time, but it doesn't have a significant negative impact on the assembly line structure. Additionally, Figure 21 This breaks the constraints of the 32-bit binary adder. On one hand, Figure 21 Will Figure 16 The separation of the carry logic circuit and the LSB section of the summation logic circuit in the adder ADD makes the application of RCA in a pipelined structure feasible. Specifically, originally Figure 16 If the 32-bit adder ADD is implemented as RCA, it will have 32 stages, and the resulting latency may be unacceptable. Figure 16 A 32-bit adder, ADD, is often implemented as a CLA, but CLAs are large in area, have many glitches, and consume a lot of power. Figure 21 In this context, the second summation logic module, SLM2, can be implemented as multiple parallel RCAs, which offers reduced area, glitches, and power consumption while achieving speeds close to those of a CLA. On the other hand, Figure 21 Will Figure 16 The separation of the carry logic circuit and the LSB section of the summation logic circuit in the adder ADD further reduces the glitches from the carry logic circuit to the summation logic circuit. The inputs of the second summation logic module SLM2 all come from registers, thus reducing or even eliminating glitches, which lowers the power consumption of circuit 300. On another front, Figure 21 Will Figure 16 The summation logic circuit of the adder ADD has its LSB and MSB sections separated. This ensures that the MSB section of the summation logic circuit has no carry from lower bits, resulting in smaller glitches and lower power consumption. Therefore, Figure 21 At an acceptable register area and power consumption cost (e.g., assuming the Nth part of the initial sum s0 and the initial carry c0 both have x bits, in an arithmetic stage, compared to...), Figure 16 29+Nx or 30+Nx single-bit registers were added, where R 15c1 It has 31-x single-bit registers and R 15c2 Having N-2 or N-1 single-bit registers in exchange for a significantly reduced adder area / glitch power consumption.

[0139] like Figure 22 and Figure 23 As shown, the first submodule 331 of the first extended data operation module 330-a between the first operation level 320-a and the second operation level 320-b includes a σ1 arithmetic unit and a full adder FAA, and is configured to operate based on the 0th extended data W0 of the first operation level 320-a. a Extended Data W9, No. 9 a and the 14th extended data W14 aCalculate the initial sum s0 and the initial carry c0. Each of the initial sum s0 and the initial carry c0 is divided into corresponding parts from 1 to N (when applying the teachings regarding adder circuit 100, N can be an integer greater than 2; when applying the teachings regarding adder circuit 100', N can be an integer greater than 1), and these parts from 1 to N represent the portion bits of each part sequentially from the least significant bit to the most significant bit. For example, s0 = [s0 N , s0 N-1 , …, s01], and c0=[c0 N c0 N-1 The first to N-1 parts of the initial sum s0 are stored in the 15th extended register module R of the second operation level 320-b. 15 The first sum register submodule R 15s1 In this process, the first to N-1 portions of the initial carry c0 are stored in the 15th extension register module R of the second arithmetic stage 320-b. 15 First carry register submodule R 15c1 middle.

[0140] The second submodule 332 of the first extended data processing module 330-a includes a carry logic module CLM. Figure 22 The carry logic module (CLM) in the middle can be similar to Figure 21 The carry logic module (CLM) in the second arithmetic stage is not discussed in detail here. The carry calculated by the carry logic module (CLM) is stored in the 15th extended register module R of the second arithmetic stage 320-b. 15 Second carry register submodule R 15c2 middle.

[0141] The third submodule 333 of the first extended data processing module 330-a includes a first summation logic module SLM1. The first summation logic module SLM1 can receive the Nth part of the initial sum s0 and the Nth part of the initial carry c0, thereby generating an intermediate sum s m The middle number s m Stored in the 15th extended register module R of the second arithmetic stage 320-b 15 The second sum register submodule R 15s2 middle.

[0142] The fourth submodule 334 of the second extended data operation module 330-b between the second operation level 320-b and the third operation level 320-c includes the second summation logic module SLM2. Figure 22 The second summation logic module SLM2 in the code can be similar to... Figure 21The second summation logic module SLM2 in the third arithmetic stage 320-c is not described in detail here. The sum calculated by the second summation logic module SLM2 is stored in the 14th extended register module R of the third arithmetic stage 320-c. 14 middle.

[0143] Additionally, the 0th extended data W0 of the first operational level 320-a a It is based on the first extended data W1 of the fourth operation level 320-d through the fifth submodule 335 (which includes a σ0 arithmetic unit and an adder ADD0) of the third extended data operation module 330-d, which is immediately preceding the first operation level 320-a and is located between the first operation level 320-a and the fourth operation level 320-d. d And the second extended data W2 d The calculated value is W0. a = W1 d +σ0(W2 d ).

[0144] Therefore, the 14th extended register module R of the third arithmetic stage 320-c 14 The 14th extended data W14 stored in the middle c With the 0th extended data W0 of the first operation level 320-a a Extended Data W9, No. 9 a and the 14th extended data W14 a The following relationship can be satisfied: W14 c =W0 a +W9 a +σ1(W14 a In addition, the 14th extended register module R of the third arithmetic stage 320-c 14 The 14th extended data W14 stored in the middle c With the first extended data W1 of the fourth operation level 320-d d Second extended data W2 d Extended Data W10 (10th Edition) d And the 15th extended data W15 d The following relationship can be satisfied: W14 c =W1 d +σ0(W2 d +W10 d +σ1(W15 d ), of which W15 d ={W15s1 d + W15c1 d + W15s2 d + W15c2 d}. W15s1 d W15c1 dW15s2 d W15c2 d These are the 15th extended register module R of the fourth arithmetic level 320-d. 15 The first sum register submodule R 15s1 First carry register submodule R 15c1 The second sum register submodule R 15s2 Second base register submodule R 15c2 The data stored in it.

[0145] Figure 22 and Figure 17 In comparison, although calculating "W1" d +σ0(W2 d +W10 d +σ1(W15 d This requires an extra round of processing time, but it doesn't have a significant negative impact on the assembly line structure. Additionally, Figure 22 This breaks the constraints of the 32-bit binary adder. On one hand, Figure 22 Will Figure 17 The carry logic circuit and the LSB section of the summation logic circuit of the adder ADD1 are separated, making the application of RCA in a pipelined structure feasible. Specifically, originally Figure 17 If the 32-bit adder ADD1 is implemented as an RCA, it will have 32 stages, and the resulting latency may be unacceptable. Figure 17 The 32-bit adder ADD1 is often implemented as a CLA, but CLAs have a large area, many glitches, and high power consumption. Figure 22 In this context, the second summation logic module, SLM2, can be implemented as multiple parallel RCAs, which offers reduced area, glitches, and power consumption while achieving speeds close to those of a CLA. On the other hand, Figure 22 Will Figure 17 The separation of the carry logic circuit and the LSB section of the summation logic circuit in the adder ADD1 further reduces the glitches from the carry logic circuit to the summation logic circuit. The inputs of the second summation logic module SLM2 all come from registers, thus reducing or even eliminating glitches, which lowers the power consumption of circuit 300. On another front, Figure 22 Will Figure 17 The summation logic circuit of adder ADD1 has its LSB and MSB sections separated. This ensures that the MSB section of the summation logic circuit has no carry from lower bits, resulting in smaller glitches and lower power consumption. Therefore, Figure 22 At an acceptable register area and power consumption cost (e.g., assuming the Nth part of the initial sum s0 and the initial carry c0 both have x bits, in an arithmetic stage, compared to...), Figure 1729+Nx or 30+Nx single-bit registers were added, where R 15c1 It has 31-x single-bit registers and R 15c2 Having N-2 or N-1 single-bit registers in exchange for a significantly reduced adder area / glitch power consumption.

[0146] like Figure 24 and Figure 25 As shown, the first submodule 331 of the first extended data operation module 330-a between the first operation level 320-a and the second operation level 320-b includes a σ0 operator, a σ1 operator, and a full adder FAA, and is configured to operate based on the 0th extended data W0 of the first operation level 320-a. a Extended Data W1 a and the 14th extended data W14 a Calculate the initial sum s0 and the initial carry c0. Each of the initial sum s0 and the initial carry c0 is divided into corresponding parts from 1 to N (when applying the teachings regarding adder circuit 100, N can be an integer greater than 2; when applying the teachings regarding adder circuit 100', N can be an integer greater than 1), and these parts from 1 to N represent the portion bits of each part sequentially from the least significant bit to the most significant bit. For example, s0 = [s0 N , s0 N-1 , …, s01], and c0=[c0 N c0 N-1 The first to N-1 parts of the initial sum s0 are stored in the 15th extended register module R of the second operation level 320-b. 15 The first sum register submodule R 15s1 In this process, the first to N-1 portions of the initial carry c0 are stored in the 15th extension register module R of the second arithmetic stage 320-b. 15 First carry register submodule R 15c1 middle.

[0147] The second submodule 332 of the first extended data processing module 330-a includes a carry logic module CLM. Figure 24 The carry logic module (CLM) in the middle can be similar to Figure 21 The carry logic module (CLM) in the second arithmetic stage is not discussed in detail here. The carry calculated by the carry logic module (CLM) is stored in the 15th extended register module R of the second arithmetic stage 320-b. 15 Second carry register submodule R 15c2 middle.

[0148] The third submodule 333 of the first extended data processing module 330-a includes a first summation logic module SLM1. The first summation logic module SLM1 can receive the Nth part of the initial sum s0 and the Nth part of the initial carry c0, thereby generating an intermediate sum s m The middle number s m Stored in the 15th extended register module R of the second arithmetic stage 320-b 15 The second sum register submodule R 15s2 middle.

[0149] The fourth submodule 334 of the second extended data operation module 330-b between the second operation level 320-b and the third operation level 320-c includes the second summation logic module SLM2. Figure 24 The second summation logic module SLM2 in the code can be similar to... Figure 21 The second summation logic module SLM2 in the third arithmetic stage 320-c is not described in detail here. The sum calculated by the second summation logic module SLM2 is stored in the 14th extended register module R of the third arithmetic stage 320-c. 14 middle.

[0150] Additionally, the 0th extended data W0 of the first operational level 320-a a The first extended data W1 of the fourth operation level 320-d is processed by the fifth submodule 335 (which includes an adder ADD0) of the third extended data operation module 330-d, which is immediately preceding the first operation level 320-a and is located between the first operation level 320-a and the fourth operation level 320-d. d and the 10th extended data W10 d The calculated value is W0. a = W1 d +W10 d .

[0151] Therefore, the 14th extended register module R of the third arithmetic stage 320-c 14 The 14th extended data W14 stored in the middle c With the 0th extended data W0 of the first operation level 320-a a Extended Data W1 a and the 14th extended data W14 a The following relationship can be satisfied: W14 c =W0 a +σ0(W1 a ) +σ1(W14 a In addition, the 14th extended register module R of the third arithmetic stage 320-c 14 The 14th extended data W14 stored in the middle c With the first extended data W1 of the fourth operation level 320-dd , the 2nd extension data W2 d , the 10th extension data W10 d , and the 15th extension data W15 d may satisfy the following relationship: W14 c = W1 d + σ0(W2 d ) + W10 d + σ1(W15 d ), where W15 d = {W15s1 d + W15c1 d + W15s2 d + W15c2 d}. W15s1 d , W15c1 d , W15s2 d , and W15c2 d are data stored in the first sum register submodule R 15 , the first carry register submodule R 15s1 , the second sum register submodule R 15c1 , and the second carry register submodule R 15s2 of the 15th extension register module R 15c2 of the fourth operation stage 320-d, respectively.

[0152] Figure 24 In comparison with Figure 18 , although the calculation of "W1 d + σ0(W2 d ) + W10 d + σ1(W15 d )" requires one more round of time, this does not have a significant negative impact on the pipelined structure. In addition, Figure 24 the constraint of 32-bit binary adder is broken. In one aspect, Figure 24 the LSB part of the carry logic and the sum logic of the adder ADD1 of Figure 18 are separated, making the application of RCA in the pipelined structure feasible. Specifically, the 32-bit adder ADD1 of Figure 18 , if implemented as RCA, will have 32 stages, and the resulting delay can be unacceptable, so the 32-bit adder ADD1 of Figure 18 is often implemented as CLA, but CLA has large area, many glitches, and high power consumption. In Figure 24 , the second sum logic module SLM2 can be implemented as multiple RCAs in parallel, which has reduced area, glitches, and power consumption, and can achieve a speed close to that of CLA. In another aspect, Figure 24 the LSB part of the carry logic and the sum logic of the adder ADD1 of Figure 18The separation of the carry logic circuit and the LSB section of the summation logic circuit in the adder ADD1 further reduces the glitches from the carry logic circuit to the summation logic circuit. The inputs of the second summation logic module SLM2 all come from registers, thus reducing or even eliminating glitches, which lowers the power consumption of circuit 300. On another front, Figure 24 Will Figure 18 The summation logic circuit of adder ADD1 has its LSB and MSB sections separated. This ensures that the MSB section of the summation logic circuit has no carry from lower bits, resulting in smaller glitches and lower power consumption. Therefore, Figure 24 At an acceptable register area and power consumption cost (e.g., assuming the Nth part of the initial sum s0 and the initial carry c0 both have x bits, in an arithmetic stage, compared to...), Figure 18 29+Nx or 30+Nx single-bit registers were added, where R 15c1 It has 31-x single-bit registers and R 15c2 Having N-2 or N-1 single-bit registers in exchange for a significantly reduced adder area / glitch power consumption.

[0153] In addition, it can be based on W0 t+1 =W1 t +σ1(W15 t W15 t+1 =W0 t +σ0(W1 t )+W9 t And W15 t+2 =W0 t+1 +σ0(W1 t+1 )+ W9 t+1 =W1 t +σ0(W2 t )+W10 t +σ1(W15 t (This can be extended to other embodiments. For example, in some embodiments, the first submodule 331 of the first extended data processing module 330-a can be based on the 0th extended data W0 of the first processing level 120-a.) a Extended Data W1 a and the 9th extended data W9 a Calculate the initial sum and initial carry, then proceed to a similar manner. Figure 22 , Figure 24 The initial sum and initial carry are then processed as the first and second numbers by an addition circuit according to various embodiments of the teachings of this disclosure, which will not be elaborated here.

[0154] This disclosure may also provide a computing chip including the circuitry described in any of the above embodiments. This disclosure may also provide a computing device including the computing chip described above.

[0155] The words "left," "right," "front," "back," "top," "bottom," "over," "under," "upper," "lower," and the like in the description and the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the disclosure described herein are capable of operation in other orientations than those illustrated or otherwise described herein. For example, if the device is inverted, then the features originally described as above other features can be described as below the other features. The device can also be oriented in other ways (rotated at 90 degrees or at other orientations), and the relative spatial relationships would be correspondingly interpreted.

[0156] In the description and claims, when an element is referred to as being "on," "attached," "connected" or "coupled" to another element, it can be directly on, attached, connected or coupled to the other element or one or more intervening elements can be present. In contrast, when an element is referred to as being "directly on," "directly attached," "directly connected" or "directly coupled" to another element, there are no intervening elements present. In the description and claims, a feature can be arranged "adjacent" to another feature, which can mean that the feature has a portion that overlaps the adjacent feature or a portion that is above or below the adjacent feature.

[0157] As used herein, the word "exemplary" means "serving as an example, instance, or illustration," and not "preferred" or "advantageous over other implementations." Furthermore, the disclosure is not to be limited to any expressed or implied theory of operation by any stated or implied theories presented in the Background or Summary or Detailed Description of the Invention. As used herein, the word "substantially" means including any small variations as a result of design, manufacturing, and / or other factors, instrument or component tolerances, environmental influences, and / or other factors. The word "substantially" also allows for differences that are within experimental error or other practical considerations.

[0158] Additionally, for purpose of reference only, the terms "first", "second", and like terms can also be used herein and, therefore, are not intended to limit the scope of the disclosure. For example, unless otherwise clear from context, the words "first", "second", and other such numerical terms when used in conjunction with describing a structure or element are not meant to connote a sequential or chronological order. It is also to be understood that the term "comprising" or "including" when used herein is taken to specify the presence of stated features, integers, steps, operations, elements, or components but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. In the present disclosure, the term "providing" is used in a broad sense to encompass all means of obtaining an object, and thus "providing an object" includes, but is not limited to, "purchasing", "preparing / manufacturing", "arranging / setting", "installing / fitting", and / or "ordering" the object, etc.

[0159] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0160] Those skilled in the art will realize that the boundaries between the above described operations merely illustrative. The multiple operations can be combined into a single operation, a single operation can be distributed in additional operations and operations can be executed at least partially overlapping in time. Moreover, alternative embodiments can include a number of instances of a particular operation, and the order of the operations can be altered in other various embodiments. However, other modifications, variations, and alternatives are also possible. The aspects and elements of all such embodiments can be combined in any manner and / or with other aspects or elements, without departing from the scope of the present disclosure. It is intended that the description and examples be considered as illustrative only, with the true scope of the disclosure being indicated by the following claims.

[0161] While certain embodiments of the disclosure have been described in detail, those skilled in the art should understand that they are merely examples of the disclosure and other embodiments can be made without departing from the spirit and scope of the disclosure. Those skilled in the art will also understand that a variety of modifications, both as to the nature of the disclosed embodiments and their implementation, can be made without departing from the spirit and scope of the disclosure. The scope of the disclosure is defined by the appended claims.

Claims

1. An adder circuit, characterized by The addition circuit is configured to calculate a sum of a first number and a second number, the addition circuit having a first input representing the first number and a second input representing the second number and having an output representing the sum of the first number and the second number, each of the first input and the second input being divided into 1st to Nth parts corresponding to each other, N being an integer greater than 1, the 1st to Nth parts sequentially representing partial bits of the input from a low bit to a high bit, the addition circuit comprising: a carry logic module configured to calculate one or more carries, each of the one or more carries corresponding to a carry generated by adding a respective one of the first input and a corresponding part of the second input; a first register module configured to store the 1st to N-1th parts of the first input; a second register module configured to store the 1st to N-1th parts of the second input; a third register module coupled to the carry logic module and configured to store the one or more carries; a first sum logic module configured to sum the Nth part of the first input and the Nth part of the second input, thereby generating an intermediate sum; a fourth register module coupled to the first sum logic module and configured to store the intermediate sum; and a second sum logic module coupled to the first to fourth register modules and configured to sum the 1st to N-1th parts of the first input, the 1st to N-1th parts of the second input, the intermediate sum, and the one or more carries, wherein the sum output by the second sum logic module sequentially represents partial bits of the output from a low bit to a high bit.

2. The addition circuit of claim 1, wherein, The carry logic module is configured to calculate the one or more carries using a look-ahead carry logic.

3. The adder circuit of claim 1, wherein, The first sum logic module is implemented as a ripple-carry adder.

4. The adder circuit of claim 1, wherein, The second sum logic module is implemented as a plurality of ripple-carry adders in parallel.

5. The adder circuit of claim 1, wherein, N is an integer greater than 2, and wherein: The carry logic module is configured to calculate N-2 carries, an i-th carry of the N-2 carries corresponding to a carry generated by adding an i-th part of the first input and an i-th part of the second input, i = 1, …, N-2; The first register module and the second register module each comprise 1st to N-1th units, and the second sum logic module comprises 1st to N-1th adders; a j-th unit of the first register module is configured to store a j-th part of the first input, a j-th unit of the second register module is configured to store a j-th part of the second input, and a j-th adder of the second sum logic module is coupled to the j-th unit of the first register module and the j-th unit of the second register module, j = 1, …, N-1; a 1st adder of the second sum logic module is configured to sum the 1st part of the first input and the 1st part of the second input; and an N-1th adder of the second sum logic module is further coupled to the third register module and the fourth register module and is configured to sum the N-1th part of the first input, the N-1th part of the second input, the intermediate sum, and an N-2th carry of the N-2 carries.

6. The adder circuit of claim 5, wherein, N is an integer greater than 3, and wherein the kth adder of the second summation logic module is further coupled to a third register module and configured to sum the kth portion of the first input, the kth portion of the second input, and the k-1th carry of the N-2 carries, k = 2, …, N-2.

7. The adder circuit of claim 5, wherein, Each of the 1st portion to the N-2th portion of each of the first input and the second input has a first number of bits, and the N-1th portion to the Nth portion of the input has a second number of bits in total, the second number of bits being equal to the first number of bits.

8. The adder circuit of claim 5, wherein, The carry logic module comprises: a preprocessor configured to perform, in parallel, an exclusive-OR operation and an AND operation on each bit of the 1st portion to the N-2th portion of the first input and a corresponding bit of the 1st portion to the N-2th portion of the second input, respectively, thereby generating a corresponding carry signal and a generate signal; and a carry generator configured to generate the N-2 carries using the carry signals and the generate signals generated by the preprocessor.

9. The adder circuit of claim 1, wherein: the carry logic module is configured to compute N-1 carries, the ith carry of the N-1 carries corresponding to a carry generated by adding the ith portion of the first input and the ith portion of the second input, i = 1, …, N-1; the first register module and the second register module each comprise 1st to N-1th cells, and the second summation logic module comprises 1st to Nth adders; the jth cell of the first register module is configured to store the jth portion of the first input, the jth cell of the second register module is configured to store the jth portion of the second input, and the jth adder of the second summation logic module is coupled to the jth cell of the first register module and the jth cell of the second register module, j = 1, …, N-1; the 1st adder of the second summation logic module is configured to sum the 1st portion of the first input and the 1st portion of the second input; and the Nth adder of the second summation logic module is further coupled to a third register module and a fourth register module and configured to sum the intermediate sum and the N-1th carry of the N-1 carries. N is an integer greater than 2, and wherein the kth adder of the second summation logic module is further coupled to a third register module and configured to sum the kth portion of the first input, the kth portion of the second input, and the k-1th carry of the N-1 carries, k = 2, …, N-1.

10. The adder circuit of claim 9, wherein, Each portion of each of the first input and the second input has a same number of bits.

11. The adder circuit of claim 9, wherein, The carry logic module comprises:

12. The adder circuit of claim 9, wherein, a preprocessor configured to perform, in parallel, an exclusive-OR operation and an AND operation on each bit of the 1st portion to the N-1th portion of the first input and a corresponding bit of the 1st portion to the N-1th portion of the second input, respectively, thereby generating a corresponding carry signal and a generate signal; and a carry generator configured to generate the N-1 carries using the carry signals and the generate signals generated by the preprocessor. The carry generator comprises a parallel prefix network.

13. The adder circuit of claim 8 or 12, wherein, The operation circuit comprises:

14. An arithmetic circuit, characterized by comprising: a summation module comprising the adder circuit according to any one of claims 1 to 13; and a carry logic module configured to compute N-1 carries, the ith carry of the N-1 carries corresponding to a carry generated by adding the ith portion of the first input and the ith portion of the second input, i = 1, …, N-1; a first operation module coupled to the sum module to provide the first input and the second input of the adder circuit.

15. The operation circuit of claim 14, wherein, the operation circuit comprises a plurality of operation stages, each of the plurality of operation stages comprises a respective register module, and the plurality of operation stages comprises a first operation stage and a second operation stage next to the first operation stage, the second operation stage further comprises the first to fourth register modules of the adder circuit, the first operation module is arranged between the first operation stage and the second operation stage and coupled to the first respective register module of the first operation stage, the first operation module is configured to operate on data from the first respective register module to generate the first input and the second input of the adder circuit, and the carry logic module and the first sum logic module of the adder circuit are arranged between the first operation stage and the second operation stage.

16. The operation circuit of claim 15, wherein, the plurality of operation stages further comprises a third operation stage next to the second operation stage, a third respective register module of the third operation stage is coupled to the sum module to receive the output of the adder circuit, and the second sum logic module of the adder circuit is arranged between the second operation stage and the third operation stage.

17. The arithmetic circuit according to claim 16, wherein the operation circuit further comprises: a second operation module arranged between the second operation stage and the third operation stage and coupled to the second respective register module of the second operation stage, the second operation module is configured to operate on data from the second respective register module.

18. The arithmetic circuit according to claim 17, wherein the sum module is a first sum module, the adder circuit is a first adder circuit, and the operation circuit further comprises: a second sum module, the second sum module comprises a second adder circuit, the second adder circuit is the adder circuit according to any one of claims 1 to 13, wherein the third operation stage further comprises the first to fourth register modules of the second adder circuit, the second operation module is coupled to the second sum module to provide the first input and the second input of the second adder circuit, and is configured to operate on data from the second respective register module to generate the first input and the second input of the second adder circuit, and the carry logic module and the first sum logic module of the second adder circuit are arranged between the second operation stage and the third operation stage.

19. A circuit for performing a hash algorithm, characterized by the circuit comprises: an input configured to receive data; and an operation configured to calculate a hash value based on the received data, and comprises a plurality of operation stages arranged in a pipeline structure, wherein: the plurality of operation stages comprises a first operation stage and a second operation stage next to the first operation stage, each of the first operation stage and the second operation stage comprises a 0th extension register module to a 15th extension register module configured to store 0th extension data to 15th extension data of the operation stage, respectively, the 15th extension register module comprises a first sum register submodule, a second sum register submodule, a first carry register submodule, and a second carry register submodule, the first operation stage further comprises a first sum logic module and a first carry logic module, the second operation stage further comprises a second sum logic module and a second carry logic module, the first sum logic module and the first carry logic module of the first operation stage are coupled to the second sum logic module and the second carry logic module of the second operation stage to provide the first input and the second input of the adder circuit, and the second sum logic module and the second carry logic module of the second operation stage are coupled to the first sum logic module and the first carry logic module of the first operation stage to receive the output of the adder circuit. The circuit further comprises a first extended data operation module arranged between the first operation stage and the second operation stage, the first extended data operation module comprising a first submodule, a second submodule and a third submodule, The first submodule is configured to calculate an initial sum and an initial carry based on the 0th extended data of the first operation stage and based on at least two of the 1st extended data, the 9th extended data and the 14th extended data of the first operation stage, each of the initial sum and the initial carry is divided into the 1st to Nth parts corresponding to each other to include, N being an integer greater than 2, the 1st to Nth parts sequentially representing partial bits of each of them from low bits to high bits, wherein the 1st to N-1th parts of the initial sum are stored in a first sum register submodule of a 15th extended register module of the second operation stage, and the 1st to N-1th parts of the initial carry are stored in a first carry register submodule of the 15th extended register module of the second operation stage, The second submodule is configured to calculate N-2 carries, the i-th carry of the N-2 carries corresponding to a carry generated by adding the i-th part of the initial sum and the i-th part of the initial carry, i = 1, …, N-2, the N-2 carries being stored in a second carry register submodule of the 15th extended register module of the second operation stage, and The third submodule is configured to sum the Nth part of the initial sum and the Nth part of the initial carry, thereby generating an intermediate sum, the intermediate sum being stored in a second sum register submodule of the 15th extended register module of the second operation stage.

20. The circuit of claim 19, wherein, The plurality of operation stages further comprises a third operation stage immediately following the second operation stage, the third operation stage comprising a 14th extended register module configured to store the 14th extended data of the operation stage, and The circuit further comprises a second extended data operation module arranged between the second operation stage and the third operation stage, the second extended data operation module comprising a fourth submodule, the fourth submodule comprising 1st to N-1th adders, The 1st adder is configured to sum the 1st part of the initial sum and the 1st part of the initial carry, The N-1th adder is configured to sum the N-1th part of the initial sum, the N-1th part of the initial carry, the intermediate sum and the N-2th carry of the N-2 carries, and The N-1 sums output by the 1st to N-1th adders are stored in the 14th extended register module of the third operation stage.

21. The circuit of claim 20, wherein, N is an integer greater than 3, wherein the kth adder of the fourth submodule is configured to sum the kth part of the initial sum, the kth part of the initial carry and the k-1th carry of the N-2 carries, k = 2, …, N-2.

22. A circuit for performing a hash algorithm, characterized by The circuit comprises: an input configured to receive data; and an operation configured to calculate a hash value based on the received data, and comprising a plurality of operation stages arranged in a pipeline structure, wherein: the first operation stage comprises a first extended register module configured to store the 0th extended data of the operation stage, The plurality of operation stages includes a first operation stage and a second operation stage next to the first operation stage, each of the first operation stage and the second operation stage includes 0th to 15th extension register modules respectively configured to store 0th to 15th extension data of the operation stage, the 15th extension register module includes a first sum register submodule, a second sum register submodule, a first carry register submodule and a second carry register submodule, The circuit further includes a first extension data operation module arranged between the first operation stage and the second operation stage, the first extension data operation module includes a first submodule, a second submodule and a third submodule, The first submodule is configured to calculate an initial sum and an initial carry based on the 0th extension data of the first operation stage and based on at least two of the 1st, 9th and 14th extension data of the first operation stage, each of the initial sum and the initial carry is divided into 1st to Nth parts corresponding to each other to represent partial bits of each thereof in turn from low bits to high bits, wherein the 1st to N-1th parts of the initial sum are stored in the first sum register submodule of the 15th extension register module of the second operation stage, and the 1st to N-1th parts of the initial carry are stored in the first carry register submodule of the 15th extension register module of the second operation stage, The second submodule is configured to calculate N-1 carries, an i-th carry of the N-1 carries corresponds to a carry generated by adding an i-th part of the initial sum and an i-th part of the initial carry, i = 1, …, N-1, the N-1 carries are stored in the second carry register submodule of the 15th extension register module of the second operation stage, and The third submodule is configured to sum the Nth part of the initial sum and the Nth part of the initial carry to generate an intermediate sum, the intermediate sum is stored in the second sum register submodule of the 15th extension register module of the second operation stage.

23. The circuit of claim 22, wherein, The plurality of operation stages further includes a third operation stage next to the second operation stage, the third operation stage includes a 14th extension register module configured to store a 14th extension data of the operation stage, and The circuit further includes a second extension data operation module arranged between the second operation stage and the third operation stage, the second extension data operation module includes a fourth submodule, the fourth submodule includes 1st to Nth adders, The 1st adder is configured to sum the 1st part of the initial sum and the 1st part of the initial carry, The Nth adder is configured to sum the intermediate sum and an N-1th carry of the N-1 carries, and The N sums output by the 1st to Nth adders are stored in the 14th extension register module of the third operation stage.

24. The circuit of claim 23, wherein, N is an integer greater than 2, wherein a kth adder of the fourth submodule is configured to sum a kth part of the initial sum, a kth part of the initial carry and a k-1th carry of the N-1 carries, k = 2, …, N-1.

25. A computing chip, comprising: The computing chip comprises the circuit according to any one of claims 1 to 24.

26. A computing device comprising: The computing device comprises the computing chip according to claim 25.

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