TSN offline-online hybrid scheduling method based on FPGA

Abstract

The invention relates to a TSN off-line-on-line hybrid scheduling method based on an FPGA. The method comprises the following steps: an off-line stage: calculating a gating table of periodic flow by using SMT; in the mapping stage, the gating table is converted into a checkable two-dimensional Boolean table through serial analysis, address decoding and a dual-port RAM; in the on-line stage, the FPGA parallel LAW calculation and ASAP window selection assembly line dynamically distributes a CQF time slot for a burst frame in a microsecond level, and returns offset through a UDP (User Datagram Protocol). According to the invention, through the architecture of off-line calculation and on-line parallel table look-up, the coexistence of periodic traffic certainty guarantee and burst traffic microsecond scheduling is realized, and the real-time performance, the resource efficiency and the expandability are considered.

Description

TECHNICAL FIELD

[0001] The application relates to a TSN offline-online hybrid scheduling method based on FPGA, which is suitable for deterministic communication and microsecond-level scheduling in a period and burst traffic coexistence scene in an intelligent networked vehicle and belongs to the technical field of vehicle-mounted time-sensitive network (TSN) scheduling. BACKGROUND

[0002] The traditional vehicle-mounted Ethernet scheduling method has some defects, mainly in static parameter rigidity: only supporting offline configured CQF gate table, unable to dynamically respond to burst event frames, leading to occasional traffic congestion or periodic traffic being interrupted; poor real-time performance: CPU side sequential traversal window, scheduling delay up to milliseconds, difficult to meet the 200 mu s E2E upper limit; resource waste: fixed bandwidth reserved for occasional traffic, leading to decreased periodic traffic utilization.

[0003] Based on the defects of the above-mentioned traditional vehicle-mounted Ethernet scheduling method, the application provides a TSN offline-online hybrid scheduling method based on FPGA, which solves and realizes mu s-level scheduling through FPGA parallel hardware by offline solver, and considers determinism and flexibility. SUMMARY

[0004] In order to overcome the phenomenon of static parameter rigidity and poor real-time performance of the existing traditional vehicle-mounted Ethernet scheduling method, the application provides a TSN offline-online hybrid scheduling method based on FPGA, which realizes the coexistence of periodic traffic deterministic guarantee and microsecond-level scheduling of burst traffic through the architecture of offline calculation and online parallel table lookup, and considers real-time performance, resource efficiency and scalability.

[0005] A TSN offline-online hybrid scheduling method based on FPGA, comprising:

[0006] Offline stage: calculating the gate table of periodic traffic by SMT;

[0007] Mapping stage: converting the gate table into a searchable two-dimensional Boolean table through serial analysis, address decoding and dual-port RAM;

[0008] Online stage: dynamically allocating CQF time slots for burst frames in microsecond level by FPGA parallel LAW calculation and ASAP window selection pipeline, and returning offset through UDP. When a burst event frame appears, an Arbiter Thread dynamically allocates a CQF time slot for it which does not collide with periodic traffic, and immediately returns the sending time to complete the scheduling of the burst frame window selection.

[0009] The offline stage comprises the following steps:

[0010] S1.1: write "E2E delay, jitter, redundancy, slack window" into constraints by Z3-SMT;

[0011] The specific method of S1.1 comprises:

[0012] S1.11: An "offset" variable is established for each link in the Z3 solver, and a "period" and "frame length" constant are established for each flow;

[0013] S1.12: An E2E delay constraint is written: the link delay and offset of a frame on a path are added together and are less than the requirement; a jitter constraint is written: the difference in arrival time of the same flow on the main path and the redundant path is less than or equal to the upper limit of the jitter; a redundancy constraint is written: the time window of the redundant member flow must be later than the original flow and earlier than the elimination node; a slack window constraint is written: n periods are forced to be empty between adjacent frames, to leave space for an online burst flow; a link capacity constraint (total frame length per slot <= bandwidth * Tcyc) and a frame isolation constraint (only one frame per slot on the same link) are added, to ensure that the solution is feasible;

[0014] S1.2: On the premise that all constraints (E2E, jitter, redundancy, and slack window) are met, the Z3 solver is called to obtain the offset of each frame on each link, to generate a GateList.

[0015] The specific method of S1.2 comprises: all constraint inequalities are introduced into the solver, and if the conditions are met, a GateList (link, slot, type) is obtained; if the solving result is UNSAT, a parameter adjustment suggestion log is automatically generated (Tcyc is increased, the frame length is reduced, the delay is relaxed, or the redundant path is optimized), and the iteration is performed again to solve, until the GateList is obtained.

[0016] The mapping stage comprises the following steps:

[0017] S2.1: The host computer writes the GateList into the FPGA row by row through the UART, to convert into a StatusArray (a two-dimensional Boolean table), and the 32-bit bus frame format at this time is {16'b linkID, 14'b slot, 2'b type};

[0018] S2.2: The 32-bit bus frame {linkID[15:0], slot[13:0], type[1:0]} is split into three independent signals by a serial parser module

[0019] S2.3: An address decoder module splices {link, slot} into a unique RAM address line, to directly locate the target unit in the StatusArray;

[0020] S2.4: A dual-port RAM is used as a one-dimensional status[link][slot] lookup table storage.

[0021] The specific format of the 32-bit bus frame in S2.1 is as follows: linkID is the global number of the link, slot is the period slot number (slot index) in the super cycle, and type represents the state of the slot, which is 00 = FREE (not occupied by any traffic), 01 = PERIODIC (offline calculated periodic frame reservation), and 10 = EVENT (burst frame occupied in the online stage).

[0022] S2.2 is specifically divided into three independent signals, which are linkID register, slot register, and type register.

[0023] The specific function of the dual-port RAM in S2.4 is as follows: one port, Write Port (B port), only writes, and writes all link+slot generated states in the mapping stage; and the other port, Read Port (A port), only reads, and queries whether a certain link and slot are idle in the online stage.

[0024] The online stage includes the following steps:

[0025] S3.1: The arbitrator thread receives the occasional event frame request from each sensor through UDP.

[0026] The specific steps of receiving the occasional event frame request through UDP in S3.1 are as follows:

[0027] The arbitrator thread starts the UDP listening task in the FPGA and binds a fixed port.

[0028] When any sensor needs to send a burst frame, an event request UDP packet is sent to the port, and the packet length is ≤64 bytes.

[0029] After the thread receives the packet, the entire packet data is stored in the receiving FIFO, and the arrival timestamp T_arb is recorded.

[0030] S3.2: The request is parsed by the FSM (state machine) into source node, destination node, frame size, priority, and routing path.

[0031] The specific message parsing in S3.2 is as follows: bytes 0-1 are the source node ID (16 bits), bytes 2-3 are the destination node ID (16 bits), bytes 4-5 are the frame size (16 bits), byte 6 is the priority (8 bits, 0-7), and bytes 7-N are the routing path (variable length, arranged in order of link number).

[0032] S3.3: Calculate LAW, calculate the searchable window range [nStart, nEnd];

[0033] S3.4: Traverse in StatusArray according to ASAP (As-Soon-As-Possible) strategy, find the earliest free slot, and mark all slots of the corresponding link as "EVENT";

[0034] S3.5: Return the calculated sending offset to the requester, and the requester sends frames under the gPTP global clock according to the offset.

[0035] The specific calculation method of LAW in S3.3 is as follows:

[0036] nStart = (T_arb + E_wcet + R_resp) / Tcyc

[0037] nEnd = (TGen + TE2ER - (h_max + 1) * Tcyc) / Tcyc

[0038] Where T_arb is the arrival time of the arbitration request frame under the global gPTP time; E_wcet is the worst-case execution time of the arbitration algorithm; R_resp is the worst-case response frame delay of returning the calculated sending offset to the source node; Tcyc is the CQF period length; TGen is the time when the event frame is generated in the source node; TE2ER is the upper limit of the end-to-end delay applied to this event frame; h_max is max(h_def, h_red), which is the maximum number of hops that the traffic passes through on the default path or the redundant path; (max(...)+1)*Tcyc is the total worst-case forwarding delay in the network;

[0039] Adder and barrel shifter are used on FPGA to realize parallel calculation of LAW: T_arb[13:0], E_wcet[13:0] and R_resp are calculated by parallel adder tree to get nStart_tmp[30:0], and the result is shifted by 31-bit barrel shifter. Once multiplication is added to right shift 16 bits, "divide by 10" can be approximately completed and the integer quotient is obtained. Finally, the high bits are taken to get nStart[13:0]. TGen, TE2ER, h_max, Tcyc are calculated by parallel adder tree to get nEnd_tmp[30:0], and then the result nEnd[13:0] is obtained by barrel shifter and taking high bits, realizing three-number addition + constant division compression to single cycle.

[0040] The specific method of finding the earliest free slot in S3.4 using ASAP strategy is as follows:

[0041] The ASAP strategy traversal is sequentially scanned from left to right (starting from nStart) in the LAW range, slot by slot, and once a certain link-slot combination is found to be idle, the combination is occupied immediately, and no further scanning is performed, so that the event frame is sent as early as possible, and the specific steps are as follows:

[0042] S3.41 Parallel reading: in each clock cycle, the FPGA sends an address in parallel, and simultaneously reads the states of all links in the same TimeWindow from the read port of the dual-port BRAM at one time, to form a state vector;

[0043] S3.42 Conflict detection: for a single time window t, a bitwise OR reduction is performed on the state vector, and if the result is zero, the window is marked as idle; then the above detection logic is copied nLAW times (LAW length), and an nLAW-wide conflict vector conflict_vec[nLAW-1:0] is generated in parallel in one clock cycle, wherein conflict_vec[t] = 1 indicates that there is a conflict in window t, and 0 indicates that it is idle;

[0044] S3.43 Priority encoding: scan the conflict_vec, and output the index with the lowest bit of 0 (i.e., the earliest idle window), which is the sending offset slot_idx of the event frame;

[0045] S3.44: realized through a pipeline structure: stage 1: read the state from the BRAM; stage 2: parallel conflict detection; stage 3: priority encoding.

[0046] The specific steps of the backhaul offset in S3.4: after window selection, the arbitrator obtains slot_idx (sending offset), packs slot_idx into a scheduling response UDP packet, bytes 0-3 are offset values, 4-5 are CRC-16 or cumulative sum check codes, and the packet is returned to the requester through UDP, and the requester obtains the offset, and injects the event frame into the network at the corresponding time of the gPTP global clock, without the need for further calculation.

[0047] Compared with the prior art, the present application has the following advantages:

[0048] The core of the present application is to improve the response speed of the sporadic event frame request through the FPGA. The present application calculates offline and uses a parallel table lookup architecture to ensure zero jitter and zero packet loss for periodic traffic, and complete scheduling within 200us for burst traffic; a parallel LAW calculation unit and an ASAP window selection pipeline are used to compress the scheduling delay to 15ns; UDP requests are supported, and gPTP global clock delivery is also supported, to realize deterministic, low-delay and low-resource scheduling of periodic-burst mixed traffic of vehicle-mounted TSN.

[0049] The application splits the scheduling problem of vehicle-mounted periodic flow and burst flow into an offline calculation and an online closed-loop table lookup architecture: the offline stage uses SMT to solve the global optimal gating table once; the mapping stage converts the gating table into a searchable two-dimensional Boolean table through serial analysis, address decoding and dual-port RAM; the online stage dynamically allocates CQF time slots for burst frames within microseconds by the FPGA parallel LAW calculation and ASAP window selection pipeline, and returns the offset through UDP, realizing zero jitter of periodic flow and zero packet loss of burst flow. The scheme takes into account real-time performance, resource efficiency and scalability, can be integrated into existing vehicle-mounted Ethernet, reduces upgrade costs, and provides high-reliability, low-latency and low-resource deterministic communication for intelligent networked vehicles. BRIEF DESCRIPTION OF DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0051] Figure 1 The specific framework diagram of the TSN offline-online hybrid scheduling method based on FPGA of the present application.

[0052] Figure 2 The offline stage flow chart of the TSN offline-online hybrid scheduling method based on FPGA of the present application.

[0053] Figure 3 The mapping stage flow chart of the TSN offline-online hybrid scheduling method based on FPGA of the present application.

[0054] Figure 4 The online stage flow chart of the TSN offline-online hybrid scheduling method based on FPGA of the present application.

[0055] Figure 5 The ASAP strategy traversal flow chart of the TSN offline-online hybrid scheduling method based on FPGA of the present application. DETAILED DESCRIPTION

[0056] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0057] REFERENCE Figure 1The application relates to a TSN offline-online hybrid scheduling method based on FPGA, which comprises the following steps:

[0058] Offline stage: using SMT to calculate the gating table of periodic traffic;

[0059] Mapping stage: converting the gating table into a searchable two-dimensional Boolean table through serial analysis, address decoding and double-port RAM;

[0060] Online stage: dynamically allocating CQF time slots for burst frames in the microsecond level by the FPGA parallel LAW calculation and ASAP window selection pipeline, and returning the offset through UDP. When a burst event frame occurs, an arbiter thread dynamically allocates a CQF time slot for the burst event frame which does not collide with periodic traffic, and immediately returns the sending time to complete the window selection and scheduling of the burst frame.

[0061] Reference Figure 2 The offline stage comprises the following steps:

[0062] S1.1: using Z3-SMT to write the “E2E delay, jitter, redundancy, slack window” as constraints;

[0063] The specific method of S1.1 comprises the following steps:

[0064] S1.11: building an “offset” variable for each link in the Z3 solver, and building “period” and “frame length” constants for each flow;

[0065] S1.12: writing the E2E delay constraint: adding the link delay and offset of the frame on the path, and being less than the requirement; writing the jitter constraint: the difference between the arrival times of the same flow on the main path and the redundant path is less than or equal to the upper limit of the jitter; writing the redundancy constraint: the time window of the redundant member flow must be later than the original flow and earlier than the elimination node; writing the slack window constraint: n periods are forced to be left between adjacent frames to leave space for the online burst flow; adding the link capacity constraint (total frame length per slot <= bandwidth * Tcyc) and the frame isolation constraint (only one frame in the same link and slot), so as to ensure that the solution is feasible;

[0066] S1.2: under the premise of meeting all the constraints (E2E, jitter, redundancy, slack window), calling the Z3 solver to obtain the offset (deterministic sending time) of each frame on each link, and generating a GateList (gating list).

[0067] The specific method of S1.2 includes: introducing all constraint inequalities into a solver, obtaining a GateList(link, slot, type) if a condition is met, automatically generating a parameter adjustment suggestion log (increasing Tcyc, reducing frame length, relaxing delay or optimizing redundant path) if the solving result is UNSAT, and solving again after iteration until a GateList is obtained.

[0068] With reference to Figure 3 The mapping stage includes the following steps:

[0069] S2.1: The host computer writes the GateList into the FPGA row by row through the UART, and converts it into a StatusArray (a two-dimensional Boolean table). At this time, the 32-bit bus frame format is {16'b linkID, 14'b slot, 2'b type}.

[0070] S2.2: The serial parser module splits the 32-bit bus frame {linkID[15:0], slot[13:0], type[1:0]} into three independent signals.

[0071] S2.3: The address decoder module combines {link, slot} into a unique RAM address line, which is used to directly locate the target unit in the StatusArray.

[0072] S2.4: The dual-port RAM is used as a one-dimensional status[link][slot] lookup table memory.

[0073] The specific format of the 32-bit bus frame in S2.1 is as follows: linkID is the global number of the link, slot is the period slot number (slotindex) in the supercycle, and type represents the state of the slot, which is 00 = FREE (not occupied by any traffic), 01 = PERIODIC (offline calculated periodic frame reservation), and 10 = EVENT (online stage assigned burst frame occupation).

[0074] S2.2 splits into three independent signals, which are bit[31:16] into the linkID register, bit[15:2] into the slot register, and bit[1:0] into the type register.

[0075] The specific function of the dual-port RAM in S2.4 is as follows: one port Write Port (B port) only writes, and writes all link+slot generated states in the mapping stage; the other port Read Port (A port) only reads, and queries whether a certain link and slot are idle in the online stage.

[0076] With reference toFigure 4 , the online stage comprises the following steps:

[0077] S3.1: The arbitrator thread receives the sporadic event frame request from each sensor through UDP;

[0078] The specific steps of receiving the sporadic event frame request in S3.1 are as follows:

[0079] The arbitrator thread starts a UDP listening task in the FPGA and binds a fixed port;

[0080] When any sensor needs to send a burst frame, an event request UDP packet is sent to the port, and the packet length is ≤64 bytes;

[0081] After the thread receives the packet, the entire packet data is stored in the receiving FIFO, and the arrival timestamp T_arb is recorded;

[0082] S3.2: The FSM (state machine) parses the request into: source node, destination node, frame size, priority, and routing path;

[0083] The packet parsing in S3.2 is as follows: bytes 0-1 are the source node ID (16 bits), bytes 2-3 are the destination node ID (16 bits), bytes 4-5 are the frame size (16 bits), byte 6 is the priority (8 bits, 0-7), and bytes 7-N are the routing path (variable length, arranged in order of link number);

[0084] S3.3: Calculate the LAW to calculate the searchable window range [nStart, nEnd];

[0085] S3.4: Traverse in the StatusArray according to the ASAP (As-Soon-As-Possible) strategy to find the earliest idle slot, and mark all slots of the corresponding link as “EVENT”;

[0086] S3.5: Return the calculated sending offset to the requester, and the requester sends the frame under the gPTP global clock according to the offset.

[0087] The specific calculation method of the LAW in S3.3 is as follows:

[0088] nStart = (T_arb + E_wcet + R_resp) / Tcyc

[0089] nEnd = (TGen + TE2ER - (h_max + 1) * Tcyc) / Tcyc

[0090] Where T_arb is the arrival time of the request frame at the arbiter under the global gPTP time; E_wcet is the worst-case execution time of the arbiter internal algorithm; R_resp is the worst-case response frame delay of returning the calculated sending offset to the source node; Tcyc is the CQF cycle length; TGen is the time when the event frame is generated in the source node; TE2ER is the upper limit of the end-to-end delay applied to this event frame; h_max is max(h_def, h_red), which is the maximum number of hops of the traffic on the default path or the redundant path; (max(...)+1)*Tcyc is the total worst-case forwarding delay in the network;

[0091] The LAW parallel calculation is implemented on the FPGA using a three-stage carry-lookahead adder and a barrel shifter: T_arb[13:0], E_wcet[13:0] and R_resp are calculated through a parallel addition tree to obtain nStart_tmp[30:0], and the result is shifted through a 31-bit barrel shifter; once multiplication is added to right shift 16 bits, the integer quotient of "divide by 10" can be approximately completed, and nStart[13:0] is obtained by taking the high bits; TGen, TE2ER, h_max and Tcyc are calculated through a parallel addition tree to obtain nEnd_tmp[30:0], and the result nEnd[13:0] is obtained by shifting and taking the high bits through a barrel shifter, so that three-number addition plus constant division is compressed into a single cycle.

[0092] The ASAP strategy traversal in S3.4 finds the earliest idle slot, and the specific method is as follows:

[0093] The ASAP strategy traversal is a sequential scanning of each slot from left to right (starting from nStart) within the LAW range, and once a link-slot combination is found to be idle, it is immediately occupied and no longer continues to look back, so as to ensure that the event frame is sent out as early as possible, and the specific steps are as follows:

[0094] S3.41 Parallel reading: in each clock cycle, the FPGA issues an address in parallel, and simultaneously reads the status of all links in the same TimeWindow from the read port of the dual-port BRAM at one time, forming a status vector;

[0095] S3.42 Conflict detection: for a single time window t, perform a bitwise OR reduction on the status vector, and if the result is zero, mark the window as idle; then copy the above detection logic nLAW times (LAW length), and generate a nLAW-wide conflict vector conflict_vec[nLAW-1:0] in parallel in one clock cycle, where conflict_vec[t] = 1 indicates that there is a conflict in window t, and 0 indicates that it is idle;

[0096] S3.43 Priority encoding: scan the conflict_vec, output the index with the lowest bit of 0 (i.e. the earliest free window), which is the sending offset slot_idx of the event frame;

[0097] S3.44: implementation through a pipeline structure: stage 1: read the state from BRAM; stage 2: parallel conflict detection; stage 3: priority encoding.

[0098] The specific steps of the backhaul offset described in S3.4: after the window selection is completed, the arbitrator obtains the slot_idx (sending offset), packs the slot_idx into a scheduling response UDP packet, the bytes 0-3 are the offset value, 4-5 are the CRC-16 or cumulative sum check code, the packet is returned to the requester through UDP, and the requester obtains the offset, injects the event frame into the network at the corresponding time of the gPTP global clock, and there is no need to calculate again.

[0099] The embodiments of the application are described in detail above with reference to the drawings, but the application is not limited to the described embodiments. For those skilled in the art, various changes, modifications, replacements and variations can be made to the embodiments without departing from the principles and spirits of the application, and still fall within the protection scope of the application.

Claims

1. A TSN off-line-online hybrid scheduling method based on FPGA, characterized in that: Comprise: Offline stage: SMT algorithm good cycle flow of the gate table; Mapping stage: through serial analysis, address decoding and dual-port RAM gate table into searchable two-dimensional Boolean table; Online stage: by FPGA parallel LAW calculation and ASAP window pipeline for burst frame dynamic allocation of CQF time slot, and through the UDP back offset.

2. The FPGA-based TSN offline-online hybrid scheduling method according to claim 1, wherein: The offline stage comprises the following steps: S1.1: "E2E latency, jitter, redundancy, relaxation window" is written into constraints by Z3-SMT; S1.2: under the premise of meeting all constraints, call Z3 solver to determine the offset of each link on each frame, generate gate list.

3. The FPGA-based TSN offline-online hybrid scheduling method of claim 1, wherein: The mapping stage comprises the following steps: S2.1: the host computer writes GataList into FPGA through UART, and converts it into StatusArray two-dimensional Boolean table, 32-bit bus frame format is {16'b linkID, 14'b slot, 2'b type}; S2.2: the serial parser module splits the 32-bit bus frame {linkID[15:0], slot[13:0], type[1:0]} into three independent signals; S2.3: the address decoder module combines {link, slot} into a unique RAM address line, which is used to directly locate the target unit in StatusArray; S2.4: dual-port RAM is used as a one-dimensional status[link][slot] lookup table storage.

4. The FPGA-based TSN offline-online hybrid scheduling method of claim 1, wherein: The online stage comprises the following steps: S3.1: the arbitrator thread receives the occasional event frame request from each sensor through UDP; S3.2: the analysis state machine splits the request into: source node, destination node, frame size, priority, routing path; S3.3: calculate LAW, calculate the searchable window range [nStart, nEnd]; S3.4: traverse in StatusArray according to ASAP strategy, find the earliest free slot, mark all slots of the corresponding link as "EVENT"; S3.5: return the calculated sending offset to the requester, and the requester sends the frame under the gPTP global clock according to the offset.

5. The FPGA-based TSN offline-online hybrid scheduling method according to claim 1, wherein: The specific format of the 32-bit bus frame in S2.1 is: linkID is the global number of the link, slot is the period slot number in the supercycle, type represents the state of the slot, which is 00 = FREE, 01 = PERIODIC, 10 = EVENT.

6. The FPGA-based TSN offline-online hybrid scheduling method according to claim 1, wherein: The specific function of the dual-port RAM in S2.4 is: The Write Port of the dual-port RAM port only writes, writes all link+slot to generate state in the mapping stage, and the Read Port only reads, queries whether a certain link slot is free in the online stage.

7. The FPGA-based TSN offline-online hybrid scheduling method according to claim 1, wherein: The specific calculation method of LAW in S3.3 is: nStart = (T_arb + E_wcet + R_resp) / Tcyc nEnd = (TGen + TE2ER - (h_max + 1) * Tcyc) / Tcyc Where T_arb is the arrival time of the request frame at the arbiter under the global gPTP time; E_wcet is the worst-case execution time of the arbiter's internal algorithm; R_resp is the worst-case response frame delay of returning the calculated sending offset to the source node; Tcyc is the CQF cycle length; TGen is the time when the event frame is generated in the source node; TE2ER is the upper limit of the end-to-end delay applied to this event frame; h_max, i.e., max(h_def, h_red), is the maximum number of hops that the flow passes through on the default path or the redundant path; (max(...)+1)*Tcyc is the total worst-case forwarding delay in the network.

8. The FPGA-based TSN offline-online hybrid scheduling method of claim 1, wherein: The specific method of the ASAP policy traversal in S3.4 is as follows: The ASAP policy traversal is a left-to-right sequential scanning of each slot within the LAW range, and once an idle link-slot combination is found, it is immediately occupied, and no further scanning is performed, so as to ensure that the event frame is sent as early as possible. The specific steps are as follows: S3.41 Parallel reading: in each clock cycle, the FPGA sends addresses in parallel, and at the same time, reads the states of all links in the same TimeWindow from the read port of the dual-port BRAM at one time, to form a state vector; S3.42 Conflict detection: for a single time window t, perform a bitwise OR reduction on the state vector, and if the result is zero, mark the window as idle; copy the above detection logic nLAW times, and form an nLAW-wide conflict vector conflict_vec[nLAW-1:0] within nLAW clock cycles, where conflict_vec[t] = 1 indicates that there is a conflict in window t, and 0 indicates that it is idle; S3.43 Priority encoding: scan the conflict_vec, and output the index with the lowest bit of 0, which is the sending offset slot_idx of the event frame; S3.44: implemented through a pipeline structure: stage 1: read the state from the BRAM; stage 2: parallel conflict detection; stage 3: priority encoding.

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