Semiconductor memory device

Abstract

A semiconductor memory device includes a first row of pillar structures and a second row of pillar structures penetrating a gate structure, extending into an interior of a source structure, and adjacent to each other. The source structure includes a first semiconductor layer and a second semiconductor layer stacked between the pillar structures of the first row and the pillar structures of the second row, or the source structure includes a first doped region and a second doped region between the pillar structures of the first row and the pillar structures of the second row, the first doped region and the second doped region have conductivity type dopants of different concentrations.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0059819, filed on May 7, 2024, in the Korean Intellectual Property Office, the entire application of which is incorporated by reference herein. TECHNICAL FIELD

[0003] The present disclosure relates generally to semiconductor memory devices and semiconductor memory devices of electronic systems, and more particularly, to three-dimensional semiconductor memory devices. BACKGROUND

[0004] Semiconductor memory devices are applied to electronic systems in various fields, including, in addition to compact electronic devices, automobiles, medical instruments, data centers, etc. Accordingly, the demand for semiconductor memory devices has increased.

[0005] Semiconductor memory devices include a memory cell array, and the memory cell array includes a plurality of memory cells for storing data. Semiconductor memory devices are classified into two-dimensional semiconductor memory devices including a two-dimensional memory cell array and three-dimensional semiconductor memory devices including a three-dimensional memory cell array.

[0006] Memory cells having a three-dimensional memory cell array are arranged three-dimensionally. The three-dimensional memory cell array has an advantage of providing a large capacity to a semiconductor memory device, whereas for a two-dimensional memory cell array, a plurality of memory cells are arranged on a plane, providing a smaller capacity. SUMMARY

[0007] According to one embodiment of the present disclosure, there is provided a semiconductor memory device including: a gate structure including a surface extending in a first direction and a second direction, the first direction being different from the second direction, the gate structure including insulating layers and conductive layers alternately disposed in a stacking direction protruding from the surface; a source structure overlapping the gate structure; and a plurality of pillar structures penetrating the insulating layers and the conductive layers, the plurality of pillar structures extending to an inside of the source structure, wherein each of the plurality of pillar structures includes: a channel structure penetrating the insulating layers and the conductive layers, the channel structure extending to the inside of the source structure; and a memory layer between the channel structure and the gate structure, and wherein the source structure includes: a first semiconductor layer including a bottom recessed portion into which the channel structure is inserted and a top recessed portion disposed between first and second rows of pillar structures adjacent to each other among the plurality of pillar structures; and a second semiconductor layer disposed above the first semiconductor layer to fill the top recessed portion.

[0008] According to one embodiment of the present disclosure, there is provided a semiconductor memory device including: a gate structure including a surface extending in a first direction and a second direction, the first direction being different from the second direction, the gate structure including insulating layers and conductive layers alternately disposed in a stacking direction protruding from the surface; a doped semiconductor structure overlapping the gate structure, the doped semiconductor structure including a conductive type dopant; and a plurality of pillar structures penetrating the insulating layers and the conductive layers, the plurality of pillar structures extending to an inside of the doped semiconductor structure, wherein each of the plurality of pillar structures includes: a channel structure penetrating the insulating layers and the conductive layers, the channel structure extending to the inside of the doped semiconductor structure; and a memory layer between the channel structure and the gate structure, wherein the doped semiconductor structure includes: a first doped region in contact with the channel structure, the first doped region including the conductive type dopant at a first concentration; and a second doped region disposed above the first doped region, the second doped region including the conductive type dopant at a second concentration different from the first concentration, and wherein a first thickness of the first doped region in the stacking direction and a second thickness of the second doped region in the stacking direction vary between a first row of the pillar structures and a second row of the pillar structures adjacent to each other among the plurality of pillar structures. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a block diagram illustrating a semiconductor memory device according to one embodiment of the present disclosure.

[0010] Figure 2A and Figure 2B is a plan view illustrating a semiconductor memory device according to one embodiment of the present disclosure.

[0011] Figure 3A , Figure 3B and Figure 3C are cross-sectional views of the semiconductor memory device illustrated in Figure 2A .

[0012] Figure 4A , Figure 4B and Figure 4C are cross-sectional views illustrating a source structure according to one embodiment of the present disclosure.

[0013] Figure 5A , Figure 5B , Figure 6A and Figure 6B are cross-sectional views illustrating a part of a manufacturing method for providing a semiconductor memory device according to one embodiment of the present disclosure.

[0014] Figure 7A , Figure 8A , Figure 9A and Figure 10Aare sectional views illustrating a manufacturing method of a semiconductor memory device according to an embodiment of the present disclosure, and Figure 7A , Figure 8A , Figure 9A and Figure 10A each illustrate a cross section of a structure of each unit process taken along a line I-I' shown in Figure 2A .

[0015] Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11 , Figure 12 and Figure 13 are sectional views illustrating a manufacturing method of a semiconductor memory device according to an embodiment of the present disclosure, and Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11 , Figure 12 and Figure 13 each illustrate a cross section of a structure of each unit process taken along a line II-II' shown in Figure 2A .

[0016] Figure 14 is a block diagram illustrating an electronic system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] The specific configuration or function descriptions of examples according to embodiments of the concepts disclosed in this specification are merely illustrated to describe examples according to embodiments of the concepts, and examples according to embodiments of the concepts can be implemented in various forms, but the descriptions are not limited to the examples of embodiments described in this specification.

[0018] Terms such as "first" and "second" are used to distinguish various elements, and do not imply size, order, priority, number, or importance of the elements. For example, in one example, a first element can be named as a second element, and in another example, a second element can be named as a first element. Terms such as "top", "above", "upper", "side", "upper portion", "lower portion", "higher", "column", "row", "inner", "outer", and other terms implying relative spatial relationships or orientations are used for the purpose of convenience of description or reference to the drawings only, and are not otherwise limiting. Cross-hatching in the drawings illustrates corresponding or similar areas between the drawings, rather than indicating materials associated with the areas.

[0019] Various embodiments provide a semiconductor memory device capable of improving operation reliability.

[0020] Figure 1 is a block diagram illustrating a semiconductor memory device according to one embodiment of the present disclosure.

[0021] Referring to Figure 1 The semiconductor memory device 50 includes a peripheral circuit 40 and a memory cell array 10.

[0022] The peripheral circuit 40 is configured to perform a program operation for storing data in the memory cell array 10, a read operation for outputting data stored in the memory cell array 10, and an erase operation for erasing data stored in the memory cell array 10. The peripheral circuit 40 includes a row decoder 33, a page buffer 37, and a source driver 39.

[0023] The memory cell array 10 includes a plurality of memory blocks BLK1 to BLKn (n is a natural number of 2 or more). The plurality of memory blocks BLK1 to BLKn are connected to the page buffer 37 through a plurality of bit lines BL. The plurality of memory blocks BLK1 to BLKn are connected to the row decoder 33 through a plurality of drain select lines DSL, a plurality of word lines WL, and a plurality of source select lines SSL. The plurality of memory blocks BLK1 to BLKn are connected to the source driver 39 through a plurality of common source layers CS.

[0024] Each memory block includes a plurality of memory cells. The plurality of memory cells can be arranged in first to third directions different from each other to constitute a three-dimensional memory cell array. Each memory block includes at least one source select line SSL, at least one drain select line DSL, and a plurality of word lines WL stacked between the at least one source select line SSL and the at least one drain select line DSL. Some of the plurality of word lines WL can be used as dummy word lines. An erase operation can be controlled in units of common source layers (CS). The common source layer CS can be connected to the memory block via a source structure.

[0025] The row decoder 33 transfers an operation voltage to the plurality of drain select lines DSL, the plurality of word lines WL, and the plurality of source select lines SSL. The page buffer 37 controls the plurality of bit lines BL, or senses a voltage or a current of the plurality of bit lines BL, thereby storing a sensed result. The source driver 39 controls the common source layer CS.

[0026] The memory cell array 10 can overlap the peripheral circuit 40. The plurality of bit lines BL, the plurality of word lines WL, the plurality of drain select lines DSL, the plurality of source select lines SSL, and the plurality of common source layers CS connected to the memory cell array 10 are electrically connected to the peripheral circuit 40 through conductive via structures.

[0027] Figure 2A and Figure 2Bis a plan view illustrating a semiconductor memory device according to one embodiment of the present disclosure.

[0028] Figure 3A 、 Figure 3B and Figure 3C is Figure 2A a cross-sectional view of the semiconductor memory device shown in

[0029] Referring to Figure 2A 、 Figure 3A and Figure 3B , the semiconductor memory device includes a first structure 70 and a second structure 80 above the first structure 70. The first structure 70 can include some conductive via structures such as an interconnect structure IC, peripheral circuit structures such as transistors TR1 and TR2, and the like. The second structure 80 includes other conductive via structures such as a peripheral circuit contact structure PCT, gate structures GS of a memory cell array, and the like.

[0030] The first structure 70 overlaps a gate region GR and a peripheral circuit contact region PCR of the semiconductor substrate SUB. The gate structures GS of the second structure 80 overlap the gate region GR, and the peripheral circuit contact structures PCT of the second structure 80 overlap the peripheral circuit contact region PCR.

[0031] The gate structures GS include insulating layers IL1, IL2, and IL3 and a conductive layer CDL. Each of the insulating layers IL1, IL2, and IL3 and the conductive layer CDL includes a surface extending in a first direction DR1 and a second direction DR2 different from each other. The insulating layers IL1, IL2, and IL3 and the conductive layer CDL are alternately disposed in a third direction DR3 orthogonal to the surface of each of the insulating layers IL1, IL2, and IL3 and the conductive layer CDL, or in one embodiment, the insulating layers IL1, IL2, and IL3 and the conductive layer CDL are alternately disposed in a stacking direction (i.e., the third direction DR3, etc.) protruding from a surface of a plane formed by the first direction DR1 and the second direction DR2. In one embodiment, the first direction DR1, the second direction DR2, and the third direction DR3 can be an X-axis direction, a Y-axis direction, and a Z-axis direction.

[0032] Each peripheral circuit contact structure PCT includes a first peripheral contact plug PCT1 disposed at the same level as the gate structures GS.

[0033] Figure 2A is a plan view illustrating a layout of the gate structures GS and the first peripheral contact plugs PCT1 of the semiconductor memory device.

[0034] Referring to Figure 2AThe gate structure GS is divided into gate stack structures GST1, GST2, and GST3 by the gate isolation structures GSS. The gate stack structures GST1, GST2, and GST3 are spaced apart from each other in the second direction DR2. Figure 2A A portion of each of the first gate stack structure GST1, the second gate stack structure GST2, and the third gate stack structure GST3 of the gate structure GS is illustrated, and the gate structure GS is mainly illustrated with respect to the second gate stack structure GST2.

[0035] The gate structure GS is penetrated by a plurality of pillar structures PS. The plurality of pillar structures PS is divided into groups corresponding to each of the gate stack structures GST1, GST2, and GST3. In one embodiment, the plurality of pillar structures PS can include first to third groups, a first group among the plurality of pillar structures PS can penetrate the first gate stack structure GST1, a second group among the plurality of pillar structures PS can penetrate the second gate stack structure GST2, and a third group among the plurality of pillar structures PS can penetrate the third gate stack structure GST3.

[0036] The pillar structures PS of each group constitute a plurality of rows and a plurality of columns. Each row is configured with the pillar structures PS arranged in a line in the first direction DR1, and each column is configured with the pillar structures PS arranged in a line in the second direction DR2. Figure 2A A portion of each of the following is illustrated: the first gate stack structure GST1 surrounding one row of pillar structures adjacent to the second gate stack structure GST2, and the third gate stack structure GST3 surrounding another row of pillar structures adjacent to the second gate stack structure GST2. Although not shown in the drawing, each of the first gate stack structure GST1 and the third gate stack structure GST3 can surround a plurality of rows of pillar structures of the group corresponding thereto, similar to the second gate stack structure GST2.

[0037] The pillar structures PS of each group include first pillar structures PS1 adjacent to the gate isolation structures GSS. Each gate isolation structure GSS is disposed between the first pillar structures PS1 of the groups adjacent to each other, and the first pillar structures PS1 of the groups adjacent to each other constitute rows adjacent to each other in the second direction DR2. In one embodiment, the first pillar structures PS1 of the first group penetrating the first gate stack structure GST1 can include first pillar structures PS1 of a first row R1, and the first pillar structures PS1 of the second group penetrating the second gate stack structure GST2 can include first pillar structures PS1 of a second row R2. The first row R1 and the second row R2 are spaced apart from each other with the gate isolation structure GSS between the first gate stack structure GST1 and the second gate stack structure GST2 (the gate isolation structure GSS is interposed therebetween), and the first row R1 and the second row R2 are adjacent to each other in the second direction DR2.

[0038] Each group of pillar structures PS also includes a central pillar structure PS_C. Within the same group, the central pillar structure PS_C is arranged further away from the gate isolation structure GSS compared to the first pillar structure PS1. The width of the gate isolation structure GSS is defined in the second direction DR2. Within the same group, the pillar structures PS are arranged at a distance narrower than the width of the gate isolation structure GSS. Therefore, in one embodiment, the arrangement density of pillar structures PS in each gate stack structure can be increased, and thus the integration level of the semiconductor memory device can be improved.

[0039] As described above, the distance between the first column structure PS1 in the first row R1 and the first column structure PS1 in the second row R2 is limited to being greater than the distance between the central column structures PS_C in each group, and greater than the distance between the first column structure PS1 and the central column structure PS_C in each group.

[0040] Each of the gate stack structures GST1, GST2, and GST3 includes a selection isolation structure SS. The selection isolation structure SS may be formed to be shorter than the gate isolation structure GSS on the third direction DR3 and may be disposed within the corresponding gate stack structure. The selection isolation structure SS and the gate isolation structure GSS extend on the first direction DR1. Through the selection isolation structure SS, some conductive layers in the conductive layers of each gate stack structure can be isolated into source select lines or drain select lines. The selection isolation structure SS may include an insulating material.

[0041] A central column structure PS_C is arranged on both sides of a selective isolation structure SS. In one embodiment, the selective isolation structure SS may overlap with some of the central column structures in the central column structure PS_C. In other words, the central column structure PS_C may include a second column structure PS2 that overlaps with the selective isolation structure SS. The second column structure PS2 is arranged along one and the other sides of the selective isolation structure SS adjacent to each other in a second direction DR2. However, embodiments of this disclosure are not limited thereto. Although not shown in the figures, in one embodiment, the column structure PS may further include dummy column structures that overlap with the selective isolation structure SS, and the central column structure PS_C may be arranged on both sides of the row with the dummy column structures so as not to overlap with the selective isolation structure SS.

[0042] Figure 2B yes Figure 2A The enlarged plan view of area "AR1" shown in the figure.

[0043] refer to Figure 2BEach pillar structure PS includes a channel structure CH and a memory layer ML. The channel structure CH extends in the third direction DR3 to penetrate the gate structure GS. The memory layer ML is interposed between the channel structure CH and the gate structure GS.

[0044] The memory layer ML includes a tunnel insulating layer TI, a data storage layer DS, and a blocking insulating layer BI. The tunnel insulating layer TI extends along the outer wall of the channel structure CH. The tunnel insulating layer T1 includes an insulating material such as a silicon oxide layer. The data storage layer DS is interposed between the gate structure GS and the tunnel insulating layer TI. In one embodiment, the data storage layer DS can continuously extend along the outer wall of the tunnel insulating layer TI. In another embodiment, the data storage layer DS can be isolated into a plurality of data storage patterns spaced apart from each other in the third direction DR3, and each data storage pattern can be disposed between the corresponding conductive layer among the conductive layers CDL shown in Figure 3A or Figure 3B the corresponding conductive layer thereof. The data storage layer DS can be formed of a material layer capable of storing data changed using Fowler-Nordheim tunneling. In one embodiment, the data storage layer DS can be formed of a charge-trapping insulating layer, formed of a floating gate layer, or formed of an insulating layer including conductive nano dots. The charge-trapping insulating layer can include a silicon nitride layer. The blocking insulating layer BI is interposed between the gate structure GS and the data storage layer DS. The blocking insulating layer BI includes at least one of a silicon dioxide layer (SiO2) and a high dielectric layer having a dielectric constant higher than that of the silicon dioxide layer. The high dielectric layer can include an aluminum oxide layer, a hafnium oxide layer, etc.

[0045] Figure 3A is a cross-sectional view of the semiconductor memory device taken along the line I-I' shown in Figure 2A and Figure 3B is a cross-sectional view of the semiconductor memory device taken along the line II-II' shown in Figure 2A .

[0046] Referring to Figure 3A and Figure 3B, the first structure 70 further includes a peripheral circuit side bonding pad PBP bonded to the second structure 80, a peripheral circuit side bonding contact PBC connecting the interconnect structure IC to the peripheral circuit side bonding pad PBP, and a peripheral circuit side insulating structure PIL. The peripheral circuit side insulating structure PIL is disposed over the semiconductor substrate SUB to cover the transistors TR1 and TR2, the interconnect structure IC, the peripheral circuit side bonding pad PBP, and the peripheral circuit side bonding contact PBC. The interconnect structure IC, the peripheral circuit side bonding pad PBP, and the peripheral circuit side bonding contact PBC are used as a conductive via structure.

[0047] Each of the transistors TR1 and TR2 includes a gate insulating layer GI, a gate electrode GE, a first junction JN1, and a second junction JN2. The gate insulating layer GI and the gate electrode GE are stacked over an active region of the semiconductor substrate SUB. The active region of the semiconductor substrate SUB is divided by an isolation structure ISO disposed in the semiconductor substrate SUB. The first junction JN1 and the second junction JN2 are disposed in the active region at both sides of the gate electrode GE and are used as a source region and a drain region. The transistors TR1 and TR2 can include Figure 1 the first transistor TR1 of the source driver 39 illustrated in FIG. 6, and Figure 1 the second transistor TR2 of the page buffer 37 illustrated in FIG. 6.

[0048] The interconnect structure IC is configured with conductive patterns constituting lines and contact plugs. The interconnect structure IC is electrically connected to the peripheral circuit structure. The interconnect structure IC includes a first group of structures connected to the gate electrode GE, the first junction JN1, and the second junction JN2 of the first transistor TR1, respectively, and a second group of structures connected to the gate electrode GE, the first junction JN1, and the second junction JN2 of the second transistor TR2, respectively.

[0049] The peripheral circuit side bonding contact PBC extends from some of the interconnect structures IC in the third direction DR3. The peripheral circuit side bonding contact PBC is connected to some of the first group of structures and the second group of structures among the interconnect structures IC, respectively. In one embodiment, the interconnect structures IC can include a first interconnect structure electrically connected to the second junction JN2 of the first transistor TR1 and a second interconnect structure electrically connected to the second junction JN2 of the second transistor TR2, and the peripheral circuit side bonding contact PBC can include a contact in contact with the first interconnect structure and a contact in contact with the second interconnect structure. The peripheral circuit side bonding contact PBC includes a conductive material such as metal.

[0050] The peripheral circuit side insulating structure PIL includes an insulating layer including at least two layers.

[0051] The peripheral circuit side bonding pads PBP are disposed in the uppermost insulating layer of the peripheral circuit side insulating structure PIL. A top surface of each peripheral circuit side bonding pad PBP can not be covered by the peripheral circuit side insulating structure PIL. The peripheral circuit side bonding pads PBP include a bonding metal such as copper, aluminum, or tungsten. Some of the peripheral circuit side bonding pads PBP can be electrically connected to the peripheral circuit structure via some of the peripheral circuit side bonding contacts PBC and the interconnect structure IC. In one embodiment, the peripheral circuit side bonding pads PBP can include a first bonding pad electrically connected to the second junction JN2 of the first transistor TR1 and a second bonding pad electrically connected to the second junction JN2 of the second transistor TR2. The first bonding pad can be electrically connected to the first transistor TR1 via a first interconnect structure among the interconnect structure IC, through any one of the peripheral circuit side bonding contacts PBC. The second bonding pad can be electrically connected to the second transistor TR2 via a second interconnect structure among the interconnect structure IC, through another one of the peripheral circuit side bonding contacts PBC.

[0052] In addition to the gate structure GS, the gate isolation structure GSS, and the peripheral circuit contact structure PCT described above, the second structure 80 further includes: a pillar structure PS of the memory cell array, a plurality of bit lines BL between the gate structure GS and the first structure 70, a connection line CCL between the peripheral circuit contact structure PCT and the first structure 70, a bit line connection structure BCT electrically connecting the pillar structure PS to the plurality of bit lines BL, a cell side bonding pad CBP bonded to the first structure 70, a cell side bonding contact CBC, a source structure SR over the gate structure GS, and an upper conductive pattern (e.g., CS) over the source structure SR. The peripheral circuit contact structure PCT, the connection line CCL, the cell side bonding pad CBP, and the cell side bonding contact CBC are used as a conductive via structure. In addition to the first peripheral contact plug PCT1 described above, each peripheral circuit contact structure PCT can further include a second peripheral contact plug PCT2 and a third peripheral contact plug PCT3.

[0053] The gate isolation structure GSS extends in the third direction DR3 to penetrate the insulating layers IL1, IL2, and IL3 and the conductive layer CDL of the gate structure GS. Thus, the insulating layers IL1, IL2, and IL3 and the conductive layer CDL are divided to constitute each gate stack structure (e.g., GST1 or GST2).

[0054] The insulating layers IL1, IL2, and IL3 of the gate structure GS include a first insulating layer IL1, a second insulating layer IL2, and a third insulating layer IL3. The first insulating layer IL1 is disposed adjacent to the source structure SR, and the third insulating layer IL3 is spaced apart from the first insulating layer IL1 with the conductive layers CDL interposed therebetween. The second insulating layer IL2 is disposed between the first insulating layer IL1 and the third insulating layer IL3 and is alternately disposed with the conductive layers CDL one after another in the third direction DR3. Thus, the conductive layers CDL adjacent to each other in the third direction DR3 are spaced apart from each other by the second insulating layers IL2 therebetween. However, embodiments of the present disclosure are not limited thereto. In one embodiment, the conductive layers CDL adjacent to each other in the third direction DR3 can be spaced apart from each other by an air gap therebetween.

[0055] At least one of the conductive layers CDL of the gate structure GS can be used as a source select line SSL, at least another one of the conductive layers CDL of the gate structure GS can be used as a drain select line DSL, and the other conductive layers CDL of the gate structure GS can be used as a plurality of word lines WL. Each conductive layer CDL includes various conductive materials such as a doped semiconductor layer and a metal layer. The doped semiconductor layer can include a doped silicon layer. The metal layer can include tungsten, copper, molybdenum, etc. Each conductive layer CDL further includes a metal nitride layer. The metal nitride layer can include titanium nitride, tantalum nitride, molybdenum nitride, etc. The first insulating layer IL1, the second insulating layer IL2, and the third insulating layer IL3 include an insulating material such as a silicon oxide layer (e.g., SiO2) or a silicon oxynitride layer (SiON).

[0056] At least one of the source select line SSL and the drain select line DSL of each gate stack structure (e.g., GST1 or GST2) can be divided into a plurality of segments by a select isolation structure SS as shown in FIG. 1B. Each segment of the source select line SSL and the drain select line DSL is narrower than each word line WL. Each word line WL is not isolated by the select isolation structure SS but can extend to overlap the select isolation structure SS. Figure 2A At least one of the source select line SSL and the drain select line DSL of each gate stack structure (e.g., GST1 or GST2) can be divided into a plurality of segments by a select isolation structure SS as shown in FIG. 1B. Each segment of the source select line SSL and the drain select line DSL is narrower than each word line WL. Each word line WL is not isolated by the select isolation structure SS but can extend to overlap the select isolation structure SS.

[0057] The pillar structure PS extends inside the source structure SR. More specifically, a channel structure CH of the pillar structure PS extends inside the source structure SR while penetrating the gate structure GS. A memory layer ML of the pillar structure PS is interposed between the gate structure GS and the channel structure CH. The channel structure CH is formed to be longer than the memory layer ML in the third direction DR3. The channel structure CH is formed of a semiconductor material to be used as a channel region of a memory cell string, and the semiconductor material includes silicon (Si), germanium (Ge), any mixture thereof, or the like. The channel structure CH has various shapes. In one embodiment, a central region of the channel structure CH can be filled with a core insulating layer CO. Each of end portions of the channel structure CH facing the bit line BL and the source structure SR includes at least one of an n-type impurity and a p-type impurity. In one embodiment, each of the end portions of the channel structure CH can be configured as an n-type doped region including an n-type impurity as a majority carrier.

[0058] Reference Figure 1 The plurality of memory cell strings of the described memory cell array 10 are arranged on the first direction DR1 and the second direction DR2, similar to the arrangement of the pillar structures PS. Each memory cell string includes a plurality of memory cells formed at an intersection of the channel structure CH and the plurality of word lines WL, a source select transistor formed at an intersection of the channel structure CH and the source select line SSL, and a drain select transistor formed at an intersection of the channel structure CH and the drain select line DSL. The source select transistor, the plurality of memory cells, and the drain select transistor are connected in series through the channel structure CH to form a memory cell string. Thus, each of the plurality of memory cell strings includes a plurality of memory cells arranged along the third direction DR3. Because the plurality of memory strings are arranged on the first direction DR1 and the second direction DR2, a three-dimensional memory cell array including memory cells arranged three-dimensionally is provided.

[0059] The second structure 80 includes a fourth insulating layer IL4 disposed at the same level as the gate structure GS. The fourth insulating layer IL4 overlaps the peripheral circuit contact region PCR. The first peripheral contact plug PCT1 of the peripheral circuit contact structure PCT is formed of a conductive material that penetrates the fourth insulating layer IL4.

[0060] The second structure 80 further includes an insulating layer disposed between the fourth insulating layer IL4 and the first structure 70, the insulating layer including at least two layers. In one embodiment, the second structure 80 can further include a fifth insulating layer IL5 to an eighth insulating layer IL8 sequentially disposed between the fourth insulating layer IL4 and the first structure 70.

[0061] Each of the fifth insulating layer IL5 and the sixth insulating layer IL6 extends in the first direction DR1 and the second direction DR2 to overlap the fourth insulating layer IL4 and the gate structure GS. The fifth insulating layer IL5 is penetrated by a plurality of first contact plugs CT1 formed of an electrically conductive material, and the sixth insulating layer IL6 is penetrated by a plurality of second contact plugs CT2 formed of an electrically conductive material.

[0062] Some of the plurality of first contact plugs CT1 and some of the plurality of second contact plugs CT2 can constitute bit line connection structures BCT. Other of the plurality of first contact plugs CT1 and other of the plurality of second contact plugs CT2 can constitute second peripheral contact plugs PCT2. Each bit line connection structure BCT is in contact with a channel structure CH of a pillar structure corresponding thereto. The second peripheral contact plugs PCT2 are in contact with the first peripheral contact plugs PCT1.

[0063] The gate isolation structure GSS extends to penetrate the fifth insulating layer IL5 and the sixth insulating layer IL6. The gate isolation structure GSS includes an insulating layer covering a sidewall of each gate stack structure (e.g., GST1 or GST2). In one embodiment, the gate isolation structure GSS can be configured with a single insulating layer. In another embodiment, the gate isolation structure GSS can include an insulating layer and a core material disposed in a central region of the gate isolation structure GSS that is open through the insulating layer. The core material can include at least one of a semiconductor material and an electrically conductive material. The semiconductor material can include at least one of an undoped semiconductor layer and a doped semiconductor layer. The doped semiconductor layer can include at least one of an n-type impurity and a p-type impurity. The electrically conductive material can include a metal, a metal nitride, etc.

[0064] A seventh insulating layer IL7 is interposed between an eighth insulating layer IL8 and the sixth insulating layer IL6 and extends in the first direction DR1 and the second direction DR2. The seventh insulating layer IL7 is penetrated by connection lines CCL and a plurality of bit lines BL. The connection lines CCL and the plurality of bit lines BL include an electrically conductive material such as a metal. Each connection line CCL can be in contact with a second peripheral contact plug PCT2 corresponding thereto. The plurality of bit lines BL are arranged to be spaced apart from each other in the first direction DR1. Each bit line BL extends in the second direction DR2. The bit lines BL overlap gate stack structures (e.g., GST1 and GST2) adjacent to each other. Pillar structures PS penetrating different gate stack structures are connected in parallel to the same bit line BL.

[0065] Cell-side bonding pads CBP and cell-side bonding contacts CBC are provided in the eighth insulating layer IL8. The cell-side bonding pads CBP are bonded to the peripheral circuit-side bonding pads PBP. Each cell-side bonding pad CBP includes a bonding surface facing a corresponding peripheral circuit-side bonding pad PBP. The bonding surface can not be covered by the eighth insulating layer IL8. The cell-side bonding pads CBP include a bonding metal such as copper, aluminum, or tungsten. Some of the cell-side bonding pads CBP can be electrically connected to the plurality of bit lines BL and the connection line CCL via the cell-side bonding contacts CBC. In one embodiment, the cell-side bonding pads CBP can include first bonding pads connected to the connection line CCL and second bonding pads connected to the plurality of bit lines BL, respectively.

[0066] The source structure SR is configured to include a doped semiconductor structure DPS of a conductivity type dopant. The source structure SR extends in the first direction DR1 and the second direction DR2 to overlap the gate structure GS and the gate isolation structure GSS.

[0067] Figure 3C is Figure 3B An enlarged sectional view of the region "AR2" shown in FIG. 6.

[0068] Referring to Figure 3A , Figure 3B and Figure 3C The source structure SR includes a first semiconductor layer SE1 and a second semiconductor layer SE2 over the first semiconductor layer SE1. The first semiconductor layer SE1 is provided as a first doped region, and the second semiconductor layer SE2 is provided as a second doped region. Each of the first semiconductor layer SE1 and the second semiconductor layer SE2 can include at least one of an n-type impurity and a p-type impurity. The first semiconductor layer SE1 constituting the first doped region includes a conductivity type dopant at a first concentration, and the second semiconductor layer SE2 constituting the second doped region includes a conductivity type dopant at a second concentration different from the first concentration. In one embodiment, the second concentration is higher than the first concentration.

[0069] The majority carriers of the first semiconductor layer SE1 and the majority carriers of the second semiconductor layer SE2 have the same conductivity type impurity. A concentration difference of the conductivity type dopants in the first semiconductor layer SE1 and the second semiconductor layer SE2 is defined as a concentration difference of the majority carriers. In one embodiment, each of the first semiconductor layer SE1 and the second semiconductor layer SE2 can include an n-type impurity as the majority carriers, and the concentration of the majority carriers in the second semiconductor layer SE2 can be higher than the concentration of the majority carriers in the first semiconductor layer SE1.

[0070] Each of the first semiconductor layer SE1 and the second semiconductor layer SE2 extends in the first direction DR1 and the second direction DR2 to overlap the plurality of pillar structures PS including the first pillar structures PS1 and the center pillar structure PS C. The second semiconductor layer SE2 is spaced apart from the plurality of pillar structures PS, the gate structure GS, and the gate isolation structure GSS by the first semiconductor layer SE1. In other words, the first semiconductor layer SE1 is interposed between each of the plurality of pillar structures PS, the gate structure GS, and the gate isolation structure GSS and the second semiconductor layer SE2.

[0071] The first semiconductor layer SE1 is in contact with the channel structure CH. In one embodiment, a concentration of a conductivity type dopant or a concentration of majority carriers is controlled to be lower in the first semiconductor layer SE1 in contact with the channel structure CH than in the second semiconductor layer SE2 spaced apart from the channel structure CH, so that gate-induced drain leakage (GIDL) can be reduced. The conductivity type dopant or the majority carriers is an n-type dopant or a p-type dopant.

[0072] The first semiconductor layer SE1 includes a bottom recessed portion BRP and a top recessed portion TRP. The channel structure CH is inserted into the bottom recessed portion BRP and contacts the first semiconductor layer SE1 along the bottom recessed portion BRP. The top recessed portion TRP is disposed between the first pillar structure PS1 of the first row R1 (i.e., PS1 / R1) and the first pillar structure PS1 of the second row R2 (i.e., PS1 / R2). A width W2 of the top recessed portion TRP is greater than a width W1 of the bottom recessed portion BRP.

[0073] A top recessed portion TRP of the first semiconductor layer SE1 is defined as a first thickness of the first semiconductor layer SE1 in the third direction DR3 varies. Between the first pillar structure PS1 of the first row R1 and the first pillar structure PS1 of the second row R2, the first thickness of the first semiconductor layer SE1 decreases as the first thickness is measured closer to the gate isolation structure GSS. For example, between the first pillar structure PS1 of the first row R1 and the first pillar structure PS1 of the second row R2, the first thickness can be formed to have a value of “TH1A” in a first region of the source structure SR, the first region being adjacent to any of the first pillar structures PS1, and the first thickness can be formed to have a value of “TH1B” in a second region of the source structure SR, the second region being closer to the gate isolation structure GSS than the first region. The value of “TH1B” is less than the value of “TH1A”.

[0074] The first semiconductor layer SE1 can fill the space between the center pillar structures PS C, which are disposed at a distance narrower than the distance between the first pillar structures PS1 of the first row R1 and the first pillar structures PS1 of the second row R2. The first thickness of the first semiconductor layer SE1 can be formed to have a value of "TH1C" on the top of each of the center pillar structures PS C and to have a value of "TH1D" on the top of each of the first pillar structures PS1 of the first row R1 and the first pillar structures PS1 of the second row R2. The value of "TH1C" is greater than the value of "TH1D".

[0075] The second semiconductor layer SE2 is disposed above the first semiconductor SE1 to fill the top recessed portions TRP. The second thickness of the second semiconductor layer SE2 in the third direction DR3 can vary between the first pillar structures PS1 of the first row R1 and the first pillar structures PS1 of the second row R2. The second thickness of the second semiconductor layer SE2 increases when measured closer to the gate isolation structure GSS between the first pillar structures PS1 of the first row R1 and the first pillar structures PS1 of the second row R2. For example, between the first pillar structures PS1 of the first row R1 and the first pillar structures PS1 of the second row R2, the second thickness can be formed to have a value of "TH2A" in a first region of the source structure SR, which is adjacent to any of the first pillar structures PS1, and the second thickness can be formed to have a value of "TH2B" in a second region of the source structure SR, which is closer to the gate isolation structure GSS than the first region. The value of "TH2B" is greater than the value of "TH2A".

[0076] The second thickness of the second semiconductor layer SE2 can be formed to have a value of "TH2C" on the top of each of the center pillar structures PS C and to have a value of "TH2D" on the top of each of the first pillar structures PS1 of the first row R1 and the first pillar structures PS1 of the second row R2. The value of "TH2C" is less than the value of "TH2D".

[0077] Because the second thickness of the second semiconductor layer SE2 varies in a trend opposite to that of the first thickness of the first semiconductor layer SE1, the surface roughness of the first semiconductor layer SE1 caused by the difference in the arrangement density of the pillar structures PS can be compensated by the second semiconductor layer SE2. In one embodiment, the sum of the first thickness of the first semiconductor layer SE1 and the second thickness of the second semiconductor layer SE2 can be constant in the respective regions of the source structure SR.

[0078] The second semiconductor layer SE2 is in contact with the metal-containing structure. The concentration of the conductivity type dopant or the concentration of the majority carriers is controlled to be higher in the second semiconductor layer SE2 than in the first semiconductor layer SE1, so that an ohmic contact can be formed by the contact between the second semiconductor layer SE2 and the metal-containing structure. Thus, in one embodiment, the operational reliability of the semiconductor memory device can be improved.

[0079] In one embodiment, the second semiconductor layer SE2 can be in contact with a source contact plug SCT including a metal. The source contact plug SCT is formed in the upper insulating layer UIL covering the source structure SR. The source contact plug SCT electrically connects the source structure SR and the common source layer CS above the upper insulating layer UIL to each other.

[0080] The first semiconductor layer SE1 includes a top surface TS higher than the bottom of the top recessed portion TRP. The second semiconductor layer SE2 extends to cover the top surface TS of the first semiconductor layer SE1. Thus, the upper insulating layer UIL is spaced apart from the top surface TS of the first semiconductor layer SE1, with the second semiconductor layer SE2 interposed between the upper insulating layer UIL and the top surface TS of the first semiconductor layer SE1.

[0081] The upper insulating layer UIL extends to overlap the peripheral circuit contact region PCR of the semiconductor substrate SUB, and the fourth insulating layer IL4 overlaps the upper insulating layer UIL. A portion region of the upper insulating layer UIL overlapping the peripheral circuit contact region PCR of the semiconductor substrate SUB is penetrated by the third peripheral contact plug PCT3 of the peripheral circuit contact structure PCT. The third peripheral contact plug PCT3 is connected to the first peripheral contact plug PCT1.

[0082] The common source layer CS includes an electrically conductive material such as a metal. The common source layer CS extends to contact the third peripheral contact plug PCT3 of a corresponding one of the peripheral circuit contact structures PCT. Thus, the common source layer CS is electrically connected to the first transistor TR1 via the first to third peripheral contact plugs PCT1 to PCT3 of the peripheral circuit contact structure PCT, the connection line CCL, the cell-side bond contact CBC, the cell-side bond pad CBP, the peripheral circuit-side bond pad PBP, the peripheral circuit-side bond contact PBC, and the interconnection structure IC.

[0083] Figure 4A 、 Figure 4B and Figure 4C is a cross-sectional view illustrating a source structure according to one embodiment of the present disclosure. Hereinafter, the description of portions overlapping those described with reference to Figures 3A-3C will be omitted or simplified.

[0084] Reference Figure 4AThe source structure SR can include a doped semiconductor structure DPS and a metal layer MTL over the doped semiconductor structure DPS. The doped semiconductor structure DPS includes a first semiconductor layer SE1 in contact with the channel structure CH and a second semiconductor layer SE2 over the first semiconductor layer SE1, as described with reference to Figures 3A-3C The metal layer MTL is disposed over and connected to the second semiconductor layer SE2. In one embodiment, the resistivity of the source structure can be reduced by the metal layer MTL, and thus the operational reliability of the semiconductor memory device can be improved.

[0085] The metal layer MTL overlaps a portion region of the second semiconductor layer SE2 disposed between the first pillar structure PS1 of the first row R1 and the first pillar structure PS1 of the second row R2. The first semiconductor layer SE1 includes a top surface TS higher than a bottom of the top recessed portion TRP. The metal layer MTL extends to both sides of the top recessed portion TRP to overlap the top surface TS of the first semiconductor layer SE1.

[0086] Each of the first semiconductor layer SE1 and the second semiconductor layer SE2 is interposed between the gate isolation structure GSS and the metal layer MTL and extends between the gate structure GS and the metal layer MTL. The concentration of the conductivity type dopant or the concentration of the majority carriers is controlled to be higher in the second semiconductor layer SE2 than in the first semiconductor layer SE1, so that an ohmic contact between the metal layer MTL and the second semiconductor layer SE2 can be formed.

[0087] The upper insulating layer UIL is disposed over the metal layer MTL, and the source contact plug SCT is connected to the metal layer MTL.

[0088] Referring to Figure 4B and Figure 4C each source structure SR includes a doped semiconductor structure DPS (i.e., DPS / SR). The doped semiconductor structure DPS includes a first semiconductor layer SE1 in contact with the channel structure CH and a second semiconductor layer SE2 over the first semiconductor layer SE1.

[0089] The first semiconductor layer SE1 overlaps the first pillar structure PS1 of the first row R1 and the first pillar structure PS1 of the second row R2 as described with reference to Figures 3A-3C and extends to overlap the center pillar structure PS_C shown in Figure 2A The first semiconductor layer SE1 includes a top recessed portion TRP defined between the first pillar structure PS1 of the first row R1 and the first pillar structure PS1 of the second row R2, and the first semiconductor layer SE1 extends to overlap the gate structure GS and the gate isolation structure GSS.

[0090] The second semiconductor layer SE2 is formed to fill the top recessed portion TRP of the first semiconductor layer SE1. The second semiconductor layer SE2 does not overlap with the top surface TS of the first semiconductor layer SE1 extending to both sides of the top recessed portion TRP and Figure 2A the center pillar structure PS_C illustrated in Figure 4B . Thus, the top surface TS of the first semiconductor layer SE1 is not covered by the second semiconductor layer SE2 but is open at both sides of the second semiconductor layer SE2. For example, the top surface TS of the first semiconductor layer SE1 is open at both sides of the second semiconductor layer SE2 as illustrated in Figure 4C and , and then overlaps with the upper insulating layer UIL and / or the metal layer MTL.

[0091] Figure 4B Referring to , the top surface TS of the first semiconductor layer SE1 and the second semiconductor layer SE2 are covered by the upper insulating layer UIL. The position of the source contact plug SCT can be controlled not to be in contact with the top surface TS of the first semiconductor layer SE1 but to be in contact with the second semiconductor layer SE2.

[0092] Figure 4C Referring to , the source structure SR further includes a metal layer MTL over the doped semiconductor structure DPS. The metal layer MTL overlaps with the second semiconductor layer SE2 and extends to overlap with the top surface TS of the first semiconductor layer SE1. The upper insulating layer UIL is disposed over the metal layer MTL, and the source contact plug SCT is connected to the metal layer MTL.

[0093] Figure 3C Referring to Figures 4A-4C and , the top recessed portion TRP of the first semiconductor layer SE1 is disposed between the first pillar structure PS1 of the first row R1 and the first pillar structure PS1 of the second row R2. As a result, the thickness of the first semiconductor layer SE1 can be formed to be partially thin between the first pillar structure PS1 of the first row R1 and the first pillar structure PS1 of the second row R2. In accordance with various embodiments of the present disclosure, the reduction in the thickness of the first semiconductor layer SE1 can be compensated for by the second semiconductor layer SE2, and thus the thickness of the doped semiconductor structure DPS between the first pillar structure PS1 of the first row R1 and the first pillar structure PS1 of the second row R2 can be ensured. Thus, in one embodiment, the threshold voltage characteristics of the source select transistors adjacent to the end portions of each of the first pillar structure PS1 of the first row R1 and the first pillar structure PS1 of the second row R2 facing the source structure SR can be stably ensured, and thus the operation reliability of the semiconductor memory device can be improved.

[0094] Figure 5A , Figure 5B , Figure 6A and Figure 6Bis a cross-sectional view illustrating a part of a manufacturing method of a semiconductor memory device according to one embodiment of the present disclosure.

[0095] Figure 7A , Figure 8A , Figure 9A and Figure 10A are cross-sectional views illustrating a manufacturing method of a semiconductor memory device according to one embodiment of the present disclosure, and Figure 7A , Figure 8A , Figure 9A and Figure 10A each illustrate a cross-section of a structure of each unit process taken along a line I-I' shown in Figure 2A .

[0096] Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11 , Figure 12 and Figure 13 are cross-sectional views illustrating a manufacturing method of a semiconductor memory device according to one embodiment of the present disclosure, and Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11 , Figure 12 and Figure 13 each illustrate a cross-section of a structure of each unit process taken along a line II-II' shown in Figure 2A .

[0097] In the following drawings, a first direction DR1, a second direction DR2, and a third direction DR3 indicate directions facing axes that intersect each other. In one embodiment, the first direction DR1, the second direction DR2, and the third direction DR3 can be an X-axis direction, a Y-axis direction, and a Z-axis direction.

[0098] Figure 5A and Figure 5B illustrate the first structure 240 and the preliminary second structure 100, and illustrate a process of aligning the first structure 240 and the preliminary second structure 100.

[0099] Referring to Figure 5A and Figure 5B , as referring to Figure 2A , Figure 3A and Figure 3BAs described, the first structure 240 includes the semiconductor substrate 211, the isolation layer 213, the first transistor 215A and the second transistor 215B of the peripheral circuit structure, the interconnect structure 221, the peripheral circuit side bonding contact 223, the peripheral circuit side bonding pad 225, and the peripheral circuit side insulating structure 217. The preliminary second structure 100 includes the sacrificial substrate 101, the first peripheral contact plug 133, the second peripheral contact plug 150B, the connection line 155CL, the gate structure 110, the plurality of pillar structures 120, the gate isolation structure 147, the plurality of bit line connection structures 150A, the plurality of bit lines 155BL, the cell side bonding contact 163, and the cell side bonding pad 165.

[0100] The gate structure 110 of the preliminary second structure 100 is formed over one surface of the sacrificial substrate 101. As described with reference to Figure 2A , Figure 3A and Figure 3B , the gate structure 110 includes the first insulating layer 111A, the conductive layer 113, the second insulating layer 111B, and the third insulating layer 111C, each of which has a surface extending in the first direction DR1 and the second direction DR2. The conductive layer 113 and the second insulating layer 111B are alternately disposed between the first insulating layer 111A and the third insulating layer 111C in the third direction DR3.

[0101] In addition to the first to third insulating layers 111A, 111B, and 111C of the gate structure 110, the preliminary second structure 100 includes a fourth insulating layer 131, a fifth insulating layer 141, a sixth insulating layer 143, a seventh insulating layer 145, and an eighth insulating layer 161. As described with reference to Figure 3A and Figure 3B , the fourth insulating layer 131 is disposed at the same level as the gate structure 110. The fourth insulating layer 131 is disposed over the one surface of the sacrificial substrate 101. As described with reference to Figure 2A , Figure 3A and Figure 3B , the fourth insulating layer 131 is penetrated by the first peripheral contact plug 133.

[0102] Each of the fifth insulating layer 141, the sixth insulating layer 143, the seventh insulating layer 145, and the eighth insulating layer 161 extends to cover the gate structure 110 and the fourth insulating layer 131. The fifth insulating layer 141 and the sixth insulating layer 143 are interposed between each of the fourth insulating layer 131 and the gate structure 110 and the seventh insulating layer 145. As described with reference to Figure 2A , Figure 3A and Figure 3BAs described, the gate isolation structures 147 penetrate the conductive layer 113 and the first to third insulating layers 111A, 111B, and 111C of the gate structure 110, and penetrate the fifth insulating layer 141 and the sixth insulating layer 143. The gate structure 110 is divided into gate stack structures (e.g., 110A and 110B) by the gate isolation structures 147.

[0103] The plurality of pillar structures 120 includes a center pillar structure 120C, a first row of pillar structures 120R1, and a second row of pillar structures 120R2. The first row of pillar structures 120R1 corresponds to the first pillar structures PS1 of the first row R1 illustrated in Figure 2A , and the second row of pillar structures 120R2 corresponds to the first pillar structures PS1 of the second row R2 illustrated in Figure 2A .

[0104] The plurality of pillar structures 120 penetrates the gate structure 110, and extends to the inside of the sacrificial substrate 101. Each pillar structure 120 includes a memory layer 123, a channel structure 125, and a core insulating layer 127. The memory layer 123 is disposed inside a channel hole. The channel hole penetrates the gate structure 110, and extends to the inside of the sacrificial substrate 101. The memory layer 123 is formed along the surface of the channel hole. The memory layer 123 includes a tunnel insulating layer, a data storage layer, and a blocking insulating layer as described with reference to Figure 2B . The channel structure 125 includes a semiconductor layer formed along the inner wall of the memory layer 123. A central region of the channel hole opened by the semiconductor layer of the channel structure 125 is filled with the core insulating layer 127 and a capping pattern. The capping pattern can constitute an end portion of the channel structure 125 facing the bit line 155BL. The capping pattern can be formed of a doped semiconductor layer.

[0105] Each of the plurality of bit line connection structures 150A and the second peripheral contact plug 150B includes a first contact plug 151 and a second contact plug 153. The first contact plug 151 of each bit line connection structure 150A is connected to the channel structure 125 corresponding thereto, and the first contact plug 151 of the second peripheral contact plug 150B is connected to the first peripheral contact plug 133. As described with reference to Figure 3A and Figure 3B , the first contact plug 151 is formed of a conductive material that penetrates the fifth insulating layer 141, and the second contact plug 153 is formed of a conductive material that penetrates the sixth insulating layer 143.

[0106] Each bit line 155BL is connected to the second contact plug 153 of the bit line connection structure 150A corresponding thereto, and the connection line 155CL is connected to the second contact plug 153 of the second peripheral contact plug 150B. As described with reference to Figure 3A and Figure 3BAs described, each of the plurality of bit lines 155BL and the connection line 155CL is formed of a conductive material that penetrates the seventh insulating layer 145.

[0107] The cell-side bonding contact 163 and the cell-side bonding pad 165 are provided inside the eighth insulating layer 161. As described with reference to Figure 3A and Figure 3B As described, the cell-side bonding contact 163 is connected to the connection line 155CL and the plurality of bit lines 155BL, and the cell-side bonding pad 165 includes a bonding surface exposed to the outside of the eighth insulating layer 161.

[0108] In one embodiment, the manufacturing process of the first structure 240 and the manufacturing process of the preliminary second structure 100 are performed separately. Thus, in one embodiment, damage to the first transistor 215A and the second transistor 215B according to various heat treatment processes performed in the manufacturing process of the preliminary second structure 100 can be prevented or reduced.

[0109] The first structure 240 and the preliminary second structure 100 provided by separate manufacturing processes are aligned with each other in one embodiment, such that the peripheral circuit-side bonding pad 225 and the cell-side bonding pad 165 face each other.

[0110] Subsequently, the peripheral circuit-side bonding pad 225 and the cell-side bonding pad 165 are bonded to each other by a bonding process as shown in Figure 6A and Figure 6B

[0111] With reference to Figure 6A and Figure 6B , the peripheral circuit-side bonding pad 225 and the cell-side bonding pad 165 are bonded to each other by the bonding process.

[0112] After the bonding process, the sacrificial substrate 101 shown in Figure 5A and Figure 5B is removed. The sacrificial substrate 101 can be removed by performing any one of a polishing process, a planarization process, a dry etching process, and a wet etching process, or two or more of the processes. Thus, each of the pillar structures 120 has a portion protruding to the outside of the gate structure 110.

[0113] Subsequently, a portion of the memory layer 123 is removed at the protruding portion of each of the pillar structures 120. Thus, the channel structure 125 of each of the pillar structures 120 is exposed.

[0114] ​After that, at least one of an n-type impurity and a p-type impurity can be implanted into the exposed portion of the channel structure 125. In one embodiment, a p-type impurity for counter-doping and an n-type impurity for a junction can be implanted into the exposed portion of the channel structure 125. The implantation of the impurities can be performed after the portion of the memory layer 123 is removed, or the implantation of the impurities can be performed before the portion of the memory layer 123 is removed.

[0115] Figure 7A Figure 7B Figure 8A Figure 8B is a cross-sectional view illustrating a process of forming a first semiconductor layer.

[0116] Referring to Figure 7A and Figure 7B , a preliminary first semiconductor layer 310A is deposited to cover the exposed surfaces of the channel structure 125. The preliminary first semiconductor layer 310A fills the spaces between the first row of pillar structures 120R1 and the second row of pillar structures 120R2 to arrange the first row of pillar structures 120R1 and the second row of pillar structures 120R2 at a wider distance than the distance between the center pillar structures 120C.

[0117] The preliminary first semiconductor layer 310A includes a conductivity type dopant that is at least one of an n-type impurity and a p-type impurity. In one embodiment, the preliminary first semiconductor layer 310A can include an n-type impurity such as phosphorus (P) as a majority carrier.

[0118] Referring to Figure 8A and Figure 8B , a heat treatment process is performed on the preliminary first semiconductor layer 310A shown in Figure 7A and Figure 7B such that the conductivity type dopant is activated. Accordingly, a first semiconductor layer 310B is formed. The heat treatment process includes a laser annealing process or the like. Due to the influence of the heat treatment process, the surface roughness of the first semiconductor layer 310B increases compared to the surface roughness of the preliminary semiconductor layer 310A shown in Figure 9A and Figure 9B . In addition, a top recessed portion 310TRP is formed at the surface of the first semiconductor layer 310B. The top recessed portion 310TRP is disposed between the first row of pillar structures 120R1 and the second row of pillar structures 120R2 to arrange the first row of pillar structures 120R1 and the second row of pillar structures 120R2 at a wider distance than the distance between the center pillar structures 120C. Accordingly, the thickness of the first semiconductor layer 310B in the third direction DR3 is smaller in the region between the first row of pillar structures 120R1 and the second row of pillar structures 120R2 than in the region between the center pillar structures 120C.

[0119] ​​​Figure 9A and Figure 9B is a cross-sectional view illustrating a process of forming a second semiconductor layer.

[0120] Referring to Figure 10A and Figure 10B , a preliminary second semiconductor layer is deposited to fill the top recessed portion 310TRP of the first semiconductor layer 310B. The preliminary second semiconductor layer is deposited over the first semiconductor layer 310B in a state where a surface of the first semiconductor layer 310B is not planarized.

[0121] The preliminary second semiconductor layer includes a conductivity type dopant that is at least one of an n-type impurity and a p-type impurity. In one embodiment, the preliminary second semiconductor layer can include an n-type impurity as a majority carrier.

[0122] Subsequently, a heat treatment process is performed on the preliminary second semiconductor layer such that the conductivity type dopant in the preliminary second semiconductor layer is activated. The heat treatment process includes a laser annealing process or the like. Thereafter, a surface of the preliminary second semiconductor layer that is heat-treated is planarized, thereby forming a second semiconductor layer 320. In one embodiment, because planarization of the preliminary second semiconductor layer is performed in a state where the pillar structures 120 are protected by the first semiconductor layer 310B, damage to the channel structure 125 of each of the pillar structures 120 by the planarization process can be reduced or prevented.

[0123] The second semiconductor layer 320 remains to fill the top recessed portion 310TRP of the first semiconductor layer 310B. The second semiconductor layer 320 covers the first semiconductor layer 310B and overlaps the center pillar structure 120C, the first row of pillar structures 120R1, and the second row of pillar structures 120R2. The concentration of the conductivity type dopant or the majority carrier is higher in the second semiconductor layer 320 than in the first semiconductor layer 310B.

[0124] Figure 11 and Figure 12 is a cross-sectional view illustrating a process of forming a source structure in accordance with one embodiment of the present disclosure.

[0125] Referring to Figure 13 and Figure 14 , portions of each of the first semiconductor layer and the second semiconductor layer that overlap the first peripheral contact plug 133 and the fourth insulating layer 131 are removed. The remaining first semiconductor layer and the remaining second semiconductor layer constitute a doped semiconductor structure. The first semiconductor layer constituting a first doped region of the doped semiconductor structure is denoted by “310S”, and the second semiconductor layer constituting a second doped region of the doped semiconductor structure is denoted by “320S”. The first semiconductor layer 310S and the second semiconductor layer 320S constitute a source structure 300A.

[0126] Figure 14 is a cross-sectional view illustrating a process of forming a source structure according to one embodiment of the present disclosure.

[0127] Referring to ​ , in ​ and ​ , a metal layer is formed over the second semiconductor layer 320. Subsequently, portions of each of the first semiconductor layer, the second semiconductor layer, and the metal layer that overlap with ​ and ​ are removed. The remaining first semiconductor layer, the remaining second semiconductor layer, and the remaining metal layer constitute the source structure 300B. The first semiconductor layer remaining to constitute the first doped region of the source structure 300B is denoted by “310S”, the second semiconductor layer remaining to constitute the second doped region of the source structure 300B is denoted by “320S”, and the metal layer remaining to constitute the source structure 300B is denoted by “330S”.

[0128] ​ is a cross-sectional view illustrating a process of forming a source structure according to one embodiment of the present disclosure.

[0129] Referring to ​ , in ​ and ​ , the second semiconductor layer 320 is planarized such that the top surface 310TS of the first semiconductor layer is exposed. Subsequently, portions of each of the first semiconductor layer and the second semiconductor layer that overlap with ​ and ​ are removed. The remaining first semiconductor layer and the remaining second semiconductor layer constitute the source structure 300C. The first semiconductor layer remaining to constitute the first doped region of the source structure 300C is denoted by “310S”, and the second semiconductor layer remaining to constitute the second doped region of the source structure 300C is denoted by “320S”.

[0130] ​ is a cross-sectional view illustrating a process of forming a source structure according to one embodiment of the present disclosure.

[0131] Referring to ​ , in ​ and ​ , the second semiconductor layer 320 is planarized such that the top surface 310TS of the first semiconductor layer is exposed or open at both sides of the second doped region 320S. Subsequently, a metal layer is formed over the planarized second semiconductor layer. Thereafter, portions of each of the first semiconductor layer, the second semiconductor layer, and the metal layer that overlap with ​ and ​The portion where the first peripheral contact plug 133 and the fourth insulating layer 131 overlap is shown. The retained first semiconductor layer, the retained second semiconductor layer, and the retained metal layer constitute the source structure 300D. The first semiconductor layer retained to constitute the first doped region of the source structure 300D is indicated by "310S", the second semiconductor layer retained to constitute the second doped region of the source structure 300D is indicated by "320S", and the metal layer retained to constitute the source structure 300D is indicated by "330S".

[0132] In formation ​ and ​ The source structure 300A shown in the figure ​ The source structure 300B shown in the figure ​ The source structure 300C or shown in the figure ​ After the source structure 300D shown, subsequent processes can be performed, such as forming an upper insulating layer, forming source contact plugs and third peripheral contact plugs, and forming an upper conductive pattern such as a common source layer.

[0133] ​ This is a block diagram illustrating an electronic system according to an embodiment of the present disclosure.

[0134] refer to ​ The electronic system 1000 can be a computing system, medical device, communication device, wearable device, memory system, etc. The electronic system 1000 may include a host 1100 and a storage device 1200.

[0135] Host 1100 can store data in storage device 1200 or retrieve data stored in storage device 1200 based on an interface. This interface may include at least one of the following: Double Data Rate (DDR) interface, Universal Serial Bus (USB) interface, Multimedia Card (MMC) interface, Embedded MMC (eMMC) interface, Peripheral Component Interconnect (PCI) interface, PCI Express (PCI-E) interface, Advanced Technology Attachment (ATA) interface, Serial ATA (SATA) interface, Parallel ATA (PATA) interface, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE) interface, FireWire interface, Universal Flash Storage (UFS) interface, and Non-Volatile Memory Express (NVMe) interface.

[0136] Storage device 1200 may include memory controller 1210 and semiconductor memory device 1220. In one embodiment, storage device 1200 may be a storage medium such as a solid-state drive (SSD) or a universal serial bus (USB) memory.

[0137] Under the control of the host 1100, the memory controller 1210 can store data in the semiconductor memory device 1220 or read data stored in the semiconductor memory device 1220.

[0138] The semiconductor memory device 1220 can include one memory chip or a plurality of memory chips. The semiconductor memory device 1220 can store data or output the stored data under the control of the memory controller 1210.

[0139] The semiconductor memory device 1220 can be a non-volatile memory device. The semiconductor memory device 1220 can include a first row of pillar structures and a second row of pillar structures, which penetrate a gate structure, extend to the inside of a source structure, and are adjacent to each other. The source structure can include a first semiconductor layer and a second semiconductor layer stacked between the first row of pillar structures and the second row of pillar structures, or the source structure can include a first doped region and a second doped region having different concentrations of conductive type dopants between the first row of pillar structures and the second row of pillar structures.

[0140] According to various embodiments of the disclosure, it is possible to secure the thickness of the semiconductor layer or the doped region of the source structure between the first row of pillar structures and the second row of pillar structures adjacent to each other. Accordingly, in one embodiment, it is possible to improve the operation reliability of the semiconductor memory device.

[0141] Although detailed embodiments of the disclosure are disclosed in the disclosure, those skilled in the art will understand that various modifications, additions and substitutions related to the embodiments are possible without departing from the scope and technical idea of the disclosure. Therefore, the scope of the disclosure should not be limited to the foregoing embodiments. All changes within the equivalent meaning and range of the claims are included within the scope thereof.

Claims

1. A semiconductor memory device, comprising: a gate structure including a surface extending in a first direction and a second direction, the first direction being different from the second direction, the gate structure including insulating layers and conductive layers, the insulating layers and the conductive layers being alternately disposed in a stacking direction protruding from the surface; a source structure overlapping the gate structure; and a plurality of pillar structures penetrating the insulating layers and the conductive layers, the plurality of pillar structures extending to an inside of the source structure, wherein each pillar structure of the plurality of pillar structures includes: a channel structure penetrating the insulating layers and the conductive layers, the channel structure extending to the inside of the source structure; and a memory layer between the channel structure and the gate structure, and wherein the source structure includes: a first semiconductor layer including a bottom recessed portion into which the channel structure is inserted and a top recessed portion disposed between first and second rows of pillar structures adjacent to each other among the plurality of pillar structures; and a second semiconductor layer disposed above the first semiconductor layer to fill the top recessed portion.

2. The semiconductor memory device of claim 1, further comprising a gate isolation structure disposed between the first and second rows of the pillar structures, the gate isolation structure penetrating the insulating layers and the conductive layers, wherein the top recessed portion of the first semiconductor layer overlaps the gate isolation structure.

3. The semiconductor memory device of claim 2, wherein the plurality of pillar structures further include center pillar structures arranged at a distance spaced apart from the gate isolation structure greater than a distance the first and second rows of the pillar structures are spaced apart from the gate isolation structure, and wherein a distance between the first and second rows of the pillar structures is greater than a distance between the center pillar structures.

4. The semiconductor memory device of claim 1, wherein a width of the top recessed portion is wider than a width of the bottom recessed portion.

5. The semiconductor memory device of claim 1, wherein the first semiconductor layer includes a top surface higher than a bottom of the top recessed portion, and wherein the second semiconductor layer extends to cover the top surface of the first semiconductor layer.

6. The semiconductor memory device of claim 5, wherein the source structure further includes a metal layer above the second semiconductor layer, and wherein each of the first and second semiconductor layers extends between the gate structure and the metal layer.

7. The semiconductor memory device of claim 1, wherein the first semiconductor layer includes a top surface higher than a bottom of the top recessed portion, and wherein the second semiconductor layer does not overlap the top surface of the first semiconductor layer.

8. The semiconductor memory device of claim 7, wherein the source structure further includes a metal layer above the second semiconductor layer, and wherein each of the first and second semiconductor layers extends between the gate structure and the metal layer. wherein the metal layer extends to overlap the top surface of the first semiconductor layer.

9. The semiconductor memory device of claim 1, wherein each of the first semiconductor layer and the second semiconductor layer comprises a conductivity type dopant, wherein a concentration of the conductivity type dopant is higher in the second semiconductor layer than in the first semiconductor layer, wherein the conductivity type dopant is an n-type dopant or a p-type dopant.

10. A semiconductor memory device, comprising: a gate structure comprising a surface extending in a first direction and a second direction, the first direction being different from the second direction, the gate structure comprising insulating layers and conductive layers, the insulating layers and the conductive layers being alternately disposed in a stacking direction protruding from the surface; a doped semiconductor structure overlapping the gate structure, the doped semiconductor structure comprising a conductivity type dopant; and a plurality of pillar structures penetrating the insulating layers and the conductive layers, the plurality of pillar structures extending to an interior of the doped semiconductor structure, wherein each pillar structure of the plurality of pillar structures comprises: a channel structure penetrating the insulating layers and the conductive layers, the channel structure extending to the interior of the doped semiconductor structure; and a memory layer between the channel structure and the gate structure, wherein the doped semiconductor structure comprises: a first doped region in contact with the channel structure, the first doped region comprising the conductivity type dopant at a first concentration; and a second doped region disposed above the first doped region, the second doped region comprising the conductivity type dopant at a second concentration different from the first concentration, and wherein a first thickness of the first doped region in the stacking direction and a second thickness of the second doped region in the stacking direction vary between a first row of pillar structures and a second row of pillar structures adjacent to each other among the plurality of pillar structures.

11. The semiconductor memory device of claim 10, wherein the second concentration is higher than the first concentration.

12. The semiconductor memory device of claim 10, wherein a sum of the first thickness and the second thickness is substantially constant between the first row of the pillar structures and the second row of the pillar structures.

13. The semiconductor memory device of claim 10, further comprising a gate isolation structure disposed between the first row of the pillar structures and the second row of the pillar structures, the gate isolation structure penetrating the insulating layers and the conductive layers. wherein the first thickness decreases as the first thickness is measured closer to the gate isolation structure, and the second thickness increases as the second thickness is measured closer to the gate isolation structure.

14. The semiconductor memory device of claim 13, wherein the plurality of pillar structures further comprises a center pillar structure arranged to be spaced apart from the gate isolation structure by a distance greater than a distance by which the first row of the pillar structures and the second row of the pillar structures are spaced apart from the gate isolation structure, and wherein a distance between the pillar structures of the first row and the pillar structures of the second row is greater than a distance between the center pillar structures.

15. The semiconductor memory device of claim 14, wherein the first doped region extends to overlap with the center pillar structures, and wherein the first thickness of the first doped region is greater on a top of each of the center pillar structures than on a top of each of the pillar structures of the first row and the second row.

16. The semiconductor memory device of claim 14, wherein the second doped region extends to overlap with the center pillar structures, and wherein the second thickness of the second doped region is less on a top of each of the center pillar structures than on a top of each of the pillar structures of the first row and the second row.

17. The semiconductor memory device of claim 14, wherein the second doped region does not overlap with the center pillar structures.

18. The semiconductor memory device of claim 10, further comprising a metal layer connected to the second doped region, wherein each of the first doped region and the second doped region extends between the gate structure and the metal layer.

19. The semiconductor memory device of claim 10, further comprising a metal layer connected to the second doped region, wherein the first doped region includes a top surface that is open at both sides of the second doped region, and wherein the metal layer extends to overlap with the top surface of the first doped region.

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