Semiconductor device and method of manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a method of manufacturing the same. A semiconductor device may include: an insulating layer; a support pattern in the insulating layer; first conductive lines each extending in a first direction and including a protruding portion protruding toward the support pattern, each protruding portion having a lower surface; second conductive lines each extending in a second direction crossing the first direction; and a memory cell at an intersection region of the first conductive line and the second conductive line.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0060024, filed on May 7, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to an electronic device and a method of manufacturing the electronic device, and more specifically, to a semiconductor device and a method of manufacturing the semiconductor device. Background Technology

[0004] The integration density of semiconductor devices is primarily determined by the area occupied by a single memory cell. Recently, as the integration density of semiconductor devices where memory cells are formed as a single layer on a substrate has reached its limit, three-dimensional semiconductor devices that stack memory cells on a substrate have been proposed. Furthermore, various structures and manufacturing methods are being developed to improve the operational reliability of semiconductor devices. Summary of the Invention

[0005] According to one embodiment of the present disclosure, a semiconductor device may include: an insulating layer; a support pattern located in the insulating layer; first conductors, each extending along a first direction, wherein the lower surface of each first conductor includes a protrusion projecting toward the support pattern; second conductors, each extending along a second direction intersecting the first direction; and a memory cell located at the intersection region of the first and second conductors.

[0006] According to an embodiment of this disclosure, a method of manufacturing a semiconductor device may include: forming a first conductive layer, wherein the upper surface of the first conductive layer includes recesses arranged in a first direction and a second direction intersecting the first direction; forming a variable resistance layer on the first conductive layer, the variable resistance layer including protrusions projecting toward the recesses of the first conductive layer; forming variable resistance lines by etching the variable resistance layer, the variable resistance lines including protrusions and all extending along the first direction; forming first conductive lines by etching the first conductive layer, the first conductive lines including recesses and all extending along the first direction; forming second conductive lines on the variable resistance lines all extending along the second direction; and forming a variable resistance pattern by etching the variable resistance lines, the variable resistance pattern being located at the intersection region of the first conductive lines and the second conductive lines and including protrusions.

[0007] According to an embodiment of the disclosure, a method of manufacturing a semiconductor device can include forming an insulating layer; forming support patterns in the insulating layer, an upper surface of each support pattern having a level lower than a level of an upper surface of the insulating layer; forming a first conductive layer on the insulating layer and the support patterns, the first conductive layer including protrusions protruding toward the support patterns; and forming a variable resistance layer over the first conductive layer, the variable resistance layer including protrusions at positions corresponding to the protrusions of the first conductive layer. BRIEF DESCRIPTION OF DRAWINGS

[0008] FIG. 1A 、 FIG. 1B and FIG. 1C are diagrams illustrating a semiconductor device according to an embodiment of the disclosure.

[0009] FIG. 2A 、 FIG. 2B 、 FIG. 3A 、 FIG. 3B 、 FIG. 4A 、 FIG. 4B 、 FIG. 5A 、 FIG. 5B 、 FIG. 6A 、 FIG. 6B 、 FIG. 7A 、 FIG. 7B 、 FIG. 8A 、 FIG. 8B and FIG. 8C are diagrams illustrating a method of manufacturing a semiconductor device according to an embodiment of the disclosure. DETAILED DESCRIPTION

[0010] Embodiments of the disclosure relate to a semiconductor device having a stable structure and improved characteristics and a method of manufacturing a semiconductor device.

[0011] According to an embodiment of the disclosure, a semiconductor device having a stable structure and improved reliability can be provided.

[0012] Hereinafter, some embodiments of the disclosure are described with reference to the accompanying drawings. As used herein, including in the claims, "or" as used in a list of items (for example, a list of items prefaced by a phrase such as "at least one of" or "one or more of") indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C).

[0013] FIGS. 1A-1C are diagrams illustrating a semiconductor device according to an embodiment of the disclosure. FIG. 1A may be a plan view, FIG. 1B is a cross-sectional view taken along line A-A' of FIG. 1A , and FIG. 1C is a cross-sectional view taken along line B-B' of FIG. 1Aa cross-sectional view taken along the B-B' line of FIG. 1.

[0014] Referring to FIGS. 1A-1C The semiconductor device can include at least one of the insulating layer 110, the support pattern 130, the first conductive line 140, the memory cell 150, or the second conductive line 180. The semiconductor device can further include at least one of the first contact via 120, the first gap fill pattern 160, the second contact via 170, or the second gap fill pattern 190.

[0015] The support pattern 130 can be located in the insulating layer 110. The support pattern 130 can be arranged at a position corresponding to the memory cell 150. For example, the support pattern 130 can be disposed to overlap the memory cell 150, respectively, when viewed in a plan view. For example, the support pattern 130 can be arranged in a first direction I and a second direction II crossing the first direction I. A horizontal height of an upper surface of the support pattern 130 can be lower than a horizontal height of an upper surface of the insulating layer 110. For example, the upper surface of each support pattern 130 can include a recess, and a horizontal height of a lower surface of the recess can be lower than the horizontal height of the upper surface of the insulating layer 110. In particular, the recess of each support pattern 130 can be entirely lower than the upper surface of the insulating layer 110 except at a boundary where the support pattern 130 is adjacent to the upper surface of the insulating layer 110. As another example, the upper surface of each support pattern 130 can be substantially flat, and a horizontal height of the flat upper surface can be lower than the horizontal height of the upper surface of the insulating layer 110. Accordingly, a step can occur between each support pattern 130 and the insulating layer 110.

[0016] Since the step occurs between the support pattern 130 and the insulating layer 110, a thickness of the variable resistance layer can be adjusted in a process of manufacturing the semiconductor device. For example, a thickness of a portion of the variable resistance layer to be etched can be adjusted to be relatively thinner than a thickness of a remaining portion. In this case, damage to the variable resistance pattern 153 can be prevented or significantly reduced in the process of manufacturing the semiconductor device. In particular, the variable resistance layer can include a first portion on an upper surface of the support pattern 130 and a second portion between adjacent support patterns 130 on an upper surface of the insulating layer 110. Since the horizontal height of the upper surface of the recess of the support pattern 130 is lower than the horizontal height of the upper surface of the insulating layer 110, a first thickness of the first portion of the variable resistance layer can be greater than a second thickness of the second portion of the variable resistance layer. Accordingly, when the second portion of the variable resistance layer having the second thickness is etched to leave the first portion of the variable resistance layer as the variable resistance pattern 153, damage to the variable resistance pattern 153 can be prevented or significantly reduced compared to when the variable resistance layer has a substantially uniform thickness greater than the second thickness.

[0017] The support pattern 130 can include the same material as that of the insulating layer 110, or can include a different material from that of the insulating layer 110. For example, the support pattern 130 and the insulating layer 110 can include an oxide. The support pattern 130 can include a material having an etching rate higher than that of the insulating layer 110. For example, the support pattern 130 can include at least one of borophosphosilicate glass (BPSG), undoped silicate glass (USG), or high aspect ratio process (HARP) oxide. Here, the insulating layer 110 can include tetraethoxysilane (TEOS).

[0018] The first conductive lines 140 can be located on the insulating layer 110 and the support pattern 130. The first conductive lines 140 can each extend in the first direction I. The first conductive lines 140 can be spaced apart from each other in the second direction II. The first conductive lines 140 can include protrusions 140P and recesses 140C. The protrusions 140P can protrude toward the support pattern 130. For example, the protrusions 140P can protrude toward the support pattern 130 to fill a space (e.g., a step) associated with a horizontal difference between the support pattern 130 and the insulating layer 110. Such a lower surface of each protrusion 140P can include a curved surface or can be substantially flat. The recesses 140C can be respectively positioned to correspond to the protrusions 140P. In particular, the recesses 140C can be respectively positioned to overlap the protrusions 140P when viewed in a plan view. For example, the recesses 140C can include an upper surface (e.g., a curved surface) or can be substantially flat. The first conductive lines 140 can be word lines or bit lines. The first conductive lines 140 can include a conductive material such as tungsten.

[0019] The second conductive lines 180 can cross the first conductive lines 140 and can be located on the first conductive lines 140. The second conductive lines 180 can each extend in the second direction II. The second conductive lines 180 can be spaced apart from each other in the first direction I. Upper and lower surfaces of the second conductive lines 180 can be substantially flat. The second conductive lines 180 can be bit lines or word lines. The second conductive lines 180 can include a conductive material such as tungsten.

[0020] The memory cells 150 can be located between the first conductive lines 140 and the second conductive lines 180. For example, the memory cells 150 can be located in an intersection region of the first conductive lines 140 and the second conductive lines 180. The memory cells 150 can be arranged in the first direction I and the second direction II. The memory cells 150 can include at least one of a first electrode pattern 151, a variable resistance pattern 153, or a second electrode pattern 155. Here, the second electrode pattern 155 can be located on the first electrode pattern 151, and the variable resistance pattern 153 can be located between the first electrode pattern 151 and the second electrode pattern 155.

[0021] The storage unit 150 can fill the space defined by the recess 140C of the first wire 140. For example, the first electrode pattern 151 can fill the space defined by the recess 140C of the first wire 140. In some examples, the lower portion of the variable resistance pattern 153 and / or the first electrode pattern 151 can fill the space defined by the recess 140C of the first wire 140. The upper surface and the lower surface of the first electrode pattern 151 can each be a curved surface. For example, the upper surface of the first electrode pattern 151 can include a recess having a curved upper surface, and the lower surface can include a protrusion having a curved lower surface. The protrusion of the lower surface of the first electrode pattern 151 can fill the space defined by the recess 140C of the first wire 140. The upper surface of the variable resistance pattern 153 can be substantially flat, and the lower surface of the variable resistance pattern 153 can be a curved surface. For example, the lower surface of the variable resistance pattern 153 can include a protrusion. The protrusion of the lower surface of the variable resistance pattern 153 can fill the space defined by the recess of the upper surface of the first electrode pattern 151. The upper surface and the lower surface of the second electrode pattern 155 can be substantially flat.

[0022] Due to the space (e.g., a step) associated with the horizontal difference between each support pattern 130 and the insulating layer 110, the upper surface and the lower surface of the first wire 140, the upper surface and the lower surface of the first electrode pattern 151, and the lower surface of the variable resistance pattern 153 can each be a curved surface. Further, by performing a planarization process in a process of manufacturing a semiconductor device, the upper surface of the variable resistance pattern 153, the upper surface and the lower surface of the second electrode pattern 155, and the upper surface and the lower surface of the second wire 180 can each be substantially flat. However, various embodiments of the present disclosure are not limited thereto, and when the variable resistance layer is formed to be sufficiently thick in the process of manufacturing a semiconductor device, the upper surface of the variable resistance pattern 153 can be substantially flat, and thus a separate planarization process can not be performed.

[0023] The first electrode pattern 151 can be a part of the first conductive line 140 or can be electrically connected to the first conductive line 140. The second electrode pattern 155 can be a part of the second conductive line 180 or can be electrically connected to the second conductive line 180. The first electrode pattern 151, or the second electrode pattern 155, or both, can include a conductive material such as polysilicon or metal. For example, the first electrode pattern 151, or the second electrode pattern 155, or both, can include polysilicon, tungsten (W), tungsten nitride (WNx), tungsten silicide (WSix), titanium (Ti), titanium nitride (TiNx), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), carbon (C), silicon carbide (SiC), silicon carbon nitride (SiCN), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), palladium (Pd), platinum (Pt), molybdenum (Mo), ruthenium (Ru), etc., and can include combinations thereof.

[0024] The variable resistance pattern 153 can remain in an amorphous state during a programming operation, and can not change to a crystalline state after the programming operation. In other words, the phase state of the variable resistance pattern 153 can not change after the programming operation. The variable resistance pattern 153 can function as both a memory element and a selection element. The variable resistance pattern 153 can include a resistive material, and can have a characteristic of reversibly changing between different resistance states according to an applied voltage or current. For example, the variable resistance pattern 153 can include a variable resistance material whose resistance changes without a phase state change, and can include a chalcogen element. The variable resistance pattern 153 can include germanium (Ge), antimony (Sb), arsenic (As), silicon (Si), indium (In), tin (Sn), gallium (Ga), etc., and can include combinations thereof.

[0025] The variable resistance pattern 153 can include a phase change material, and can include a chalcogenide. The variable resistance pattern 153 can include a chalcogenide glass, a chalcogenide alloy, etc. The variable resistance pattern 153 can change a phase state according to a programming operation. For example, the variable resistance pattern 153 can have a crystalline state with a low resistance by a set operation. Also, the variable resistance pattern 153 can have an amorphous state with a high resistance by a reset operation. Accordingly, data can be stored in the memory cell 150 by using a resistance difference according to the phase state of the variable resistance pattern 153.

[0026] The variable resistance pattern 153 can include a transition metal oxide, or can include a metal oxide such as a perovskite-based material. Accordingly, data can be stored in the memory cell as an electrical path is generated or disappears in the variable resistance pattern 153.

[0027] The variable resistance pattern 153 can have an MTJ structure, and can include a magnetization pinned layer, a magnetization free layer, and a tunnel barrier layer disposed between the magnetization pinned layer and the magnetization free layer. For example, the magnetization pinned layer and the magnetization free layer can include a magnetic material, and the tunnel barrier layer can include an oxide such as magnesium (Mg), aluminum (Al), zinc (Zn), and titanium (Ti). Here, the magnetization direction of the magnetization free layer can be changed by a spin torque of electrons in an applied current. Accordingly, data can be stored in the memory cell 150 according to a change in the magnetization direction of the magnetization free layer with respect to the magnetization direction of the magnetization pinned layer.

[0028] In addition, the variable resistance pattern 153 can have a metal-insulator-metal (MIM) structure including a metal oxide. In this case, data can be stored in the memory cell 150 using a resistance change of the metal oxide that occurs when a short electrical pulse is applied.

[0029] The memory cell 150 can further include at least one of a switching pattern (not shown) or a third electrode pattern (not shown). For example, the switching pattern can be located on the first electrode pattern 151, and the third electrode pattern can be located between the switching pattern and the variable resistance pattern 153. However, embodiments of the present disclosure are not limited thereto, and the positions of the variable resistance pattern 153 and the switching pattern can be changed with respect to each other.

[0030] The first electrode pattern 151, the switching pattern, and the third electrode pattern can constitute a selection element. In addition, the third electrode pattern, the variable resistance pattern 153, and the second electrode pattern 155 can constitute a memory element. In this case, the memory element and the selection element can share the third electrode pattern. The selection element can be a diode, a PNP diode, a transistor, a vertical transistor, a bipolar junction transistor (BJT), a metal insulator transition (MIT) element, a mixed ionic electronic conductor (MIEC) element, an ovonic threshold switch (OTS) element, or the like. For example, the switching pattern, or the variable resistance pattern 153, or both, can include a chalcogenide material. The first electrode pattern 151 can be a lower electrode, the third electrode pattern can be an intermediate electrode, and the second electrode pattern 155 can be an upper electrode.

[0031] The first gap fill pattern 160, or the second gap fill pattern 190, or both, can be located on the insulating layer 110. The first gap fill pattern 160, or the second gap fill pattern 190, or both, can be located between the memory cells 150. For example, the first gap fill pattern 160 can be located between adjacent memory cells 150 in the second direction II, and the second gap fill pattern 190 can be located between adjacent memory cells 150 in the first direction I. The first gap fill pattern 160, or the second gap fill pattern 190, or both, can include an insulating material such as an oxide.

[0032] The first contact via 120 may be located within the insulating layer 110. For example, the first contact via 120 may extend through the insulating layer 110. The first contact via 120 may be connected to the first wire 140. The horizontal level of the upper surface of the first contact via 120 may be substantially the same as the horizontal level of the upper surface of the insulating layer 110. However, embodiments of this disclosure are not limited thereto, and the horizontal level of the upper surface of the first contact via 120 may be lower than the horizontal level of the upper surface of the insulating layer 110. For example, the upper surface of the first contact via 120 may include a recess, and the horizontal level of the lower surface of the recess may be lower than the horizontal level of the upper surface of the insulating layer 110. As another example, the upper surface of the first contact via 120 may be substantially flat, and the horizontal level of the flat upper surface of the first contact via 120 may be lower than the horizontal level of the upper surface of the insulating layer 110. Each first contact via 120 may include a conductive material such as tungsten.

[0033] The second contact via 170 can pass through the insulating layer 110. Each second contact via 170 may include a first portion 170A and a second portion 170B located on the first portion 170A. The first portion 170A can pass through the insulating layer 110, while the second portion 170B can pass through the first gap fill pattern 160. The second contact via 170 can be connected to a second conductor 180. The horizontal height of the upper surface of the first portion 170A of the second contact via 170 may be substantially the same as the horizontal height of the upper surface of the insulating layer 110. However, embodiments of this disclosure are not limited thereto, and the horizontal height of the upper surface of the first portion 170A may be lower than the horizontal height of the upper surface of the insulating layer 110. This is because the first portion 170A may be formed during the process of manufacturing a semiconductor device when forming the first contact via 120. The second contact via 170 may include a conductive material such as tungsten.

[0034] According to the above structure, the horizontal height of the upper surface of the support pattern 130 can be lower than the horizontal height of the upper surface of the insulating layer 110. In this case, a space (e.g., a step) associated with this height difference can appear between each support pattern 130 and the insulating layer 110. Therefore, damage to the variable resistor pattern 153 to be formed at the position corresponding to the support pattern 130 can be reduced during the process of manufacturing the semiconductor device.

[0035] FIGS. 2A-8C This is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 2A , FIG. 3A , FIG. 4A , FIG. 5A , FIG. 6A , FIG. 7A and FIG. 8A It can be a floor plan. FIG. 2B, FIG. 3B , FIG. 4B , FIG. 5B , FIG. 6B and FIG. 8B are cross-sectional views taken along lines C-C' of FIG. 2A , FIG. 3A , FIG. 4A , FIG. 5A , FIG. 6A and FIG. 8A . In the following, descriptions overlapping with the above-described descriptions can be omitted for the sake of brevity. FIG. 7B FIG. 8C Referring to FIG. 7A and FIG. 8A , the insulating layer 210 can be formed. Here, the insulating layer 210 can include an oxide. For example, the insulating layer 210 can include TEOS.

[0036] Subsequently, first contact vias 220 can be formed in the insulating layer 210. The first contact vias 220 can be formed in regions where first wires (not shown) or second wires (not shown) will be formed. Here, the first contact vias 220 formed in regions where the second wires will be formed can each be used as a part of a second contact via (not shown) (e.g., a first portion 170A in FIG. 2A FIG. 2B The first contact vias 220 can include a conductive material such as tungsten.

[0037] Referring to FIG. 1C and , trenches T can be formed in the insulating layer 210. The trenches T can be formed in the insulating layer 210 to be arranged in a first direction I and a second direction II crossing the first direction I.

[0038] FIG. 3A Subsequently, a support layer 230A can be formed to fill the trenches T. For the sake of clarity in showing structures below the support layer 230A, FIG. 3B the support layer 230A is not shown in Here, the support layer 230A can include a material substantially the same as that of the insulating layer 210 or can include a material different from that of the insulating layer 210. For example, the support layer 230A can include an oxide. The support layer 230A can include a material having an etching rate different from that of the insulating layer 210. For example, the support layer 230A can include a material having a higher etching rate than that of the insulating layer 210. The support layer 230A can include borophosphosilicate glass (BPSG), undoped silicate glass (USG), or high aspect ratio process (HARP) oxide.

[0039] FIG. 3B Subsequently, a support layer 230A can be formed to fill the trenches T. For the sake of clarity in showing structures below the support layer 230A, FIG. 3A the support layer 230A is not shown in ​​

[0040] Referring to FIG. 4A and FIG. 4B The support pattern 230 can be formed. For example, the support pattern 230 can be formed by planarizing the support layer 230A such that the upper surface of the insulating layer 210 is exposed. Here, since the support layer 230A includes a material having a higher etching rate than the insulating layer 210, the support layer 230A can be etched more than the insulating layer 210 in a process of planarizing the support layer 230A, and a recess can occur at the upper surface of the support pattern 230. In this case, the horizontal height of the upper surface of the support pattern 230 can be lower than the horizontal height of the upper surface of the insulating layer 210. Thus, a space (e.g., a step) can be formed due to the difference in the horizontal height between the support pattern 230 and the insulating layer 210.

[0041] In FIG. 4A and FIG. 4B embodiments, the first contact via 220 is not substantially etched in the planarization process, but embodiments of the present disclosure are not limited thereto. For example, a portion of the upper surface of the first contact via 220 can be etched in the planarization process, and a recess can occur on the upper surface of the first contact via 220. In this case, the horizontal height of the upper surface of the first contact via 220 can be lower than the horizontal height of the upper surface of the insulating layer 210.

[0042] Referring to FIG. 5A and FIG. 5B The first conductive layer 240A can be formed on the insulating layer 210 and the support pattern 230. For example, the first conductive layer 240A can be conformally formed along the profile of the support pattern 230. In this case, the first conductive layer 240A can be formed to fill the space (e.g., the step) between the support pattern 230 and the insulating layer 210. For example, the first conductive layer 240A can include protrusions 240P protruding toward the support pattern 230 and each having a lower surface. The protrusions 240P can be formed to fill the space between the support pattern 230 and the insulating layer 210. For example, each of the protrusions 240P can be formed to fill the space defined by the recess of the corresponding support pattern 230 among the support patterns 230. In addition, the first conductive layer 240A can include recesses 240C each having an upper surface. Here, the recesses 240C can be respectively positioned in correspondence with the support patterns 230. Thus, the recesses 240C can be arranged in the first direction I and the second direction II. The first conductive layer 240A can include a conductive material such as tungsten.

[0043] Subsequently, the first electrode layer 251A can be formed along the profile of the first conductive layer 240A. In this case, the first electrode layer 251A can include protrusions filling the concave portions 240C of the first conductive layer 240A, each protrusion having a lower surface (e.g., a lower curved surface), and the first electrode layer 251A can include concave portions respectively positioned corresponding to the support patterns 230, each concave portion having an upper surface (e.g., an upper curved surface). The first electrode layer 251A can be formed of a conductive material including tungsten or carbon.

[0044] Subsequently, the variable resistance layer 253A can be formed on the first electrode layer 251A. For example, the variable resistance layer 253A can be formed along the profile of the first electrode layer 251A. In this case, the variable resistance layer 253A can include protrusions 253P protruding toward the concave portions 240C of the first conductive layer 240A and each protrusion having a lower surface (e.g., a lower curved surface), and the variable resistance layer 253A can include concave portions respectively positioned corresponding to the support patterns 230 and each concave portion having an upper surface (e.g., an upper curved surface). In other words, the variable resistance layer 253A can include protrusions 253P at positions corresponding to the protrusions 240P of the first conductive layer 240A. For example, the variable resistance layer 253A can include protrusions 253P respectively filling the concave portions of the first electrode layer 251A. The variable resistance layer 253A can include a chalcogenide material.

[0045] Referring to FIG. 6A and FIG. 6B The variable resistance layer 253A can be planarized. For example, the variable resistance layer 253A can be planarized such that the upper surface of the variable resistance layer 253A is substantially planar. In this case, the variable resistance layer 253A can include a first portion 253A1 including the protrusions 253P and a second portion 253A2 not including the protrusions 253P. Here, the first portion 253A1 can have a first thickness T1, and the second portion 253A2 can have a second thickness T2 thinner than the first thickness T1. For example, the first portion 253A1 can have the first thickness T1 as a maximum thickness, and the second portion 253A2 can have a substantially uniform thickness T2.

[0046] In one embodiment, the second thickness T2 can be in the range of about 20% to 80% of the first thickness T1. When the second thickness T2 is greater than about 80% of the first thickness T1, the risk of damaging the variable resistance pattern during etching the variable resistance layer 253A to form the variable resistance pattern may be excessively increased. When the second thickness T2 is less than about 20% of the first thickness T1, conformal deposition of the variable resistance layer 253A on the first electrode layer 251A may be difficult. However, the ranges of the first thickness T1 and the second thickness T2 are not limited to the above ranges. That is, the second thickness T2 must be less than the first thickness T1. The first portion 253A1 can be the region where a memory cell (not shown) is to be formed, while the second portion 253A2 can both be the region between memory cells. The second portion 253A2 can be removed in a subsequent process.

[0047] For reference, although FIG. 5A and FIG. 5B Although not shown, when the variable resistance layer 253A is formed to a sufficiently thick thickness on the first electrode layer 251A, no recesses will appear in the upper surface of the variable resistance layer 253A. In other words, the upper surface of the variable resistance layer 253A can be substantially flat. In this case, the process of planarizing the variable resistance layer 253A can be omitted.

[0048] Subsequently, a second electrode layer 255A can be formed on the variable resistance layer 253A. Here, the upper and lower surfaces of the second electrode layer 255A can be substantially flat. Therefore, a memory layer 250A including the first electrode layer 251A, the variable resistance layer 253A, and the second electrode layer 255A can be defined. The second electrode layer 255A can be formed of a conductive material including tungsten or carbon.

[0049] Reference FIG. 7A and FIG. 7B A second electrode line 255L extending along the first direction I can be formed by etching the second electrode layer 255A. The second electrode lines 255L can be spaced apart from each other in the second direction II.

[0050] Subsequently, a variable resistance line 253L including the protrusion 253P and extending in the first direction I can be formed by etching the variable resistance layer 253A. For example, the variable resistance line 253L can be formed by etching the second portions 253A2 of the variable resistance layer 253A. In other words, the relatively thin second portions 253A2 can be removed, and the relatively thick first portions 253A1 can be left to form the variable resistance line 253L. Specifically, the second portions 253A2 of the variable resistance layer 253A, which extend in the first direction I and are arranged in the second direction II, can be removed to form the variable resistance line 253L. Here, since the second portions 253A2 are relatively thin, the etching time can be reduced. Accordingly, according to embodiments of the present disclosure, damage to the first portions 253A1, which are regions where the memory cells are to be formed, can be prevented or significantly reduced due to the reduction in etching time.

[0051] Subsequently, a first electrode line 251L extending in the first direction I can be formed by etching the first electrode layer 251A. The first electrode lines 251L can be spaced apart from each other in the second direction II. Accordingly, the memory lines 250L including the first electrode lines 251L, the variable resistance lines 253L, and the second electrode lines 255L can be defined.

[0052] Subsequently, a first conductive line 240 including the recess 240C and extending in the first direction I can be formed by etching the first conductive layer 240A. Here, the first conductive line 240 can be a word line or a bit line. The first contact via 220 can be connected to the first conductive line 240.

[0053] Subsequently, a first gap fill pattern 260 can be formed. First, a first gap fill layer 260A can be formed to fill spaces between the memory lines 250L. Subsequently, the first gap fill layer 260A can be planarized until the upper surfaces of the memory lines 250L are exposed. In this case, the first gap fill layer 260A can be separated into the first gap fill pattern 260. The first gap fill pattern 260 can include an insulating material such as an oxide.

[0054] Next, a second contact via 270 can be formed in the first gap fill pattern 260. The second contact via 270 can be formed in a region where a second conductive line (not shown) is to be formed. For example, the second contact via 270 can be formed to connect to some of the first contact vias 220 formed in the region where the second conductive line is to be formed. Here, such first contact vias 220 formed in the region where the second conductive line is to be formed can be electrically connected to the second contact via 270. The second contact via 270 can include a conductive material such as tungsten.

[0055] Reference FIGS. 8A-8CA second conductive line 280 extending in the second direction II can be formed. First, a second conductive layer 280A can be formed on the memory line 250L. Subsequently, the second conductive line 280 can be formed by etching the second conductive layer 280A. Here, the second conductive line 280 can be a bit line or a word line. The second contact via 270 can be connected to the second conductive line 280.

[0056] Subsequently, the memory cell 250 can be formed. For example, the second electrode pattern 255, the variable resistance pattern 253, and the first electrode pattern 251 can be formed by sequentially etching the second electrode line 255L, the variable resistance line 253L, and the first electrode line 251L. Accordingly, the memory cell 250 including the second electrode pattern 255, the variable resistance pattern 253, and the first electrode pattern 251 can be formed. Here, the relatively thin second portion 253A2 of the variable resistance line 253L can be removed by etching, and the first portion 253A1 to form the memory cell 250 can be preserved. Here, the remaining first portion 253A1 can configure the variable resistance pattern 253 of the memory cell 250. The variable resistance pattern 253 can include the protrusion 253P.

[0057] Subsequently, the second gap fill pattern 290 can be formed. First, a second gap fill layer 290A can be formed to fill a space between the memory cells 250 adjacent in the first direction I. Subsequently, the second gap fill layer 290A can be planarized until the upper surfaces of the memory cells 250 are exposed. In this case, the second gap fill layer 290A can be separated into the second gap fill pattern 290. The second gap fill pattern 290 can include an insulating material such as an oxide.

[0058] According to the manufacturing method described above, the support pattern 230 whose upper surface has a level height lower than that of the upper surface of the insulating layer 210 can be formed. In this case, a space (e.g., a step) associated with the level height difference can occur between the insulating layer 210 and each support pattern 230.

[0059] The first conductive layer 240A can be formed to fill a space defined by the insulating layer 210 and the support pattern 230. The memory layer 250A including the variable resistance layer 253A can be formed on the first conductive layer 240A. Accordingly, the variable resistance layer 253A can include the relatively thin second portion 253A2 and the relatively thick first portion 253A1 corresponding to the support pattern 230. Here, since each second portion 253A2 is relatively thin, etching time to remove the second portion 253A2 to form the variable resistance pattern 253 can be significantly reduced. Accordingly, according to the present disclosure, damage to the first portion 253A1 as an area to form the memory cell can be prevented or significantly reduced due to the reduced etching time.

[0060] Although some embodiments according to the technical spirit of the present disclosure have been described with reference to the accompanying drawings, various embodiments of the present disclosure are not limited to the above-described embodiments. Those skilled in the art to which the present disclosure pertains can make various forms of substitution, modification, and change to the embodiments according to the teachings of the present disclosure, and these various forms of substitution, modification, and change can belong to the scope of the present disclosure.

Claims

1. A semiconductor device comprising: an insulating layer; support patterns in the insulating layer; first conductive lines each extending in a first direction, wherein a lower surface of each of the first conductive lines includes a protrusion toward the support patterns; second conductive lines each extending in a second direction crossing the first direction; and memory cells at intersection regions of the first conductive lines and the second conductive lines.

2. The semiconductor device of claim 1, wherein, An upper surface of each of the first conductive lines includes a recess positioned to correspond to the protrusion.

3. The semiconductor device of claim 2, wherein, The memory cells fill spaces defined by the recesses.

4. The semiconductor device of claim 1, wherein, The support patterns are arranged in the first direction and the second direction.

5. The semiconductor device of claim 1, wherein, An upper surface of each of the support patterns has a level lower than a level of an upper surface of the insulating layer.

6. The semiconductor device of claim 1, wherein, Each of the memory cells includes a first electrode pattern, a second electrode pattern on the first electrode pattern, and a variable resistance pattern between the first electrode pattern and the second electrode pattern, and wherein an upper surface of the variable resistance pattern is substantially flat, and a lower surface of the variable resistance pattern includes a curved surface.

7. The semiconductor device of claim 6, wherein, The variable resistance pattern includes a phase change material.

8. The semiconductor device of claim 6, wherein, An upper surface and a lower surface of the first electrode pattern each include a curved surface.

9. The semiconductor device of claim 6, wherein, An upper surface and a lower surface of the second electrode pattern are each substantially flat.

10. The semiconductor device of claim 1, wherein, An upper surface and a lower surface of each of the second conductive lines are substantially flat.

11. The semiconductor device of claim 1, wherein, The support patterns each include a material having an etching rate different from an etching rate of the insulating layer.

12. The semiconductor device of claim 11, wherein, The support patterns each include a material having an etching rate higher than an etching rate of the insulating layer.

13. The semiconductor device of claim 12, wherein, The support patterns each include at least one of borophosphosilicate glass (BPSG), undoped silicate glass (USG), or high aspect ratio process (HARP) oxide.

14. A method of manufacturing a semiconductor device, the method comprising: forming a first conductive layer, wherein an upper surface of the first conductive layer includes recesses arranged in a first direction and a second direction crossing the first direction; forming a variable resistance layer over the first conductive layer, the variable resistance layer including protrusions toward the recesses of the first conductive layer; forming variable resistance lines by etching the variable resistance layer, the variable resistance lines including the protrusions and each extending in the first direction; forming first conductive lines by etching the first conductive layer, the first conductive lines including the recesses and each extending in the first direction; forming second conductive lines each extending in the second direction on the variable resistance lines; and forming a variable resistance pattern by etching the variable resistance layer, the variable resistance pattern at intersection regions of the first conductive lines and the second conductive lines and including the protrusions.

15. The method of claim 14, further comprising: forming an insulating layer before forming the first conductive layer; and forming support patterns in the insulating layer, an upper surface of each of the support patterns having a level lower than a level of an upper surface of the insulating layer. Forming the support patterns includes:

16. The method of claim 15, wherein, forming trenches in the insulating layer arranged in the first direction and the second direction; ​ forming a support layer to fill the trenches, the support layer comprising a material having an etching rate different from that of the insulating layer; and forming the support patterns in the trenches by planarizing the support layer so that the upper surface of the insulating layer is exposed.

17. The method of claim 15, wherein, The support patterns each comprise a material having an etching rate higher than that of the insulating layer.

18. The method of claim 17, wherein, The support patterns each comprise at least one of borophosphosilicate glass (BPSG), undoped silicate glass (USG), or high aspect ratio process (HARP) oxide.

19. The method of claim 18, wherein, The insulating layer comprises tetraethoxysilane (TEOS).

20. The method of claim 15, wherein, The recesses of the first conductive layer are positioned to correspond to the support patterns.

21. The method of claim 15, wherein, A lower surface of the first conductive layer further comprises protrusions toward the support patterns.

22. The method of claim 14, wherein, The variable resistance layer comprises: first portions comprising the protrusions; and second portions between the first portions, and wherein each of the first portions has a first thickness, and each of the second portions has a second thickness thinner than the first thickness.

23. The method of claim 22, wherein, The variable resistance lines are formed by etching the second portions.

24. The method of claim 14, further comprising: forming a first electrode layer along a profile of the first conductive layer; forming the variable resistance layer on the first electrode layer; planarizing the variable resistance layer; and forming a second electrode layer on the variable resistance layer to form a memory layer comprising the first electrode layer, the variable resistance layer, and the second electrode layer.

25. The method of claim 24, further comprising: forming a memory line comprising second electrode lines, the variable resistance lines, and first electrode lines by etching the second electrode layer, the variable resistance layer, and the first electrode layer.

26. The method of claim 25, further comprising: forming a memory cell comprising second electrode patterns, the variable resistance patterns, and first electrode patterns by etching the second electrode lines, the variable resistance lines, and the first electrode lines.

27. A method of manufacturing a semiconductor device, the method comprising: forming an insulating layer; forming support patterns in the insulating layer, an upper surface of each of the support patterns having a level lower than that of an upper surface of the insulating layer; forming a first conductive layer on the insulating layer and the support patterns, the first conductive layer comprising protrusions toward the support patterns; and forming a variable resistance layer on the first conductive layer, the variable resistance layer comprising protrusions at positions corresponding to the protrusions of the first conductive layer. forming the support patterns comprises: forming trenches arranged in a first direction and a second direction intersecting the first direction in the insulating layer; 28. The method of claim 27, wherein, forming a support layer to fill the trenches, the support layer comprising a material having an etching rate different from that of the insulating layer; and forming the support patterns in the trenches by planarizing the support layer so that the upper surface of the insulating layer is exposed. The support patterns each comprise a material having an etching rate higher than that of the insulating layer. ​ 29. The method of claim 27, wherein, ​ 30. The method of claim 27, wherein, The support pattern includes at least one of borophosphosilicate glass (BPSG), undoped silicate glass (USG), or high aspect ratio process (HARP) oxide, and the insulating layer includes tetraethoxysilane (TEOS).

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