High-frequency and high-gain triode and preparation method thereof
By designing an asymmetrical base region structure and deep trench electrodes in the transistor, the electric field distribution is optimized, solving the problem of increasing the transistor frequency and gain coefficient, and achieving high frequency and high gain effects.
Patent Information
- Application Number
- CN202511207991.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-27
- Publication Date
- 2025-11-07
AI Technical Summary
Existing transistors have room for improvement in high frequency and high gain, especially with parameters such as base doping concentration, base thickness, and emitter area fixed, making it difficult to further increase frequency and gain coefficient.
By designing an asymmetrical base region structure with varying widths in the transistor, placing the emitter region above the bottom spacer region of the base region, and fabricating a deep trench electrode within the base region, the distance between the emitter region and the collector region is reduced, thereby optimizing the electric field distribution to decrease carrier transit time and recombination efficiency.
It increases the transistor's operating frequency by 30% and gain coefficient by 1.2 times, while also improving the device's current density without adding any extra process steps, and is compatible with existing fabrication processes.
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Figure CN120916451A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, in particular to a high-frequency and high-gain triode and a preparation method thereof. BACKGROUND
[0002] In the field of power electronic devices, triodes are commonly used as a kind of semiconductor device, commonly used in switching circuits and amplifying circuits. With the development of the application field of power electronic devices towards high frequency and high power, the development and performance optimization of triodes are also developing towards high frequency and high power.
[0003] Currently, the high frequency and high gain of triodes are mainly optimized and improved through the following schemes: 1. Thinning the base region thickness to reduce the recombination time of carriers in the base region and improve the frequency of the triode; 2. Reducing the base region doping to reduce the recombination time of carriers in the base region and improve the frequency of the triode; 3. Increasing the emitter region doping concentration, increasing the contact area of the unit area base region and the emitter region, and increasing the contact area of the unit area base region and the collector region, all of which can increase the current density per unit area of the device, thereby improving the gain coefficient of the device.
[0004] However, for traditional structure triodes, the base region doping concentration, base region thickness, emitter region area and other parameters are basically fixed after determining the application scenario. Therefore, it is an urgent technical problem to be solved in the present case to innovate the structure of the triode to further improve the application frequency and gain coefficient of the triode. SUMMARY
[0005] In view of the above problems, the present application provides a high-frequency and high-gain triode and a preparation method thereof, which can reduce the transit time and recombination efficiency of carriers incident into the base region from the emitter region, improve the working frequency and gain coefficient of the triode, and increase the current density of the device.
[0006] The technical scheme of the present application is as follows: A high-frequency and high-gain triode and a preparation method thereof, comprising the following steps: Step S100, preparing a first mask on an epitaxial wafer, spacing apart windows and preparing a plurality of first heavily doped base regions connected at the top and spaced apart at the bottom in the epitaxial wafer; Step S200, preparing a second mask on the epitaxial wafer, opening a window above the first heavily doped base region spacing area, and preparing a second heavily doped emitter region in the first heavily doped base region; Step S300, preparing a first isolation layer on the epitaxial wafer, opening a window at the first heavily doped base region to prepare a deep trench, and preparing a base electrode in the deep trench; Step S400, opening a window at the second heavily doped emitter region to prepare an emitter electrode; Step S500, preparing the collector electrode on the back of the epitaxial wafer.
[0007] Specifically, step S100 includes: Step S110, using a mask to protect the external area of the first heavily doped base region by a photolithography process; forming a plurality of first heavily doped base regions connected at the top and spaced at the bottom by a diffusion process or an ion implantation process. Specifically, step S200 includes: Step S210, using a mask to protect the external area of the second heavily doped emitter region by a photolithography process; preparing the second heavily doped emitter region on the window above the spaced bottom area of the first heavily doped base region by a diffusion process or an ion implantation process.
[0008] Specifically, step S300 includes: Step S310, preparing the first isolation layer by chemical vapor deposition, protecting the external area of the base electrode by a photolithography process using a mask, and preparing the deep trench by a window etching process. Step S320, preparing the base electrode in the deep trench by a stripping process or an etching process.
[0009] Specifically, step S400 includes: Step S410, protecting the external area of the emitter electrode by a photolithography process using a mask, and preparing the window by an etching process. Step S420, preparing the emitter electrode at the window by a stripping process or an etching process.
[0010] Specifically, step S500 includes: Step S510, thinning the epitaxial wafer by a thinning process, and preparing the collector electrode on the back of the epitaxial wafer by a sputtering process or a deposition process.
[0011] A high-frequency and high-gain triode includes, from bottom to top, a collector electrode, an epitaxial wafer, and a first isolation layer. The epitaxial wafer is provided with: A first heavily doped base region is provided with a plurality of regions, each extending downward from the top surface of the epitaxial wafer; the top parts of adjacent first heavily doped base regions are interconnected, and the bottom parts are spaced apart from each other. A second heavily doped emitter region is provided with a plurality of regions, each extending downward from the top surface of the first heavily doped base region and located inside the interconnected top parts of adjacent first heavily doped base regions. A base electrode is provided with a plurality of regions, each extending downward from the top surface of the first isolation layer to the first heavily doped base region, and a spacing is provided between the base electrode and the bottom surface of the first heavily doped base region; the base electrode and the first heavily doped base region form a good ohmic contact. The emitter electrode is provided with several emitter electrodes respectively extending downward from the top surface of the first isolation layer and connected with the top surface of the second heavily doped emitter region, and forms a good ohmic contact with the second heavily doped emitter region.
[0012] Specifically, the first heavily doped base region has a cross section in a structure of wide top and narrow bottom.
[0013] Specifically, the bottom surface of the base electrode is located below the bottom surface of the second heavily doped emitter region.
[0014] Specifically, the lateral width of the second heavily doped emitter region is greater than the lateral width of the emitter electrode.
[0015] For improving the frequency and gain coefficient of the triode, the triode base region is prepared by an innovative method in the application, forming a structure of asymmetric width from top to bottom, top connection and bottom spacing, the emitter region is arranged above the bottom spacing area of the base region, the distance from the emitter region to the collector region is reduced, a deep trench electrode is arranged in the base region, the electric field distribution from the emitter region to the base region is more uniform, the overall carrier injected into the base region from the emitter region is closer to the collector region compared with the traditional triode device, thereby reducing the transit time and recombination efficiency of the carrier injected into the base region from the emitter region, improving the working frequency and gain coefficient of the triode, improving the current density of the device, and the application does not increase additional process steps compared with commercial products and processes on the market, and is fully compatible with the existing triode preparation process. BRIEF DESCRIPTION OF DRAWINGS
[0016] Figure 1 is a process flow chart of the application; Figure 2 is a first mask cross-sectional structure schematic diagram; Figure 3 is a first heavily doped base region cross-sectional structure schematic diagram prepared in a structure of top connection and bottom spacing; Figure 4 is a second mask cross-sectional structure schematic diagram; Figure 5 is a second heavily doped emitter region cross-sectional structure schematic diagram prepared above the bottom spacing area of the first heavily doped base region; Figure 6 is a deep trench cross-sectional structure schematic diagram; Figure 7 is a base electrode cross-sectional structure schematic diagram; Figure 8 is an emitter electrode cross-sectional structure schematic diagram; Figure 9 is a collector electrode cross-sectional structure schematic diagram; Figure 1 is an epitaxial wafer, 2 is a first mask, 3 is a first heavily doped base region, 4 is a second mask, 5 is a second heavily doped emitter region, 6 is a first isolation layer, 7 is a base electrode, 8 is an emitter electrode, and 9 is a collector electrode. DETAILED DESCRIPTION
[0017] Embodiments of the present application are described below in detail with reference to the accompanying drawings, in which like or similar elements or elements having the same or similar functions are denoted by the same or similar reference numerals throughout the drawings. The embodiments described below by reference to the accompanying drawings are exemplary only and are intended to explain the present application, and should not be construed as limiting the present application.
[0018] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection", and "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0019] Reference is made below Figures 1-9 to describe the present application; A method for preparing a high-frequency and high-gain triode, comprising the following steps: Step S100, a first mask 2 is prepared on an epitaxial wafer 1, windows are spaced apart and a plurality of first heavily doped base regions 3 are prepared in the epitaxial wafer 1, which are top-connected and bottom-spaced, as shown in Figures 2-3 ; Step S110, using a photolithography process, the first heavily doped base region 3 is protected outside using the mask 2; through a diffusion process or an ion implantation process, a plurality of first heavily doped base regions 3 are formed which are top-connected and bottom-spaced; Correspondingly, the first doped region and the second doped region are P regions or N regions with opposite doping electrical properties, the thickness of the epitaxial wafer 1 is 100-2000um, the thickness of the first heavily doped base region 3 is set to 1-50um, the window width is set to 1-500um, the window spacing distance is set to 1-100um, the doping concentration range of N-type doping is 1e 14 .cm -3 -1e 20 .cm -3 , the doping concentration range of P-type doping is 1e 15 .cm -3 -1e 20 .cm -3 , the related parameters are related to the design of device electrical properties; The first doped region is P region and the second doped region is N region in the embodiment, the thickness of the epitaxial wafer 1 is 350um; the thickness of the first heavily doped base region 3 is 8um, the window width is 20um, the window interval distance is 10um, and the doping concentration is 1e 16 .cm -3 The 3um-thick top first heavily doped base region 3 and the 5um-thick first heavily doped base region 3 with the interval distance increasing from top to bottom are formed by using the diffusion process to prepare the first heavily doped base region 3.
[0020] In step S200, the second mask 4 is prepared on the epitaxial wafer 1, the window is opened above the interval area at the bottom of the first heavily doped base region 3, and the second heavily doped emitter region 5 is prepared in the first heavily doped base region 3, as shown in Fig. 2. Figures 4-5 In step S210, the outer area of the second heavily doped emitter region 5 is protected by using the mask 4 through the photolithography process, and the second heavily doped emitter region 5 is prepared at the window opening position above the interval area at the bottom of the first heavily doped base region 3 through the diffusion process or the ion implantation process.
[0021] Correspondingly, the thickness of the second heavily doped emitter region 5 is set to 0.5-49um, and the window width is set to 0.5-400um. In the embodiment, the thickness of the second heavily doped emitter region 5 is set to 2um, the window width is set to 15um, and the doping concentration is 1e 19. cm -3 The second heavily doped emitter region 5 is prepared by using the ion implantation process.
[0022] In step S300, the first isolation layer 6 is prepared on the epitaxial wafer 1, the deep trench is prepared by opening the window at the first heavily doped base region 3, and the base electrode 7 is prepared in the deep trench, as shown in Fig. 3. Figures 6-7 In step S310, the first isolation layer 6 is prepared by using the chemical vapor deposition, the outer area of the base electrode 7 is protected by using the mask through the photolithography process, and the deep trench is prepared by opening the window through the etching process. In step S320, the base electrode 7 is prepared in the deep trench by using the stripping process or the etching process. Correspondingly, the first isolation layer 6 plays a protection role, the material is SiO2 or Si3N4, the thickness is set to 10-5000nm, the deep trench is prepared by opening the window through the ICP dry etching, the window extends from the top surface of the first isolation layer 6 to the inside of the first heavily doped base region 3, the bottom surface of the deep trench is not higher than the bottom surface of the first heavily doped base region 3, the base electrode 7 fills the deep trench, and the ohmic contact is formed by contacting the first heavily doped base region 3; the related parameters are set in relation to the device electrical property design. In this embodiment, Si3N4 is used as the first isolation layer 6, and the thickness is set to 200 nm. Deep grooves are prepared by ICP dry etching. The depth of the deep grooves is 2200 nm. Ti / Al two-layer metal is prepared as the base electrode 7 by a local heavy doping and remetallization process and a stripping process.
[0023] In step S400, the emitter electrode 8 is prepared by opening a window in the second heavy doping emitter region 5. Referring to FIG. 4, the emitter electrode 8 is prepared by opening a window in the second heavy doping emitter region 5. Figure 8 In step S410, the outer region of the emitter electrode 8 is protected by using a mask through a photolithography process, and an etching process is used to open a window. In step S420, the emitter electrode 8 is prepared by using a stripping process or an etching process at the opening. Correspondingly, ICP dry etching is used to open a window, which extends from the top surface of the first isolation layer 6 downward to the inside of the second heavy doping emitter region 5. The emitter electrode 8 is in contact with the second heavy doping emitter region 5 to form an ohmic contact. The related parameters are related to the design of the device electrical properties. In this embodiment, ICP dry etching is used to open a window, and the depth of the window is 200 nm. A 200-nm-thick Ti / Al two-layer metal is prepared as the emitter electrode 8 by using a stripping process.
[0024] In step S500, the collector electrode 9 is prepared on the back surface of the epitaxial wafer. Referring to FIG. 5, the collector electrode 9 is prepared on the back surface of the epitaxial wafer. Figure 9
[0025] Correspondingly, the epitaxial wafer 1 is thinned by a thinning process to a corresponding thickness. A deposition process or a sputtering process is used to prepare the collector electrode 9 on the back surface of the epitaxial wafer. In this embodiment, the 350-um-thick epitaxial wafer 1 is thinned to 180 um by a thinning process. A 1-um-thick Ti / Al is prepared as the collector electrode 9 by using a deposition process.
[0026] A high-frequency and high-gain triode includes, from bottom to top, a collector electrode 9, an epitaxial wafer 1, and a first isolation layer 6. The epitaxial wafer 1 is provided with: A first heavy doping base region 3 is provided with a plurality of regions, which respectively extend downward from the top surface of the epitaxial wafer 1. Adjacent top portions of the first heavy doping base regions 3 are interconnected, and the bottom portions are spaced apart from each other. A second heavy doping emitter region 5 is provided with a plurality of regions, which respectively extend downward from the top surface of the first heavy doping base region 3 and are located inside the interconnected top portions of adjacent first heavy doping base regions 3. A base electrode 7 is provided with a plurality of regions, which respectively extend downward from the top surface of the first isolation layer 6 to the first heavy doping base region 3 and are spaced apart from the bottom surface of the first heavy doping base region 3. The base electrode 7 forms a good ohmic contact with the first heavy doping base region 3. The emitter electrode 8 is provided with several, respectively extending downward from the top surface of the first isolation layer 6 and connected with the top surface of the second heavily doped emitter region 5, and the second heavily doped emitter region 5 forms a good ohmic contact.
[0027] The first heavily doped base region 3 is in a structure of wide top and narrow bottom.
[0028] The bottom surface of the base electrode 7 is below the bottom surface of the second heavily doped emitter region 5.
[0029] The lateral width of the second heavily doped emitter region 5 is greater than the lateral width of the emitter electrode 8.
[0030] The present application aims to improve the frequency and gain coefficient of the triode, and the triode base region is prepared by an innovative method, forming a structure of asymmetric width from top to bottom, top interconnection and bottom spacing. The emitter region is arranged above the bottom spacing area of the base region, reducing the distance from the emitter region to the collector region. At the same time, a deep groove electrode is arranged in the base region, making the electric field distribution of the emitter region to the base region more uniform. Compared with the traditional triode device, the overall carrier injected into the base region from the emitter region is closer to the collector region, thereby reducing the transit time and recombination efficiency of the carrier injected into the base region from the emitter region. Under the same process conditions and test conditions, the working frequency of the triode of the present application is increased by 30%, the gain coefficient is increased by 1.2 times, the current density of the device is improved, and the present application does not increase additional process steps compared with commercial products and processes on the market, and is fully compatible with the existing triode preparation process.
[0031] For the content disclosed in the present case, the following points need to be explained: The embodiment disclosed in the present case only relates to the structure involved in the embodiment disclosed in the present case, and other structures can be referred to the usual design; In the case of no conflict, the embodiments disclosed in the present case and the features in the embodiments can be combined to obtain new embodiments; The above is only a specific embodiment disclosed in the present case, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.
Claims
1. A method of manufacturing a high frequency high gain triode, characterized by, The method comprises the following steps: Step S100, preparing a first mask (2) on an epitaxial wafer (1), spacing apart windows and preparing a plurality of first heavily doped base regions (3) which are top-connected and bottom-spaced in the epitaxial wafer (1); Step S200, preparing a second mask (4) on the epitaxial wafer (1), opening windows above the bottom-spaced regions of the first heavily doped base regions (3) and preparing second heavily doped emitter regions (5) in the first heavily doped base regions (3); Step S300, preparing a first isolation layer (6) on the epitaxial wafer (1), opening windows at the first heavily doped base regions (3) to prepare deep trenches and preparing base electrodes (7) in the deep trenches; Step S400, opening windows at the second heavily doped emitter regions (5) to prepare emitter electrodes (8); Step S500, preparing collector electrodes (9) on the back of the epitaxial wafer.
2. The method of claim 1, wherein the high frequency high gain triode is prepared by the steps of: Step S100 comprises: Step S110, using a photolithography process, using the mask (2) to protect the external regions of the first heavily doped base regions (3); through a diffusion process or an ion implantation process, a plurality of first heavily doped base regions (3) which are top-connected and bottom-spaced are formed.
3. The method for fabricating a high-frequency, high-gain transistor according to claim 1, characterized in that, Step S200 comprises: Step S210, using a photolithography process, using the mask (4) to protect the external regions of the second heavily doped emitter regions (5); through a diffusion process or an ion implantation process, the second heavily doped emitter regions (5) are prepared at the windowed positions above the bottom-spaced regions of the first heavily doped base regions (3).
4. The method of claim 1, wherein the high frequency high gain triode is prepared by the steps of: Step S300 comprises: Step S310, using a chemical vapor deposition to prepare the first isolation layer (6), using a mask to protect the external regions of the base electrodes (7) through a photolithography process, and using an etching process to open windows to prepare deep trenches; Step S320, using a stripping process or an etching process to prepare the base electrodes (7) in the deep trenches.
5. The method for fabricating a high-frequency, high-gain transistor according to claim 1, characterized in that, Step S400 comprises: Step S410, using a mask to protect the external regions of the emitter electrodes (8) through a photolithography process, and using an etching process to open windows; Step S420, using a stripping process or an etching process to prepare the emitter electrodes (8) at the windowed positions.
6. The method for fabricating a high-frequency, high-gain transistor according to claim 1, characterized in that, Step S500 comprises: Step S510, thinning the epitaxial wafer through a thinning process, and using a sputtering process or a deposition process to prepare the collector electrodes (9) on the back of the epitaxial wafer.
7. A high frequency and high gain triode prepared by the method of claim 1, characterized by, The collector electrodes (9), the epitaxial wafer (1) and the first isolation layer (6) are sequentially arranged from bottom to top; The epitaxial wafer (1) is provided with: The first heavily doped base regions (3) are provided in a plurality of numbers and respectively extend downward from the top surface of the epitaxial wafer (1); the top portions of adjacent first heavily doped base regions (3) are interconnected and the bottom portions are spaced apart from each other; The second heavily doped emitter regions (5) are provided in a plurality of numbers and respectively extend downward from the top surface of the first heavily doped base regions (3) and are located inside the interconnection of the top portions of adjacent first heavily doped base regions (3); The base electrodes (7) are provided in a plurality of numbers and respectively extend downward from the top surface of the first isolation layer (6) into the first heavily doped base regions (3) and are spaced apart from the bottom surface of the first heavily doped base regions (3); The emitter electrode (8) is provided with several, respectively extending downward from the top surface of the first isolation layer (6) and connected with the top surface of the second heavily doped emitter region (5).
8. A high frequency and high gain triode according to claim 7, characterized in that The first heavily doped base region (3) is in the form of an upper wide and lower narrow structure in cross section.
9. A high frequency and high gain triode according to claim 7, characterized in that, The bottom surface of the base electrode (7) is below the bottom surface of the second heavily doped emitter region (5).
10. A high frequency and high gain triode according to claim 7, characterized in that, The lateral width of the second heavily doped emitter region (5) is greater than the lateral width of the emitter electrode (8).