Manufacturing method of semiconductor structure and semiconductor structure

Abstract

The embodiment of the invention provides a manufacturing method of a semiconductor structure and the semiconductor structure. The method comprises the following steps: providing a substrate comprising a substrate and at least two gate transition structures formed on the substrate; the gate transition structure comprises a gate and a gate mask layer, and has a gate extension direction and a gate width direction vertical to the gate extension direction; the widths of different gate transition structures are different; the distances from the surfaces, far away from the substrate, of different gate transition structures to the substrate are different; forming a first planarization function layer on the surface of the substrate to obtain a transition substrate with at least part of the gate mask layer exposed; forming a second planarization function layer which is made of the same material as the exposed gate mask layer on the surface of the transition substrate; and removing the second planarization function layer and at least part of the gate mask layer to obtain semiconductor structures with the same distances from the surfaces, far away from the substrate, of the different gate structures to the substrate. According to the embodiment of the invention, the technological process for eliminating the height difference between the grids with different widths is simplified.

Description

TECHNICAL FIELD

[0001] Embodiments in the present application relate to the technical field of semiconductor manufacturing, and in particular to a manufacturing method of a semiconductor structure and the semiconductor structure. BACKGROUND

[0002] In the design and manufacturing process of CMOS (Complementary Metal-Oxide-Semiconductor) transistors, in order to meet the diversified current control requirements, optimize the working performance of the circuit and the overall performance of the CMOS transistor, it is necessary to form gates with different widths. However, due to the influence of the front end of line (FEOL), the height of the gate with a larger width is usually greater than the height of the gate with a smaller width.

[0003] However, the height difference between different gates may cause local concave or convex, which reduces the formation quality of subsequent structures. In order to reduce the adverse effects of the height difference between different gates on the precision of subsequent processes and improve the stability of the performance of the CMOS transistor, it is necessary to eliminate the height difference between gates with different widths and achieve the height consistency of gates with different widths.

[0004] In the prior art, multiple processes such as photo lithography, etching and chemical mechanical polishing (CMP) are required to eliminate the height difference between gates with different widths, and the process is relatively complex. SUMMARY

[0005] Therefore, embodiments of the present application provide a manufacturing method of a semiconductor structure and the semiconductor structure to simplify the process for eliminating the height difference between gates with different widths.

[0006] In one aspect, one embodiment of the present application provides a method for manufacturing a semiconductor structure, comprising: providing a substrate; wherein the substrate comprises a substrate and at least two gate transition structures formed on the substrate; the gate transition structure comprises a gate and a gate mask layer; the gate transition structure has a gate extension direction and a gate width direction perpendicular to the gate extension direction; different gate transition structures have different widths along the gate width direction; different gate transition structures have different distances from the surface of the substrate to the substrate; forming a first planarization functional layer on the surface of the substrate to obtain a transition substrate; wherein at least part of the gate mask layer is exposed in the transition substrate; forming a second planarization functional layer on the surface of the transition substrate; wherein the second planarization functional layer is the same material as the exposed gate mask layer; removing the second planarization functional layer, part of the first planarization functional layer and at least part of the gate mask layer to obtain the semiconductor structure; wherein the semiconductor structure comprises at least two gate structures formed on the substrate, and different gate structures have the same distance from the surface of the substrate to the substrate.

[0007] Optionally, the gate mask layer comprises at least two sub-gate mask layers, and in the case that the materials of the at least two sub-gate mask layers are different, the second planarization functional layer is the same material as at least one sub-gate mask layer away from the substrate.

[0008] Optionally, in the at least two sub-gate mask layers, the material of the sub-gate mask layer away from the substrate is silicon oxide, and the material of the sub-gate mask layer close to the substrate is silicon nitride.

[0009] Optionally, removing the second planarization functional layer, part of the first planarization functional layer and at least part of the gate mask layer comprises: using an endpoint detection polishing process, taking the surface of the sub-gate mask layer close to the substrate away from the substrate as the detection endpoint, and polishing to remove the second planarization functional layer, part of the first planarization functional layer and the sub-gate mask layer with the same material as the second planarization functional layer.

[0010] Optionally, the step of forming a second planarization functional layer on the surface of the transition substrate comprises: using a flow control chemical vapor deposition process or a spin coating process to form the second planarization functional layer on the surface of the transition substrate; wherein the second planarization functional layer on the surface of different gate transition structures has the same distance from the surface of the substrate to the substrate.

[0011] Optionally, the first planarization functional layer comprises an etching stop layer and an interlayer dielectric layer; the step of forming the first planarization functional layer on the substrate surface to obtain a transition substrate comprises: sequentially forming an initial etching stop layer and an initial dielectric layer on the substrate surface; thinning the initial dielectric layer to form the interlayer dielectric layer; removing part of the initial etching stop layer to form the etching stop layer, thereby obtaining the transition substrate.

[0012] Optionally, the material of the etching stop layer is silicon nitride; and the material of the interlayer dielectric layer is silicon oxide.

[0013] Optionally, the at least two gate transition structures comprise a first gate transition structure and a second gate transition structure; in the substrate and the transition substrate, the distance from the surface of the substrate to the substrate of the first gate transition structure is greater than the distance from the surface of the substrate to the substrate of the second gate transition structure; the step of thinning the initial dielectric layer to form the interlayer dielectric layer comprises: using an end-point detection polishing process to polish the initial dielectric layer until the initial etching stop layer on the surface of the second gate transition structure is exposed to form a transition dielectric layer, with the initial etching stop layer on the surface of the second gate transition structure being away from the surface of the substrate as the detection end-point; using a dry etching process to etch the transition dielectric layer until the initial etching stop layer on the surface of the at least two gate transition structures is exposed to form the interlayer dielectric layer; correspondingly, the step of removing part of the initial etching stop layer comprises: using an etching process to etch the initial etching stop layer until at least part of the gate mask layer of the at least two gate transition structures is exposed.

[0014] Optionally, the distance from the surface of the substrate to the substrate of the interlayer dielectric layer is greater than the distance from the surface of the substrate to the substrate of the gate.

[0015] In another aspect, an embodiment of the present application provides a semiconductor structure manufactured by the method for manufacturing a semiconductor structure as described in the above embodiment, the semiconductor structure comprising: a substrate; and at least two gate structures formed on the substrate; wherein the gate structure has a gate extension direction and a gate width direction perpendicular to the gate extension direction; the widths of different gate structures along the gate width direction are different; and the distances from the surface of the substrate to the substrate of different gate structures are the same.

[0016] In the embodiments of the present application, a substrate including a substrate and at least two gate transition structures is provided, wherein the gate transition structures include a gate and a gate mask layer, the widths of different gate transition structures are different, and the distances from the surfaces of different gate transition structures to the substrate are different, a first planarization functional layer is formed on the surface of the substrate to obtain a transition substrate, at least part of the gate mask layer is exposed in the transition substrate, a second planarization functional layer with the same material as the exposed gate mask layer is formed on the surface of the transition substrate, and the second planarization functional layer, part of the first planarization functional layer and at least part of the gate mask layer are removed to obtain a semiconductor structure including the substrate and at least two gate structures, wherein the distances from the surfaces of different gate structures to the substrate are the same, and the unexpected effects achieved include that, since the second planarization functional layer and the exposed gate mask layer in the transition substrate are the same, the height difference between the gate transition structures with different widths is eliminated by using the second planarization functional layer first, and then the second planarization functional layer, part of the first planarization functional layer and the exposed gate mask layer are removed by using one process, so that the height consistency of the gate structures with different widths is achieved, and the process of eliminating the height difference of the gates with different widths is simplified. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed for describing the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort.

[0018] Figure 1 A structure schematic diagram of a semiconductor substrate provided by the related art.

[0019] Figure 2 A schematic diagram of forming a buffer layer on the surface of a semiconductor substrate provided by the related art.

[0020] Figure 3 A schematic diagram of exposing and developing a bottom anti-reflective coating and a photoresist layer on the surface of a buffer layer provided by the related art.

[0021] Figure 4 A schematic diagram of removing a photoresist layer provided by the related art.

[0022] Figure 5 A schematic diagram of removing part of a bottom anti-reflective coating provided by the related art.

[0023] Figure 6 A schematic diagram of removing part of a buffer layer and part of a hard mask layer provided by the related art.

[0024] Figure 7A schematic diagram of a structure of a transition semiconductor substrate provided by the related art.

[0025] Figure 8 A schematic diagram of sequentially forming a stop layer and a dielectric layer on a surface of a transition semiconductor substrate provided by the related art.

[0026] Figure 9 A schematic diagram of a gate-equal-height structure provided by the related art.

[0027] Figure 10 A schematic diagram of a flow of a semiconductor manufacturing method provided by one embodiment of the present application.

[0028] Figure 11 A schematic diagram of a structure of a substrate provided by one embodiment of the present application.

[0029] Figure 12 A schematic diagram of a flow of forming a first planarization functional layer on a surface of a substrate provided by one embodiment of the present application.

[0030] Figure 13 A schematic diagram of forming an initial etching stop layer on a surface of a substrate provided by one embodiment of the present application.

[0031] Figure 14 A schematic diagram of forming an initial dielectric layer on a surface of an initial etching stop layer provided by one embodiment of the present application.

[0032] Figure 15 A schematic diagram of polishing the initial dielectric layer to form a transition dielectric layer provided by one embodiment of the present application.

[0033] Figure 16 A schematic diagram of etching the transition dielectric layer to form an interlayer dielectric layer provided by one embodiment of the present application.

[0034] Figure 17 A schematic diagram of a structure of a transition substrate provided by one embodiment of the present application.

[0035] Figure 18 A schematic diagram of forming a second planarization functional layer on a surface of a transition substrate provided by one embodiment of the present application.

[0036] Figure 19 A schematic diagram of a structure of a semiconductor structure provided by one embodiment of the present application.

[0037] Structure Number Explanation 100, semiconductor substrate; 200, transition semiconductor substrate; 300, gate contour structure; 400, substrate; 500, transition substrate; 600, semiconductor structure; 110, semiconductor substrate; 121, first dummy gate; 122, first bottom hard mask layer; 123, first top hard mask layer; 124, first initial sidewall; 125, first sidewall; 131, second dummy gate; 132, second bottom hard mask layer; 133, second top hard mask layer; 134, second initial sidewall; 135, second sidewall; 140, initial buffer layer; 141, buffer layer; 150, bottom anti-reflective coating layer; 151, thinned bottom anti-reflective coating layer; 160, photoresist layer; 170, initial stop layer; 171, stop layer; 180, initial dielectric layer; 181, dielectric layer; 210, substrate; 220, first gate transition structure; 220a, first gate structure; 221, first gate; 222, first sub-gate mask layer; 223, second sub-gate mask layer; 224, first gate transition sidewall; 225, first gate sidewall; 230, second gate transition structure; 230a, second gate structure; 231, second gate; 232, third sub-gate mask layer; 233, fourth sub-gate mask layer; 234, second gate transition sidewall; 235, second gate sidewall; 240, initial etch stop layer; 241, etch stop layer; 242, thinned etch stop layer; 250, initial dielectric layer; 251, transition dielectric layer; 252, interlayer dielectric layer; 253, thinned interlayer dielectric layer; 260, second planarization functional layer. DETAILED DESCRIPTION

[0038] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments of the present application.

[0039] The drawings provided in the embodiments of the present application only schematically illustrate the basic concepts of the present application, and only show the components related to the present application in the drawings, but are not drawn according to the number, shape and size of the components in actual implementation. The shapes, number and ratio of the components in actual implementation can be changed, and the layout form of the components can be more complex.

[0040] In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", "center", and the like, indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application, and do not indicate or imply that the device or component referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. The terms "first", "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features.

[0041] With the continuous shrinking of the semiconductor process node, in order to improve the device performance of the CMOS transistor, the related art usually adopts a gate-last process to form a high dielectric constant metal gate in the manufacturing process of the CMOS transistor, that is, a dummy gate is first formed, and then a metal gate is used to replace the dummy gate. To meet the diversified current control requirements of CMOS transistors for realizing different functions, in some cases, at least two dummy gates with different widths need to be formed on the substrate of the CMOS transistor. After the formation of the dummy gate, a hard mask layer is formed on the surface of the dummy gate to protect the dummy gate from damage in the subsequent process.

[0042] Due to the influence of edge effect and material accumulation characteristics, the hard mask layers on the surfaces of the dummy gates with different widths are lost to different degrees in the front-end-of-line (FEOL) process, so that the thicknesses of the hard mask layers on the surfaces of the dummy gates with different widths are different in the semiconductor substrate obtained after the FEOL process.

[0043] Please refer to Figure 1 . Taking a semiconductor substrate 100 including two dummy gates with different widths as an example, the semiconductor substrate 100 includes a semiconductor substrate 110 and a first dummy gate structure and a second dummy gate structure formed on the surface of the semiconductor substrate 110. The first dummy gate structure includes a first dummy gate 121, a first bottom hard mask layer 122 and a first top hard mask layer 123 formed in sequence on the side of the first dummy gate 121 away from the semiconductor substrate 110, and a first initial side wall 124 formed on the side surface of the first dummy gate 121. The second dummy gate structure includes a second dummy gate 131, a second bottom hard mask layer 132 and a second top hard mask layer 133 formed in sequence on the side of the second dummy gate 131 away from the semiconductor substrate 110, and a second initial side wall 134 formed on the side surface of the second dummy gate 131.

[0044] The semiconductor substrate 100 has a pseudo-gate extending direction and a width direction perpendicular to the pseudo-gate extending direction. The width of the first pseudo-gate 121 along the width direction is smaller than the width of the second pseudo-gate 131 along the width direction, and the distance from the surface of the semiconductor substrate 110 to the semiconductor substrate 110 of the first pseudo-gate 121 is equal to the distance from the surface of the semiconductor substrate 110 to the semiconductor substrate 110 of the second pseudo-gate 131.

[0045] Since the top hard mask layer protects the bottom hard mask layer in the previous process, the edge effect only affects the top hard mask layer, that is, the distance from the surface of the semiconductor substrate 110 to the semiconductor substrate 110 of the first bottom hard mask layer 122 is equal to the distance from the surface of the semiconductor substrate 110 to the semiconductor substrate 110 of the second bottom hard mask layer 132, and the distance from the surface of the semiconductor substrate 110 to the semiconductor substrate 110 of the first top hard mask layer 123 is smaller than the distance from the surface of the semiconductor substrate 110 to the semiconductor substrate 110 of the second top hard mask layer 133. Therefore, the height difference between the first pseudo-gate structure and the second pseudo-gate structure along the pseudo-gate extending direction is actually caused by the thickness difference between the first top hard mask layer 123 and the second top hard mask layer 133 along the pseudo-gate extending direction.

[0046] In the process of removing the pseudo-gate, the height difference between the first pseudo-gate structure and the second pseudo-gate structure along the pseudo-gate extending direction can cause a larger recess in the dielectric layer between the two pseudo-gate structures, thereby causing metal residues in subsequent processes and reducing the electrical performance of the CMOS transistor.

[0047] To reduce the negative impact of the height difference between the two pseudo-gate structures on the performance of the CMOS transistor, in the related art, processes such as photolithography, etching, deposition, and chemical mechanical polishing are usually used to eliminate the thickness difference between the two top hard mask layers. The following will be described in detail in combination with Figures 2 to 9 The process of eliminating the thickness difference between the two top hard mask layers in the related art will be briefly introduced.

[0048] Please refer to Figure 2 First, an initial buffer layer 140 is formed on the surface of the semiconductor substrate 100 to protect the first pseudo-gate 121 and the second pseudo-gate 131 in subsequent processes. The material of the initial buffer layer 140 can be oxide.

[0049] Please refer to Figure 3Secondly, an initial bottom anti-reflection coating (BARC) and an initial photoresist layer are formed on the surface of the initial buffer layer 140 in sequence, and a portion of the initial photoresist layer far from the semiconductor substrate 110 is removed by exposure and development to obtain a photoresist layer 160. Then, the photoresist layer 160 is used as a mask to remove a portion of the initial bottom anti-reflection coating far from the semiconductor substrate 110 to obtain a bottom anti-reflection coating 150. Due to the edge effect, a protrusion may be generated at a position corresponding to the edge of the second dummy gate 131 in the photoresist layer 160 and the bottom anti-reflection coating 150.

[0050] Please refer to Figure 3 and Figure 4 Subsequently, the photoresist layer 160 is removed by a solvent cleaning or a plasma etching process, and only the bottom anti-reflection coating 150 is reserved.

[0051] Please refer to Figure 4 and Figure 5 Then, the bottom anti-reflection coating 150 is thinned by a plasma etching process until the initial buffer layer 140 far from the semiconductor substrate 110 of the first dummy gate 121 and the second dummy gate 131 is exposed to obtain a thinned bottom anti-reflection coating 151.

[0052] Please refer to Figure 5 and Figure 6 Next, the exposed portion of the initial buffer layer 140 is removed by a dry etching process to obtain a buffer layer 141, and the first top hard mask layer 123 and the second top hard mask layer 133 are continuously removed by the dry etching process to eliminate the thickness difference therebetween. By controlling the etching selectivity ratio and the etching time, the damage to the first bottom hard mask layer 122 and the second bottom hard mask layer 132 can be reduced while completely removing the portion of the initial buffer layer 140, the first top hard mask layer 123 and the second top hard mask layer 133.

[0053] Please refer to Figure 6 and Figure 7 After the first bottom hard mask layer 122 and the second bottom hard mask layer 132 are exposed, the first bottom hard mask layer 122, the second bottom hard mask layer 132, the buffer layer 141 and the thinned bottom anti-reflection coating 151 are continuously removed by the dry etching process to obtain a transition semiconductor substrate 200. By controlling the etching selectivity ratio and the etching time, the damage to the first initial sidewall 124 and the second initial sidewall 134 can be reduced while completely removing the first bottom hard mask layer 122, the second bottom hard mask layer 132, the buffer layer 141 and the thinned bottom anti-reflection coating 151.

[0054] It can be seen that the thickness difference between the first top hard mask layer and the second top hard mask layer is continued to the first initial side wall 124 and the second initial side wall 134. Please refer to Figure 7 To eliminate the thickness difference between the first initial side wall 124 and the second initial side wall 134, an initial stop layer 170 and an initial dielectric layer 180 are sequentially formed on the surface of the transition semiconductor substrate 200, and then a chemical mechanical polishing process is performed to obtain a gate contour structure 300. Specifically, the gate contour structure 300 includes the semiconductor substrate 110, the first dummy gate 121, the first side wall 125, the second dummy gate 131, the second side wall 135, the stop layer 171, and the dielectric layer 181. Figures 7 to 9

[0055] Since the hard mask layers on the surfaces of the first dummy gate 121 and the second dummy gate 131 are removed, the surface of the first dummy gate 121 away from the semiconductor substrate 110 and the surface of the second dummy gate 131 away from the semiconductor substrate 110 are exposed, and the distances of the two from the semiconductor substrate 110 are equal, so in the gate contour structure 300, the thickness difference between the first top hard mask layer and the second top hard mask layer has been eliminated, and the influence on the subsequent process has been eliminated.

[0056] Please refer to Figure 1 and Figure 6 However, in the actual manufacturing process, researchers found that the thickness difference between the first top hard mask layer 123 and the second top hard mask layer 133 is large by measuring the semiconductor substrate 100. For example, the thickness of the first top hard mask layer 123 along the thickness direction is 20 Å, and the thickness of the second top hard mask layer 133 along the thickness direction is 100 Å. In this case, in the process of removing the first top hard mask layer 123 and the second top hard mask layer 133 by using a dry etching process, a longer etching time is needed to achieve complete removal of the second top hard mask layer 133. However, for the first top hard mask layer 123, a longer etching time will cause over-etching, which may cause damage to the first bottom hard mask layer 122 or even the first dummy gate 121, and may also cause a reduction in the subsequent process window, resulting in a decrease in the production yield of CMOS transistors.

[0057] In summary, in the related art, the number of process steps to eliminate the thickness difference between the two top hard mask layers is large, the process complexity is high, and the subsequent process window may be reduced, causing a decrease in the production yield of CMOS transistors.

[0058] ​Therefore, for a substrate including a substrate and at least two gate transition structures with different widths and different distances from the surface of the substrate to the substrate, it is necessary to provide a manufacturing method of a semiconductor structure, which forms a first planarization functional layer on the surface of the substrate to obtain a transition substrate, exposes a gate mask layer of at least part of the gate transition structures in the transition substrate, forms a second planarization functional layer with the same material as the exposed gate mask layer on the surface of the transition substrate, uses the second planarization functional layer to eliminate the height difference between the gate transition structures with different widths, and uses one process to remove the second planarization functional layer, part of the first planarization functional layer, and the exposed gate mask layer, so as to simplify the process of eliminating the height difference between the gates with different widths.

[0059] Referring to Figure 10 One embodiment of the present application provides a manufacturing method of a semiconductor structure. The manufacturing method of the semiconductor structure can include steps S310, S320, S330, and S340.

[0060] S310: providing a substrate.

[0061] In the embodiment, the substrate can include a substrate and at least two gate transition structures formed on the substrate.

[0062] In the embodiment, the substrate can be used as a basis for forming a CMOS transistor. Specifically, an N-well (NW) and a P-well (PW) can be defined in a wafer first. After the N-well and the P-well are formed, the position of an active area (AA) can be defined, and a separation region can be formed in the wafer. For example, the separation region can be a shallow trench isolation (STI) structure for reducing leakage. Then, different types of doping ions can be injected into different regions of the wafer to form a lightly doped drain (LDD), a pocket, and a source and drain (S / D) in the wafer to obtain the substrate. The wafer can be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. For example, the wafer can be made of silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC), etc. The wafer can be a single-layer structure or a multi-layer structure. In the embodiment, silicon wafer is used as the wafer considering factors such as dielectric loss requirement, manufacturing process, and manufacturing cost.

[0063] In the embodiment, the gate transition structure can be used to determine the position of the gate in the CMOS transistor manufacturing process. Specifically, the gate transition structure can include a gate and a gate mask layer formed on the side of the gate away from the substrate. In addition to the gate and the gate mask layer, the gate transition structure can also include a gate transition sidewall formed on the side of the gate and the gate mask layer, which can be used to protect the gate and the gate mask layer from the side. The material of the gate can be polysilicon, and the material of the gate transition sidewall can be silicon oxide (SiO2), silicon nitride (Si3N4) or other materials.

[0064] In the embodiment, the gate transition structure can have a gate extension direction and a gate width direction perpendicular to the gate extension direction. To meet the design requirements of the current control of the CMOS transistor, the widths of different gate transition structures along the gate width direction can be different. Specifically, since the current control function is realized by the gate, the width of the gate transition structure along the gate width direction can be determined according to the width of the gate along the gate width direction.

[0065] In the embodiment, due to the edge effect, the distance from the surface of different gate transition structures away from the substrate to the substrate is different. Specifically, since the gate mask layer corresponding to the gate with smaller width is subjected to a relatively large etching rate in the etching process in the front-end-of-line, and the removed part is more, the distance from the surface of the gate transition structure with larger width along the gate width direction away from the substrate to the substrate can be greater than the distance from the surface of the gate transition structure with smaller width along the gate width direction away from the substrate to the substrate.

[0066] In some embodiments, the gate mask layer can include at least two layers of sub-gate mask layers. Specifically, the materials of the at least two layers of sub-gate mask layers can be the same or different. In the case where the number of sub-gate mask layers is greater than two, the materials of the multiple layers of sub-gate mask layers can be different, which can be that the materials of each layer of sub-gate mask layers are different, or that the materials of a part of sub-gate mask layers are the same, and the materials of another part of sub-gate mask layers are different.

[0067] In the embodiment, in the at least two layers of sub-gate mask layers, the material of the sub-gate mask layer away from the substrate can be silicon oxide, and the material of the sub-gate mask layer close to the substrate can be silicon nitride. Specifically, in the case where the number of sub-gate mask layers is two, the material of the sub-gate mask layer away from the substrate can be silicon oxide, and the material of the sub-gate mask layer close to the substrate can be silicon nitride. In the case where the number of sub-gate mask layers is greater than two, the material of the sub-gate mask layer farthest from the substrate can be silicon oxide, the material of the sub-gate mask layer closest to the substrate can be silicon nitride, and the materials of the sub-gate mask layers between them can be one or more of silicon oxide, silicon nitride, titanium nitride or silicon carbon nitride.

[0068] In some embodiments, the gate mask layer can be a single layer structure. Specifically, the material of the gate mask layer can be one or more of silicon oxide, silicon nitride, titanium nitride, or silicon carbon nitride.

[0069] Please refer to Figure 11 . Taking the example that the substrate includes two gate transition structures and the gate mask layer includes two sub-gate mask layers, a brief description is made on the structure of the substrate 400 provided in the embodiment.

[0070] In the embodiment, the substrate 400 can include a substrate 210, a first gate transition structure 220 and a second gate transition structure 230 formed on the substrate 210. The first gate transition structure 220 includes a first gate 221 formed on the surface of the substrate 210, a first sub-gate mask layer 222 and a second sub-gate mask layer 223 formed in sequence on the side of the first gate 221 away from the substrate 210, and a first gate transition side wall 224 formed on the side of the first gate 221, the first sub-gate mask layer 222 and the second sub-gate mask layer 223. The second gate transition structure 230 includes a second gate 231 formed on the surface of the substrate 210, a third sub-gate mask layer 232 and a fourth sub-gate mask layer 233 formed in sequence on the side of the second gate 231 away from the substrate 210, and a second gate transition side wall 234 formed on the side of the second gate 231, the third sub-gate mask layer 232 and the fourth sub-gate mask layer 233.

[0071] The distance from the surface of the first gate 221 away from the substrate 210 to the substrate 210 is equal to the distance from the surface of the second gate 231 away from the substrate 210 to the substrate 210, and the distance from the surface of the first sub-gate mask layer 222 away from the substrate 210 to the substrate 210 is equal to the distance from the surface of the third sub-gate mask layer 232 away from the substrate 210 to the substrate 210. The first gate transition structure 220 and the second gate transition structure 230 each have a gate extension direction and a gate width direction perpendicular to the gate extension direction. The width of the first gate transition structure 220 along the gate width direction is less than the width of the second gate transition structure 230 along the gate width direction. The distance from the surface of the first gate transition structure 220 away from the substrate 210 to the substrate 210 is less than the distance from the surface of the second gate transition structure 230 away from the substrate 210 to the substrate 210.

[0072] S320: Form a first planarization functional layer on the surface of the substrate to obtain a transition substrate.

[0073] In some embodiments, the first planarization functional layer can include an etch stop layer and an interlayer dielectric layer. Specifically, the etch stop layer can be used as an endpoint detection (EPD) to detect the endpoint to prevent over-etching, and the material thereof can be silicon nitride. The interlayer dielectric layer can be used to achieve isolation between different interconnection layers to reduce signal interference, and the material thereof can be silicon oxide.

[0074] Referring to Figure 12 In the present embodiment, the step of forming the first planarization functional layer on the surface of the substrate to obtain a transition substrate can include sub-steps S321, S322 and S323.

[0075] S321: sequentially forming an initial etch stop layer and an initial dielectric layer on the surface of the substrate.

[0076] Referring to Figure 11 , Figure 13 and Figure 14 In the present embodiment, the initial etch stop layer 240 and the initial dielectric layer 250 can be sequentially deposited on the surface of the substrate 400 by a chemical vapor deposition (CVD) process. Specifically, to improve the process precision, the initial etch stop layer 240 can be a contact etch stop layer (CESL). To improve the electrical insulation performance, the distance from the surface of the substrate 210 to the substrate 210 of the initial dielectric layer 250 is greater than the distance from the surface of the substrate 210 to the substrate 210 of the second gate transition structure 230.

[0077] S322: thinning the initial dielectric layer to form an interlayer dielectric layer.

[0078] Referring to Figures 14 to 16 To reduce the damage degree of the gate transition structure in the process of thinning the initial dielectric layer 250 and improve the control precision of the thinning degree of the initial dielectric layer 250, in some embodiments, the step of thinning the initial dielectric layer to form an interlayer dielectric layer can include: using an endpoint detection grinding process to grind the initial dielectric layer 250 until the initial etch stop layer 240 on the surface of the second gate transition structure 230 is exposed, using the initial etch stop layer 240 on the surface of the second gate transition structure 230 as the detection endpoint, to form a transition dielectric layer 251; and using a dry etching process to etch the transition dielectric layer 251 until the initial etch stop layer 240 on the surface of at least two gate transition structures is exposed to form an interlayer dielectric layer 252.

[0079] In the embodiment, the initial dielectric layer 250 is polished by using endpoint detection polishing process. The initial dielectric layer 250 can be polished by using chemical mechanical polishing (CMP) process. When the initial dielectric layer 250 is polished to expose the initial etching stop layer 240 on the surface of the second gate transition structure 230, the detection signal will fluctuate greatly, and then the polishing is stopped. The thinned initial dielectric layer 250 is used as the transition dielectric layer 251. Since the distance between the initial etching stop layer 240 on the surface of the second gate transition structure 230 and the substrate 210 is greater than the distance between the initial etching stop layer 240 on the surface of the first gate transition structure 220 and the substrate 210, the portion of the initial dielectric layer 250 removed from the side of the first gate transition structure 220 away from the substrate 210 can be greater than the portion of the initial dielectric layer 250 removed from the side of the second gate transition structure 230 away from the substrate 210. Therefore, the distance from the surface of the transition dielectric layer 251 away from the substrate 210 to the substrate 210 corresponding to the position of the first gate transition structure 220 can be less than the distance from the surface of the transition dielectric layer 251 away from the substrate 210 to the substrate 210 corresponding to the position of the second gate transition structure 230.

[0080] In the embodiment, the distance from the surface of the interlayer dielectric layer 252 away from the substrate 210 to the substrate 210 can be greater than the distance from the surface of the gate away from the substrate 210 to the substrate 210. Specifically, since the distance from the surface of the first gate 221 away from the substrate 210 to the substrate 210 is equal to the distance from the surface of the second gate 231 away from the substrate 210 to the substrate 210, in order to reduce the risk of reducing the production yield caused by the reduction of the process window in the subsequent process, the distance from the surface of the interlayer dielectric layer 252 away from the substrate 210 to the substrate 210 is at least greater than the distance from the surface of the gate away from the substrate 210 to the substrate 210.

[0081] In some embodiments, since the distance from the surface of the first sub-gate mask layer 222 away from the substrate 210 to the substrate 210 is equal to the distance from the surface of the third sub-gate mask layer 232 away from the substrate 210 to the substrate 210, in the case that the materials of the first sub-gate mask layer 222 and the second sub-gate mask layer 223 are different, and the materials of the third sub-gate mask layer 232 and the fourth sub-gate mask layer 233 are different, the distance from the surface of the interlayer dielectric layer 252 away from the substrate 210 to the substrate 210 can be greater than the distance from the surface of the first sub-gate mask layer 222 or the third sub-gate mask layer 232 away from the substrate 210 to the substrate 210.

[0082] S323: removing part of the initial etching stop layer to form an etching stop layer, and obtaining a transition substrate.

[0083] Please refer to Figure 16 and Figure 17To simplify the process of eliminating the height difference of different gate transition structures along the gate extension direction, the second sub-gate mask layer 223 and the fourth sub-gate mask layer 233 need to be exposed. In the embodiment, removing part of the initial etching stop layer can include: etching the initial etching stop layer 240 by using an etching process until at least part of the gate mask layer of at least two gate transition structures is exposed. For example, the exposed initial etching stop layer 240 can be removed by using a dry etching process until the second sub-gate mask layer 223 of the first gate transition structure 220 and the fourth sub-gate mask layer 233 of the second gate transition structure 230 are exposed.

[0084] Since the above-mentioned sub-steps S321 to S323 have not eliminated the height difference of the first gate transition structure 220 and the second gate transition structure 230 along the gate extension direction, in the transition base 500, the distance from the surface of the substrate 210 to the substrate 210 of the first gate transition structure 220 is still smaller than the distance from the surface of the substrate 210 to the substrate 210 of the second gate transition structure 230.

[0085] S330: Forming a second planarization functional layer on the surface of the transition base.

[0086] Please refer to Figure 17 and Figure 18 . To avoid the inconsistent performance of different gate transition structures during the planarization process, which leads to the reduction of the subsequent process window, a second planarization functional layer 260 can be formed on the surface of the transition base 500, so that the height difference of different gate transition structures along the gate extension direction can be eliminated by using the second planarization functional layer 260, and a redundancy can be left for the subsequent planarization process. To improve the formation quality of the second planarization functional layer 260, and further improve the process quality of the subsequent planarization process, in the embodiment, the step of forming the second planarization functional layer on the surface of the transition base can include: forming the second planarization functional layer 260 on the surface of the transition base 500 by using a flow control chemical vapor deposition (FCVD) process or a spin coating process. Specifically, the distance from the surface of the substrate 210 to the substrate 210 of the second planarization functional layer 260 on the surface of different gate transition structures is the same.

[0087] To simplify the process of eliminating the height difference of the different gate transition structures along the extension direction of the gate, a process is needed to remove the second planarization functional layer 260 and the exposed gate mask layer, so in this embodiment, the second planarization functional layer 260 is the same material as the exposed gate mask layer. Specifically, in the case that the gate mask layer includes at least two layers of sub-gate mask layers, and the materials of the at least two layers of sub-gate mask layers are different, the second planarization functional layer 260 is the same material as at least one layer of sub-gate mask layer away from the substrate 210. For example, the materials of the exposed second sub-gate mask layer 223 and the fourth sub-gate mask layer 233 are silicon oxide, and the material of the second planarization functional layer 260 is also silicon oxide.

[0088] S340: Remove the second planarization functional layer, part of the first planarization functional layer, and at least part of the gate mask layer to obtain a semiconductor structure.

[0089] Please refer to Figure 18 and Figure 19 . To reduce the damage of the planarization process to the gate, in this embodiment, removing the second planarization functional layer, part of the first planarization functional layer, and at least part of the gate mask layer can include: using an endpoint detection polishing process, with the surface of the sub-gate mask layer close to the substrate 210 as the detection endpoint, to polish and remove the second planarization functional layer 260, part of the first planarization functional layer, and the sub-gate mask layer with the same material as the second planarization functional layer 260. Specifically, in the case that the gate mask layer includes at least two layers of sub-gate mask layers, and the materials of the at least two layers of sub-gate mask layers are different, the material of the sub-gate mask layer close to the substrate 210 is different from that of the second planarization functional layer 260, so when the sub-gate mask layer close to the substrate 210 is exposed during polishing, the detection signal will have a large fluctuation, and then the polishing is stopped. For example, taking the surface of the first sub-gate mask layer 222 or the third sub-gate mask layer 232 away from the substrate 210 as the detection endpoint, to polish and remove the second planarization functional layer 260, the second sub-gate mask layer 223 and the fourth sub-gate mask layer 233, and to remove part of the etching stop layer 241 and the interlayer dielectric layer 252, to obtain a thinned etching stop layer 242 and a thinned interlayer dielectric layer 253. It is worth noting that the first gate transition side wall 224 and the second gate transition side wall 234 may contain the same material as the first sub-gate mask layer 222 or the third sub-gate mask layer 232, for example, silicon nitride, but due to the small amount, it will not affect the result of endpoint detection.

[0090] In some embodiments, the gate mask layer includes at least two sub-gate mask layers, but the materials of different sub-gate mask layers are the same, or in the case that the gate mask layer is a single layer structure, the second planarization functional layer 260 is the same as the material of the gate mask layer but different from the material of the gate electrode. Accordingly, the surface of the gate electrode away from the substrate 210 can be used as a detection end point, and the polishing is stopped when the surface of the gate electrode away from the substrate 210 is exposed.

[0091] One embodiment of the present application provides a semiconductor structure, which can be manufactured by the method for manufacturing a semiconductor structure according to any one of the above embodiments. The semiconductor structure can include a substrate and at least two gate structures formed on the substrate. The gate structure has a gate extension direction and a gate width direction perpendicular to the gate extension direction. The widths of different gate structures along the gate width direction are different, and the distances from the surfaces of different gate structures away from the substrate to the substrate are the same.

[0092] Referring to Figure 19 For example, the semiconductor structure 600 provided in the present embodiment is briefly described below, taking the semiconductor structure including two gate structures as an example.

[0093] In the present embodiment, the semiconductor structure 600 includes a substrate 210, a first gate structure 220a and a second gate structure 230a formed on the substrate 210, and a thinning etching stop layer 242 and a thinning interlayer dielectric layer 253 formed between the first gate structure 220a and the second gate structure 230a. The first gate structure 220a includes a first gate electrode 221 formed on the surface of the substrate 210, a first sub-gate mask layer 222 formed on the side of the first gate electrode 221 away from the substrate 210, and a first gate sidewall 225 formed on the side surfaces of the first gate electrode 221 and the first sub-gate mask layer 222. The second gate structure 230a includes a second gate electrode 231 formed on the surface of the substrate 210, a third sub-gate mask layer 232 formed on the side of the second gate electrode 231 away from the substrate 210, and a second gate sidewall 235 formed on the side surfaces of the second gate electrode 231 and the third sub-gate mask layer 232. The width of the first gate structure 220a along the gate width direction is smaller than the width of the second gate structure 230a along the gate width direction. The distance from the surface of the first gate structure 220a away from the substrate 210 to the substrate 210 is equal to the distance from the surface of the second gate structure 230a away from the substrate 210 to the substrate 210.

[0094] In the embodiments of the present application, for a substrate including a substrate and at least two gate transition structures with different widths and different distances from the surface of the substrate to the substrate, a first planarization functional layer is first formed on the surface of the substrate to obtain a transition substrate in which a gate mask layer of at least part of the gate transition structures is exposed, then a second planarization functional layer with the same material as the exposed gate mask layer is formed on the surface of the transition substrate, and finally the second planarization functional layer, part of the first planarization functional layer and the exposed gate mask layer are removed to obtain a semiconductor structure including the substrate and at least two gate structures with the same distance from the surface of the substrate to the substrate, and the unexpected technical effects achieved include: since the second planarization functional layer has the same material as the exposed gate mask layer in the transition substrate, the height difference between the gate transition structures with different widths is eliminated by using the second planarization functional layer first, and then the second planarization functional layer, part of the first planarization functional layer and the exposed gate mask layer are removed by using one process, so that the process of eliminating the height difference between the gate structures with different widths is simplified, and the process complexity is reduced.

[0095] It can be understood that the specific examples in the present application are only to help those skilled in the art better understand the embodiments of the present application, and not to limit the scope of the present application.

[0096] It can be understood that in various embodiments in the present application, the size of the serial number of each process does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0097] It can be understood that the various embodiments described in the present application can be implemented alone or in combination, and the embodiments of the present application do not limit this.

[0098] Unless otherwise specified, all technical and scientific terms used in the embodiments of the present application have the same meanings as those commonly understood by those skilled in the art of the present application. The terms used in the present application are only for the purpose of describing the specific embodiments and are not intended to limit the scope of the present application. The term "and / or" used in the present application includes any and all combinations of one or more related listed items. The singular forms "a", "an" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0099] In several embodiments provided in the present application, it should be understood that the disclosed semiconductor structure can be implemented in other ways. For example, the above-described embodiments of the semiconductor structure are only illustrative.

[0100] The above merely provides the specific embodiments of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method of manufacturing a semiconductor structure, characterized by, The method comprises the following steps: providing a substrate; wherein the substrate comprises a substrate and at least two gate transition structures formed on the substrate; the gate transition structure comprises a gate and a gate mask layer; the gate transition structure has a gate extension direction and a gate width direction perpendicular to the gate extension direction; different gate transition structures have different widths along the gate width direction; and different gate transition structures have different distances from the surface of the substrate to the substrate; forming a first planarization functional layer on the surface of the substrate to obtain a transition substrate; wherein in the transition substrate, at least part of the gate mask layer is exposed; forming a second planarization functional layer on the surface of the transition substrate; wherein the second planarization functional layer is the same material as the exposed gate mask layer; removing the second planarization functional layer, part of the first planarization functional layer and at least part of the gate mask layer to obtain the semiconductor structure; wherein the semiconductor structure comprises at least two gate structures formed on the substrate, and different gate structures have the same distance from the surface of the substrate to the substrate.

2. The method of claim 1, wherein, The gate mask layer comprises at least two sub-gate mask layers; in the case that the materials of the at least two sub-gate mask layers are different, the second planarization functional layer is the same material as at least one sub-gate mask layer away from the substrate.

3. The method of claim 2, wherein, In the at least two sub-gate mask layers, the material of the sub-gate mask layer away from the substrate is silicon oxide; and the material of the sub-gate mask layer close to the substrate is silicon nitride.

4. The method of claim 2, wherein, The step of removing the second planarization functional layer, part of the first planarization functional layer and at least part of the gate mask layer comprises: using an endpoint detection polishing process to remove the second planarization functional layer, part of the first planarization functional layer and the sub-gate mask layer with the same material as the second planarization functional layer as the detection endpoint, wherein the sub-gate mask layer close to the substrate is away from the surface of the substrate.

5. The method of claim 1, wherein, The step of forming a second planarization functional layer on the surface of the transition substrate comprises: forming the second planarization functional layer on the surface of the transition substrate by using a flow control chemical vapor deposition process or a spin coating process; wherein the second planarization functional layer on the surface of different gate transition structures has the same distance from the surface of the substrate to the substrate.

6. The method of claim 1, wherein, The first planarization functional layer comprises an etching stop layer and an interlayer dielectric layer; the step of forming a first planarization functional layer on the surface of the substrate to obtain a transition substrate comprises: forming an initial etching stop layer and an initial dielectric layer on the surface of the substrate in sequence; thinning the initial dielectric layer to form the interlayer dielectric layer; removing part of the initial etching stop layer to form the etching stop layer to obtain the transition substrate.

7. The method of claim 6, wherein, The material of the etching stop layer is silicon nitride; and the material of the interlayer dielectric layer is silicon oxide.

8. The method of claim 6, wherein, The at least two gate transition structures include a first gate transition structure and a second gate transition structure; in the substrate and the transition substrate, the first gate transition structure is farther away from the surface of the substrate than the second gate transition structure. The step of thinning the initial dielectric layer to form the interlayer dielectric layer includes: The step of thinning the initial dielectric layer to form the interlayer dielectric layer includes: The step of thinning the initial dielectric layer to form the interlayer dielectric layer includes: The step of thinning the initial dielectric layer to form the interlayer dielectric layer includes: Correspondingly, removing part of the initial etching stop layer includes:

9. The method of claim 6, wherein, The step of thinning the initial dielectric layer to form the interlayer dielectric layer includes:

10. A semiconductor structure, characterized by The interlayer dielectric layer is farther away from the surface of the substrate than the gate structure. The semiconductor structure is manufactured by the method for manufacturing a semiconductor structure according to any one of claims 1-9, and the semiconductor structure includes: a substrate; at least two gate structures formed on the substrate; wherein the gate structure has a gate extension direction and a gate width direction perpendicular to the gate extension direction; different gate structures have different widths along the gate width direction; and different gate structures are the same distance away from the surface of the substrate. at least two gate structures formed on the substrate; wherein the gate structure has a gate extension direction and a gate width direction perpendicular to the gate extension direction; different gate structures have different widths along the gate width direction; and different gate structures are the same distance away from the surface of the substrate.

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