Method of manufacturing a semiconductor structure and semiconductor structure

Abstract

Embodiments of the present application provide a semiconductor structure manufacturing method and a semiconductor structure. The method comprises: providing a base including a substrate and at least two gate transition structures formed on the substrate; the gate transition structure includes a gate and a gate mask layer, and has a gate extension direction and a gate width direction perpendicular to the gate extension direction; the widths of different gate transition structures are different; the distances from the surfaces of different gate transition structures to the substrate are different; forming a first planarization functional layer on the surface of the base to obtain a transition base in which at least part of the gate mask layer is exposed; forming a second planarization functional layer on the surface of the transition base, the second planarization functional layer being made of the same material as the exposed gate mask layer; removing the second planarization functional layer and at least part of the gate mask layer to obtain a semiconductor structure in which the distances from the surfaces of different gate structures to the substrate are the same. Through the embodiments of the present application, the process of eliminating the height difference between gate structures with different widths is simplified.

Description

Technical Field

[0001] The embodiments in this application relate to the field of semiconductor manufacturing technology, specifically to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Technology

[0002] In the design and manufacturing of CMOS (Complementary Metal-Oxide-Semiconductor) transistors, gates of varying widths are required to meet diverse current control needs and optimize circuit performance and overall CMOS transistor performance. However, due to the influence of the front end of line (FEOL) process, the height of a wider gate is usually greater than that of a narrower gate.

[0003] However, the height difference between different gates may cause local depressions or protrusions, which can reduce the formation quality of subsequent structures. In order to reduce the adverse effects of different gate height differences on the accuracy of subsequent processes and improve the stability of CMOS transistor performance, it is necessary to eliminate the height difference between gates of different widths and achieve the height consistency of gates of different widths.

[0004] In existing technologies, multiple processes such as photolithography, etching, and chemical mechanical polishing (CMP) are required to eliminate the height difference between gates of different widths, making the process quite complex. Summary of the Invention

[0005] In view of this, several embodiments of this application provide a method for manufacturing a semiconductor structure and a semiconductor structure to simplify the process for eliminating height differences between gates of different widths.

[0006] In one aspect, an embodiment of this application provides a method for manufacturing a semiconductor structure, comprising: providing a substrate; wherein the substrate includes a substrate and at least two gate transition structures formed on the substrate; the gate transition structure includes a gate and a gate mask layer; the gate transition structure has a gate extension direction and a gate width direction perpendicular to the gate extension direction; different gate transition structures have different widths along the gate width direction; different gate transition structures have different distances from their surfaces away from the substrate to the substrate; forming a first planarization functional layer on the surface of the substrate to obtain a transition substrate; wherein at least a portion of the gate mask layer is exposed in the transition substrate; forming a second planarization functional layer on the surface of the transition substrate; wherein the second planarization functional layer is made of the same material as the exposed gate mask layer; removing the second planarization functional layer, a portion of the first planarization functional layer, and at least a portion of the gate mask layer to obtain the semiconductor structure; wherein the semiconductor structure includes at least two gate structures formed on the substrate, and the different gate structures have the same distance from their surfaces away from the substrate to the substrate.

[0007] Optionally, the gate mask layer includes at least two sub-gate mask layers, and if the materials of the at least two sub-gate mask layers are different, the second planarization functional layer is made of the same material as at least one of the sub-gate mask layers located away from the substrate.

[0008] Optionally, in the at least two sub-gate mask layers, the material of the sub-gate mask layer farther from the substrate is silicon oxide; and the material of the sub-gate mask layer closer to the substrate is silicon nitride.

[0009] Optionally, removing the second planarization functional layer, a portion of the first planarization functional layer, and at least a portion of the gate mask layer includes: using an endpoint detection grinding process, with the surface of the sub-gate mask layer near the substrate away from the substrate as the detection endpoint, grinding to remove the second planarization functional layer, a portion of the first planarization functional layer, and the sub-gate mask layer made of the same material as the second planarization functional layer.

[0010] Optionally, the step of forming a second planarization functional layer on the surface of the transition substrate includes: forming the second planarization functional layer on the surface of the transition substrate using a flow-controlled chemical vapor deposition process or a spin coating process; wherein the distance from the surface of the second planarization functional layer away from the substrate to the substrate is the same for different gate transition structure surfaces.

[0011] Optionally, the first planarization functional layer includes an etch stop layer and an interlayer dielectric layer; the step of forming the first planarization functional layer on the substrate surface to obtain a transition substrate includes: sequentially forming an initial etch stop layer and an initial dielectric layer on the substrate surface; thinning the initial dielectric layer to form the interlayer dielectric layer; removing a portion of the initial etch stop layer to form the etch stop layer, thereby obtaining the transition substrate.

[0012] Optionally, the etch stop layer is made of silicon nitride; the interlayer dielectric layer is made of silicon oxide.

[0013] Optionally, the at least two gate transition structures include a first gate transition structure and a second gate transition structure; in the substrate and the transition substrate, the distance from the surface of the first gate transition structure away from the substrate to the substrate is greater than the distance from the surface of the second gate transition structure away from the substrate to the substrate; the step of thinning the initial dielectric layer to form the interlayer dielectric layer includes: using an endpoint detection polishing process, with the surface of the initial etch stop layer on the surface of the second gate transition structure away from the substrate as the detection endpoint, polishing the initial dielectric layer until the initial etch stop layer on the surface of the second gate transition structure is exposed, to form a transition dielectric layer; using a dry etching process to etch the transition dielectric layer until the initial etch stop layer on the surfaces of the at least two gate transition structures is exposed, to form the interlayer dielectric layer; correspondingly, removing a portion of the initial etch stop layer includes: using an etching process to etch the initial etch stop layer until at least a portion of the gate mask layer of the at least two gate transition structures is exposed.

[0014] Optionally, the distance from the surface of the interlayer dielectric layer away from the substrate to the substrate is greater than the distance from the surface of the gate away from the substrate to the substrate.

[0015] In another aspect, one embodiment of this application provides a semiconductor structure manufactured by the semiconductor structure manufacturing method described in the above embodiments. The semiconductor structure includes: a substrate; at least two gate structures formed on the substrate; wherein the gate structures have a gate extension direction and a gate width direction perpendicular to the gate extension direction; different gate structures have different widths along the gate width direction; and the surfaces of different gate structures away from the substrate are at the same distance from the substrate.

[0016] In several embodiments of this application, a substrate including a substrate and at least two gate transition structures is provided. Each gate transition structure includes a gate and a gate mask layer. Different gate transition structures have different widths and different distances from the surface of the gate transition structure furthest from the substrate to the substrate. A transition substrate is obtained by first forming a first planarization functional layer on the substrate surface, exposing at least a portion of the gate mask layer in the transition substrate, and then forming a second planarization functional layer on the transition substrate surface with the same material as the exposed gate mask layer. The second planarization functional layer, a portion of the first planarization functional layer, and at least a portion of the gate mask layer are then removed to obtain a semiconductor structure including a substrate and at least two gate structures. The unexpected effect achieved is that, since the second planarization functional layer and the exposed gate mask layer in the transition substrate are made of the same material, the height difference between gate transition structures of different widths is eliminated first using the second planarization functional layer. Then, a single process is used to remove the second planarization functional layer, a portion of the first planarization functional layer, and the exposed gate mask layer, achieving height consistency for gate structures of different widths and simplifying the process of eliminating height differences between gates of different widths. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in describing the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A schematic diagram of the structure of a semiconductor substrate provided for related technologies.

[0019] Figure 2 A schematic diagram illustrating the formation of a buffer layer on the surface of a semiconductor substrate, provided for related technologies.

[0020] Figure 3 This is a schematic diagram illustrating the exposure and development of the bottom anti-reflective coating and photoresist layer on the surface of the buffer layer, provided for related technologies.

[0021] Figure 4 A schematic diagram illustrating the removal of the photoresist layer for related technologies.

[0022] Figure 5 A schematic diagram illustrating the removal of a portion of the bottom anti-reflective coating, provided for related technologies.

[0023] Figure 6 A schematic diagram illustrating the removal of a portion of the buffer layer and a portion of the hard mask layer, provided for related technologies.

[0024] Figure 7A schematic diagram of the structure of a transition semiconductor substrate provided for related technologies.

[0025] Figure 8 A schematic diagram illustrating the sequential formation of a stop layer and a dielectric layer on the surface of a transition semiconductor substrate, provided for related technologies.

[0026] Figure 9 A schematic diagram of the gate height structure provided for related technologies.

[0027] Figure 10 This is a schematic flowchart of a semiconductor manufacturing method provided in one embodiment of this application.

[0028] Figure 11 A schematic diagram of the structure of a substrate provided for one embodiment of this application.

[0029] Figure 12 This is a schematic diagram of the process for forming a first planarization functional layer on a substrate surface, provided as an embodiment of this application.

[0030] Figure 13 This is a schematic diagram of forming an initial etch stop layer on the substrate surface, provided as an embodiment of this application.

[0031] Figure 14 This is a schematic diagram of forming an initial dielectric layer on the surface of an initial etch stop layer, provided as an embodiment of this application.

[0032] Figure 15 This is a schematic diagram of the formation of a transition dielectric layer by grinding an initial dielectric layer, provided as an embodiment of this application.

[0033] Figure 16 This is a schematic diagram of an etched transition dielectric layer forming an interlayer dielectric layer, provided as an embodiment of this application.

[0034] Figure 17 This is a schematic diagram of the structure of a transition substrate provided in one embodiment of this application.

[0035] Figure 18 This is a schematic diagram of forming a second planarization functional layer on the surface of a transition substrate, provided as an embodiment of this application.

[0036] Figure 19 This is a schematic diagram of a semiconductor structure provided in one embodiment of this application.

[0037] Structural designation explanation

[0038] 100. Semiconductor substrate; 200. Transition semiconductor substrate; 300. Gate height structure; 400. Substrate; 500. Transition substrate; 600. Semiconductor structure; 110. Semiconductor substrate; 121. First dummy gate; 122. First bottom hard mask layer; 123. First top hard mask layer; 124. First initial sidewall; 125. First sidewall; 131. Second dummy gate; 132. Second bottom hard mask layer; 133. Second top hard mask layer; 134. Second initial sidewall; 135. Second sidewall; 140. Initial buffer layer; 141. Buffer layer; 150. Bottom anti-reflective coating; 151. Thinned bottom anti-reflective coating; 160. Photoresist layer; 170. Initial stop layer; 171. Stop layer; 180. Initial dielectric layer; 181. 210. Dielectric layer; 220. Substrate; 220. First gate transition structure; 220a. First gate structure; 221. First gate; 222. First sub-gate mask layer; 223. Second sub-gate mask layer; 224. First gate transition sidewall; 225. First gate sidewall; 230. Second gate transition structure; 230a. Second gate structure; 231. Second gate; 232. Third sub-gate mask layer; 233. Fourth sub-gate mask layer; 234. Second gate transition sidewall; 235. Second gate sidewall; 240. Initial etch stop layer; 241. Etch stop layer; 242. Thinning etch stop layer; 250. Initial dielectric layer; 251. Transition dielectric layer; 252. Interlayer dielectric layer; 253. Thinning interlayer dielectric layer; 260. Second planarization functional layer. Detailed Implementation

[0039] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0040] The accompanying drawings provided in this application are only schematic illustrations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component may be changed, and the layout of the components may also be more complex.

[0041] In the description of the embodiments of this application, it should be understood that the terms "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," "center," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" and "second" may explicitly or implicitly include one or more of the stated features.

[0042] As semiconductor process nodes continue to shrink, to improve the device performance of CMOS transistors, related technologies typically employ a back-gate process to form high-dielectric-constant metal gates during CMOS transistor manufacturing. This involves first forming dummy gates, and then replacing them with the metal gate. To meet the diverse current control requirements of CMOS transistors used to implement different functions, in some cases, it is necessary to form at least two dummy gates with different widths on the CMOS transistor substrate. After the dummy gates are formed, a hard mask layer is then formed on their surface to protect them from damage during subsequent processes.

[0043] Due to edge effects and material stacking characteristics, the hard mask layer on dummy gate surfaces of different widths suffers different losses during the front-end process. Therefore, in the semiconductor substrate obtained after the front-end process, the thickness of the hard mask layer on dummy gate surfaces of different widths is different.

[0044] Please see Figure 1 Taking a semiconductor substrate 100 comprising two dummy gates of different widths as an example, the semiconductor substrate 100 includes a semiconductor substrate 110 and a first dummy gate structure and a second dummy gate structure formed on the surface of the semiconductor substrate 110. The first dummy gate structure includes a first dummy gate 121, a first bottom hard mask layer 122 and a first top hard mask layer 123 sequentially formed on the side of the first dummy gate 121 away from the semiconductor substrate 110, and a first initial sidewall 124 formed on the side of the first dummy gate 121. The second dummy gate structure includes a second dummy gate 131, a second bottom hard mask layer 132 and a second top hard mask layer 133 sequentially formed on the side of the second dummy gate 131 away from the semiconductor substrate 110, and a second initial sidewall 134 formed on the side of the second dummy gate 131.

[0045] The semiconductor substrate 100 has a dummy gate extension direction and a width direction perpendicular to the dummy gate extension direction. The width of the first dummy gate 121 along the width direction is smaller than the width of the second dummy gate 131 along the width direction, and the distance from the surface of the first dummy gate 121 away from the semiconductor substrate 110 to the semiconductor substrate 110 is equal to the distance from the surface of the second dummy gate 131 away from the semiconductor substrate 110 to the semiconductor substrate 110.

[0046] Since the top hard mask layer protects the bottom hard mask layer in the front-end process, the edge effect only affects the top hard mask layer. Specifically, the distance from the surface of the first bottom hard mask layer 122 away from the semiconductor substrate 110 is equal to the distance from the surface of the second bottom hard mask layer 132 away from the semiconductor substrate 110. However, the distance from the surface of the first top hard mask layer 123 away from the semiconductor substrate 110 is less than the distance from the surface of the second top hard mask layer 133 away from the semiconductor substrate 110. Therefore, the height difference between the first and second dummy gate structures along the dummy gate extension direction is actually caused by the thickness difference between the first and second top hard mask layers 123 and 133 along the dummy gate extension direction.

[0047] During the removal of dummy gates, the height difference between the first and second dummy gate structures along the dummy gate extension direction may cause a large depression in the dielectric layer between the two dummy gate structures, resulting in residual metal in subsequent processes and reducing the electrical performance of the CMOS transistor.

[0048] To reduce the negative impact of the height difference between two dummy gate structures on the performance of CMOS transistors, related technologies typically utilize processes such as photolithography, etching, deposition, and chemical mechanical polishing to eliminate the thickness difference between the two top hard mask layers. The following combines... Figures 2 to 9 This paper provides a brief introduction to the process of eliminating the thickness difference between two top hard mask layers in related technologies.

[0049] Please see Figure 2 First, an initial buffer layer 140 is formed on the surface of the semiconductor substrate 100 to protect the first dummy gate 121 and the second dummy gate 131 during subsequent processes. The initial buffer layer 140 may be made of an oxide.

[0050] Please see Figure 3Next, an initial bottom anti-reflection coating (BARC) and an initial photoresist layer are sequentially formed on the surface of the initial buffer layer 140. A portion of the initial photoresist layer on the side of the second dummy gate 131 away from the semiconductor substrate 110 is removed by exposure and development, resulting in a photoresist layer 160. The photoresist layer 160 is then used as a mask for the initial bottom anti-reflection coating, and a portion of the initial bottom anti-reflection coating on the side of the second dummy gate 131 away from the semiconductor substrate 110 is removed, resulting in a bottom anti-reflection coating 150. Due to edge effects, protrusions may occur at positions corresponding to the edge of the second dummy gate 131 in both the photoresist layer 160 and the bottom anti-reflection coating 150.

[0051] Please refer to the following: Figure 3 and Figure 4 Subsequently, the photoresist layer 160 is removed using processes such as solvent cleaning or plasma etching, leaving only the bottom anti-reflective coating 150.

[0052] Please refer to the following: Figure 4 and Figure 5 Next, the bottom anti-reflective coating 150 is thinned using processes such as plasma etching until the initial buffer layer 140 on the side of the first dummy gate 121 and the second dummy gate 131 away from the semiconductor substrate 110 is exposed, thus obtaining the thinned bottom anti-reflective coating 151.

[0053] Please refer to the following: Figure 5 and Figure 6 Next, a portion of the exposed initial buffer layer 140 is removed using a dry etching process to obtain a buffer layer 141. Then, the first top hard mask layer 123 and the second top hard mask layer 133 are removed using the same dry etching process to eliminate the thickness difference between them. By controlling the etch selectivity and etch time, damage to the first bottom hard mask layer 122 and the second bottom hard mask layer 132 can be reduced while completely removing a portion of the initial buffer layer 140, the first top hard mask layer 123, and the second top hard mask layer 133.

[0054] Please refer to the following: Figure 6 and Figure 7 After the first bottom hard mask layer 122 and the second bottom hard mask layer 132 are exposed, a dry etching process is used to remove the first bottom hard mask layer 122, the second bottom hard mask layer 132, the buffer layer 141, and the thinned bottom anti-reflective coating 151 to obtain the transition semiconductor substrate 200. By controlling the etch selectivity and etch time, damage to the first initial sidewall 124 and the second initial sidewall 134 is reduced while completely removing the first bottom hard mask layer 122, the second bottom hard mask layer 132, the buffer layer 141, and the thinned bottom anti-reflective coating 151.

[0055] Depend on Figure 7 It can be seen that the thickness difference between the first top hard mask layer and the second top hard mask layer extends to the first initial sidewall 124 and the second initial sidewall 134. Please refer to both. Figures 7 to 9 To eliminate the thickness difference between the first initial sidewall 124 and the second initial sidewall 134, an initial stop layer 170 and an initial dielectric layer 180 are sequentially formed on the surface of the transition semiconductor substrate 200, and then planarized using a chemical mechanical polishing process to obtain a gate-level structure 300. Specifically, the gate-level structure 300 includes a semiconductor substrate 110, a first dummy gate 121, a first sidewall 125, a second dummy gate 131, a second sidewall 135, a stop layer 171, and a dielectric layer 181.

[0056] Since the hard mask layers on the surfaces of the first dummy gate 121 and the second dummy gate 131 are both removed, the surfaces of the first dummy gate 121 and the second dummy gate 131 that are away from the semiconductor substrate 110 are exposed, and the distances from the two to the semiconductor substrate 110 are equal. Therefore, in the gate equal-height structure 300, the effect of the thickness difference between the first top hard mask layer and the second top hard mask layer on the subsequent process has been eliminated.

[0057] Please refer to the following: Figure 1 and Figure 6 However, in actual manufacturing, researchers found through measurements of the semiconductor substrate 100 that there is a significant thickness difference between the first top hard mask layer 123 and the second top hard mask layer 133. For example, the thickness of the first top hard mask layer 123 along the thickness direction is 20 Å, and the thickness of the second top hard mask layer 133 along the thickness direction is 100 Å. In this case, a longer etching time is required to completely remove the second top hard mask layer 133 during the dry etching process. However, for the first top hard mask layer 123, the longer etching time will lead to over-etching, which may cause damage to the first bottom hard mask layer 122 or even the first dummy gate 121, and may also reduce the subsequent process window, resulting in a decrease in the production yield of CMOS transistors.

[0058] In summary, in the relevant technologies, the process steps to eliminate the thickness difference between the two top hard mask layers are numerous and the process complexity is high. Furthermore, it may cause the subsequent process window to shrink, leading to a decrease in the yield of CMOS transistor production.

[0059] Therefore, for a substrate including a substrate and at least two gate transition structures with different widths and different distances from the substrate, it is necessary to provide a method for manufacturing a semiconductor structure. This method involves first forming a first planarization functional layer on the substrate surface to obtain a transition substrate, exposing a gate mask layer of at least part of the gate transition structure in the transition substrate, and then forming a second planarization functional layer on the transition substrate surface with the same material as the exposed gate mask layer. The second planarization functional layer is used to eliminate the height difference between gate transition structures of different widths, and the second planarization functional layer, part of the first planarization functional layer, and the exposed gate mask layer are removed in one step to simplify the process of eliminating the height difference between gates of different widths.

[0060] Please see Figure 10 One embodiment of this application provides a method for manufacturing a semiconductor structure. The method for manufacturing the semiconductor structure may include steps S310, S320, S330, and S340.

[0061] S310: Provides a substrate.

[0062] In this embodiment, the substrate may include a substrate and at least two gate transition structures formed on the substrate.

[0063] In this embodiment, the substrate can serve as the basis for forming CMOS transistors. Specifically, N-wells (NW) and P-wells (PW) can be defined in the substrate first. After the N-wells and P-wells are formed, the location of the active area (AA) can be defined, and a separation region can be formed in the substrate. For example, the separation region can be a shallow trench isolation (STI) structure to reduce leakage current. Subsequently, different types of dopant ions can be implanted into various regions of the substrate to form lightly doped source / drain regions (LDD), pocket doped regions, and source / drain regions (S / D) in the substrate, thus obtaining the substrate. The substrate can be constructed from semiconductor materials, insulating materials, conductive materials, or any combination thereof. For example, the substrate can be made of silicon (Si), silicon-germanium (SiGe), silicon-germanium-carbon (SiGeC), silicon carbide (SiC), etc. The substrate can be a single-layer structure or a multi-layer structure. In this embodiment, considering factors such as dielectric loss requirements, manufacturing process, and manufacturing cost, a silicon wafer is used as the substrate.

[0064] In this embodiment, the gate transition structure can be used to determine the location of the gate during the CMOS transistor manufacturing process. Specifically, the gate transition structure may include a gate and a gate mask layer formed on the side of the gate away from the substrate. In addition to the gate and the gate mask layer, the gate transition structure may also include gate transition sidewalls formed on the sides of the gate and the gate mask layer, which can be used to protect the gate and the gate mask layer from the side. The gate material can be polysilicon, and the gate transition sidewall material can be silicon oxide (SiO2), silicon nitride (Si3N4), or other materials.

[0065] In this embodiment, the gate transition structure may have a gate extension direction and a gate width direction perpendicular to the gate extension direction. To meet the design requirements of CMOS transistor current control, the width of different gate transition structures along the gate width direction can be different. Specifically, since the current control function is implemented by the gate, the width of the gate transition structure along the gate width direction can be determined based on the width of the gate along the gate width direction.

[0066] In this embodiment, due to the edge effect, the distance from the surface of different gate transition structures away from the substrate is different. Specifically, since the gate mask layer corresponding to the smaller gate width experiences a relatively higher etching rate during the front-end etching process, and more of it is removed, the distance from the surface of the gate transition structure with a larger width along the gate width direction away from the substrate can be greater than the distance from the surface of the gate transition structure with a smaller width along the gate width direction away from the substrate.

[0067] In some embodiments, the gate mask layer may include at least two sub-gate mask layers. Specifically, the materials of the at least two sub-gate mask layers may be the same or different. When the number of sub-gate mask layers is greater than two, the different materials of the multiple sub-gate mask layers can be that each sub-gate mask layer is made of a different material, or that some sub-gate mask layers are made of the same material while others are made of a different material.

[0068] In this embodiment, in at least two sub-gate mask layers, the material of the sub-gate mask layer furthest from the substrate can be silicon oxide, and the material of the sub-gate mask layer closest to the substrate can be silicon nitride. Specifically, when there are two sub-gate mask layers, the material of the sub-gate mask layer furthest from the substrate can be silicon oxide, and the material of the sub-gate mask layer closest to the substrate can be silicon nitride. When there are more than two sub-gate mask layers, the material of the sub-gate mask layer furthest from the substrate can be silicon oxide, the material of the sub-gate mask layer closest to the substrate can be silicon nitride, and the material of the sub-gate mask layer between them can be one or more of silicon oxide, silicon nitride, titanium nitride, or silicon carbide nitride.

[0069] In some embodiments, the gate mask layer can be a single-layer structure. Specifically, the material of the gate mask layer can be one or more of silicon oxide, silicon nitride, titanium nitride, or silicon carbide nitride.

[0070] Please see Figure 11 Taking a substrate comprising two gate transition structures and a gate mask layer comprising two sub-gate mask layers as an example, the structure of the substrate 400 provided in this embodiment will be briefly described.

[0071] In this embodiment, the substrate 400 may include a substrate 210, a first gate transition structure 220 formed on the substrate 210, and a second gate transition structure 230. The first gate transition structure 220 includes a first gate 221 formed on the surface of the substrate 210, a first sub-gate mask layer 222 and a second sub-gate mask layer 223 sequentially formed on the side of the first gate 221 away from the substrate 210, and a first gate transition sidewall 224 formed on the sides of the first gate 221, the first sub-gate mask layer 222, and the second sub-gate mask layer 223. The second gate transition structure 230 includes a second gate 231 formed on the surface of the substrate 210, a third sub-gate mask layer 232 and a fourth sub-gate mask layer 233 sequentially formed on the side of the second gate 231 away from the substrate 210, and a second gate transition sidewall 234 formed on the sides of the second gate 231, the third sub-gate mask layer 232, and the fourth sub-gate mask layer 233.

[0072] The distance from the surface of the first gate 221 away from the substrate 210 to the substrate 210 is equal to the distance from the surface of the second gate 231 away from the substrate 210 to the substrate 210. The distance from the surface of the first sub-gate mask layer 222 away from the substrate 210 to the substrate 210 is equal to the distance from the surface of the third sub-gate mask layer 232 away from the substrate 210 to the substrate 210. Both the first gate transition structure 220 and the second gate transition structure 230 have a gate extension direction and a gate width direction perpendicular to the gate extension direction. The width of the first gate transition structure 220 along the gate width direction is smaller than the width of the second gate transition structure 230 along the gate width direction. The distance from the surface of the first gate transition structure 220 away from the substrate 210 to the substrate 210 is smaller than the distance from the surface of the second gate transition structure 230 away from the substrate 210 to the substrate 210.

[0073] S320: A first planarization functional layer is formed on the substrate surface to obtain a transition substrate.

[0074] In some embodiments, the first planarization functional layer may include an etch stop layer and an interlayer dielectric layer. Specifically, the etch stop layer can be used as the detection endpoint for Endpoint Detection (EPD) to prevent over-etching, and its material may be silicon nitride. The interlayer dielectric layer can be used to achieve isolation between different interconnect layers to reduce signal interference, and its material may be silicon oxide.

[0075] Please see Figure 12 In this embodiment, the step of forming a first planarization functional layer on the substrate surface to obtain a transition substrate may include sub-steps S321, S322, and S323.

[0076] S321: An initial etch stop layer and an initial dielectric layer are sequentially formed on the substrate surface.

[0077] Please see Figure 11 , Figure 13 and Figure 14 In this embodiment, an initial etch stop layer 240 and an initial dielectric layer 250 can be sequentially deposited on the surface of the substrate 400 using a chemical vapor deposition (CVD) process. Specifically, to improve process accuracy, the initial etch stop layer 240 can be a contact etch stop layer (CESL). To improve electrical insulation performance, the distance from the surface of the initial dielectric layer 250 away from the substrate 210 to the substrate 210 is greater than the distance from the surface of the second gate transition structure 230 away from the substrate 210 to the substrate 210.

[0078] S322: Thinning the initial dielectric layer to form an interlayer dielectric layer.

[0079] Please see Figures 14 to 16 To reduce the damage to the gate transition structure during the thinning of the initial dielectric layer 250 and improve the control accuracy of the thinning degree of the initial dielectric layer 250, in some embodiments, the step of thinning the initial dielectric layer to form an interlayer dielectric layer may include: using an endpoint detection polishing process, with the surface of the initial etch stop layer 240 on the surface of the second gate transition structure 230 away from the substrate 210 as the detection endpoint, polishing the initial dielectric layer 250 until the initial etch stop layer 240 on the surface of the second gate transition structure 230 is exposed, forming a transition dielectric layer 251; using a dry etching process to etch the transition dielectric layer 251 until the initial etch stop layers 240 on the surfaces of at least two gate transition structures are exposed, forming an interlayer dielectric layer 252.

[0080] In this embodiment, the initial dielectric layer 250 is polished using an endpoint detection polishing process. The initial dielectric layer 250 can be polished using a chemical mechanical planarization (CMP) process. When the initial etch stop layer 240 on the surface of the second gate transition structure 230 is exposed, the detection signal will fluctuate significantly, so polishing is stopped, and the thinned initial dielectric layer 250 is used as the transition dielectric layer 251. Since the distance between the initial etch stop layer 240 on the surface of the second gate transition structure 230 and the substrate 210 is greater than the distance between the initial etch stop layer 240 on the surface of the first gate transition structure 220 and the substrate 210, the portion of the initial dielectric layer 250 on the side of the first gate transition structure 220 away from the substrate 210 that is ground away may be greater than the portion of the initial dielectric layer 250 on the side of the second gate transition structure 230 away from the substrate 210 that is ground away. Therefore, the distance from the surface of the transition dielectric layer 251 at the position of the first gate transition structure 220 away from the substrate 210 to the substrate 210 may be less than the distance from the surface of the transition dielectric layer 251 at the position of the second gate transition structure 230 away from the substrate 210 to the substrate 210.

[0081] In this embodiment, the distance from the surface of the interlayer dielectric layer 252 away from the substrate 210 to the substrate 210 can be greater than the distance from the surface of the gate away from the substrate 210 to the substrate 210. Specifically, since the distance from the surface of the first gate 221 away from the substrate 210 to the substrate 210 is equal to the distance from the surface of the second gate 231 away from the substrate 210 to the substrate 210, in order to reduce the risk of reduced production yield due to the shrinkage of the subsequent process window, the distance from the surface of the interlayer dielectric layer 252 away from the substrate 210 to the substrate 210 is at least greater than the distance from the surface of the gate away from the substrate 210 to the substrate 210.

[0082] In some embodiments, since the distance from the surface of the first sub-gate mask layer 222 away from the substrate 210 to the substrate 210 is equal to the distance from the surface of the third sub-gate mask layer 232 away from the substrate 210 to the substrate 210, when the materials of the first sub-gate mask layer 222 and the second sub-gate mask layer 223 are different, and the materials of the third sub-gate mask layer 232 and the fourth sub-gate mask layer 233 are different, the distance from the surface of the interlayer dielectric layer 252 away from the substrate 210 to the substrate 210 can be greater than the distance from the surface of the first sub-gate mask layer 222 or the third sub-gate mask layer 232 away from the substrate 210 to the substrate 210.

[0083] S323: Remove part of the initial etch stop layer to form an etch stop layer and obtain a transition substrate.

[0084] Please refer to the following: Figure 16 and Figure 17To simplify the process of eliminating the height difference between different gate transition structures along the gate extension direction, it is necessary to expose the second sub-gate mask layer 223 and the fourth sub-gate mask layer 233. In this embodiment, removing part of the initial etch stop layer may include etching the initial etch stop layer 240 using an etching process until at least a portion of the gate mask layers of at least two gate transition structures are exposed. For example, the exposed initial etch stop layer 240 may be removed using a dry etching process until the second sub-gate mask layer 223 of the first gate transition structure 220 and the fourth sub-gate mask layer 233 of the second gate transition structure 230 are exposed.

[0085] Since the height difference between the first gate transition structure 220 and the second gate transition structure 230 along the gate extension direction has not been eliminated in the above sub-steps S321 to S323, the distance from the surface of the first gate transition structure 220 away from the substrate 210 to the substrate 210 is still less than the distance from the surface of the second gate transition structure 230 away from the substrate 210 to the substrate 210 in the transition substrate 500.

[0086] S330: A second planarization functional layer is formed on the surface of the transition substrate.

[0087] Please refer to the following: Figure 17 and Figure 18 To avoid the reduction of subsequent process windows due to inconsistencies in the performance of different gate transition structures during planarization, a second planarization functional layer 260 can be formed on the surface of the transition substrate 500. This second planarization functional layer 260 can eliminate the height difference between different gate transition structures along the gate extension direction and provide redundancy for subsequent planarization processes. To improve the formation quality of the second planarization functional layer 260 and thus the process quality of subsequent planarization, in this embodiment, the step of forming the second planarization functional layer on the surface of the transition substrate can include: forming the second planarization functional layer 260 on the surface of the transition substrate 500 using a flow-controlled chemical vapor deposition (FCVD) process or a spin coating process. Specifically, the distance from the surface of the second planarization functional layer 260 away from the substrate 210 on the surfaces of different gate transition structures is the same.

[0088] To simplify the process of eliminating the height difference between different gate transition structures along the gate extension direction, a single step is required to remove the second planarization functional layer 260 and the exposed gate mask layer. Therefore, in this embodiment, the second planarization functional layer 260 is made of the same material as the exposed gate mask layer. Specifically, when the gate mask layer includes at least two sub-gate mask layers, and the materials of the at least two sub-gate mask layers are different, the second planarization functional layer 260 is made of the same material as at least one sub-gate mask layer away from the substrate 210. For example, if the exposed second sub-gate mask layer 223 and fourth sub-gate mask layer 233 are made of silicon oxide, then the material of the second planarization functional layer 260 is also silicon oxide.

[0089] S340: Remove the second planarization functional layer, part of the first planarization functional layer, and at least part of the gate mask layer to obtain a semiconductor structure.

[0090] Please refer to the following: Figure 18 and Figure 19 To reduce damage to the gate during planarization, in this embodiment, removing the second planarization functional layer, a portion of the first planarization functional layer, and at least a portion of the gate mask layer may include: using an endpoint detection polishing process, with the surface of the sub-gate mask layer near the substrate 210 away from the substrate 210 as the detection endpoint, polishing to remove the second planarization functional layer 260, a portion of the first planarization functional layer, and a sub-gate mask layer made of the same material as the second planarization functional layer 260. Specifically, when the gate mask layer includes at least two sub-gate mask layers, and the materials of the at least two sub-gate mask layers are different, the sub-gate mask layer near the substrate 210 is made of a different material than the second planarization functional layer 260. Therefore, when polishing reaches the point where the sub-gate mask layer near the substrate 210 is exposed, the detection signal will fluctuate significantly, and polishing will be stopped. For example, using the surface of the first sub-gate mask layer 222 or the third sub-gate mask layer 232 furthest from the substrate 210 as the detection endpoint, the second planarization functional layer 260, the second sub-gate mask layer 223, and the fourth sub-gate mask layer 233 are removed by grinding, and a portion of the etch stop layer 241 and the interlayer dielectric layer 252 are removed, resulting in a thinned etch stop layer 242 and a thinned interlayer dielectric layer 253. It is worth noting that the first gate transition sidewall 224 and the second gate transition sidewall 234 may contain the same material as the first sub-gate mask layer 222 or the third sub-gate mask layer 232, such as silicon nitride, but because the content is small, it will not affect the endpoint detection results.

[0091] In some embodiments, when the gate mask layer includes at least two sub-gate mask layers, but the different sub-gate mask layers are made of the same material, or when the gate mask layer is a single-layer structure, the second planarization functional layer 260 is made of the same material as the gate mask layer, but different material from the gate. Accordingly, the surface of the gate away from the substrate 210 can be used as the detection endpoint, and grinding can be stopped when the surface of the gate away from the substrate 210 is exposed.

[0092] One embodiment of this application provides a semiconductor structure that can be manufactured by the semiconductor structure manufacturing method described in any of the above embodiments. The semiconductor structure may include: a substrate and at least two gate structures formed on the substrate. Each gate structure has a gate extension direction and a gate width direction perpendicular to the gate extension direction. Different gate structures have different widths along the gate width direction, and the distance from the surface of each gate structure away from the substrate to the substrate is the same.

[0093] Please see Figure 19 Taking a semiconductor structure including two gate structures as an example, the semiconductor structure 600 provided in this embodiment will be briefly described.

[0094] In this embodiment, the semiconductor structure 600 includes a substrate 210, a first gate structure 220a and a second gate structure 230a formed on the substrate 210, and a thinning etch stop layer 242 and a thinning interlayer dielectric layer 253 formed between the first gate structure 220a and the second gate structure 230a. The first gate structure 220a includes a first gate 221 formed on the surface of the substrate 210, a first sub-gate mask layer 222 formed on the side of the first gate 221 away from the substrate 210, and a first gate sidewall 225 formed on the sides of the first gate 221 and the first sub-gate mask layer 222. The second gate structure 230a includes a second gate 231 formed on the surface of the substrate 210, a third sub-gate mask layer 232 formed on the side of the second gate 231 away from the substrate 210, and a second gate sidewall 235 formed on the sides of the second gate 231 and the third sub-gate mask layer 232. The width of the first gate structure 220a along the gate width direction is smaller than the width of the second gate structure 230a along the gate width direction. The distance from the surface of the first gate structure 220a away from the substrate 210 to the substrate 210 is equal to the distance from the surface of the second gate structure 230a away from the substrate 210 to the substrate 210.

[0095] In this embodiment, for a substrate comprising a substrate and at least two gate transition structures with different widths and different distances from the substrate to their surfaces, a transition substrate is obtained by first forming a first planarization functional layer on the substrate surface, exposing a gate mask layer of at least a portion of the gate transition structure in the transition substrate, then forming a second planarization functional layer on the transition substrate surface with the same material as the exposed gate mask layer, and finally removing the second planarization functional layer, a portion of the first planarization functional layer, and the exposed gate mask layer to obtain a semiconductor structure comprising a substrate and at least two gate structures. The unexpected technical effects achieved include: since the second planarization functional layer and the exposed gate mask layer in the transition substrate are made of the same material, the height difference between gate transition structures of different widths is first eliminated using the second planarization functional layer, and then the second planarization functional layer, a portion of the first planarization functional layer, and the exposed gate mask layer are removed in a single process, thereby simplifying the process of eliminating the height difference between gate structures of different widths and reducing process complexity.

[0096] It is understood that the specific examples in this application are only intended to help those skilled in the art better understand the embodiments of this application, and are not intended to limit the scope of this application.

[0097] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this application in any way.

[0098] It is understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited in this respect.

[0099] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0100] As should be understood from the several embodiments provided in this application, the disclosed semiconductor structure can be implemented in other ways. For example, the embodiments of the semiconductor structure described above are merely illustrative.

[0101] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided; wherein the substrate includes a substrate and at least two gate transition structures formed on the substrate; the gate transition structure includes a gate, a gate mask layer, and gate transition sidewalls formed on the sides of the gate and the gate mask layer; the gate transition structure has a gate extension direction and a gate width direction perpendicular to the gate extension direction; different gate transition structures have different widths along the gate width direction; different gate transition structures have different distances from the surface away from the substrate to the substrate; with the gate extension direction as the thickness direction, the thickness of the gate mask layer along the thickness direction is positively correlated with the width of the gate transition structure along the gate width direction; the gate mask layer includes at least two sub-gate mask layers; Forming a first planarization functional layer on the surface of the substrate to obtain a transition substrate includes: sequentially forming an initial etch stop layer and an initial dielectric layer on the surface of the substrate; thinning the initial dielectric layer to form an interlayer dielectric layer; removing a portion of the initial etch stop layer to form the etch stop layer, thereby obtaining the transition substrate; wherein the first planarization functional layer includes an etch stop layer and an interlayer dielectric layer; removing a portion of the initial etch stop layer includes: selectively removing the initial etch stop layer using an etching process, while retaining the gate transition sidewalls, until at least a portion of the gate mask layer of the at least two gate transition structures is exposed; A second planarization functional layer is formed on the surface of the transition substrate; wherein the second planarization functional layer is made of the same material as the exposed gate mask layer; Using an endpoint detection polishing process, with the surface of the sub-gate mask layer closest to the substrate away from the substrate as the detection endpoint, the second planarization functional layer, part of the first planarization functional layer, and the sub-gate mask layer of the same material as the second planarization functional layer are removed in one polishing step to obtain the semiconductor structure; wherein, the semiconductor structure includes at least two gate structures formed on the substrate, and the distance from the surface of different gate structures away from the substrate to the substrate is the same.

2. The method according to claim 1, characterized in that, When the materials of the at least two sub-gate mask layers are different, the second planarization functional layer is made of the same material as at least one of the sub-gate mask layers located away from the substrate.

3. The method according to claim 2, characterized in that, In the at least two sub-gate mask layers, the material of the sub-gate mask layer farther from the substrate is silicon oxide; the material of the sub-gate mask layer closer to the substrate is silicon nitride.

4. The method according to claim 1, characterized in that, The step of forming a second planarization functional layer on the surface of the transition substrate includes: The second planarization functional layer is formed on the surface of the transition substrate using a flow-controlled chemical vapor deposition process or a spin coating process; wherein, the distance from the surface of the second planarization functional layer away from the substrate to the substrate is the same for different gate transition structure surfaces.

5. The method according to claim 1, characterized in that, The etch stop layer is made of silicon nitride; the interlayer dielectric layer is made of silicon oxide.

6. The method according to claim 1, characterized in that, The at least two gate transition structures include a first gate transition structure and a second gate transition structure; in the substrate and the transition substrate, the distance from the surface of the first gate transition structure away from the substrate to the substrate is less than the distance from the surface of the second gate transition structure away from the substrate to the substrate; The step of thinning the initial dielectric layer to form the interlayer dielectric layer includes: Using an endpoint detection grinding process, the initial dielectric layer is ground until the initial etch stop layer on the surface of the second gate transition structure is exposed, with the surface of the initial etch stop layer away from the substrate as the detection endpoint, to form a transition dielectric layer. The transition dielectric layer is etched using a dry etching process until the initial etch stop layer on the surface of the at least two gate transition structures is exposed, thereby forming the interlayer dielectric layer.

7. The method according to claim 1, characterized in that, The distance from the surface of the interlayer dielectric layer away from the substrate to the substrate is greater than the distance from the surface of the gate away from the substrate to the substrate.

8. A semiconductor structure, characterized in that, The semiconductor structure is manufactured by the semiconductor structure manufacturing method according to any one of claims 1-7, and the semiconductor structure comprises: Substrate; At least two gate structures are formed on the substrate; wherein the gate structure has a gate extension direction and a gate width direction perpendicular to the gate extension direction; the widths of different gate structures along the gate width direction are different; and the distances from the surfaces of different gate structures away from the substrate to the substrate are the same.

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