Three-dimensional semiconductor device

Abstract

A three-dimensional semiconductor device is provided. The three-dimensional semiconductor device may include: a first active region on a substrate, the first active region including a first channel pattern and a first source / drain pattern connected to each other; a second active region stacked on the first active region, the second active region including a second channel pattern and a second source / drain pattern connected to each other; a gate electrode on the first channel pattern and the second channel pattern; a bottom active contact electrically connected to the first source / drain pattern and extending from the first source / drain pattern in the first direction; a lower metal layer disposed below the bottom active contact, the lower metal layer including a bottom via pattern electrically connected to the bottom active contact and a bottom interconnect line; and a division structure electrically connected to at least one of the bottom via patterns. The division structure may include a division liner pattern and a connection metal pattern penetrating the division liner pattern.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0060074, filed on May 7, 2024, in the Korean Intellectual Property Office, the contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to a three-dimensional semiconductor device, and more particularly, to a three-dimensional semiconductor device having a high integration density and improved reliability and a method of manufacturing a three-dimensional semiconductor device. BACKGROUND

[0003] Semiconductor devices include integrated circuits composed of metal oxide semiconductor field effect transistors (MOS-FETs). In order to meet increasing demand for semiconductor devices having small pattern sizes and reduced design rules, MOS-FETs are being actively scaled down. Scaling down of MOS-FETs can cause deterioration of operating characteristics of semiconductor devices. Various studies are being conducted to overcome technical limitations arising from scaling down of semiconductor devices and to provide high-performance semiconductor devices. SUMMARY

[0004] In general, in some aspects, the present disclosure relates to a three-dimensional semiconductor device having a high integration density and improved reliability, and a method of manufacturing a three-dimensional semiconductor device having a high integration density and improved reliability.

[0005] According to some embodiments, the present disclosure relates to a three-dimensional semiconductor device including: a first active region on a substrate, the first active region including a first channel pattern and a first source / drain pattern connected to the first channel pattern; a second active region stacked on the first active region, the second active region including a second channel pattern and a second source / drain pattern connected to the second channel pattern; a gate electrode on the first channel pattern and the second channel pattern; a bottom active contact electrically connected to the first source / drain pattern, the bottom active contact having a strip shape extending from the first source / drain pattern in a first direction; a lower metal layer disposed below the bottom active contact, the lower metal layer including a bottom via pattern and a bottom interconnection line electrically connected to the bottom active contact; and a division structure electrically connected to at least one of the bottom via patterns. The division structure can include a division pad pattern and a connection metal pattern penetrating the division pad pattern.

[0006] According to some embodiments, the disclosure relates to a three-dimensional semiconductor device including a substrate including an insulating pattern, a device isolation layer defining the insulating pattern, a division structure extending in a first direction crossing the insulating pattern, a lower metal layer disposed below the substrate, the lower metal layer including a bottom via pattern and a bottom interconnection line, and a first metal layer on the division structure, the first metal layer including an upper via pattern and an upper interconnection line. The division structure can include a connection metal pattern and a division spacer pattern disposed on side surfaces of the connection metal pattern to surround the connection metal pattern. The bottom interconnection line, the bottom via pattern, the connection metal pattern, the upper via pattern, and the upper interconnection line can be electrically connected to each other.

[0007] According to some embodiments, the disclosure relates to a three-dimensional semiconductor device including a first active region on a substrate, the first active region including a first channel pattern and a first source / drain pattern connected to the first channel pattern, a dummy region stacked on the first active region, the dummy region including a dummy pattern on the first channel pattern and an interlayer insulating layer on the first source / drain pattern, a second active region stacked on the dummy region, the second active region including a second channel pattern and a second source / drain pattern connected to the second channel pattern, a gate electrode on the first channel pattern and the second channel pattern, a bottom active contact electrically connected to the first source / drain pattern, a lower metal layer disposed below the bottom active contact, the lower metal layer including a bottom via pattern electrically connected to the bottom active contact and a bottom interconnection line, an upper active contact electrically connected to the second source / drain pattern, and a division structure electrically connected to at least one of the bottom via patterns. The division structure can include a division spacer pattern and a connection metal pattern penetrating the division spacer pattern, and the connection metal pattern can be in direct contact with the first source / drain pattern and the second source / drain pattern.

[0008] According to some embodiments, the bottom interconnection line, the bottom via pattern, the lower penetrating via, the third gate electrode, the fourth gate electrode, the upper penetrating via, the upper via pattern, and the upper interconnection line can be electrically connected to each other.

[0009] According to some embodiments, a threshold voltage of a transistor including the fourth gate electrode can be greater than a threshold voltage of a transistor including the second gate electrode.

[0010] According to some embodiments, the disclosure relates to a method of manufacturing a three-dimensional semiconductor device, the method including: forming a lower stack pattern, a division layer, and an upper stack pattern vertically stacked on a substrate, the step of forming each of the lower stack pattern and the upper stack pattern including alternately forming an active layer and a sacrificial layer; forming a sacrificial pattern extending in a first direction on the lower stack pattern, the division layer, and the upper stack pattern; etching the lower stack pattern and the upper stack pattern using the sacrificial pattern as a mask to form recesses, the active layer including a plurality of semiconductor patterns exposed by the recesses; forming a first source / drain pattern and a second source / drain pattern connected to the plurality of semiconductor patterns exposed by the recesses and vertically stacked; removing the sacrificial pattern and the sacrificial layer to expose the plurality of semiconductor patterns and replacing the division layer with dummy patterns; sequentially forming a gate insulating layer and a gate electrode on the exposed plurality of semiconductor patterns; and etching at least one of the gate electrodes to form a division structure, wherein the step of forming the division structure includes: forming an upper division structure on a recessed region formed by etching the at least one of the gate electrodes; inverting the resulting structure; and forming a lower division structure connected to the upper division structure.

[0011] According to some embodiments, the step of forming the upper division structure can include forming a first division spacer pattern, and forming a first connection metal pattern extending into the first division spacer pattern.

[0012] According to some embodiments, the step of forming the lower division structure can include forming a second division spacer pattern, and forming a second connection metal pattern extending into the second division spacer pattern.

[0013] According to some embodiments, the first connection metal pattern can be in direct contact with the second source / drain pattern.

[0014] According to some embodiments, the second connection metal pattern can be in direct contact with the first source / drain pattern. BRIEF DESCRIPTION OF DRAWINGS

[0015] The example embodiments will become more fully understood from the detailed description given herein below, and the accompanying drawings, which are given by way of illustration and by way of context, and not limitation of the presented examples.

[0016] Figure 1 and Figure 2 are diagrams illustrating examples of a logic unit of a semiconductor device according to some embodiments.

[0017] Figure 3A and Figure 3B are plan views illustrating examples of a three-dimensional semiconductor device according to some embodiments.

[0018] Figures 4A to 4E are cross-sectional views of a semiconductor device according to some embodiments, respectively along Figure 3Across-sectional view taken along line A-A', line B-B', line C-C', line D-D', and line E-E' of

[0019] Figures 5A to 5C is a cross-sectional view showing an example of a three-dimensional semiconductor device according to some embodiments. Figure 4A is a cross-sectional view showing an example of a three-dimensional semiconductor device according to some embodiments.

[0020] Figures 6A to 6C is a cross-sectional view taken along line A-A', line B-B', and line E-E' of Figure 3A

[0021] Figures 7A to 25E is a cross-sectional view showing an example of a method of manufacturing a three-dimensional semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0022] Hereinafter, example embodiments will be explained in detail with reference to the accompanying drawings.

[0023] Figure 1 is a diagram showing an example of a logic cell of a two-dimensional semiconductor device according to some embodiments. In Figure 1 , a single height cell SHC' can be provided. In detail, a first power line POR1 and a second power line POR2 can be disposed on the substrate 105. A drain voltage VDD (e.g., a power supply voltage) can be applied to one of the first power line POR1 and the second power line POR2. A source voltage VSS (e.g., a ground voltage) can be applied to the other of the first power line POR1 and the second power line POR2. In some embodiments, the source voltage VSS can be applied to the first power line POR1, and the drain voltage VDD can be applied to the second power line POR2.

[0024] A single height cell SHC' can be defined between the first power line POR1 and the second power line POR2. The single height cell SHC' can include a first active region AR1 and a second active region AR2. One of the first active region AR1 and the second active region AR2 can be a P-type metal oxide semiconductor field effect transistor (PMOS-FET) region, and the other of the first active region AR1 and the second active region AR2 can be an N-type metal oxide semiconductor field effect transistor (NMOS-FET) region. For example, the first active region AR1 can be an NMOS-FET region, and the second active region AR2 can be a PMOS-FET region. That is, the single height cell SHC' can include a complementary metal oxide semiconductor (CMOS) structure disposed between the first power line POR1 and the second power line POR2.

[0025] ​In some embodiments, the semiconductor device can be a two-dimensional device in which transistors of a front-end-of-line (FEOL) layer are arranged two-dimensionally. For example, the NMOS-FET of the first active region AR1 and the PMOS-FET of the second active region AR2 can be formed to be spaced apart from each other in the first direction D1.

[0026] Each of the first active region AR1 and the second active region AR2 can have a first width W1 in the first direction D1. In Figure 1 In particular, a length of the single height cell SHC' in the first direction D1 can be defined as a first height HE1. The first height HE1 can be substantially equal to a distance (e.g., pitch) between the first power line POR1 and the second power line POR2.

[0027] The single height cell SHC' can constitute a single logic cell. In the present disclosure, a logic cell can refer to a logic device (e.g., AND, OR, XOR, XNOR, inverter, etc.) configured to perform a specific function. In other words, the logic cell can include transistors constituting the logic device and interconnection lines connecting the transistors to each other.

[0028] In Figure 1 In particular, since the single height cell SHC' includes a two-dimensional device, the first active region AR1 and the second active region AR2 can not be overlapped with each other and can be spaced apart from each other in the first direction D1. Accordingly, the first height HE1 of the single height cell SHC' should be defined as spanning both the first active region AR1 and the second active region AR2 spaced apart from each other in the first direction D1. As a result, the first height HE1 of the single height cell SHC' in the comparative example can have a relatively increased value. That is, the single height cell SHC' in the comparative example can have a relatively large area.

[0029] Figure 2 FIG. 1 is a diagram illustrating an example of a logic cell of a three-dimensional semiconductor device according to some embodiments. In Figure 2 In particular, a single height cell SHC including a three-dimensional device having stacked transistors can be provided. In detail, a first power line POR1 and a second power line POR2 can be disposed on a substrate 105. The single height cell SHC can be defined between the first power line POR1 and the second power line POR2.

[0030] The single height cell SHC can include a first active region AR1 and a second active region AR2. One of the first active region AR1 and the second active region AR2 can be a PMOS-FET region, and the other of the first active region AR1 and the second active region AR2 can be an NMOS-FET region.

[0031] In some embodiments, the semiconductor device can be a three-dimensional device in which transistors of the FEOL layer are stacked vertically. A first active region AR1 as a bottom tier can be disposed on the substrate 105, and a second active region AR2 as a top tier can be stacked on the first active region AR1. For example, NMOS-FETs of the first active region AR1 can be disposed on the substrate 105, and PMOS-FETs of the second active region AR2 can be stacked on the NMOS-FETs. The first active region AR1 and the second active region AR2 can be spaced apart from each other in a vertical direction (i.e., the third direction D3).

[0032] Each of the first active region AR1 and the second active region AR2 can have a first width W1 in the first direction D1. In some embodiments, a length of a single height cell SHC in the first direction D1 can be defined as a second height HE2.

[0033] Since the single height cell SHC includes a three-dimensional device (i.e., stacked transistors), the first active region AR1 can be superposed with the second active region AR2. Accordingly, the second height HE2 of the single height cell SHC can have a dimension that spans the single active region, or can be greater than the first width W1. As a result, the second height HE2 of the single height cell SHC according to the present embodiment can be smaller than the first height HE1 of the single height cell SHC' described above. Figure 1 In other words, the single height cell SHC can have a relatively small area. This can enable an increase in the integration density of the three-dimensional semiconductor device.

[0034] Figure 3A and Figure 3B are plan views showing examples of a three-dimensional semiconductor device according to some embodiments. Figure 3A is a front-side plan view of the three-dimensional semiconductor device, and Figure 3B is a back-side plan view of the three-dimensional semiconductor device. Figures 4A to 4E are detailed examples of a portion of the single height cell of Figure 3A along the line A-A', the line B-B', the line C-C', the line D-D', and the line E-E' of Figures 4A to 4E The three-dimensional semiconductor device of Figure 2 is a detailed example of a portion of the single height cell of

[0035] In Figure 3AIn the present embodiment, a substrate 105 can be provided, and here, a portion LC P of a logic cell that constitutes a logic circuit can be provided in the substrate 105. The substrate 105 can be an insulating substrate including an insulating material. In some embodiments, the substrate 105 can be a semiconductor substrate formed of silicon, germanium, silicon-germanium, a compound semiconductor material, or the like, or a semiconductor substrate including silicon, germanium, silicon-germanium, a compound semiconductor material, or the like.

[0036] Reference will be made previously Figure 2 A portion of the single-height cell SHC can be provided in the portion LC P of the logic cell. In other words, a division structure DBST can be provided in the portion LC P of the logic cell to separate vertically-stacked transistors of the FEOL layer from adjacent single-height cells in the single-height cell SHC from each other. The adjacent single-height cells in the single-height cell SHC can be adjacent to each other in the second direction D2. The division structure DBST can separate the adjacent single-height cells in the single-height cell SHC from each other in the second direction D2.

[0037] Hereinafter, the portion LC P of the logic cell in the three-dimensional semiconductor device will be described in more detail with reference to Figure 3A , Figure 3B and Figures 4A to 4E The single-height cell SHC as the logic cell can include a first active region AR1 and a second active region AR2 that are sequentially stacked on the substrate 105. One of the first active region AR1 and the second active region AR2 can be a PMOS-FET region, and the other of the first active region AR1 and the second active region AR2 can be an NMOS-FET region. The first active region AR1 can be disposed as a bottom layer of the FEOL layer, and the second active region AR2 can be disposed as a top layer of the FEOL layer. The NMOS-FET and the PMOS-FET of the first active region AR1 and the second active region AR2 can be vertically stacked to form a three-dimensionally stacked transistor. In some embodiments, the first active region AR1 can be a PMOS-FET region, and the second active region AR2 can be an NMOS-FET region.

[0038] The insulating pattern IP can be defined by a trench TR formed in the substrate 105. The insulating pattern IP can be a vertically protruding portion of the substrate 105. When viewed in a plan view, the insulating pattern IP can be a bar-shaped pattern extending in the second direction D2. The first active region AR1 and the second active region AR2 described above can be sequentially stacked on the insulating pattern IP. The insulating pattern IP can include at least one of an insulating material (e.g., silicon oxide, silicon nitride, and silicon oxynitride).

[0039] The device isolation layer ST can be disposed to fill the trench TR. The device isolation layer ST can include a silicon oxide layer. A top surface of the device isolation layer ST can be coplanar with or lower than a top surface of the insulating pattern IP. The device isolation layer ST can not cover the first channel pattern CH1 and the second channel pattern CH2, which will be described below.

[0040] A first active region AR1 including the first channel pattern CH1 and the first source / drain pattern SD1 can be disposed on the insulating pattern IP. The first channel pattern CH1 can be interposed between a pair of the first source / drain pattern SD1. The first channel pattern CH1 can connect the pair of the first source / drain pattern SD1 to each other.

[0041] The first channel pattern CH1 can include a first semiconductor pattern SP1 and a second semiconductor pattern SP2 stacked to be spaced apart from each other. Each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 can be formed of or include at least one of silicon (Si), germanium (Ge), and silicon germanium (SiGe). In some embodiments, each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 can be formed of or include crystalline silicon.

[0042] The first source / drain pattern SD1 can be disposed on a top surface of the insulating pattern IP. Each of the first source / drain pattern SD1 can be an epitaxial pattern formed through a selective epitaxial growth (SEG) process. In some embodiments, a top surface of the first source / drain pattern SD1 can be higher than a top surface of the second semiconductor pattern SP2 of the first channel pattern CH1.

[0043] The first source / drain pattern SD1 can be doped with an impurity to have a first conductivity type. The first conductivity type can be an n-type or a p-type. In some embodiments, the first conductivity type can be a p-type. The first source / drain pattern SD1 can include silicon germanium (SiGe) and / or silicon (Si).

[0044] A first etch stop layer ESL1 can be disposed on the first source / drain pattern SD1 (for example, see Figure 4D ). A first interlayer insulating layer 110 can be disposed on the first etch stop layer ESL1. The first interlayer insulating layer 110 can cover the first source / drain pattern SD1.

[0045] The second interlayer insulating layer 120 and the second active region AR2 can be disposed on the first interlayer insulating layer 110. The second active region AR2 can include a second channel pattern CH2 and a second source / drain pattern SD2. The second channel pattern CH2 can be vertically overlaid with the first channel pattern CH1, respectively. The second source / drain pattern SD2 can be vertically overlaid with the first source / drain pattern SD1, respectively. The second channel pattern CH2 can be interposed between a pair of the second source / drain patterns SD2. The second channel pattern CH2 can connect the pair of the second source / drain patterns SD2 to each other.

[0046] The second channel pattern CH2 can include a third semiconductor pattern SP3 and a fourth semiconductor pattern SP4 stacked to be spaced apart from each other. The third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 of the second channel pattern CH2 can include the same semiconductor material as the semiconductor material of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 of the first channel pattern CH1 described above.

[0047] At least one dummy pattern DSP can be interposed between the first channel pattern CH1 and the second channel pattern CH2 thereon. The dummy pattern DSP can be spaced apart from the first source / drain pattern SD1 and the second source / drain pattern SD2. In other words, the dummy pattern DSP can not be connected to any source / drain pattern. The dummy pattern DSP can be formed of or include at least one of a semiconductor material (e.g., silicon (Si), germanium (Ge), or silicon germanium (SiGe)) and a silicon-based insulating material (e.g., silicon oxide or silicon nitride). In some embodiments, the dummy pattern DSP can include the silicon-based insulating material.

[0048] The second source / drain pattern SD2 can be disposed on a top surface of the first interlayer insulating layer 110. A second etch stop layer ESL2 can be disposed on the second source / drain pattern SD2 (e.g., see Figure 4D ). The second interlayer insulating layer 120 can be disposed on the second etch stop layer ESL2. The second interlayer insulating layer 120 can cover the second source / drain pattern SD2.

[0049] Each of the second source / drain patterns SD2 can be an epitaxial pattern formed through a selective epitaxial growth (SEG) process. In some embodiments, a top surface of the second source / drain pattern SD2 can be higher than a top surface of the fourth semiconductor pattern SP4 of the second channel pattern CH2.

[0050] The second source / drain pattern SD2 can be doped with impurities to have a second conductivity type. The second conductivity type can be different from the first conductivity type of the first source / drain pattern SD1. For example, the second conductivity type can be n-type. The second source / drain pattern SD2 can be formed of silicon (Si) and / or silicon germanium (SiGe), or include silicon (Si) and / or silicon germanium (SiGe).

[0051] The second interlayer insulating layer 120 and the third interlayer insulating layer 130 can be disposed on the second etch stop layer ESL2. The second interlayer insulating layer 120 can cover the second source / drain pattern SD2. A top surface of the third interlayer insulating layer 130 can be coplanar with a top surface of each of the upper active contacts AC, which will be described below.

[0052] The gate electrode GE can be disposed on the stacked first and second channel patterns CH1 and CH2 (see, for example, Figure 4C ). When viewed in a plan view, the gate electrode GE can be a strip-shaped pattern extending in the first direction D1. The gate electrode GE can be vertically superposed with the first and second channel patterns CH1 and CH2.

[0053] The gate electrode GE can extend in a vertical direction (i.e., the third direction D3) from a top surface of the device isolation layer ST (or a top surface of the insulating pattern IP) to the gate cap pattern GP. The gate electrode GE can extend in the third direction D3 from the first channel pattern CH1 of the first active region AR1 to the second channel pattern CH2 of the second active region AR2. The gate electrode GE can extend in the third direction D3 from the lowermost semiconductor pattern (i.e., the first semiconductor pattern SP1) to the uppermost semiconductor pattern (i.e., the fourth semiconductor pattern SP4).

[0054] The gate electrode GE can be disposed on a top surface, a bottom surface, and opposite side surfaces of each of the first to fourth semiconductor patterns SP1 to SP4. In other words, the transistor can be a three-dimensional field effect transistor (e.g., a multi-bridge channel FET (MBCFET) or a gate-all-around FET (GAAFET)) in which the gate electrode GE is disposed to three-dimensionally surround the channel pattern.

[0055] The gate electrode GE can include a first gate electrode GE1 disposed in a bottom layer (i.e., the first active region AR1) of the FEOL layer and a second gate electrode GE2 disposed in a top layer (i.e., the second active region AR2) of the FEOL layer. The first gate electrode GE1 and the second gate electrode GE2 can be stacked on each other when viewed in a plan view. The first gate electrode GE1 and the second gate electrode GE2 can be connected to each other. That is, the gate electrode GE according to the present embodiment can be a common gate electrode connecting the first gate electrode GE1 on the first channel pattern CH1 and the second gate electrode GE2 on the second channel pattern CH2 to each other.

[0056] The first gate electrode GE1 can include a first inner electrode PO1 interposed between the insulating pattern IP and the first semiconductor pattern SP1, a second inner electrode PO2 interposed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, and a third inner electrode PO3 interposed between the second semiconductor pattern SP2 and the dummy pattern DSP.

[0057] The second gate electrode GE2 can include a fourth inner electrode PO4 interposed between the dummy pattern DSP and the third semiconductor pattern SP3, a fifth inner electrode PO5 interposed between the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4, and an outer electrode PO6 interposed on the fourth semiconductor pattern SP4.

[0058] A pair of gate spacers GS can be disposed on opposite side surfaces of the gate electrode GE, respectively. In Figure 4A In some embodiments, a pair of gate spacers GS can be disposed on opposite side surfaces of the outer electrode PO6, respectively. The gate spacer GS can extend along the gate electrode GE and in the first direction D1. A top surface of the gate spacer GS can be higher than a top surface of the gate electrode GE. The top surface of the gate spacer GS can be coplanar with a top surface of the second interlayer insulating layer 120. The gate spacer GS can be formed of or include at least one of SiCN, SiCON, and SiN. In some embodiments, the gate spacer GS can be a multi-layer structure including at least two different materials selected from SiCN, SiCON, and SiN.

[0059] A gate cover pattern GP can be disposed on a top surface of the gate electrode GE. The gate cover pattern GP can extend along the gate electrode GE or in the first direction D1. In some embodiments, the gate cover pattern GP can be formed of or include at least one of SiON, SiCN, SiCON, and SiN. A second etch stop layer ESL2 can be disposed on a side surface of the gate spacer GS.

[0060] A gate insulating layer GI can be interposed between the gate electrode GE and the first to fourth semiconductor patterns SP1 to SP4. The gate insulating layer GI can include a silicon oxide layer, a silicon oxynitride layer, and / or a high-k dielectric layer. In some embodiments, the gate insulating layer GI can include a silicon oxide layer formed to directly cover the first to fourth semiconductor patterns SP1 to SP4 and a high-k dielectric layer formed on the silicon oxide layer. In other words, the gate insulating layer GI can be a multi-layer structure including the silicon oxide layer and the high-k dielectric layer.

[0061] The high-k dielectric layer can be formed of, or include, at least one of a high-k dielectric material having a dielectric constant higher than that of silicon oxide. For example, the high-k dielectric material can include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0062] The gate electrode GE can include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern can be disposed on the gate insulating layer GI and can be adjacent to the first to fourth semiconductor patterns SP1 to SP4. The first metal pattern can include a work function metal, which can be used to adjust a threshold voltage of the transistor. By adjusting the thickness and composition of the first metal pattern, a transistor having a desired threshold voltage can be implemented. For example, the first, second, and third inner electrodes PO1, PO2, and PO3 of the first gate electrode GE1 and the fourth and fifth inner electrodes PO4 and PO5 of the second gate electrode GE2 can be composed of the first metal pattern, which is a work function metal. In some embodiments, the work function metal of the first, second, and third inner electrodes PO1, PO2, and PO3 of the first gate electrode GE1 can be a different material from the work function metal of the fourth and fifth inner electrodes PO4 and PO5 of the second gate electrode GE2.

[0063] The first metal pattern can include a metal nitride layer. For example, the first metal pattern can include at least one metal material selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), molybdenum (Mo), and nitrogen (N). In some embodiments, the first metal pattern can further include carbon (C). The first metal pattern can include a plurality of work function metal layers stacked.

[0064] The second metal pattern can be formed of a metal pattern having a lower resistance than the first metal pattern, or include a metal pattern having a lower resistance than the first metal pattern. For example, the second metal pattern can include at least one metal material selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta). For example, the outer electrode PO6 of the second gate electrode GE2 can include the first metal pattern and the second metal pattern on the first metal pattern.

[0065] The cut pattern CT can be disposed to penetrate the gate electrode GE. The gate electrodes GE adjacent to each other in the first direction D1 can be separated from each other by the cut pattern CT. For example, referring to Figure 4C A pair of cut patterns CT can be respectively disposed at opposite end portions of the gate electrode GE. The cut pattern CT can be formed of, or include, at least one of an insulating material (e.g., silicon oxide, silicon nitride, and a combination thereof).

[0066] The third interlayer insulating layer 130 can be disposed on the gate cover pattern GP, the cut pattern CT, and the second interlayer insulating layer 120. The gate contact GC can be disposed to penetrate the third interlayer insulating layer 130 and the gate cover pattern GP and electrically connected to the gate electrode GE. When viewed in a plan view, the gate contact GC can be freely disposed on the gate electrode GE without any restriction in its position.

[0067] The upper active contact AC can be disposed to be electrically connected to the second source / drain pattern SD2, respectively. For example, referring to Figure 4A and Figure 4B The upper active contact AC can be disposed to penetrate the third interlayer insulating layer 130, the second interlayer insulating layer 120, and the second etch stop layer ESL2, and can be directly connected to the second source / drain pattern SD2. In some embodiments, a pair of upper active contacts AC can be respectively disposed at both sides of the gate electrode GE. When viewed in a plan view, the upper active contact AC can be in a strip shape (e.g., a strip pattern) extending in the first direction D1.

[0068] The upper active contact AC can be a self-aligned contact. For example, the upper active contact AC can be formed using the gate cover pattern GP and the gate spacer GS through a self-alignment process. For example, the upper active contact AC can cover at least a portion of a side surface of the gate spacer GS. The upper active contact AC can cover a portion of a top surface of the gate cover pattern GP.

[0069] A metal-semiconductor compound layer SC (e.g., a silicide layer) can be interposed between the upper active contact AC and the second source / drain pattern SD2. The upper active contact AC can be electrically connected to the second source / drain pattern SD2 through the metal-semiconductor compound layer SC. For example, the metal-semiconductor compound layer SC can be formed of, or include, at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

[0070] Each of the upper active contact AC and the gate contact GC can include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM can be formed of, or include, at least one of a metal material (e.g., aluminum, copper, tungsten, molybdenum, and cobalt). The barrier pattern BM can be disposed to cover side surfaces and a bottom surface of the conductive pattern FM. In some embodiments, the barrier pattern BM can include a metal layer and / or a metal nitride layer. The metal layer can be formed of, or include, at least one of titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer can be formed of, or include, at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0071] The bottom active contacts BAC can be disposed to be electrically connected to the first source / drain patterns SD1, respectively. For example, referring to FIG. 1A, the bottom active contacts BAC can be disposed to penetrate the insulating pattern IP and can be directly connected to the first source / drain patterns SD1. In some embodiments, a pair of the bottom active contacts BAC can be disposed at both sides of the gate electrode GE, respectively. When viewed in a plan view, the bottom active contacts BAC can be in a strip shape (e.g., a strip pattern) extending in the first direction D1. Figure 4A and Figure 4B The bottom active contacts BAC can be disposed to penetrate the insulating pattern IP and can be directly connected to the first source / drain patterns SD1. In some embodiments, a pair of the bottom active contacts BAC can be disposed at both sides of the gate electrode GE, respectively. When viewed in a plan view, the bottom active contacts BAC can be in a strip shape (e.g., a strip pattern) extending in the first direction D1.

[0072] A metal-semiconductor compound layer SC (e.g., a silicide layer) can be interposed between the bottom active contact BAC and the first source / drain pattern SD1. The bottom active contact BAC can be electrically connected to the first source / drain pattern SD1 through the metal-semiconductor compound layer SC. For example, the metal-semiconductor compound layer SC can be formed of, or include, at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

[0073] The bottom active contact BAC can include a bottom conductive pattern BFM and a bottom barrier pattern BBM surrounding the bottom conductive pattern BFM. For example, the bottom conductive pattern BFM can be formed of or include at least one of a metal material (e.g., aluminum, copper, tungsten, molybdenum, and cobalt). The bottom barrier pattern BBM can cover side surfaces and a top surface of the bottom conductive pattern BFM. The bottom barrier pattern BBM can include a metal layer and / or a metal nitride layer. The metal layer can be formed of or include at least one of titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer can be formed of or include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN). The bottom conductive pattern BFM can be formed of or include the same material as the conductive pattern FM, and the bottom barrier pattern BBM can be formed of or include the same material as the barrier pattern BM.

[0074] The division structure DBST can be disposed at a boundary between adjacent single height cells in a single height cell or between adjacent logical cells in a logical cell. The division structure DBST can extend in the first direction D1 to be parallel to the gate electrode GE (e.g., see Figure 3A The pitch between the division structure DBST and the gate electrode GE adjacent to each other can be equal to the pitch between the gate electrodes GE.

[0075] The division structure DBST can penetrate the first interlayer insulating layer 110, the second interlayer insulating layer 120, and the third interlayer insulating layer 130, and can extend into the insulating pattern IP. For example, the division structure DBST can be disposed to penetrate the first interlayer insulating layer 110, the second interlayer insulating layer 120, the third interlayer insulating layer 130, and the insulating pattern IP. The division structure DBST can include a division liner pattern and a connection metal pattern penetrating the division liner pattern. In other words, the division liner pattern can be disposed on side surfaces of the connection metal pattern to surround or enclose the connection metal pattern.

[0076] The division liner pattern can include a first division liner pattern DBL1 and a second division liner pattern DBL2, and the connection metal pattern can include a first connection metal pattern DBM1 and a second connection metal pattern DBM2.

[0077] The division structure DBST can include a lower division structure LDB disposed in the insulating pattern IP and the first active region AR1, and an upper division structure UDB disposed in the first interlayer insulating layer 110, the second interlayer insulating layer 120, and the third interlayer insulating layer 130, and the second active region AR2. The upper division structure UDB can be disposed on the lower division structure LDB. For example, the upper division structure UDB can include a first division spacer pattern DBL1 and a first connection metal pattern DBM1 penetrating the first division spacer pattern DBL1, and the lower division structure LDB can include a second division spacer pattern DBL2 and a second connection metal pattern DBM2 penetrating the second division spacer pattern DBL2.

[0078] In Figure 4E The first division spacer pattern DBL1 can be in direct contact with the second division spacer pattern DBL2, and the first connection metal pattern DBM1 can be in direct contact with the second connection metal pattern DBM2 when measured in the third direction D3. The first interface IF1 between the first connection metal pattern DBM1 and the second connection metal pattern DBM2 can be located at a lower height than the second interface IF2 between the first division spacer pattern DBL1 and the second division spacer pattern DBL2 when measured in the third direction D3. In some embodiments, at least one of the first interface IF1 and the second interface IF2 can not be visible or measurable. This is because the first division spacer pattern DBL1 and the second division spacer pattern DBL2 include the same material, and the first connection metal pattern DBM1 and the second connection metal pattern DBM2 include the same material.

[0079] The cut pattern CT can be disposed on the device isolation layer ST, and can be disposed on opposite side surfaces of the division structure DBST. For example, the cut pattern CT can be disposed on side surfaces of the first division spacer pattern DBL1 and the second division spacer pattern DBL2. A top surface of the cut pattern CT can be located at a lower height than a top surface of the division structure DBST in the third direction D3. The top surface of the division structure DBST can be located at the same height as a top surface of the third interlayer insulating layer 130, and the bottom surface of the division structure DBST can be located at the same height as a bottom surface of the device isolation layer ST when measured in the third direction D3.

[0080] In Figure 4A and Figure 4BIn some embodiments, the first dividing spacer pattern DBL1 and the second dividing spacer pattern DBL2 can horizontally separate the first connection metal pattern DBM1 and the second connection metal pattern DBM2 from the upper active contacts AC, the bottom active contacts BAC, and the first source / drain pattern SD1 and the second source / drain pattern SD2. The first dividing spacer pattern DBL1 and the second dividing spacer pattern DBL2 can include at least one of an insulating material (e.g., silicon oxide, silicon nitride, and silicon oxynitride). In some embodiments, the first dividing spacer pattern DBL1 and the second dividing spacer pattern DBL2 can be formed of or include silicon nitride.

[0081] The first dividing spacer pattern DBL1 can have a first thickness L1 in the second direction D2. The second dividing spacer pattern DBL2 can include a first portion adjacent to the first source / drain pattern SD1 and a second portion disposed below the first portion and adjacent to the insulating pattern IP. The first portion and the second portion of the second dividing spacer pattern DBL2 can have a second thickness L2 and a third thickness L3, respectively, when measured in the second direction D2.

[0082] Each of the first thickness L1 and the second thickness L2 can be substantially constant. The third thickness L3 can increase as a distance to a lower metal layer BSM1 to be described below decreases. The second thickness L2 can be greater than the first thickness L1 and the third thickness L3. This is because each of the first gate electrode GE1 and the first channel pattern CH1 in the first active region AR1 has a first width in the second direction D2 that is greater than a second width in the second direction D2 of each of the second gate electrode GE2 and the second channel pattern CH2 in the second active region AR2. That is, since the dividing structure DBST is formed in the first active region AR1 and the second active region AR2 on a boundary of the logic cell to correspond to the first width and the second width, the second thickness L2 can be greater than the first thickness L1 and the third thickness L3. A minimum value of the third thickness L3 can be less than the first thickness L1, and a maximum value of the third thickness L3 can be equal to the first thickness L1.

[0083] The first connection metal pattern DBM1 and the second connection metal pattern DBM2 can be electrically connected to the lower metal layer BSM1 and a first metal layer M1 to be described below. The first connection metal pattern DBM1 and the second connection metal pattern DBM2 can be formed of or include at least one of a metal material (e.g., aluminum, copper, tungsten, molybdenum, and cobalt). In some embodiments, the first connection metal pattern DBM1 and the second connection metal pattern DBM2 can be formed of or include molybdenum or cobalt.

[0084] A fourth interlayer insulating layer 140 can be disposed on the third interlayer insulating layer 130, the gate contact GC, the upper active contact AC, and the division structure DBST. A first metal layer M1 can be disposed in the fourth interlayer insulating layer 140. The first metal layer M1 can include first and second upper via patterns VI1 and VI2, an upper interconnection line MIL, and first and second power lines POR1 and POR2. The first and second upper via patterns VI1 and VI2, the upper interconnection line MIL, and the first and second power lines POR1 and POR2 can be formed of or include at least one of a metal material, e.g., copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo). In an embodiment, the upper interconnection line MIL in the fourth interlayer insulating layer 140 can serve as an interconnection line for applying a source voltage.

[0085] In some embodiments, the gate contact GC can be connected to the upper interconnection line MIL through the first upper via pattern VI1. The upper active contact AC can be connected to the upper interconnection line MIL through the second upper via pattern VI2. The division structure DBST can be connected to the upper interconnection line MIL through the second upper via pattern VI2. In other words, the division structure DBST can be electrically connected to the second source / drain pattern SD2 through the second upper via pattern VI2 and the upper interconnection line MIL.

[0086] Additional metal layers (e.g., M2, M3, M4, etc.) (not shown) can be stacked on the first metal layer M1. The first metal layer M1 and the additional metal layers (e.g., M2, M3, M4, etc.) on the first metal layer M1 can constitute back-end-of-line (BEOL) layers of the semiconductor device. The additional metal layers (e.g., M2, M3, M4, etc.) on the first metal layer M1 can include lines of wiring for connecting logic cells to each other.

[0087] A fifth interlayer insulating layer 150 can be disposed on a bottom surface of the substrate 105. A lower metal layer BSM1 can be disposed in the fifth interlayer insulating layer 150 (e.g., disposed under the bottom active contact BAC). The lower metal layer BSM1 can include a first bottom via pattern BVI1 and a second bottom via pattern BVI2, and a bottom interconnection line BMIL. The first bottom via pattern BVI1 and the second bottom via pattern BVI2, and the bottom interconnection line BMIL can be formed of or include at least one of a metal material (e.g., copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo)). In an embodiment, the bottom interconnection line BMIL in the fifth interlayer insulating layer 150 can function as an interconnection line for applying a drain voltage.

[0088] In some embodiments, the bottom active contact BAC can be directly connected to the bottom interconnection line BMIL through the first bottom via pattern BVI1 and the second bottom via pattern BVI2. The division structure DBST can be connected to the bottom interconnection line BMIL through the first bottom via pattern BVI1. In other words, the division structure DBST can be electrically connected to the first source / drain pattern SD1 through the first bottom via pattern BVI1 and the bottom interconnection line BMIL.

[0089] In Figure 4E , the division structure DBST can be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2. For example, the division structure DBST can be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2 through the bottom interconnection line BMIL, the first bottom via pattern BVI1, the first connection metal pattern DBM1 and the second connection metal pattern DBM2, the second upper via pattern VI2, and the upper interconnection line MIL.

[0090] In a three-dimensional semiconductor device, in some embodiments, source / drain regions of vertically stacked transistors can be connected to each other through a division structure (e.g., a single diffusion break (SDB)), and in this case, an over-head phenomenon caused by a connection pattern for connecting the source / drain regions can be able to be prevented. In other words, an occupation area of the connection pattern in a logic cell can be able to be reduced. Accordingly, an effective area of the logic cell can be reduced, and an integration density of the three-dimensional semiconductor device can be increased.

[0091] In addition, the connection pattern can generate a parasitic capacitance related to an adjacent gate electrode. This is because the distance between the connection pattern and the gate electrode is relatively small, and the connection pattern is formed of a conductive material. However, according to some embodiments, since the division structure includes an insulating material and is separated by a sufficient distance from the gate electrode (e.g., gate-to-gate pitch), it can be possible to reduce the parasitic capacitance problem. Thus, the reliability of the three-dimensional semiconductor device can be improved.

[0092] Hereinafter, embodiments will be described with reference to Figures 5A to 5C An example of a three-dimensional semiconductor device will be described in more detail. Figures 5A to 5C may correspond to a modified example of the embodiments of Figure 4A In the following description, for the sake of a concise description, previously described elements can be identified by the same reference numerals without repeating the repetitive description thereof.

[0093] The single height cell SHC as a logic cell can include a first active region AR1, a dummy region DR, and a second active region AR2 sequentially stacked on the substrate 105. One of the first active region AR1 and the second active region AR2 can be a PMOS-FET region, and the other of the first active region AR1 and the second active region AR2 can be an NMOS-FET region. The first active region AR1 can be disposed as a bottom layer of the FEOL layer, and the second active region AR2 can be disposed as a top layer of the FEOL layer. The NMOS-FET and the PMOS-FET of the first active region AR1 and the second active region AR2 can be vertically stacked to form a three-dimensional stacked transistor.

[0094] The dummy region DR can include a dummy pattern DSP interposed between the first channel pattern CH1 and the second channel pattern CH2, and a first interlayer insulating layer 110 interposed between the first source / drain pattern SD1 and the second source / drain pattern SD2.

[0095] The division structure DBST can include a division pad pattern and a connection metal pattern penetrating the division pad pattern. The division pad pattern can include a first division pad pattern DBL1 and a second division pad pattern DBL2, and the connection metal pattern can include a first connection metal pattern DBM1 and a second connection metal pattern DBM2.

[0096] The division structure DBST can include a lower division structure LDB disposed in the insulating pattern IP and the first active region AR1, and an upper division structure UDB disposed in the first interlayer insulating layer 110, the second interlayer insulating layer 120 and the third interlayer insulating layer 130, and the second active region AR2. The upper division structure UDB can be disposed on the lower division structure LDB. For example, the upper division structure UDB can include a first division pad pattern DBL1 and a first connection metal pattern DBM1 penetrating the first division pad pattern DBL1, and the lower division structure LDB can include a second division pad pattern DBL2 and a second connection metal pattern DBM2 penetrating the second division pad pattern DBL2.

[0097] In Figure 5A the first connection metal pattern DBM1 of the upper division structure UDB can include a first portion DBM1_P1 disposed between the first division pad patterns DBL1, a second portion DBM1_P2 directly contacting the second source / drain pattern SD2, and a third portion DBM1_P3 disposed between the dummy patterns DSP.

[0098] The first division pad pattern DBL1 can be disposed on a first side surface of the second portion DBM1_P2, and the second source / drain pattern SD2 can be disposed on a second side surface of the second portion DBM1_P2 opposite the first side surface. In other words, the second portion DBM1_P2 of the first connection metal pattern DBM1 can directly contact the second source / drain pattern SD2. Since the first division pad pattern DBL1 is not disposed on the second side surface of the second portion DBM1_P2, a width of the second portion DBM1_P2 in the second direction D2 can be greater than a width of each of the first portion DBM1_P1 and the third portion DBM1_P3 in the second direction D2.

[0099] The second connection metal pattern DBM2 of the lower division structure LDB can include a fourth portion DBM2_P1 directly contacting the first source / drain pattern SD1 and a fifth portion DBM2_P2 disposed between the second division pad patterns DBL2.

[0100] The second division liner pattern DBL2 can be disposed on a first side surface of the fourth portion DBM2_P1, and the first source / drain pattern SD1 can be disposed on a second side surface of the fourth portion DBM2_P1 opposite the first side surface. In other words, the fourth portion DBM2_P1 of the second connection metal pattern DBM2 can be in direct contact with the first source / drain pattern SD1. Since the second division liner pattern DBL2 is not disposed on the second side surface of the fourth portion DBM2_P1, a width of the fourth portion DBM2_P1 in the second direction D2 can be greater than a width of the fifth portion DBM2_P2 in the second direction D2.

[0101] In Figure 5B , the liner layer LIN can be disposed on a second side surface of the third portion DBM1_P3, and the dummy pattern DSP can be disposed on a first side surface of the third portion DBM1_P3 opposite the second side surface. In this case, a width of the second portion DBM1_P2 in the second direction D2 can be substantially equal to a width of the third portion DBM1_P3 in the second direction D2.

[0102] In Figure 5C , the division liner pattern can be disposed only on the first side surface of the first and second connection metal patterns DBM1 and DBM2. For example, the first division liner pattern DBL1 can be disposed only on the first side surface of the first connection metal pattern DBM1, and the second division liner pattern DBL2 can be disposed only on the first side surface of the second connection metal pattern DBM2. The second etch stop layer ESL2, the second source / drain pattern SD2, and the liner layer LIN can be disposed on a second side surface of the first connection metal pattern DBM1 opposite the first side surface. The first source / drain pattern SD1 and the insulating pattern IP can be disposed on a second side surface of the second connection metal pattern DBM2 opposite the first side surface.

[0103] Hereinafter, a three-dimensional semiconductor device will be described in more detail with reference to Figures 6A to 6C the accompanying drawings. In the following description of the three-dimensional semiconductor device, previously described elements can be identified by the same reference numerals without repeating the repetitive description thereof for the sake of brief description.

[0104] A single height cell SHC as a logic unit can include a first active region AR1 and a second active region AR2 sequentially stacked on the base 105. One of the first active region AR1 and the second active region AR2 can be a PMOS-FET region, and the other of the first active region AR1 and the second active region AR2 can be an NMOS-FET region. The first active region AR1 can be disposed as a bottom layer of the FEOL layer, and the second active region AR2 can be disposed as a top layer of the FEOL layer. The NMOS-FET and the PMOS-FET of the first active region AR1 and the second active region AR2 can be vertically stacked to form a three-dimensional stacked transistor.

[0105] The first gate electrode GE1 and the third gate electrode GE3 can be disposed on each of the first channel patterns CH1. The first gate electrode GE1 and the third gate electrode GE3 can be spaced apart from each other with the first source / drain pattern SD1 interposed therebetween.

[0106] The second gate electrode GE2 and the fourth gate electrode GE4 can be disposed on each of the second channel patterns CH2. The second gate electrode GE2 and the fourth gate electrode GE4 can be spaced apart from each other with the second source / drain pattern interposed therebetween.

[0107] The first gate electrode GE1 and the third gate electrode GE3 can include different metal materials, and the second gate electrode GE2 and the fourth gate electrode GE4 can include different metal materials. In other words, the first gate electrode GE1 and the third gate electrode GE3 can be formed of or include work function metals different from each other, and the second gate electrode GE2 and the fourth gate electrode GE4 can be formed of or include work function metals different from each other. In this case, the transistor including the third gate electrode GE3 and the fourth gate electrode GE4 can be configured to have a threshold voltage different from that of the transistor including the first gate electrode GE1 and the second gate electrode GE2. Accordingly, it can be possible to prevent a leakage current path from being formed between adjacent cells in a cell.

[0108] In the case where the first gate electrode GE1 is a gate electrode of a PMOS-FET and the second gate electrode GE2 is a gate electrode of an NMOS-FET, the third gate electrode GE3 can be a gate electrode of an NMOS-FET and the fourth gate electrode GE4 can be a gate electrode of a PMOS-FET. In this case, the threshold voltage of the transistor including the fourth gate electrode GE4 can be greater than that of the transistor including the second gate electrode GE2.

[0109] In the case where the first gate electrode GE1 is a gate electrode of a PMOS-FET and the second gate electrode GE2 is a gate electrode of an NMOS-FET, the third gate electrode GE3 can be a gate electrode of an NMOS-FET and the fourth gate electrode GE4 can be a gate electrode of a PMOS-FET. In this case, the threshold voltage of the transistor including the fourth gate electrode GE4 can be greater than that of the transistor including the second gate electrode GE2. Figure 6CIn the present embodiment, the first source / drain pattern SD1 and the second source / drain pattern SD2 (see Figure 6A and Figure 6B ) can be electrically connected to each other using the gate electrode GE. For example, the gate electrode GE can include a third gate electrode GE3 and a fourth gate electrode GE4, and the third gate electrode GE3 and the fourth gate electrode GE4 can be in contact with each other.

[0110] In other words, the first source / drain pattern SD1 and the second source / drain pattern SD2 can be electrically connected to each other by the bottom interconnection line BMIL, the first bottom via pattern BVI1, the lower through via TRV1, the third gate electrode GE3 and the fourth gate electrode GE4, the upper through via TRV2, the second upper via pattern VI2, and the upper interconnection line MIL.

[0111] Figures 7A to 25E is a cross-sectional view illustrating an example of a method of manufacturing a three-dimensional semiconductor device according to some embodiments. In detail, Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A and Figure 25A are cross-sectional views corresponding to line A-A' of Figure 3A . Figure 17B , Figure 20B , Figure 21B , Figure 22B and Figure 25B are cross-sectional views corresponding to line B-B' of Figure 3A . Figure 7B , Figure 8B , Figure 9B , Figure 12B , Figure 13B , Figure 14 , Figure 15B , Figure 16B , Figure 17C , Figure 20C , Figure 21C , Figure 22C and Figure 25C are cross-sectional views corresponding to line C-C' of Figure 3A . Figure 9C , Figure 10B , Figure 11B , Figure 17D , Figure 20D、 Figure 21D 、 Figure 22D 、 Figure 25D are sectional views corresponding to line D-D' of Figure 3A . Figure 18B 、 Figure 19B 、 Figure 20E 、 Figure 21E 、 Figure 22E 、 Figure 23B 、 Figure 24B and Figure 25E are sectional views corresponding to line E-E' of Figure 3A .

[0112] In Figure 7A and Figure 7B , a first sacrificial layer SAL1 and a first active layer ACL1 can be alternately stacked on the semiconductor substrate 100. The first sacrificial layer SAL1 and the first active layer ACL1 can be formed of or include at least one of silicon (Si), germanium (Ge), and silicon germanium (SiGe), and can be formed of different materials from each other. For example, the first sacrificial layer SAL1 can be formed of or include silicon germanium (SiGe), and the first active layer ACL1 can be formed of or include silicon (Si). A concentration of germanium (Ge) in each of the first sacrificial layers SAL1 can be in a range of 10 at% to 30 at%.

[0113] A division layer DSL can be formed on an uppermost one of the first sacrificial layers SAL1. In some embodiments, a thickness of the division layer DSL can be greater than a thickness of each of the first active layer ACL1 and the first sacrificial layer SAL1. The division layer DSL can be formed of or include silicon (Si) or silicon germanium (SiGe). In a case where the division layer DSL includes silicon germanium (SiGe), a germanium concentration of the division layer DSL can be higher than a germanium concentration of the first sacrificial layer SAL1. For example, the germanium concentration of the division layer DSL can be in a range of 40 at% to 90 at%.

[0114] A second sacrificial layer SAL2 and a second active layer ACL2 can be alternately stacked on the division layer DSL. Each of the second sacrificial layers SAL2 can be formed of or include the same material as the first sacrificial layer SAL1, and each of the second active layers ACL2 can be formed of or include the same material as the first active layer ACL1. The division layer DSL can be interposed between the first sacrificial layers SAL1 and the second sacrificial layers SAL2.

[0115] The first and second sacrificial layers SAL1, SAL2, the first and second active layers ACL1, ACL2, and the division layer DSL can be patterned to form a stack pattern STP. The formation of the stack pattern STP can include forming a hard mask pattern on an uppermost one of the second active layers ACL2, and etching the layers SAL1, SAL2, ACL1, ACL2, and DSL on the semiconductor substrate 100 using the hard mask pattern as an etch mask. During the formation of the stack pattern STP, an upper portion of the semiconductor substrate 100 can be etched to form a trench TR that defines the active pattern AP. The stack pattern STP can be a bar pattern extending in the second direction D2.

[0116] The stack pattern STP can include a lower stack pattern STP1 on the active pattern AP, an upper stack pattern STP2 on the lower stack pattern STP1, and a division layer DSL between the lower stack pattern STP1 and the upper stack pattern STP2. The lower stack pattern STP1 can include the first sacrificial layers SAL1 and the first active layers ACL1 stacked alternately. The upper stack pattern STP2 can include the second sacrificial layers SAL2 and the second active layers ACL2 stacked alternately.

[0117] A device isolation layer ST can be formed on the semiconductor substrate 100 to fill the trench TR. For example, an insulating layer can be formed on the front surface of the semiconductor substrate 100 to cover the active pattern AP and the stack pattern STP. The device isolation layer ST can be formed by recessing the insulating layer to expose the stack pattern STP.

[0118] In Figure 8A and Figure 8B The sacrificial pattern PP can be formed to cross the stack pattern STP. The sacrificial pattern PP can be formed to have a linear shape extending in the first direction D1. For example, the formation of the sacrificial pattern PP can include forming a sacrificial layer on the front surface of the semiconductor substrate 100, forming a hard mask pattern MP on the sacrificial layer, and patterning the sacrificial layer using the hard mask pattern MP as an etch mask. The sacrificial layer can be formed of, or include, amorphous silicon and / or polysilicon.

[0119] A pair of gate spacers GS can be formed on opposite side surfaces of the sacrificial pattern PP, respectively. For example, a spacer layer can be conformally formed on the front surface of the semiconductor substrate 100. The spacer layer can cover the sacrificial pattern PP and the hard mask pattern MP. For example, the spacer layer can be formed of, or include, at least one of SiCN, SiCON, and SiN. The gate spacers GS can be formed by anisotropically etching the spacer layer.

[0120] In Figures 9A to 9C , an etching process can be performed on the stack pattern STP using the gate spacers GS and the hard mask pattern MP as etching masks. The recess RS can be formed at both sides of the sacrificial pattern PP by the etching process.

[0121] The liner layer LIN can be formed uniformly on the opposite side surfaces of the upper stack pattern STP2, the opposite side surfaces of the gate spacer GS, and the top surface of the hard mask pattern MP. The liner layer LIN can prevent the upper stack pattern STP2 from being exposed to the recess RS. The liner layer LIN can be formed to expose the lower stack pattern STP1. In some embodiments, the liner layer LIN can include silicon nitride.

[0122] In Figure 10A and Figure 10B , a first source / drain pattern SD1 can be formed in the recess RS, respectively. For example, the first source / drain pattern SD1 can be formed by a first SEG process in which the exposed side surfaces of the lower stack pattern STP1 are used as seed layers. The first source / drain pattern SD1 can be grown using the first active layer ACL1 and the active pattern AP exposed through the recess RS as seed layers. In some embodiments, the first SEG process can include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

[0123] During the first SEG process, impurities can be implanted into the first source / drain pattern SD1 in an in-situ manner. In some embodiments, after the formation of the first source / drain pattern SD1, impurities can be implanted into the first source / drain pattern SD1. The first source / drain pattern SD1 can be doped to have a first conductivity type (e.g., p-type).

[0124] The first active layer ACL1 interposed between a pair of the first source / drain patterns SD1 can constitute a first channel pattern CH1. In other words, the first semiconductor pattern SP1 and the second semiconductor pattern SP2 of the first channel pattern CH1 can be formed from the first active layer ACL1. The first channel pattern CH1 and the first source / drain pattern SD1 can constitute a first active region AR1 that is a bottom layer of a three-dimensional device.

[0125] The side surfaces of the upper stack pattern STP2 can be covered with the liner layer LIN. That is, due to the liner layer LIN, the second active layer ACL2 of the upper stack pattern STP2 can not be exposed to the outside during the first SEG process. Accordingly, an additional semiconductor layer can not be grown on the upper stack pattern STP2 during the first SEG process.

[0126] A first etch stop layer ESL1 can be formed to cover the first source / drain pattern SD1 and a first interlayer insulating layer 110 can be formed on the first etch stop layer ESL1. A top surface of the first interlayer insulating layer 110 can be coplanar with a top surface of the liner layer LIN. The first interlayer insulating layer 110 can fill the recess RS after the formation of the first source / drain pattern SD1. In some embodiments, the first interlayer insulating layer 110 can include a silicon oxide layer.

[0127] In Figure 11A and Figure 11B , a top surface of the first interlayer insulating layer 110 can be recessed to a level of a bottom surface of a lowermost one of the second active layers ACL2. As a result of the recessing step, an exposed portion of the liner layer LIN can be removed. A remaining portion of the liner layer LIN covered with the first interlayer insulating layer 110 can cover side surfaces of the division layer DSL. After the recessing step, the second active layers ACL2 can be exposed to the outside since the liner layer LIN is removed.

[0128] Second source / drain patterns SD2 can be formed on opposite side surfaces of the upper stack pattern STP2, respectively. For example, the second source / drain patterns SD2 can be formed by a second SEG process in which the side surfaces of the upper stack pattern STP2 are used as seed layers. The second source / drain patterns SD2 can be grown using the second active layers ACL2 exposed by the recess RS as seed layers. The second source / drain patterns SD2 can be doped to have a second conductivity type (e.g., n-type) different from the first conductivity type.

[0129] The second active layers ACL2 interposed between a pair of the second source / drain patterns SD2 can constitute a second channel pattern CH2. That is, the third and fourth semiconductor patterns SP3 and SP4 of the second channel pattern CH2 can be formed of the second active layers ACL2. The second channel pattern CH2 and the second source / drain patterns SD2 can constitute a second active region AR2 that is a top layer of the three-dimensional device.

[0130] The liner layer LIN can be removed by an etching process. A second etch stop layer ESL2 can be formed to cover the second source / drain patterns SD2, the gate spacers GS, and the hard mask pattern MP. A second interlayer insulating layer 120 can be formed on the second etch stop layer ESL2. A top surface of the second interlayer insulating layer 120 can be coplanar with a top surface of the second etch stop layer ESL2 on the hard mask pattern MP. In some embodiments, the second interlayer insulating layer 120 can include a silicon oxide layer.

[0131] In Figure 12A and Figure 12BIn this process, the second interlayer insulating layer 120 and the second etch stop layer ESL2 can be planarized to expose the top surface of the sacrificial pattern PP. The planarization of the second interlayer insulating layer 120 and the second etch stop layer ESL2 can be performed using an etch-back process or a chemical mechanical polishing (CMP) process. The hard mask pattern MP can be completely removed during the planarization process. As a result, the top surface of the second interlayer insulating layer 120 can be coplanar with the top surface of the sacrificial pattern PP and the top surface of the gate spacer GS.

[0132] exist Figure 12B In this process, a dicing pattern (CT) can be formed to penetrate the sacrificial pattern (PP). The dicing pattern (CT) can be formed on the cell boundary of a logic cell. The dicing pattern (CT) can be formed from at least one of silicon oxide and silicon nitride, or include at least one of silicon oxide and silicon nitride.

[0133] The exposed sacrificial pattern PP can be selectively removed. As a result of removing the sacrificial pattern PP, an outer region ORG can be formed to expose the first channel pattern CH1 and the second channel pattern CH2 (e.g., see...). Figure 12B Removal of the sacrificial pattern PP may include a wet etching process performed using an etchant solution capable of selectively etching polysilicon.

[0134] In some implementations, the partition layer DSL exposed through the outer region ORG can be removed by a wet etching process performed using an etch solution capable of selectively etching polysilicon.

[0135] exist Figure 13A , Figure 13B and Figure 14 In this process, a dummy pattern DSP can be formed to cover the lower stacked pattern STP1 and the upper stacked pattern STP2 exposed through the outer region ORG. The dummy pattern DSP can cover the gate spacer GS, the second etch stop layer ESL2, and the second interlayer insulating layer 120 (e.g., see...). Figure 13A The dummy pattern DSP may include a silicon-based insulating material, and in this embodiment, the dummy pattern DSP may include a silicon nitride layer.

[0136] A dry etching process can be performed to locally leave a dummy pattern DSP between the lower stacked pattern STP1 and the upper stacked pattern STP2. Figure 15A and Figure 15BIn this process, a dummy pattern DSP can be interposed between the lower stacked pattern STP1 and the upper stacked pattern STP2, and between the uppermost first sacrificial layer in the first sacrificial layer SAL1 of the lower stacked pattern STP1 and the lowermost second sacrificial layer in the second sacrificial layer SAL2. Furthermore, the first sacrificial layer SAL1 and the second sacrificial layer SAL2 exposed through the outer region ORG can be selectively removed to form the first inner region IRG1 to the sixth inner region IRG6, respectively (e.g., see...). Figure 15B For example, an etching process that selectively etches the first sacrificial layer SAL1 and the second sacrificial layer SAL2 can be performed to preserve the first semiconductor patterns SP1 to the fourth semiconductor patterns SP4 and the dummy pattern DSP, while removing only the first sacrificial layer SAL1 and the second sacrificial layer SAL2. The etching process can be performed using an etching formulation selected to have a high etching rate for silicon-germanium patterns with a relatively high germanium concentration. For example, the etching process can be selected to have a high etching rate for silicon-germanium layers with a germanium concentration higher than 10 at%.

[0137] Because the first sacrificial layer SAL1 and the second sacrificial layer SAL2 are selectively removed, the first semiconductor pattern SP1 and the second semiconductor pattern SP2 can be retained on the first active region AR1, and the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 can be retained on the second active region AR2. A dummy pattern DSP can be retained between the second semiconductor pattern SP2 and the third semiconductor pattern SP3.

[0138] exist Figure 15A and Figure 15B In this context, the empty space between the active pattern AP and the first semiconductor pattern SP1 can be defined as the first inner region IRG1; the empty space between the first semiconductor pattern SP1 and the second semiconductor pattern SP2 can be defined as the second inner region IRG2; and the empty space between the second semiconductor pattern SP2 and the dummy pattern DSP can be defined as the third inner region IRG3. The empty space between the dummy pattern DSP and the third semiconductor pattern SP3 can be defined as the fourth inner region IRG4; the empty space between the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 can be defined as the fifth inner region IRG5; and the empty space on the fourth semiconductor pattern SP4 can be defined as the sixth inner region IRG6. The sixth inner region IRG6 can be defined as an empty region extending into the outer region ORG.

[0139] exist Figure 16A and Figure 16BIn this process, a gate insulating layer GI can be conformally formed on the exposed first semiconductor pattern SP1 to the fourth semiconductor pattern SP4. A gate electrode GE can be formed on the gate insulating layer GI. The formation of the gate electrode GE may include forming a first inner electrode PO1 to a fifth inner electrode PO5 in the first inner region IRG1 to the fifth inner region IRG5, respectively, and forming an outer electrode PO6 in the outer region ORG (or the sixth inner region IRG6).

[0140] The gate electrode GE can be vertically recessed to have a reduced height. A gate cover pattern GP can be formed on the recessed gate electrode GE. A planarization process can be performed on the gate cover pattern GP such that the top surface of the gate cover pattern GP is coplanar with the top surface of the second interlayer insulating layer 120 and the top surface of the second etch stop layer ESL2.

[0141] exist Figures 17A to 17D In this process, a third interlayer insulating layer 130 may be formed on the second interlayer insulating layer 120 and the gate overlay pattern GP. In some embodiments, the third interlayer insulating layer 130 may include a silicon oxide layer.

[0142] Contact holes can be formed to penetrate the third interlayer insulating layer 130, the second etch stop layer ESL2, and the second interlayer insulating layer 120. Active contacts AC can be formed on the second source / drain pattern SD2 exposed through the contact holes. Active contacts AC can be formed in a self-aligned manner using the gate overlay pattern GP and the gate spacer GS.

[0143] A gate contact hole can be formed to penetrate the third interlayer insulating layer 130 and the gate cover pattern GP. A gate contact GC can be formed on the external electrode PO6 exposed through the gate contact hole.

[0144] For example, the formation of the active contact AC and the gate contact GC may include forming a blocking pattern BM and forming a conductive pattern FM on the blocking pattern BM. A metal-semiconductor compound layer SC may further be formed between each of the second source / drain patterns SD2 and the active contact AC. The active contact AC may be electrically connected to the second source / drain pattern SD2, and the gate contact GC may be connected to the second gate electrode GE2.

[0145] exist Figure 18A and Figure 18BIn the third interlayer insulating layer 130, the upper active contact AC, and the gate contact GC, a hard mask pattern can be formed, and an etching process using the hard mask pattern can be performed. The etching process can be an anisotropic dry etching process. The division recessed region RS_DB can be formed by the etching process. In some embodiments, the division recessed region RS_DB can be formed to expose a top surface of the dummy pattern DSP and side surfaces of the pair of second source / drain patterns SD2.

[0146] For example, the division recessed region RS_DB can be formed to penetrate the third interlayer insulating layer 130 and the gate cover pattern GP and expose a top surface of the dummy pattern DSP. A portion of the side surfaces of the cut pattern CT can be exposed by the division recessed region RS_DB (see, for example, Figure 18B ). The exposed top surface of the dummy pattern DSP can be coplanar with a top surface of the dummy gate electrode DGE and a top surface of the gate insulating layer GI.

[0147] In Figure 19A and Figure 19B , an upper division structure UDB can be formed in the division recessed region RS_DB. The formation of the upper division structure UDB can include forming a first division liner pattern DBL1 in the division recessed region RS_DB, performing an etching process to remove a portion of the first division liner pattern DBL1 and the dummy pattern DSP, and forming a first connection metal pattern DBM1.

[0148] A bottom surface of the first connection metal pattern DBM1 can be located at a lower height than a bottom surface of the first division liner pattern DBL1 in the third direction D3. That is, the first connection metal pattern DBM1 can be formed to include a portion extending into the dummy gate electrode DGE.

[0149] In Figures 20A to 20E , a fourth interlayer insulating layer 140 can be formed on the third interlayer insulating layer 130, the upper active contact AC, the gate contact GC, and the upper division structure UDB. A first upper via pattern VI1 and a second upper via pattern VI2 and an upper interconnection line MIL can be formed in the fourth interlayer insulating layer 140. The first upper via pattern VI1 and the second upper via pattern VI2 and the upper interconnection line MIL can be defined as a first metal layer M1.

[0150] For example, the upper division structure UDB can be electrically connected to the second source / drain pattern SD2 through the second upper via pattern VI2, the upper interconnection line MIL, and the upper active contact AC. The second gate electrode GE2 can be electrically connected to the upper interconnection line MIL through the first upper via pattern VI1.

[0151] Figures 7A to 20EThe semiconductor substrate 100 can be inverted after a back end of line (BEOL) process. In view of the semiconductor substrate 100 being inverted, in Figures 21A to 25E The terms "top surface" and "upper" in the following description of the three-dimensional semiconductor device should be understood to refer to the "bottom surface" and "lower" in the final structure of the three-dimensional semiconductor device described with reference to Figures 4A to 4E The terms "bottom surface" and "lower" in the following description of the three-dimensional semiconductor device should be understood to refer to the "top surface" and "upper" in the final structure of the three-dimensional semiconductor device described with reference to Figures 21A to 25E The terms "bottom surface" and "lower" in the following description of the three-dimensional semiconductor device should be understood to refer to the "top surface" and "upper" in the final structure of the three-dimensional semiconductor device described with reference to Figures 4A to 4E The terms "bottom surface" and "lower" in the following description of the three-dimensional semiconductor device should be understood to refer to the "top surface" and "upper" in the final structure of the three-dimensional semiconductor device described with reference to

[0152] In Figures 21A to 21E , if the BEOL process is completed, the semiconductor substrate 100 can be inverted so that the bottom surface of the semiconductor substrate 100 is exposed to the outside. A portion of the exposed semiconductor substrate 100 can be removed.

[0153] In some embodiments, the semiconductor substrate 100 can include silicon (Si). In this case, the partial removal of the semiconductor substrate 100 can include performing a planarization process SAF on the bottom surface 100b of the semiconductor substrate 100 to reduce the thickness of the semiconductor substrate 100, and performing a cleaning process to selectively remove silicon (Si) atoms from the semiconductor substrate 100. That is, after the partial removal of the semiconductor substrate 100, the device isolation layer ST can be exposed. In this case, the top surface of the device isolation layer ST can be coplanar with the top surface of the active pattern AP.

[0154] In Figures 22A to 22E , a cleaning process or a wet etching process can be performed to remove the remaining semiconductor substrate 100 except for the device isolation layer ST including the silicon-based insulating material. After the semiconductor substrate 100 is removed, a silicon-based insulating material can be deposited to form an insulating pattern IP.

[0155] The formation of the insulating pattern IP can include removing the semiconductor substrate 100, depositing a silicon-based insulating material on the region where the silicon is removed, and performing a planarization process on the silicon-based insulating material to form the insulating pattern IP. The planarization process can be performed to expose the top surface of the device isolation layer ST.

[0156] A backside contact hole can be formed to penetrate the insulating pattern IP. A bottom active contact BAC can be formed on the first source / drain pattern SD1 exposed through the backside contact hole. The formation of the bottom active contact BAC can include forming a hard mask pattern on the insulating pattern IP and performing an etching process using the hard mask pattern.

[0157] For example, the formation of the bottom active contact BAC can include forming a bottom barrier pattern BBM and forming a bottom conductive pattern BFM on the bottom barrier pattern BBM. A metal-semiconductor compound layer SC can be further formed between each of the first source / drain patterns SD1 and the bottom active contact BAC. The bottom active contact BAC can be electrically connected to the first source / drain patterns SD1. In some embodiments, the bottom active contact BAC can be formed to penetrate the insulating pattern IP and can extend into the first source / drain patterns SD1.

[0158] In Figure 23A and Figure 23B , a hard mask pattern can be formed on the insulating pattern IP, and an etching process can be performed using the hard mask pattern. The etching process can be an anisotropic dry etching process. As a result of the etching process, a lower division recessed region RS BDB can be formed. In some embodiments, the lower division recessed region RS BDB can be formed to expose a top surface of the first connection metal pattern DBM1 and side surfaces of the pair of first source / drain patterns SD1.

[0159] For example, the lower division recessed region RS BDB can be an empty region formed by removing the dummy gate electrode DGE to penetrate the device isolation layer ST and the insulating pattern IP and expose a top surface of the first connection metal pattern DBM1. A portion of the side surfaces of the cut pattern CT can be exposed by the lower division recessed region RS BDB (e.g., see Figure 23B ). The exposed top surface of the first connection metal pattern DBM1 can be located at a higher height than a top surface of the first division liner pattern DBL1 in the third direction D3.

[0160] In Figure 24A and Figure 24B , a lower division structure LDB can be formed on the lower division recessed region RS BDB. The formation of the lower division structure LDB can include forming a second division liner pattern DBL2 on the lower division recessed region RS BDB, performing an etching process to remove a portion of the second division liner pattern DBL2, and forming a second connection metal pattern DBM2.

[0161] The second connection metal pattern DBM2 can be in contact with the first connection metal pattern DBM1, and the second division liner pattern DBL2 can be in contact with the first division liner pattern DBL1. The first interface IF1 between the first connection metal pattern DBM1 and the second connection metal pattern DBM2 can be located at a higher height than the second interface IF2 between the first division liner pattern DBL1 and the second division liner pattern DBL2 when measured in the third direction D3. In some embodiments, at least one of the first interface IF1 and the second interface IF2 can not be observable or measurable. This is because the first division liner pattern DBL1 and the second division liner pattern DBL2 include the same material, and the first connection metal pattern DBM1 and the second connection metal pattern DBM2 include the same material.

[0162] In Figures 25A to 25E , a fifth interlayer insulation layer 150 can be formed on the insulation pattern IP, the bottom active contact BAC, and the lower division structure LDB. A first bottom via pattern BVI1 and a second bottom via pattern BVI2 and a bottom interconnection line BMIL can be formed in the fifth interlayer insulation layer 150. The first bottom via pattern BVI1 and the second bottom via pattern BVI2 and the bottom interconnection line BMIL can be defined as a lower metal layer BSM1.

[0163] For example, the lower division structure LDB can be electrically connected to the first source / drain pattern SD1 through the first bottom via pattern BVI1, the bottom interconnection line BMIL, and the bottom active contact BAC.

[0164] In Figure 4E , in the three-dimensional semiconductor device, the vertically stacked first source / drain pattern SD1 and the second source / drain pattern SD2 can be electrically connected to each other through the division structure DBST.

[0165] In the three-dimensional field effect transistor according to some embodiments, the source / drain regions of the vertically stacked transistors can be connected to each other through a division structure (e.g., a single diffusion break (SDB)), and in this case, an overhead phenomenon caused by a connection pattern for connecting the source / drain regions can be prevented. In other words, the effective area of a logic cell can be reduced, and thus, the integration density of the three-dimensional semiconductor device can be increased.

[0166] In the three-dimensional field effect transistor according to some embodiments, it can be possible to reduce a parasitic capacitance between a gate electrode and a division structure. Thus, the three-dimensional semiconductor device can have improved reliability.

[0167] While the present disclosure contains many specific embodiments, these should not be construed as limiting the scope of that which can require protection or equivalent action under law. Certain features that are described in the context of separate embodiments can also be implemented in combination with each other. Conversely, various features that are described in the context of a single embodiment can also be implemented separately from that single embodiment or in any appropriate subcombination. Moreover, although features can be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised, and the claimed combination can then be directed to a subcombination or variation of a subcombination.

Claims

1. A three-dimensional semiconductor device comprising: a first active region on a substrate, the first active region including a first channel pattern and a first source / drain pattern connected to the first channel pattern; a second active region stacked on the first active region, the second active region including a second channel pattern and a second source / drain pattern connected to the second channel pattern; a gate electrode over the first channel pattern and the second channel pattern; a bottom active contact electrically connected to the first source / drain pattern, the bottom active contact having a strip shape extending from the first source / drain pattern in a first direction; a lower metal layer disposed below the bottom active contact, the lower metal layer including a bottom via pattern and a bottom interconnect electrically connected to the bottom active contact, and a division structure electrically connected to at least one of the bottom via pattern, wherein the division structure includes a division spacer pattern and a connection metal pattern extending into the division spacer pattern.

2. The three-dimensional semiconductor device of claim 1, further comprising: an upper active contact electrically connected to the second source / drain pattern, the upper active contact having a strip shape extending from the second source / drain pattern in the first direction; and a first metal layer over the upper active contact, the first metal layer including an upper via pattern and an upper interconnect electrically connected to the upper active contact, wherein the division structure is electrically connected to at least one of the upper via pattern.

3. The three-dimensional semiconductor device of claim 2, the division spacer pattern includes a first division spacer pattern and a second division spacer pattern, wherein wherein the connection metal pattern includes a first connection metal pattern and a second connection metal pattern, wherein the division structure includes: a lower division structure; and an upper division structure over the lower division structure, wherein the upper division structure includes the first division spacer pattern and the first connection metal pattern extending into the first division spacer pattern, and wherein the lower division structure includes the second division spacer pattern and the second connection metal pattern extending into the second division spacer pattern. The first division spacer pattern has a constant first thickness in a second direction crossing the first direction.

4. The three-dimensional semiconductor device of claim 3, wherein, 5. The three-dimensional semiconductor device of claim 3, the second division spacer pattern includes a first portion adjacent to the first source / drain pattern and a second portion disposed below the first portion, wherein wherein the first portion has a constant second thickness in a second direction crossing the first direction, and wherein the second portion has a third thickness in the second direction that increases as a distance to the lower metal layer decreases.

6. The three-dimensional semiconductor device of claim 3, the first division spacer pattern has a first thickness in a second direction crossing the first direction, wherein wherein the second division spacer pattern includes a first portion adjacent to the first source / drain pattern and a second portion disposed below the first portion, wherein the first portion has a second thickness in the second direction, wherein the second portion has a third thickness in the second direction, and wherein the second thickness is greater than the first thickness and the third thickness. A maximum of the third thickness is equal to the first thickness.

7. The three-dimensional semiconductor device of claim 6, wherein, 8. The three-dimensional semiconductor device of claim 3, ​ wherein The first division spacer pattern and the second division spacer pattern include an insulating material, and The first connection metal pattern and the second connection metal pattern include a metal material.

9. The three-dimensional semiconductor device of claim 8, wherein The insulating material includes at least one of silicon oxide, silicon nitride, and silicon oxynitride, and The metal material includes at least one of aluminum, copper, tungsten, molybdenum, and cobalt.

10. A three-dimensional semiconductor device, comprising: a substrate including an insulating pattern defined by a device isolation layer; a division structure extending in a first direction crossing the insulating pattern; a lower metal layer disposed below the substrate, the lower metal layer including a bottom via pattern and a bottom interconnection line; and a first metal layer on the division structure, the first metal layer including an upper via pattern and an upper interconnection line, The division structure includes: a connection metal pattern; and a division spacer pattern disposed on side surfaces of the connection metal pattern and surrounding the connection metal pattern, and The bottom interconnection line, the bottom via pattern, the connection metal pattern, the upper via pattern, and the upper interconnection line are electrically connected to each other.

11. The three-dimensional semiconductor device of claim 10, further comprising: a cut pattern disposed on the device isolation layer and on opposite side surfaces of the division structure.

12. The three-dimensional semiconductor device of claim 10, wherein, The division structure includes a lower division structure and an upper division structure on the lower division structure.

13. The three-dimensional semiconductor device of claim 10, wherein, The connection metal pattern includes molybdenum or cobalt, and The division spacer pattern includes silicon nitride.

14. A three-dimensional semiconductor device, comprising: a first active region on the substrate, the first active region including a first channel pattern and a first source / drain pattern connected to the first channel pattern; a dummy region stacked on the first active region, the dummy region including a dummy pattern on the first channel pattern and an interlayer insulating layer on the first source / drain pattern; a second active region stacked on the dummy region, the second active region including a second channel pattern and a second source / drain pattern connected to the second channel pattern; a gate electrode on the first channel pattern and the second channel pattern; a bottom active contact electrically connected to the first source / drain pattern; a lower metal layer disposed below the bottom active contact, the lower metal layer including a bottom via pattern and a bottom interconnection line electrically connected to the bottom active contact; an upper active contact electrically connected to the second source / drain pattern; and a division structure electrically connected to at least one of the bottom via patterns, The division structure includes a division spacer pattern and a connection metal pattern extending into the division spacer pattern, and The connection metal pattern is in direct contact with the first source / drain pattern and the second source / drain pattern.

15. The three-dimensional semiconductor device of claim 14, wherein The division spacer pattern includes a first division spacer pattern and a second division spacer pattern, The connection metal pattern includes a first connection metal pattern and a second connection metal pattern, The division structure includes: a lower division structure; and an upper division structure on the lower division structure, The upper division structure includes the first division spacer pattern and a first connection metal pattern extending into the first division spacer pattern, and The second division spacer pattern includes a second connection metal pattern extending into the second division spacer pattern. The lower division structure includes a second division pad pattern and a second connection metal pattern extending into the second division pad pattern.

16. The three-dimensional semiconductor device of claim 15, wherein, The first division pad pattern includes a plurality of first division pad patterns, and the dummy pattern includes a plurality of dummy patterns, The first connection metal pattern includes a first portion between the plurality of first division pad patterns, a second portion in contact with the second source / drain pattern, and a third portion between the plurality of dummy patterns, and The width of the second portion is greater than the width of the first portion and the width of the third portion.

17. The three-dimensional semiconductor device of claim 15, wherein, The second division pad pattern includes a plurality of second division pad patterns, The second connection metal pattern includes a first portion in contact with the first source / drain pattern and a second portion between the plurality of second division pad patterns, and The width of the first portion is greater than the width of the second portion.

18. The three-dimensional semiconductor device of claim 15, wherein The first division pad pattern includes a plurality of first division pad patterns, The first connection metal pattern includes a first portion between the plurality of first division pad patterns, a second portion in contact with the second source / drain pattern, and a third portion below the second portion, and The dummy pattern is disposed on a side surface of the third portion.

19. The three-dimensional semiconductor device of claim 15, wherein The first division pad pattern is disposed on one side surface of the first connection metal pattern, and The second division pad pattern is disposed on one side surface of the second connection metal pattern.

20. A three-dimensional semiconductor device comprising: a substrate including an insulating pattern; a first active region on the insulating pattern, the first active region including first channel patterns horizontally spaced apart from each other and first source / drain patterns disposed between the first channel patterns and connected to the first channel patterns; a second active region stacked on the first active region, the second active region including second channel patterns horizontally spaced apart from each other and second source / drain patterns disposed between the second channel patterns and connected to the second channel patterns; first and third gate electrodes disposed on the first channel patterns, respectively; second and fourth gate electrodes disposed on the second channel patterns, respectively; a lower metal layer disposed below the substrate, the lower metal layer including a bottom via pattern and a bottom interconnection line; a first metal layer on the first and third gate electrodes, the first metal layer including an upper via pattern and an upper interconnection line; a lower through via connecting the third gate electrode to the bottom via pattern; and an upper through via connecting the fourth gate electrode to the upper via pattern, The first and third gate electrodes include different materials from each other, and The second and fourth gate electrodes include different materials from each other. ​

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