Silicon nanowire net channel neuron transistor and preparation method thereof

Abstract

The invention provides a silicon nanowire net channel neuron transistor and a preparation method thereof, and relates to the technical field of semiconductors. The silicon nanowire network channel neuron transistor comprises a phase change inner gate; the first dielectric layer covers the phase change inner gate; the phase change inner gate electrode is arranged on the first dielectric layer and is used for transmitting the received electric pulse signal to the phase change inner gate; the transparent electrode is arranged on the first dielectric layer and is used for transmitting a received optical pulse signal to the phase change inner gate; wherein the phase change inner gate is configured to regulate and control the phase state of the phase change inner gate according to the received electric pulse signal and optical pulse signal.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly, to a silicon nanowire network channel neuron transistor and a preparation method thereof. BACKGROUND

[0002] In recent years, the rapid development of artificial intelligence has led to an increasing demand for high-speed and high-efficiency computing hardware. As the scale of algorithm models expands exponentially, the demand for computing power, data processing speed, and energy consumption also increases. The traditional computing architecture based on the von Neumann system has a problem of high energy consumption and low speed due to the separation of storage and calculation, and the frequent transfer of data between the two, which is the main constraint for processing large-scale neural network tasks. In addition, the traditional digital CMOS circuit relies on time-division multiplexing of the computing unit, and the Boolean operation characteristics of the logic gate cannot directly simulate the continuous adjustability of the synaptic weight. There are inherent limitations in simulating the parallel computing and adaptive learning of the human brain, making it difficult to meet the needs of edge computing, brain-like computing, and real-time AI applications. Therefore, researching new neuron transistors to build neural network circuits has become a key direction to break through the existing computing bottleneck.

[0003] The human brain can complete complex cognitive tasks with extremely low power consumption due to its high degree of parallel synaptic plasticity and neuron pulse computing mechanism. Inspired by this, neuromorphic computing devices aim to simulate the dynamic characteristics of biological neural networks through hardware to achieve efficient and low-power intelligent computing. Among them, electronic synapses can simulate the weight adjustment of biological synapses, and neuron transistors can mimic the pulse firing mechanism of neurons. The neural network circuit composed of these devices can directly implement machine learning algorithms at the hardware level, thereby avoiding the data transfer bottleneck of traditional AI chips. However, existing technologies are still limited by non-ideal device characteristics and system-level integration challenges. SUMMARY

[0004] Therefore, the present disclosure provides a silicon nanowire network channel neuron transistor and a preparation method thereof, which can at least partially solve the above technical problems.

[0005] In one aspect, the present disclosure provides a silicon nanowire network channel neuron transistor, comprising: a phase change inner gate; a first dielectric layer covering the phase change inner gate; a phase change inner gate electrode disposed on the first dielectric layer and configured to transmit a received electrical pulse signal to the phase change inner gate; and a transparent electrode disposed on the first dielectric layer and configured to transmit a received optical pulse signal to the phase change inner gate; wherein the phase change inner gate is configured to regulate the phase state of the phase change inner gate according to the received electrical pulse signal and optical pulse signal.

[0006] According to an embodiment of the present disclosure, the phase change inner gate is further configured to regulate the phase state of the phase change inner gate according to a time interval between the optical pulse signal and the electrical pulse signal; the time interval Δt satisfies: or 5 ns≤Δt≤+50 ns.

[0007] According to an embodiment of the present disclosure, the wavelength of the optical pulse signal is 500 nm-1550 nm, and the width of the optical pulse signal is 20 ns-200 ns; the voltage of the electrical pulse signal is 1 V-2.5 V, and the width of the electrical pulse signal is 50 ns-500 ns.

[0008] According to an embodiment of the present disclosure, further comprising: a micro-nano lens disposed on the transparent electrode, configured to regulate the intensity of the optical pulse signal.

[0009] According to an embodiment of the present disclosure, further comprising: a second dielectric layer disposed between the transparent electrode and the micro-nano lens, configured to isolate the transparent electrode and the micro-nano lens; the thickness of the second dielectric layer is λ / 4n, wherein λ is the center wavelength of the optical pulse signal, and n is the refractive index of the second dielectric layer.

[0010] According to an embodiment of the present disclosure, further comprising: a source region silicon conductive mesa, a silicon nanowire periodic network structure and a drain region silicon conductive mesa connected in sequence along a first direction, and a third dielectric layer covering the source region silicon conductive mesa, the silicon nanowire periodic network structure and the drain region silicon conductive mesa; a part of the phase change inner gate is disposed on the third dielectric layer and located on a region corresponding to the silicon nanowire periodic network structure; wherein the transparent electrode and the phase change inner gate form a resistance-capacitance parallel structure, and the channel current of the silicon nanowire periodic network structure is regulated according to the phase state of the phase change inner gate.

[0011] According to an embodiment of the present disclosure, the phase change inner gate comprises at least one strip gate along a second direction, and the second direction is perpendicular to the first direction.

[0012] According to an embodiment of the present disclosure, the silicon nanowire periodic network structure is a polygon surrounded by an array of silicon nanowires, and the polygon includes one of a triangle, a quadrilateral and a hexagon, and the side length of the polygon is 30 nm-1000 nm.

[0013] According to an embodiment of the present disclosure, the material of the third dielectric layer includes at least one of SiO2, Si3N4, Al2O3, HfO2, ZrO2 and HfxZr (1-x) O2.

[0014] The second aspect of the present disclosure provides a preparation method of a silicon nanowire network channel neuron transistor, comprising: depositing a phase change material to prepare a phase change inner gate; preparing a first dielectric layer on the phase change inner gate; depositing a phase change inner gate electrode and a transparent electrode on the first dielectric layer respectively; wherein the phase change inner gate electrode is configured to transmit the received electrical pulse signal to the phase change inner gate; the transparent electrode is configured to transmit the received optical pulse signal to the phase change inner gate; and the phase change inner gate is configured to regulate the phase state of the phase change inner gate according to the received electrical pulse signal and optical pulse signal.

[0015] The silicon nanowire network channel neuron transistor provided by the embodiment of the present disclosure has at least the following beneficial effects:

[0016] By integrating the transparent electrode to receive the optical pulse signal and the phase-change inner gate electrode to receive the electrical pulse signal, the transistor can process electrical signals and optical signals simultaneously. During the phase change, the optical pulse can provide the necessary energy to change the state of the phase-change material. Compared with using only electrical pulse driving, the optical pulse can generate higher energy density locally, thereby more effectively triggering the phase change. This allows the required electrical driving voltage to be reduced, thereby reducing overall energy consumption. And this photoelectric collaborative design not only increases the functional diversity of the device, but also makes it more suitable for application scenarios that require multiple types of input.

[0017] At the same time, by finely controlling the state of the phase-change inner gate, the transistor can more accurately simulate the weight change process in the biological synapse. The photoelectric collaborative way allows more flexible and accurate adjustment of the input signal, which helps to build more efficient and functionally rich transistor-based neural network circuits. BRIEF DESCRIPTION OF DRAWINGS

[0018] The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure, taken in conjunction with the accompanying drawings, in which:

[0019] Figure 1 The structure schematic diagram of the transistor according to the embodiment of the present disclosure is schematically shown;

[0020] Figure 2 The cross-sectional view of the transistor along the first direction according to the embodiment of the present disclosure is schematically shown;

[0021] Figure 3 The cross-sectional view of the transistor along the second direction according to the embodiment of the present disclosure is schematically shown;

[0022] Figure 4 The structure schematic diagram of the discrete phase-change inner gate according to the embodiment of the present disclosure is schematically shown;

[0023] Figure 5 The schematic diagram of the silicon nanowire periodic network structure according to the embodiment of the present disclosure is schematically shown;

[0024] Figure 6 The equivalent circuit diagram of the transistor according to the embodiment of the present disclosure is schematically shown;

[0025] Figure 7 The transistor array connection diagram according to the embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0026] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that the description is merely exemplary and is not intended to limit the scope of the present disclosure. In the following detailed description of the embodiments, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. However, it would be apparent to those skilled in the art that the embodiments can be practiced without these specific details. In other instances, well-known systems and methods have not been described in detail in order to avoid obscuring the concepts of the present disclosure.

[0027] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the term "includes" and tautological expressions thereof, such as "including," "includes," "include," "contains," "containing," and so on, mean the presence of stated features, steps, operations, elements, and / or components but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0028] All terms used herein, including technical and scientific terms, have the meanings commonly understood by one of ordinary skill in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted as having a meaning that is consistent with the context of the specification, and should not be interpreted in an idealized or overly formal way.

[0029] In the case of using expressions similar to "at least one of A, B, and C, etc.", it should generally be interpreted to include at least one of each item enumerated, in the sense of including, e.g., at least one of A, at least one of B, at least one of C, combinations thereof, etc.

[0030] Figure 1 A schematic diagram of a structure of a transistor according to an embodiment of the present disclosure is schematically shown.

[0031] Figure 2 A cross-sectional view of a transistor according to an embodiment of the present disclosure along a first direction is schematically shown.

[0032] Figure 3 A cross-sectional view of a transistor according to an embodiment of the present disclosure along a second direction is schematically shown.

[0033] As Figures 1-3 shown, the silicon nanowire mesh channel neuron transistor of this embodiment includes a phase-change inner gate 1, a first dielectric layer 2, a phase-change inner gate electrode 3, and a transparent electrode 4.

[0034] The first dielectric layer 2 is disposed on the phase-change inner gate 1.

[0035] The phase-change inner gate electrode 3 is disposed on the first dielectric layer 2 and is used to transmit a received electrical pulse signal to the phase-change inner gate 1.

[0036] A transparent electrode 4 is disposed on the first dielectric layer 2, for transmitting the received optical pulse signal to the phase-change inner gate 1.

[0037] The phase-change inner gate 1 is configured to regulate the phase state of the phase-change inner gate 1 according to the received electrical pulse signal and optical pulse signal.

[0038] In embodiments of the present disclosure, by introducing photoelectric synergistic operation, the optical pulse can provide the necessary energy to change the state of the phase-change material during the phase change process. Compared with driving only using electrical pulse, the optical pulse can generate higher energy density locally, thereby more effectively triggering the phase change, which reduces the required electrical driving voltage and thus reduces the overall energy consumption; and by finely regulating the state of the phase-change inner gate, the transistor can more accurately simulate the weight change process in biological synapses. The photoelectric synergistic implementation allows more flexible and accurate adjustment of the input signal, which helps to build more efficient and functionally rich transistor-based neural network circuits. By integrating the transparent electrode 4 to receive the optical pulse signal and the phase-change inner gate electrode 3 to receive the electrical pulse signal, the transistor can process electrical signals and optical signals simultaneously. This photoelectric synergistic design not only increases the functional diversity of the device, but also makes it more suitable for application scenarios that require multiple types of input. At the same time, for image recognition and other applications, traditional systems usually need to convert optical information into electrical signals before processing. In the present embodiment, since the optical pulse signal can be directly received and processed, the optical-electric conversion step is omitted, simplifying the signal processing process and improving efficiency. This is of great significance for improving image processing speed and reducing delay.

[0039] Further, the transparent electrode 4 can be an indium tin oxide (ITO) electrode. ITO has excellent light transmittance and conductivity. Compared with other electrodes such as metal electrodes, the optical pulse signal passing through ITO to the phase-change material will not be significantly absorbed, reducing energy transmission loss. In addition, directly transmitting strong light to the phase-change layer can cause damage to the structure of the phase-change material, degradation of performance, or unstable phase change. Using ITO as an intermediate layer can buffer and homogenize the signal distribution, avoid thermal breakdown, and thus control the crystallization and amorphization process of the phase-change material.

[0040] According to embodiments of the present disclosure, the phase-change inner gate 1 is further configured to regulate the phase state of the phase-change inner gate 1 according to the timing interval between the optical pulse signal and the electrical pulse signal.

[0041] The timing interval Δt satisfies: or 5ns≤Δt≤+50ns.

[0042] In the embodiments of the present disclosure, the optical pulse signal is generally short, and can instantaneously trigger the local phase change of the phase change material; the electrical pulse signal is relatively long, and can provide a slow regulation or determination time window, so as to ensure that the Δt is adjustable, thereby simulating the plasticity (Spike-Timing-Dependent Plasticity, STDP for short) behavior of the biological synapse.

[0043] When the photoelectric cooperative pulse regulation is received, the crystallization degree of the phase state of the phase change material can be affected by the time difference of the photoelectric pulse signal. When the time difference of the photoelectric pulse signal makes the crystallization enhanced, the conductivity of the phase change material is increased, which is effective in enhancing the gate control ability of the transistor, so that the source-drain current of the transistor is increased, and the weight is increased. Conversely, the weight is reduced. Meanwhile, under the photoelectric cooperative regulation, the STDP behavior and the like can also be simulated. For the optical pulse signal with high frequency and energy and the electrical pulse signal with low frequency and energy, when the optical pulse signal reaches the ITO electrode first, the phase change material is locally and rapidly heated to near the crystallization temperature, and then the electrical pulse signal with low energy is superimposed, so that the phase change material is continuously maintained in the temperature zone near the crystallization temperature, the phase change material is crystallized, thereby simulating the biological synapse enhancement (LTP), and the weight is increased. When the electrical pulse signal reaches the ITO electrode first, the phase change material is preheated, and then when the optical pulse signal arrives, the energy is transferred to the phase change material in the subheat zone, and the temperature instantaneously exceeds the melting point, and then the phase change material is rapidly cooled to the amorphous state after the end of the pulse, thereby simulating the weakening of the biological synapse (LTD), that is, the weight is reduced.

[0044] That is, there is a time interval Δt between the optical pulse signal and the electrical pulse signal. When the optical pulse arrives first, it is recorded as Δt>0, and the synapse enhancement is realized. Conversely, when Δt<0, the synapse inhibition is realized. The time interval Δt is generally limited by the relaxation time and the heat diffusion time of the phase change material. The maximum allowed Δt should not exceed the crystallization time of the phase change material, so as to ensure that the provided pulse signal can effectively regulate the crystalline state.

[0045] On the basis of the above-mentioned embodiments, the wavelength of the optical pulse signal is 500nm to 1550nm, and the width of the optical pulse signal is 20ns to 200ns. The voltage of the electrical pulse signal is 1V to 2.5V, and the width of the electrical pulse signal is 50ns to 500ns.

[0046] In the embodiments of the present disclosure, the phase change behavior of the phase change material is excited by using the optical pulse with a wavelength in the range of 500nm to 1550nm. Optionally, the wavelength of the light source includes but is not limited to 532nm, 650nm, 785nm, 1064nm and the like, so as to adapt to the material absorption window and the power consumption control requirement.

[0047] Further, the frequency of the optical pulse signal can be 10Hz to 1kHz; and the frequency of the electrical pulse signal can be 10Hz to 1kHz.

[0048] According to an embodiment of the present disclosure, the micro-nano lens 6 is arranged on the transparent electrode 4 and is used to regulate the intensity of the optical pulse signal.

[0049] In an embodiment of the present disclosure, each micro-nano lens 6 corresponds to a transistor unit, which can ensure that the optical pulse only acts on the target phase change material region to avoid crosstalk, and can further focus and enhance the light field to achieve the pulse intensity of the modulated phase change material.

[0050] Further, the lens material can be , SiN, but is not limited thereto.

[0051] According to an embodiment of the present disclosure, the silicon nanowire network channel neuron transistor further comprises a second dielectric layer 5 arranged between the transparent electrode 4 and the micro-nano lens 6, and used to isolate the transparent electrode 4 and the micro-nano lens 6.

[0052] The thickness of the second dielectric layer 5 is λ / 4n, wherein λ is the center wavelength of the optical pulse signal, and n is the refractive index of the second dielectric layer 5.

[0053] In an embodiment of the present disclosure, the second dielectric layer 5 arranged on the transparent electrode 4 can be used for optical antireflection, electric field modulation, and interface passivation.

[0054] By regulating the thickness of the first dielectric layer 2, the device can be sensitive to the light of the center wavelength and the waveband near the center wavelength, thereby improving the sensitivity to the light to be identified, and equivalently improving the weight.

[0055] Further, the materials of the first dielectric layer 2 and the second dielectric layer 5 can be Al2O3, SiO2, and other oxidized insulating materials, but are not limited thereto.

[0056] According to an embodiment of the present disclosure, the silicon nanowire network channel neuron transistor further comprises a source region silicon conductive mesa 7, a silicon nanowire periodic network structure 14, and a drain region silicon conductive mesa 8 connected in sequence along a first direction, and a third dielectric layer 9 covering the source region silicon conductive mesa 7, the silicon nanowire periodic network structure 14, and the drain region silicon conductive mesa 8.

[0057] Part of the phase change inner gate 1 is arranged on the third dielectric layer 9 and located on the region corresponding to the silicon nanowire periodic network structure 14.

[0058] The transparent electrode 4 and the phase change inner gate 1 form a resistance-capacitance parallel structure, and the channel current of the silicon nanowire periodic network structure 14 is regulated according to the phase state of the phase change inner gate 1.

[0059] In the embodiment of the present disclosure, the phase change inner gate 1 is arranged in the mesh of the silicon nanowire periodic network 14 and on the third dielectric layer 9 outside the mesh, which is suitable for forming an inner gate capacitor with the silicon nanowire periodic network channel. By filling the phase change gate material into the line mesh gap, the gate control capability of the device can be effectively improved. The phase change gate can be designed as a resistance-capacitance (RC) oscillation circuit, which can modulate the charging and discharging time of the gate charge through the resistance and dielectric constant change of the phase change material, which is very helpful for the weighted calculation function and threshold firing behavior of the transistor analog neuron.

[0060] Further, the phase change inner gate electrode 3 is connected with the phase change inner gate 1 through the contact hole, and the transparent electrode 4 is connected with the phase change inner gate 1 through the contact hole. The source ohmic contact electrode 10 and the drain ohmic contact electrode 11 are respectively formed on the source region silicon conductive platform 7 and the drain region silicon conductive platform 8 through the contact hole.

[0061] The doping type of the source region silicon conductive platform 7, the drain region silicon conductive platform 8 and the channel region of the silicon nanowire periodic network structure 14 is N type or P type, and the doping concentration is 5×10 17 cm -3 ~5×10 21 cm -3 ; wherein, when the doping type of the source region and the drain region and the doping type and the doping concentration of the channel region are the same, the neuron transistor is a junctionless device.

[0062] Figure 4 The structure schematic diagram of the discrete phase change inner gate according to the embodiment of the present disclosure is schematically shown.

[0063] As Figure 4 shown, the phase change inner gate 1 of the embodiment includes at least one strip gate along the second direction, and the second direction is perpendicular to the first direction.

[0064] Specifically, the phase change inner gate 1 can include discrete strip gates 1-1 and 1-2 arranged along the second direction.

[0065] Further, the thickness of the phase change inner gate 1 is 3 nm to 100 nm, and the width is 100 nm to 1000 nm; for the discrete phase change inner gate, the interval matches the size of the nanowire honeycomb network channel, and the interval is 30 nm to 1000 nm.

[0066] In the embodiment of the present disclosure, the silicon nanowire mesh channel size can be prepared as a plurality of discrete structures, and the discrete phase change inner gate can receive multiple input pulse signals to jointly control the equivalent gate length and gate resistance to simulate the multi-signal weighted summation function of the synapse.

[0067] Figure 5 The schematic diagram of the silicon nanowire periodic network structure according to the embodiment of the present disclosure is schematically shown.

[0068] As shown in Figure 5 The silicon nanowire periodic network structure of this embodiment is a polygon surrounded by an array of silicon nanowires, the polygon includes one of a triangle, a quadrilateral and a hexagon, the side length of the polygon is 30nm-1000nm, and the thickness is 3nm-100nm.

[0069] In the embodiments of the present disclosure, an N×N network can be constructed according to application requirements, the channel length is extended or shortened by changing the value of N, the number of discrete phase change inner gates 9 is increased in a larger network structure to process more input signals, and the size of a single transistor is smaller in a smaller network structure to facilitate integration. Meanwhile, the through-hole formed by the nanowire honeycomb network channel has a low thermal conductivity, which can reduce the local hot spots of the phase change material, avoid the separation of amorphous and crystal phases caused by temperature gradient, and help to maintain the stability of the phase state. Compared with a single nanowire device, the silicon nanowire network channel neuron transistor of this embodiment can enhance the total current carrying capacity of the channel and has a higher driving current output; and the multi-branch conduction path of the network channel can effectively balance the current distribution and improve the electrical linearity of the device.

[0070] According to the embodiments of the present disclosure, the material of the third dielectric layer 9 includes at least one of SiO2, Si3N4, Al2O3, HfO2, ZrO2 and HfxZr (1-x) O2.

[0071] Figure 6 An equivalent circuit diagram of a transistor according to an embodiment of the present disclosure is schematically shown.

[0072] As shown in Figure 6 , the transistor drain electrode 11 is connected to a bias voltage V d , and the source electrode 10 is connected to ground; the phase change inner gate 1 and the phase change inner gate electrode 3 are connected and can be equivalent to a phase change inner gate resistance, and the transparent electrode 4 is separated from the phase change inner gate 1 by the first dielectric layer 2 and can be equivalent to a capacitor function, so that the phase change inner gate 1, the first dielectric layer 2, the phase change inner gate electrode 3 and the transparent electrode 4 together form a resistance-capacitance parallel structure, which provides time integration modulation and voltage delay response characteristics for the light and electrical pulse signals applied to the gate, so that the timing difference of the input signals is converted into different voltage accumulation strengths. A suitable RC time constant τ can filter out high-frequency noise Δt accuracy to match the STDP window of the synapse. In addition, when the phase change inner gate is a plurality of discrete phase change inner gates, the effective channel length of the transistor can be adjusted by applying or not applying signals to different phase change inner gates. The transistor embedded with a single or multiple phase change inner gates can be regarded as an “integrate-fire” unit: when the equivalent gate voltage formed by the superposition of the capacitance voltages of the single or multiple RC paths is high enough, the transistor is turned on, and the current is output through the transistor; if the gate voltage does not reach the threshold, the transistor remains cut off, thereby simulating the neuron behavior of threshold Value turn-on.

[0073] Figure 7 A transistor array connection diagram is schematically shown according to an embodiment of the present disclosure.

[0074] As shown in Figure 7 , each silicon nanowire network channel neuron transistor is taken as an adjustable conductance synapse unit, and an array is formed in a cross-over wiring manner. The ITO gate of each transistor is connected in rows to form a word line (WL), which is modulated by inputting an electrical pulse to the neuron, and each transistor can be regarded as a pixel point, which receives a light pulse through a lens. The drain of each transistor is connected in columns to form a bit line (BL), which provides a bias voltage to drive and read a current, and outputs the neuron. The phase change material filled in the hole of the transistor is taken as a weight storage, and the crystallization degree of the phase change material is changed under different light and electrical pulses to change the weight and affect the size of the final transistor output current.

[0075] The second aspect of the present disclosure provides a preparation method of a silicon nanowire network channel neuron transistor, comprising:

[0076] Depositing a phase change material to prepare a phase change inner gate 1.

[0077] Preparing a first dielectric layer 2 on the phase change inner gate.

[0078] Depositing a phase change inner gate electrode 3 and a transparent electrode 4 on the first dielectric layer, respectively.

[0079] The phase change inner gate electrode 3 is configured to transmit the received electrical pulse signal to the phase change inner gate 1, and the transparent electrode 4 is configured to transmit the received light pulse signal to the phase change inner gate 1. The phase change inner gate 1 is configured to regulate the phase state of the phase change inner gate 1 according to the received electrical pulse signal and light pulse signal.

[0080] In an embodiment of the present disclosure, the preparation method is compatible with the CMOS process, and has the advantages of simple process, small device size, high integration density, and wide application value.

[0081] In some possible embodiments, the preparation method of the embodiment comprises:

[0082] In operation S101, a SiO2 mask is formed by thermal oxidation on the surface of an SOI substrate, and N-type or P-type ion doping is injected into the top silicon through the mask.

[0083] Specifically, the top silicon surface of the SOI wafer is subjected to thermal oxidation at a temperature of 850-1000°C to form a thermal oxide layer with a thickness of 10-30 nm, and then doped by ion implantation of N-type or P-type impurities at an implantation energy of 20-50 keV. After rapid thermal annealing in a nitrogen atmosphere at a temperature of 900-1100°C and for an annealing time of 10-60 s, the impurity concentration of the N-type or P-type impurities in the top silicon is 10 17 cm -3 ~10 21 cm -3

[0084] Further, the SOI substrate comprises a silicon substrate, a substrate insulating layer and a top silicon layer which are sequentially stacked.

[0085] In operation S102, the silicon nanowire net channel 14, the source region silicon conduction mesa 7 and the drain region silicon conduction mesa 8 are prepared on the substrate by electron beam exposure and ICP etching.

[0086] Specifically, the wafer after oxidation is cleaned, and a negative or positive electron beam resist with a thickness of 80-120 nm and matching the layout design is coated on the sample. After drying for 1 min by a hot plate at 85°C, the pattern on the layout is exposed by an electron beam lithography device, and then the silicon dioxide mask and the top silicon thin layer are etched by plasma dry etching (ICP) to form the silicon nanowire net channel 14, the source region silicon conduction mesa 7 and the drain region silicon conduction mesa 8.

[0087] In operation S103, the third dielectric layer 9 is formed on the surface of the silicon nanowire net channel 14, the source region silicon conduction mesa 7 and the drain region silicon conduction mesa 8 by thermal oxidation or atomic layer deposition process.

[0088] The thickness of the third dielectric layer 9 is 1-20 nm.

[0089] In operation S104, the phase change material is deposited on the third dielectric layer 9 on the silicon nanowire net channel 3 to form a single or multiple phase change inner gate 1.

[0090] Specifically, the positive electron beam resist with a thickness of 80-120 nm is uniformly coated on the prepared first dielectric layer 2, and then the phase change inner gate region is exposed by an electron beam device. The phase change material is deposited on the third dielectric layer 9 by magnetron sputtering process, and then the single or multiple phase change inner gate 1 is prepared by metal lift-off process.

[0091] ​Further, the phase-change inner gate 1 can also be prepared in another way, including: first depositing a phase-change material on the third dielectric layer 9 through a magnetron sputtering process, then uniformly coating 80-120 nm thick negative electron beam glue on the phase-change material, then exposing the phase-change inner gate area through an electron beam device, and then preparing a single or multiple phase-change inner gates 1 through dry etching.

[0092] The material of the phase-change inner gate 1 is any one of Ge2Sb2Te5, GeTe, SbTe, SiSbTe, or GeSb.

[0093] In operation S105: generating the first dielectric layer 2 on the surface of the phase-change inner gate 1 through a thermal oxidation or atomic layer deposition process.

[0094] Further, for discrete phase-change inner gates, the generated first dielectric layer 2 should have a thickness slightly larger than that of the discrete phase-change inner gate to sufficiently isolate and prevent communication between the two discrete inner gates.

[0095] In operation S106: forming a contact hole in the third dielectric layer 9 above the source silicon conduction mesa 7 and the drain silicon conduction mesa 8 through a photolithography, dry etching, ion implantation, and annealing process, and forming a source ohmic contact electrode 10 and a drain ohmic contact electrode 11 through electron beam evaporation and metal stripping process, and forming an ohmic contact between the source (drain) ohmic contact electrode and the source (drain) silicon conduction mesa.

[0096] The material of the source ohmic contact electrode and the drain ohmic contact electrode includes any one or more of annealed Al, Ni / Al alloy, and Ti / Al alloy.

[0097] In operation S107: preparing the ITO transparent electrode 4 and the phase-change inner gate electrode 3 on the first dielectric layer 2 through sputtering and stripping.

[0098] Further, the material of the phase-change inner gate electrode 3 includes at least one of polycrystalline silicon material, metal material, alloy material, or light-conducting, heat-conducting, and electricity-conducting material with phase-change function; and the length of the strip gate part of the phase-change inner electrode conduction mesa along the vertical silicon nanowire net channel direction is 10 nm-10 µm.

[0099] In operation S108: generating the second dielectric layer 5 on the transparent electrode 4, and preparing a micro-nano lens array on the second dielectric layer 5 through nano-imprinting, so that in the array of silicon nanowire net channel neuron transistors, each nano lens corresponds to a transistor unit to ensure that the light pulse only acts on the target GST area.

[0100] Those skilled in the art can understand that the features recited in various embodiments and / or claims of the present disclosure can be combined and / or integrated in various combinations, even if such combinations or integrations are not expressly recited in the present disclosure. In particular, the features recited in various embodiments and / or claims of the present disclosure can be combined and / or integrated in various combinations without departing from the spirit and teachings of the present disclosure. All such combinations and / or integrations fall within the scope of the present disclosure.

[0101] The above describes embodiments of the present disclosure. However, these embodiments are merely for illustrative purposes, and are not intended to limit the scope of the present disclosure. Although each embodiment is described above separately, this does not mean that the measures in each embodiment cannot be advantageously used in combination. The scope of the present disclosure is defined by the appended claims and their equivalents. Those skilled in the art can make various substitutions and modifications without departing from the scope of the present disclosure, and all such substitutions and modifications shall fall within the scope of the present disclosure.

Claims

1. A silicon nanowire network channel neuron transistor, characterized by, The application relates to a phase change inner gate, which comprises the following parts: a phase change inner gate; a first dielectric layer covering the phase change inner gate; a phase change inner gate electrode arranged on the first dielectric layer and used for transmitting a received electric pulse signal to the phase change inner gate; and a transparent electrode arranged on the first dielectric layer and used for transmitting a received light pulse signal to the phase change inner gate; The phase change inner gate is configured to regulate the phase state of the phase change inner gate according to the received electric pulse signal and the light pulse signal. The phase change inner gate is further configured to regulate the phase state of the phase change inner gate according to the time interval between the light pulse signal and the electric pulse signal.

2. The silicon nanowire network channel neuron transistor of claim 1, wherein, The wavelength of the light pulse signal is 500nm-1550nm, and the width of the light pulse signal is 20ns-200ns. The timing interval At satisfies: or 5 ns ≤ At ≤ + 50 ns.

3. The silicon nanowire network channel neuron transistor of claim 2, wherein, The voltage of the electric pulse signal is 1V-2.5V, and the width of the electric pulse signal is 50ns-500ns. The application further comprises a micro-nano lens arranged on the transparent electrode and used for regulating the intensity of the light pulse signal.

4. The silicon nanowire network channel neuron transistor of claim 1, wherein, The application further comprises a second dielectric layer arranged between the transparent electrode and the micro-nano lens and used for isolating the transparent electrode and the micro-nano lens. The thickness of the second dielectric layer is lambda / 4n, wherein lambda is the central wavelength of the light pulse signal, and n is the refractive index of the second dielectric layer.

5. The silicon nanowire network channel neuron transistor of claim 4, wherein, The application further comprises a source region silicon conductive mesa, a silicon nanowire periodic network structure and a drain region silicon conductive mesa connected in sequence along a first direction, and a third dielectric layer covering the source region silicon conductive mesa, the silicon nanowire periodic network structure and the drain region silicon conductive mesa. Part of the phase change inner gate is arranged on the third dielectric layer and located on the region corresponding to the silicon nanowire periodic network structure. The transparent electrode and the phase change inner gate form a resistance-capacitance parallel structure, and the channel current of the silicon nanowire periodic network structure is regulated according to the phase state of the phase change inner gate.

6. The silicon nanowire network channel neuron transistor of claim 1, wherein, The phase change inner gate comprises at least one strip gate along a second direction, and the second direction is perpendicular to the first direction. The silicon nanowire periodic network structure is a polygon surrounded by array-arranged silicon nanowires, the polygon comprises one of a triangle, a quadrilateral and a hexagon, and the side length of the polygon is 30nm-1000nm. The application relates to a phase change inner gate, which comprises the following parts: The application relates to a phase change inner gate, which comprises the following parts:

7. The silicon nanowire network channel neuron transistor of claim 6, wherein, a phase change inner gate electrode and a transparent electrode are respectively deposited on the first dielectric layer; 8. The silicon nanowire network channel neuron transistor of claim 6, wherein, The phase change inner gate electrode is used for transmitting a received electric pulse signal to the phase change inner gate; 9. The silicon nanowire network channel neuron transistor of claim 6, wherein, The material of the third dielectric layer includes at least one of SiO2, Si3N4, Al2O3, HfO2, ZrO2, and HfxZr (1-x) O2.

10. A method of fabricating a silicon nanowire network channel neuron transistor, comprising: The transparent electrode is used for transmitting a received light pulse signal to the phase change inner gate; The phase change inner gate is configured to regulate the phase state of the phase change inner gate according to the received electric pulse signal and the light pulse signal. ​ ​ ​ ​ ​

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