Media scanning method for reducing active idle power of memory device

Abstract

A method for reducing active idle power in a memory device includes incrementing, by a first processing device, a first counter when a read or write request is not received from a host system for a first predetermined time period, and transitioning to a sleep mode in response to determining that the first counter has reached a first predetermined threshold. The method also includes incrementing, by a second processing device, a second counter when no read or write request is received from the host system for a second predetermined time period, and transitioning to the sleep mode in response to determining that the second counter has reached a second predetermined threshold.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to memory sub-systems, and more specifically, to systems and methods for reducing active idle power of a memory device in a memory sub-system. BACKGROUND

[0002] A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory sub-system to store data at the memory devices and retrieve data from the memory devices. BRIEF DESCRIPTION OF DRAWINGS

[0003] The present disclosure will be more fully understood from the following detailed description taken in connection with the accompanying drawings, from which like reference numerals represent similar structures, and in which:

[0004] Figure 1 An example computing system including a memory sub-system according to some embodiments of the present disclosure is described.

[0005] Figure 2 A block diagram of a processor in a memory sub-system according to some embodiments of the present disclosure is described.

[0006] Figure 3 A media scan operation for reducing active idle power in a memory device according to some embodiments of the present disclosure is described.

[0007] Figure 4A A media scan operation for reducing active idle power in a memory device according to some embodiments of the present disclosure is described.

[0008] Figure 4B A media scan operation for reducing active idle power in a memory device according to some embodiments of the present disclosure is described.

[0009] Figure 5A A flow diagram of an example method for reducing active idle power in a memory device according to some embodiments of the present disclosure is described.

[0010] Figure 5B A flow diagram of an example method for reducing active idle power in a memory device according to some embodiments of the present disclosure is described.

[0011] Figure 6 A block diagram of an example computer system in which embodiments of the present disclosure can operate. DETAILED DESCRIPTION

[0012] Aspects of the disclosure relate to systems and methods for reducing active idle power of a memory device. Active idle power is the power consumed by a memory device in an active idle state. A memory device is in an active idle state when a host system is not performing read or write operations. A memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices and memory modules are described below in connection with Figure 1 Examples of storage devices and memory modules are described. Generally, a host system can utilize a memory sub-system that includes one or more components, such as a memory device that stores data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.

[0013] A memory sub-system can include high-density non-volatile memory devices, where retention of data is required when no power is supplied to the memory device. One example of a non-volatile memory device is a “not- and” (NAND) memory device. Examples of non-volatile memory devices are described below in connection with Figure 1 Other examples of non-volatile memory devices are described. Each of the memory devices can include one or more arrays of memory cells. A memory cell (“cell”) is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more bits of binary information and have various logical states related to the number of bits stored. The logical states can be represented by binary values, such as “0” and “1,” or combinations of these values. For example, a single-level cell (SLC) can store one bit of information and have two logical states. Similarly, a multi-level cell (MLC) can store two bits per cell, a triple-level cell (TLC) can store three bits per cell, a quad-level cell (QLC) can store four bits per cell, and a penta-level cell (PLC) can store five bits per cell. A memory sub-system includes a memory sub-system controller that can communicate with the memory devices to perform operations such as reading data, writing data, or erasing data at the memory devices, and other such operations. Examples of memory sub-system controllers are described below in connection with Figure 1 A memory sub-system controller is described in more detail.

[0014] When performing memory access operations (e.g., read operations (e.g., in response to a received memory access request / command)), a memory sub-system can correct errors present in data being read. For example, after reading data from a memory device, a memory sub-system controller can perform an error detection and correction operation. The error detection and correction operation includes identifying one or more errors (e.g., bit flip errors) in the read data. The memory sub-system can have the ability to correct a certain number of errors per management unit (e.g., using an error correction code (ECC)). As long as the number of errors in a management unit is within the ECC capability of the memory sub-system, the errors can be corrected before providing the data to a requester (e.g., a host system). The percentage of bits containing incorrect data before applying the ECC is referred to as the raw bit error rate (RBER). The percentage of bits containing incorrect data after applying the ECC is referred to as the uncorrectable bit error rate (UBER). To prevent the existence of those same errors when performing subsequent memory access operations to the same management unit (e.g., block or page or super block), the memory sub-system can perform a write back operation. In a write back operation, the data from the management unit is overwritten with the corrected data that was just read from the memory device. Thus, when data is read, any errors present in the data will be corrected such that these errors do not persist.

[0015] However, some "not and" (NAND) memory devices experience an increase in raw bit error rate (RBER) over time due to charge loss and / or charge gain. If not handled in an efficient manner, this can create a large threshold voltage (Vt) distribution valley margin, leading to data degradation on a NAND page, which can result in an increase in bit error count and can eventually lead to data loss. Therefore, media scan operations can be performed at regular time intervals in order to meet the data retention requirements of the memory device. However, the time required to perform a super page scan can be long. During a media scan operation, multiple processors within a memory subsystem controller are invoked when each processor maintains a separate clock. For example, a flash translation layer processor within the subsystem controller can send a scan request to a back end processor to obtain the RBER of a scan page and can trigger a valley health check scan if the RBER is greater than a threshold. Similarly, when a media scan operation invokes a firmware module, corresponding hardware blocks are also invoked, including the memory subsystem controller, dynamic random access memory (DRAM), and NAND device. Such activities can increase the peak power used by the SSD in an active idle state, which is also referred to as "sleep mode" hereinafter, and the sleep interval between two consecutive media scan operations can be short since the memory subsystem controller enters and exits sleep mode each time it receives a "wake up" signal from each of the processors. The SSD can initiate some power saving mechanisms, such as processor sleep, clock reduction, or DRAM self-refresh, in order to meet the active idle power expectation. However, when such power saving mechanisms are applied, the functionality and data integrity of the drive can be compromised, and this impact is more pronounced in higher capacity SSDs.

[0016] Accordingly, one embodiment of the present disclosure is a method for reducing active idle power or power consumed by a memory device in sleep mode. The method includes decoupling some of the processors from input / output read processors such that the decoupled processors can continue to perform the required media scan operations, but the input / output read processors and the input / output interface between the memory subsystem controller and the host system can transition to sleep mode to reduce the active idle power. The method further includes combining two or more media scan operations and performing a burst scan operation such that the sleep interval between one burst scan operation and a subsequent burst scan operation is increased. In some embodiments, the memory subsystem controller can perform media scan operations on multiple channels on an open NAND flash interface (ONFI) bus simultaneously. In some embodiments, the memory subsystem controller can perform burst scan operations on multiple channels on an ONFI bus simultaneously such that the sleep interval between one burst scan operation and a subsequent burst scan operation is increased, and then reduce the active idle power in sleep mode.

[0017] Advantages of this approach include, but are not limited to, reducing active idle power in a memory device. For example, a memory device using the approach described herein uses less than 5 watts of power in active idle mode over a 30 second period of time regardless of form factor or capacity. The power saving effects are magnified in end applications such as data center SSDs. The disclosed approach provides an optimized active idle mode detection and control method by decoupling the I / O path from the media scan operation so that the I / O path can enter the sleep mode more frequently. The disclosed approach also provides an optimized media scan method in the sleep mode so that the media scan operation and the corresponding hardware block have additional opportunities to enter the sleep mode. The disclosed approach also provides a media scan sub-module that is silent during the sleep mode to further reduce the power used by the hardware block. A memory device using the media scan method described in this disclosure can be readily compliant with the requirements of the Open Computer Project (OCP) that requires active idle power to be less than 5 watts.

[0018] Figure 1 An example computing system 100 including a memory sub-system 110 according to some embodiments of this disclosure is described. The memory sub-system 110 can include media such as one or more volatile memory devices (e.g., memory devices 140), one or more non-volatile memory devices (e.g., memory devices 130), or a combination of such media.

[0019] The memory sub-system 110 can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid state drives (SSDs), zone namespace (ZNS) SSDs, flash drives, universal serial bus (USB) flash drives, embedded multimedia controllers (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0020] The computing system 100 can be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other means of transportation), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such computing device including a memory and a processing device.

[0021] The computing system 100 can include a host system 120 coupled to one or more memory sub-systems 110. In some embodiments, the host system 120 is coupled to different types of memory sub-systems 110. Figure 1An example of a host system 120 coupled to a memory sub-system 110 is described. As used herein, “coupled to” or “coupled with” generally refers to a connection between components that can be an indirect communicative connection or direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0022] The host system 120 can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, memory controllers (e.g., NVDIMM controllers), and storage protocol controllers (e.g., PCIe controllers, SATA controllers). The host system 120 uses the memory sub-system 110, for example, to write data to and read data from the memory sub-system 110.

[0023] The host system 120 can be coupled to the memory sub-system 110 via a physical host interface. Examples of a physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), etc. The physical host interface can be used to transfer data between the host system 120 and the memory sub-system 110. When the memory sub-system 110 is coupled with the host system 120 by a physical host interface (e.g., a PCIe bus), the host system 120 can further utilize an NVM Express (NVMe) interface to access components (e.g., the memory devices 130). The physical host interface can provide an interface for communicating control, address, data, and other signals between the memory sub-system 110 and the host system 120. Figure 1 The memory sub-system 110 is described as an example. In general, the host system 120 can access multiple memory sub-systems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0024] The memory devices 130, 140 can include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., the memory devices 140) can be, but are not limited to, random access memories (RAMs), such as dynamic random access memories (DRAMs) and synchronous dynamic random access memories (SDRAMs).

[0025] Some examples of non-volatile memory devices (e.g., memory devices 130) include NAND-type flash memory and in-place write memory, such as a three-dimensional cross-point (“3D cross-point”) memory device, which is a cross-point array of non-volatile memory cells. A cross-point array of non-volatile memory can perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-grided data access array. Additionally, in contrast to many flash-based memories, cross-point non-volatile memory can perform in-place write operations, where a non-volatile memory cell can be programmed without prior erasure of the non-volatile memory cell. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0026] Each of the memory devices 130 can include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), can store one bit per cell. Other types of memory cells, such as a multi-level cell (MLC), a triple-level cell (TLC), a quad-level cell (QLC), and a penta-level cell (PLC), can store multiple bits per cell. In some embodiments, each of the memory devices 130 can include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination of such arrays of memory cells. In some embodiments, a particular memory device can include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory devices 130 can be grouped into pages, which can refer to a logical unit of the memory device for storing data. For some types of memory (e.g., NAND), pages can be grouped to form blocks (e.g., super blocks). A “super block” refers to a group of physical blocks that includes physical blocks from each plane within a corresponding group, and a super block can span multiple memory devices.

[0027] Although non-volatile memory components such as 3D cross-point non-volatile memory cell arrays and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory devices 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), “not-or” (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0028] The memory sub-system controller 115 (or, for simplicity, the controller 115) can communicate with the memory devices 130 to perform operations such as reading data, writing data, or erasing data at the memory devices 130, among other such operations. The memory sub-system controller 115 can include hardware such as one or more integrated circuits and / or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory sub-system controller 115 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0029] The memory sub-system controller 115 can be a processing device that includes one or more processors (e.g., the processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory sub-system controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory sub-system 110, including handling communications between the memory sub-system 110 and the host system 120.

[0030] In some embodiments, the local memory 119 can include memory registers that store memory pointers, fetched data, and the like. The local memory 119 can also include read-only memory (ROM) for storing microcode. Although Figure 1 The example memory sub-system 110 in FIG. 1 has been illustrated as including the memory sub-system controller 115, but in another embodiment of the present disclosure, the memory sub-system 110 does not include the memory sub-system controller 115 and can instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory sub-system).

[0031] In general, memory sub-system controller 115 can receive commands or operations from host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to memory devices 130. Memory sub-system controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical address (e.g., logical block address (LBA), namespace) and a physical address (e.g., physical block address) associated with memory devices 130. Memory sub-system controller 115 can also include host interface circuitry to communicate with host system 120 via a physical host interface. The host interface circuitry can convert commands received from a host system into command instructions to access memory devices 130, as well as convert responses associated with memory devices 130 into information for host system 120.

[0032] Memory sub-system 110 can also include additional circuitry or components not illustrated. In some embodiments, memory sub-system 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that can receive an address from memory sub-system controller 115 and decode the address to access memory devices 130.

[0033] In some embodiments, memory devices 130 include a local media controller 135 that operates in conjunction with memory sub-system controller 115 to perform operations on one or more memory units of memory devices 130. An external controller (e.g., memory sub-system controller 115) can externally manage memory devices 130 (e.g., perform media management operations on memory devices 130). In some embodiments, memory devices 130 are managed memory devices, which are raw memory devices combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0034] In one embodiment, the memory sub-system 110 includes a sleep mode management component 113 that receives clock signals (e.g., sleep signals) from various processors (e.g., those represented by the processor 117). The sleep mode management component 113 decouples some of the processors from input / output read processors (e.g., at the firmware and / or control signal level), such that the decoupled processors can continue to perform required media scan operations, but the input / output interface between the input / output read processors and the memory sub-system controller 115 and the host system 120 can transition to a sleep mode to reduce active idle power. Subsequently, when a wake-up event occurs, such as receiving a read or write command from the host system 120, receiving a PCIe reset request from the host system 120, or receiving any other command from the host system 120, the sleep mode management component 113 can resume normal operation (e.g., drive activity) of the memory sub-system 110.

[0035] In some embodiments, the memory sub-system controller 115 includes at least a portion of the sleep mode management component 113. For example, the memory sub-system controller 115 can include a processor 117 (e.g., processing device) configured to execute instructions stored in local memory 119 for performing the operations described herein. In other embodiments, the sleep mode management component 113 is part of the memory sub-system 110, but separate from the memory sub-system controller 115. In other embodiments, the local media controller 135 includes at least a portion of the sleep mode management component 113 and is configured to perform the functionality described herein. In some embodiments, the processor 117 can combine two or more media scan operations and perform a burst scan operation such that the sleep interval between one burst scan operation and a subsequent burst scan operation is increased. In some embodiments, the processor 117 can perform media scan operations simultaneously on multiple channels on an ONFI bus that connects the memory sub-system controller 115 to one or more memory devices 130. In some embodiments, the processor 117 can perform burst scan operations simultaneously on multiple channels on an ONFI bus such that the sleep interval between one burst scan operation and a subsequent burst scan operation is increased and then reduce active idle power in a sleep mode.

[0036] Figure 2A block diagram illustrating a processor 117 in a memory sub-system 110 in accordance with some embodiments is described. The processor 117 can include an input / output read processor 202. The processor 202 can be responsible for processing input / output (I / O) requests received from the host system 120, ensuring data integrity and efficient storage, and managing the underlying NAND flash memory (e.g., memory devices 130). When the processor 202 processes I / O requests, it performs several operations on both the requests and the data. For the requests, the processor 202 schedules the requests in a manner that ensures correctness and provides high performance. For the data, the processor 202 can scramble the data to improve raw bit error rates, perform ECC encoding / decoding, and in some cases compress / decompress and / or encrypt / decrypt the data and employ super-page level data parity. To manage the NAND flash memory, the processor 202 runs firmware that maps host data to physical NAND flash pages, performs garbage collection on flash pages that have been invalidated, applies wear leveling to distribute the effects of writes across all pages uniformly to NAND flash reliability, and manages bad NAND flash blocks. The processor 202 can include a firmware sleep mode control 210 and a sleep detector 212. The sleep detector 212 can include a counter that increments when no read or write requests are received from the host system 120 for a predetermined period of time. When the counter reaches a predetermined threshold, the sleep detector can send a sleep signal to the firmware sleep mode control 210, which can transition the memory sub-system 110 to a sleep mode.

[0037] The processor 117 can also include a flash translation layer (FTL) processor 206, which can include a separate hibernation detector 216. The processor 206 can manage the mapping of logical addresses (i.e., the address space utilized by the host system 120) to physical addresses in the underlying flash memory (e.g., the address space of the actual locations where data is stored, visible only to the memory controller 115) for each page of data. By providing this redirection between address spaces, the FTL can remap logical addresses to different physical addresses (e.g., move data to different physical addresses) without notifying the host system 120. Whenever the host system 120 writes or moves a page of data for underlying SSD maintenance operations (e.g., garbage collection), the old data (e.g., the physical location where the overwritten data resided) is simply marked as invalid in the metadata of the physical block, and the new data is written to a page in the flash block that is currently open for writing. The processor 206 is also responsible for wear leveling to ensure that all blocks within the SSD are worn evenly. By evenly distributing wear (e.g., the number of program and erase cycles that occur) between different blocks, the memory controller 115 reduces the unevenness of the amount of wear between these blocks, thereby extending the life of the device. When the current block being written to is full (e.g., there are no more pages in the block available for writing), a wear leveling algorithm is invoked, and it enables the controller to select a new block from the free list to direct future writes. The wear leveling algorithm dictates which block to select from the free list. One simple approach is to select the block with the fewest number of program and erase cycles in the free list to minimize the variance in the amount of wear between the blocks. The hibernation detector 216 can include a counter that increments when no read or write requests are received from the host system 120 for a predetermined period of time. When the counter reaches a predetermined threshold, the hibernation detector can send a hibernation signal to the firmware hibernation mode control 210, which can transition the memory sub-system 110 to a hibernation mode.

[0038] In some embodiments, the processor 117 can include additional processors, such as an I / O write processor 204 and a back-end processor 208, which can each include their own hibernation detector units 214 and 218, respectively. The back-end processor 208 can be coupled to each of the memory devices via one or more channels (e.g., channels 0-7) on an ONFI bus that connects the memory sub-system controller 115 to the memory devices. However, in Figure 2In the embodiment illustrated in FIG. 3, the processors 204 and 208 are decoupled from the processor 202 (e.g., at the firmware and / or control signal level) such that the decoupled processors (e.g., labeled 'X') can continue to perform the required media scan operations, but the input / output read processor 202 and the memory sub-system controller 115 can transition to a sleep mode to reduce active idle power between the input / output interface and the host system 120. Subsequently, when a wake-up event occurs, such as receiving a read or write command from the host system 120, receiving a PCIe reset request from the host system 120, or receiving any other command from the host system 120, the processor 202 can resume normal operation (e.g., drive activity) of the memory sub-system 110.

[0039] Figure 3 A method 300 for performing media scan operations for reducing active idle power in a memory device is described in accordance with some embodiments. While the processors 202 and 206 are in a sleep mode, the back-end processor 208 can continue to perform media scan operations to maintain data integrity. For example, the media scan operations can include read operations, write operations, and or sense operations performed on a memory management unit (e.g., a page or a block or a super block). Under normal operation, the back-end processor 208 can periodically perform media scan operations 304 on each ONFI bus channel 302 such that the scan operations are evenly distributed over a period of time. The number of scan operations to perform can depend on the number of pages to be scanned, and this number can vary based on the number of pages in a block or the number of super pages in a super block. In some embodiments, as illustrated in method 350, the back-end processor 208 determines the number of scan operations to perform on the memory device, and combines two or more media scan operations 304, and performs a burst scan operation 308 such that the sleep interval 310 between one burst scan operation and a subsequent burst scan operation increases. This not only reduces power between burst scan operations 308, but also creates a burst scan interval 312 between one burst scan cycle (e.g., across all memory blocks in the memory device) and the next burst scan cycle.

[0040] Figure 4AAn alternative method 400 for performing media scan operations for reducing active idle power in a memory device is illustrated in accordance with some embodiments. In this example, the backend processor 208 can concurrently perform media scan operations 404 on multiple channels 302 on the ONFI bus connecting the memory subsystem controller 115 with one or more memory devices 130 when the processors 202 and 206 are in a sleep mode. As a result, the scan interval 406 between a first scan operation 404 and a subsequent scan operation is increased, which in turn maintains the I / O path between the processors 202 and 206 and the memory controller 115 and the host system 120 in a sleep mode for a longer period of time.

[0041] Figure 4B An alternative method 450 for performing media scan operations for reducing active idle power in a memory device is illustrated in accordance with some embodiments. In this example, the backend processor 208 combines the media scan operations of the methods 350 and 400, where the backend processor 208 can concurrently perform burst scan operations 414 on multiple channels on the ONFI bus when the processors 202 and 206 are in a sleep mode, such that the sleep interval or idle scan interval 416 between one burst scan operation and a subsequent burst scan operation is significantly increased, and the active idle power of the memory subsystem in a sleep mode is subsequently reduced.

[0042] Some operations performed by the backend processor 208 do not require any input or control signals from the ONFI bus interface or decoders or memory devices 140 (e.g., DRAM). For example, operations such as block selection and page selection do not require any input or control signals from the ONFI bus interface or decoders or memory devices 140. However, the modules performing scan operations and the error handling module require input from the ONFI bus interface or decoders. In addition, the error handling operations and logging operations require input from the memory devices 140 (e.g., DRAM). Thus, in some embodiments, the backend processor 208 can transition the memory devices 140 coupled to the memory subsystem controller 115 to a self-refresh mode when the input / output path connecting the memory controller 115 and the host system 120 is in a sleep mode. When in a self-refresh mode, the memory devices 140 are able to refresh themselves (e.g., via a read or sense operation) at periodic time intervals. Since the frequency of invoking block selection or page selection or the modules performing scan operations is extremely high, by placing the memory devices 140 in a self-refresh mode, the memory controller 115 is able to significantly reduce the active idle power.

[0043] Figure 5AExample operations in a method 500 for reducing active idle power in a memory device according to some embodiments are illustrated. The method 500 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 500 is performed by the sleep mode management component 113 of Figure 1 Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0044] At operation 510, processing logic of a processing device (e.g., I / O read processor 202) can increment a counter associated with the processing device when no read or write requests are received from a host system (e.g., host system 120) for a predetermined period of time. At operation 512, the processing logic of the processing device can send a sleep signal to a firmware sleep mode control that can transition the memory sub-system to a sleep mode when the counter reaches a predetermined threshold.

[0045] At operation 514, processing logic of another processing device (e.g., FTL processor 206) can increment a counter associated with the processing device when no read or write requests are received from the host system 120 for a predetermined period of time. At operation 516, the processing logic of the processing device can send a sleep signal to a firmware sleep mode control associated with the first processing device and transition to a sleep mode when the counter reaches a predetermined threshold. At operation 518, the first processing device can transition itself and an I / O path connecting the memory sub-system to the host system to a sleep mode when the processing logic of the first processing device determines that the second processing device is in a sleep mode, in turn reducing active idle power.

[0046] The method can also include decoupling a first processor (e.g., processor 202) from other processors, for example, at the firmware and / or control signal level, such that the decoupled processors can continue to perform required media scan operations, but the input / output interface between the first processing device and the memory sub-system controller and the host system can transition to a sleep mode to reduce active idle power. Subsequently, when a wake-up event occurs, such as receiving a read or write command from the host system, receiving a PCIe reset request from the host system, or receiving any other command from the host system, the processing logic of the first processing device can resume normal operation (e.g., drive activity) of the memory sub-system.

[0047] Figure 5B Example operations in a method 550 for reducing active idle power in a memory device according to some embodiments are illustrated. At operation 520, while the first processing device and the second processing device are in a sleep mode, processing logic of a third processing device (e.g., processor 208) can continue to perform media scan operations to maintain data integrity. For example, the media scan operations can include read operations, write operations, and or sense operations performed on a memory management unit (e.g., a page or a block or a superblock). Under normal operation, the processing logic of the third processing device can periodically perform media scan operations on each ONFI bus channel such that the scan operations are evenly distributed over a period of time. At operation 522, the processing logic of the third processing device determines a number of scan operations to perform on the memory device. The number of scan operations to perform can depend on the number of pages to scan, and this number can vary based on the number of pages in a block or the number of superpages in a superblock. At operation 524, the processing logic of the third processing device combines two or more media scan operations and performs a burst scan operation such that a sleep interval between one burst scan operation and a subsequent burst scan operation is increased. This not only reduces power between burst scan operations, but also reduces a burst scan interval between one burst scan cycle (e.g., across all memory blocks in the memory device) and a next burst scan cycle.

[0048] At operation 526, while the first processing device and the second processing device are in a sleep mode, processing logic of a memory subsystem controller can concurrently perform media scan operations on multiple channels on an ONFI bus connecting the memory subsystem controller and one or more memory devices. Thus, a scan interval between a first scan operation and a subsequent scan operation is increased, in turn maintaining the first processing device and the second processing device and the I / O path between the memory controller and the host system in a sleep mode for a longer period of time.

[0049] In some embodiments, the processing logic of the third processing device combines media scan operations 524 and 526, wherein when the first and second processing devices are in sleep mode, the processing logic of the third processing device can simultaneously perform burst scan operations on multiple channels on the ONFI bus, significantly increasing the sleep interval or idle scan interval between a burst scan operation and subsequent burst scan operations, and subsequently reducing the active idle power of the memory subsystem in sleep mode. At operation 528, when the input / output path connecting the memory controller and the host system is also in sleep mode, the processing logic of the third processing device can switch the volatile memory device coupled to the memory subsystem controller to a self-refresh mode. In self-refresh mode, the volatile memory device can refresh itself at periodic time intervals (e.g., via read or sense operations). Because the modules that invoke block select or page select or perform scan operations are called very frequently, the third processing device can significantly reduce active idle power by placing the volatile memory device in self-refresh mode.

[0050] In some embodiments, the controller receives I / O requests via a host interface, which consists of a system I / O bus and a protocol for communication along the bus. When an application running on the host system needs to access the memory subsystem, it generates an I / O request, which is sent via the host controller interface through the host system. The memory subsystem controller receives the I / O request and inserts it into a queue. The controller uses a scheduling policy to determine the order in which the requests in the queue are processed. The controller then sends the selected requests for scheduling to the FTL. The host controller interface (e.g., NVMe) determines how to send requests to the memory subsystem and how to queue requests for scheduling. NVMe exposes multiple memory subsystem I / O queues directly to the application running on the host system. By exposing the queues directly to the application, NVMe simplifies the software I / O stack, eliminating most OS involvement, which in turn reduces communication overhead. Memory subsystems using the NVMe interface maintain a separate set of queues for each application within the host interface. With more queues, the controller has a larger number of requests to choose from during scheduling, which improves its ability to utilize idle resources (i.e., channels, dies, planes) and makes it easier to manage and control the amount of interference the application experiences from other concurrently running applications.

[0051] Figure 6 An example machine is described as representing computer system 600, within which a set of instructions for causing the machine to perform any one or more of the methods discussed herein can be executed. In some embodiments, computer system 600 may correspond to a host system (e.g., Figure 1a host system 120) that includes, is coupled to, or utilizes the memory sub-system (e.g., Figure 1 a memory sub-system 110) or can be used to perform operations of the controller (e.g., execute an operating system to perform operations corresponding to Figure 1 a hibernate mode management component 113, a memory sub-system controller 115, or a local media controller 135). In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine can operate in the capacity of a server or a client machine in client-server network environments, as a peer machine in peer-to-peer (or distributed) network environments, or as a server or a client machine in a cloud computing infrastructure or environment.

[0052] The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0053] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0054] Processing device 602 represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processing device can be complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device 602 can also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. The processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. The computer system 600 can further include a network interface device 608 to communicate over the network 620.

[0055] Data storage system 618 can include a machine-readable storage medium 624 (also known as a computer-readable medium) on which is stored one or more sets of instructions 626 or software embodying any one or more of the methodologies or functions described herein. The instructions 626 can also reside, completely or at least partially, within the main memory 604 and / or within the processing device 602 during execution thereof by the computer system 600, the main memory 604 and the processing device 602 also constituting machine-readable storage media. The machine-readable storage medium 624, data storage system 618, and / or main memory 604 can correspond to memory subsystem 110 of FIG. 1. Figure 1

[0056] In one embodiment, the instructions 626 include instructions to implement functionality corresponding to the hibernate mode management component 113 of FIG. 1. While the machine-readable storage medium 624 is shown in an example embodiment to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media. Figure 1

[0057] Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. The algorithms described herein are generally

[0058] It is also important to note that the machine-readable storage medium 624 can correspond to a single physical memory device or multiple physical memory devices, such as a central processing unit (CPU) of the computer system 600, a chipset of the computer system 600, or any other memory device(s) of the computer system 600. Furthermore, the machine-readable storage medium 624 can correspond to a computer-readable storage medium of a communication device or a storage device that is external to the computer system 600.

[0059] ​​The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the intended purposes, or it can include a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0060] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as described in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure as described herein.

[0061] The present disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. The machine-readable medium can include any mechanism for storing information in a form accessible by a machine (e.g., computer), such as machine-readable (e.g., computer-readable) media, in some embodiments, machine-readable (e.g., computer-readable) media include machine- readable (e.g., computer-readable) storage media, such as read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory components, etc.

[0062] In the foregoing specification, embodiments of the disclosure have been described with reference to specific embodiments thereof. It will be evident that various modifications can be made to the application without departing from the broader spirit and scope of embodiments of the application as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A method comprising: incrementing, by a first processing device in a memory sub-system controller, a first counter when no read or write requests directed to one or more memory devices are received from a host system within a first predetermined time period; in response to determining that the first counter has reached a first predetermined threshold, transitioning the first processing device to a sleep mode; incrementing, by a second processing device in the memory sub-system controller, a second counter when no read or write requests directed to the one or more memory devices are received from the host system within a second predetermined time period; in response to determining that the second counter has reached a second predetermined threshold, transitioning the second processing device to the sleep mode; and in response to determining that the second processing device is in a sleep mode, transitioning, by the first processing device, an input / output path coupling the memory sub-system controller and the host system to the sleep mode.

2. The method of claim 1, further comprising: in response to detecting a wake-up event, transitioning, by the first processing device, the second processing device and the input / output path to an active mode.

3. The method of claim 2, wherein the wake-up event comprises one or more of: receiving a read or write command from the host system, or receiving a PCIe reset request from the host system.

4. The method of claim 1, further comprising: while the first processing device and the second processing device are in the sleep mode, performing, by a third processing device of the memory sub-system controller, a media scan operation on the one or more memory devices coupled to the memory sub-system controller.

5. The method of claim 4, wherein the first processing device comprises an input / output read processor, the second processing device comprises a flash translation layer processor, and the third processing device comprises a back-end processor.

6. The method of claim 4, wherein the media scan operation comprises one or more of a read operation, a write operation, or a sense operation.

7. The method of claim 4, wherein performing the media scan operation on one or more memory devices further comprises: determining, by the third processing device, a number of media scan operations to perform within a predetermined time period, wherein the number of media scan operations is based on a number of pages to be scanned in the one or more memory devices; and combining the media scan operations to be performed within the predetermined time period and performing a burst scan operation comprising two or more of the media scan operations, thereby increasing a time period between the burst scan operation and a subsequent burst scan operation.

8. The method of claim 4, wherein performing the media scan operation on one or more memory devices further comprises: determining, by the third processing device, a number of media scan operations to perform within a predetermined time period, wherein the number of media scan operations is based on a number of pages to be scanned in the one or more memory devices; and performing the media scan operations concurrently on a plurality of channels coupling the one or more memory devices to the memory sub-system controller.

9. The method of claim 4, further comprising: in response to determining that the input / output path is in a hibernate mode, transitioning, by the third processing device, a volatile memory device coupled to the memory sub-system controller to a self-refresh mode.

10. A system comprising: a memory device; and a processing device, operatively coupled with the memory device, for performing operations comprising: incrementing a first counter when no read or write requests directed to the memory device are received from a host system within a first predetermined time period; in response to determining that the first counter has reached a first predetermined threshold, transitioning a first processing unit in a memory sub-system controller to a hibernate mode; incrementing a second counter when no read or write requests directed to the memory device are received from the host system within a second predetermined time period; in response to determining that the second counter has reached a second predetermined threshold, transitioning a second processing unit in the memory sub-system controller to the hibernate mode; and in response to determining that the first processing unit and the second processing unit are in a hibernate mode, transitioning an input / output path coupling the memory sub-system controller and the host system to the hibernate mode.

11. The system of claim 10, wherein the operations further comprise: in response to detecting a wake-up event, transitioning the first processing unit, the second processing unit, and the input / output path to an active mode.

12. The system of claim 11, wherein the wake-up event comprises one or more of: receiving a read or write command from the host system, or receiving a PCIe reset request from the host system.

13. The system of claim 10, wherein the operations further comprise: performing media scan operations on one or more memory devices coupled to the memory sub-system controller while the first processing unit and the second processing unit are in the hibernate mode.

14. The system of claim 13, wherein the first processing unit comprises an input / output read processor and the second processing unit comprises a flash translation layer processor.

15. The system of claim 13, wherein performing the media scan operations on one or more memory devices further comprises: determining a number of media scan operations to perform within a predetermined time period, wherein the number of media scan operations is based on a number of pages to be scanned in the one or more memory devices; and combining the media scan operations to be performed within the predetermined time period and performing a burst scan operation comprising two or more of the media scan operations, thereby increasing a time period between the burst scan operation and a subsequent burst scan operation.

16. The system of claim 13, performing the media scan operations on one or more memory devices further comprises: determining a number of media scan operations to be performed within a predetermined time period, wherein the number of media scan operations is based on a number of pages to be scanned in the one or more memory devices; and performing the media scan operations concurrently on a plurality of channels coupling the one or more memory devices to the memory sub-system controller.

17. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: incrementing a first counter when no read or write request directed to one or more memory devices is received from a host system within a first predetermined time period; in response to determining that the first counter has reached a first predetermined threshold, transitioning a first processing unit in a memory sub-system controller to a sleep mode; incrementing a second counter when no read or write request directed to the one or more memory devices is received from the host system within a second predetermined time period; in response to determining that the second counter has reached a second predetermined threshold, transitioning a second processing unit in the memory sub-system controller to the sleep mode; and in response to determining that the first processing unit and the second processing unit are in a sleep mode, transitioning an input / output path coupling the memory sub-system controller and the host system to the sleep mode.

18. The non-transitory computer-readable storage medium of claim 17, wherein the operations further comprise: performing media scan operations on one or more memory devices coupled to the memory sub-system controller while the first processing unit and the second processing unit are in the sleep mode.

19. The non-transitory computer-readable storage medium of claim 18, wherein performing the media scan operations on one or more memory devices further comprises: determining a number of media scan operations to be performed within a predetermined time period, wherein the number of media scan operations is based on a number of pages to be scanned in the one or more memory devices; and combining the media scan operations to be performed within the predetermined time period and performing a burst scan operation comprising two or more of the media scan operations, thereby increasing a time period between the burst scan operation and a subsequent burst scan operation.

20. The non-transitory computer-readable storage medium of claim 18, wherein performing the media scan operations on one or more memory devices further comprises: determining a number of media scan operations to be performed within a predetermined time period, wherein the number of media scan operations is based on a number of pages to be scanned in the one or more memory devices; and performing the media scan operations concurrently on a plurality of channels coupling the one or more memory devices to the memory sub-system controller.

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