Load matching for current steering digital-to-analog converters

Abstract

Certain aspects of the present disclosure relate to a digital-to-analog converter (DAC) system. The DAC system generally includes a first driver and a plurality of current steering units. A first current steering unit of the plurality of current steering units includes a first current source coupled to a first current steering transistor and a second current steering transistor, wherein the grid electrode of the first current guiding transistor and the grid electrode of the second current guiding transistor are respectively coupled to the first output end and the second output end of the first driver; a first transistor having a source coupled to the current source path and a drain coupled to a reference potential node; and a second transistor having a source coupled to the current source path and a drain coupled to the reference potential node.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims the benefit of and priority to U.S. Patent Application No. 18 / 189,350, filed March 24, 2023, which is hereby incorporated by reference in its entirety. TECHNICAL FIELD

[0003] Certain aspects of the present disclosure generally relate to electronic components, and more particularly to circuits for digital-to-analog conversion.

[0004] BACKGROUND

[0005] Electronic devices include computing devices such as desktop computers, notebook computers, tablet computers, smartphones, wearable devices like smartwatches, internet servers, and the like. These various electronic devices provide information, entertainment, social interaction, security, safety, productivity, transportation, manufacturing, and other services to human users. Many of the functions of these various electronic devices rely on wireless communication. Wireless communication systems and devices are widely deployed to provide various types of communication content such as voice, video, packet data, messaging, broadcast, and the like. These systems can be able to support communication with multiple users by sharing the available system resources (e.g., time, frequency, and power). Examples of such systems include Code Division Multiple Access (CDMA) systems, Time Division Multiple Access (TDMA) systems, Frequency Division Multiple Access (FDMA) systems, and Orthogonal Frequency Division Multiple Access (OFDMA) systems (e.g., a Long Term Evolution (LTE) system, or a New Radio (NR) system). Wireless devices can include a transmitter for processing signals to be transmitted via an antenna. The transmitter can include one or more digital-to-analog converters (DACs) configured to convert signals from a digital domain to an analog domain for further processing (e.g., amplification) prior to transmission. SUMMARY

[0006] The systems, methods, and devices of the present disclosure each have several aspects, no single one of which is solely responsible for its desirable attributes. Without limiting the scope of this disclosure as expressed by the claims which follow, some features will now be discussed briefly. In consideration of this discussion, one will understand how features of the present disclosure provide advantages such as those described herein.

[0007] Certain aspects of the present disclosure relate to a digital-to-analog converter (DAC) system. The DAC system generally includes a first driver and a plurality of current steering cells. A first current steering cell of the plurality of current steering cells includes: a first current source coupled to a first current steering transistor and a second current steering transistor, wherein a gate of the first current steering transistor and a gate of the second current steering transistor are coupled to a first output and a second output, respectively, of the first driver; a first transistor having a source coupled to a current source path, a drain coupled to a reference potential node, and a gate coupled to the first output of the first driver; and a second transistor having a source coupled to the current source path, a drain coupled to the reference potential node, and a gate coupled to the second output of the first driver.

[0008] Certain aspects of the present disclosure relate to a method for digital-to-analog conversion. The method generally includes: receiving, at a first driver of a DAC, a first digital input via an input path of the DAC; and generating, by controlling, based on the first digital input, a first current steering transistor and a second current steering transistor of a first current steering cell of a plurality of current steering cells via the first driver, an analog output signal based on the first digital input, the first current steering cell having a first current source coupled to the first current steering transistor and the second current steering transistor. The first current steering cell further includes: a first transistor having a source coupled to a current source path, a drain coupled to a reference potential node, and a gate coupled to the first driver; and a second transistor having a source coupled to the current source path, a drain coupled to the reference potential node, and a gate coupled to the first driver.

[0009] Certain aspects of the present disclosure relate to an apparatus for digital-to-analog conversion. The apparatus generally includes: means for receiving a first digital input; and a first current steering cell of a plurality of current steering cells coupled to the means for receiving, wherein the means for receiving includes means for controlling, based on the first digital input, a first current steering transistor and a second current steering transistor of the first current steering cell, the first current steering cell having a first current source coupled to the first current steering transistor and the second current steering transistor. The first current steering cell further includes: a first transistor having a source coupled to a current source path, a drain coupled to a reference potential node, and a gate coupled to the means for controlling; and a second transistor having a source coupled to the current source path, a drain coupled to the reference potential node, and a gate coupled to the means for controlling.

[0010] To the accomplishment of the foregoing and related ends, one or more aspects comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more aspects. These aspects are indicative, however, of but a few of the various ways in which principles of various aspects can be employed. Other aspects, advantages, and novel features of the disclosure will be described below to facilitate a complete understanding of various aspects of the disclosure and the BRIEF DESCRIPTION OF DRAWINGS

[0011] In order that the aforementioned and other features and advantages of the present disclosure can be understood in detail, a more particular description will be rendered by reference to the following commentary, which is intended to be illustrative only, and should not be taken in a limiting sense. For purposes of clarity, identical reference numbers have been used in the drawings to denote similar elements.

[0012] FIG. 1 is a diagram of an example wireless communication network in which aspects of the present disclosure can be practiced.

[0013] FIG. 2 is a block diagram of an example access point (AP) and an example user terminal that can be used within the present disclosure.

[0014] FIG. 3 is a block diagram of an example transceiver front-end that can be used within the present disclosure.

[0015] FIG. 4 An example digital-to-analog converter (DAC) in accordance with certain aspects of the present disclosure is shown.

[0016] FIG. 5 and FIG. 6 An example current steering cell in accordance with certain aspects of the present disclosure is illustrated.

[0017] FIG. 7 is a flow diagram depicting an example operation for digital-to-analog conversion in accordance with certain aspects of the present disclosure.

[0018] To facilitate an understanding of this description, like reference characters are used to identify like elements in the figures. It should be noted that elements disclosed in one aspect can be beneficially utilized on other aspects without specific recitation. DETAILED DESCRIPTION

[0019] Certain aspects of the present disclosure generally relate to techniques and apparatus for digital-to-analog conversion. For example, certain aspects provide a digital-to-analog converter (DAC) that includes a current steering cell implemented with an architecture that reduces timing-skew error across DAC segmentation boundaries. Timing-skew error degrades noise floor and out-of-band DAC emissions. As described in greater detail herein, timing-skew error can be reduced by connecting a dummy transistor to a switch driver output.

[0020] Example Wireless Communications

[0021] FIG. 1 A wireless communication system 100 with access point 110 and user terminal 120 is illustrated, in which various aspects of this disclosure can be practiced. For simplicity, FIG. 1 Only one access point 110 is shown. An access point (AP) is typically a fixed station that communicates with a user terminal and may also be referred to as a base station (BS), evolved Node B (eNB), next-generation Node B (gNB), or some other term. A user terminal (UT) can be fixed or mobile and may also be referred to as a mobile station (MS), access terminal, user equipment (UE), station (STA), client, wireless device, or some other term. A user terminal can be a wireless device such as a cellular phone, personal digital assistant (PDA), handheld device, wireless modem, laptop computer, tablet computer, personal computer, etc.

[0022] Access point 110 can communicate with one or more user terminals 120 at any given time, on both the downlink and uplink. The downlink (i.e., the forward link) is the communication link from the access point to the user terminal, while the uplink (i.e., the reverse link) is the communication link from the user terminal to the access point. User terminals can also communicate peer-to-peer with other user terminals. System controller 130 can be coupled to the access point and provides coordination and control for the access point.

[0023] The wireless communication system 100 uses multiple transmit antennas and multiple receive antennas to transmit data on the downlink and uplink. The access point 110 may be equipped with multiple (N) ap (N) antennas are used to achieve transmit diversity for downlink transmissions and / or receive diversity for uplink transmissions. A group (N) u The selected user terminals 120 can receive downlink transmissions and transmit uplink transmissions. Each selected user terminal transmits user-specific data to and / or receives user-specific data from the access point. Typically, each selected user terminal may be equipped with one or more antennas (i.e., N). ut 1). N u Each selected user terminal may have the same number of antennas or a different number of antennas.

[0024] The wireless communication system 100 can be a time-division duplex (TDD) system or a frequency-division duplex (FDD) system. In a TDD system, the downlink and uplink share the same frequency band. In an FDD system, the downlink and uplink use different frequency bands. The wireless communication system 100 can also use a single carrier or multiple carriers for transmission. Each user terminal 120 can be equipped with a single antenna (e.g., to reduce cost) or multiple antennas (e.g., where additional cost can be supported). In some aspects, the user terminal 120 or access point 110 may include a digital-to-analog converter (DAC) with a current-guiding unit implemented using an architecture for reducing timing skew errors, as described in more detail herein.

[0025] FIG. 2 A block diagram of an access point 110 and two user terminals 120m and 120x in a wireless communication system 100 is shown. Access point 110 is equipped with N... ap Each antenna is 224a to 224ap. The user terminal 120m is equipped with N... ut,m Each antenna is 252 mA to 252 mA, while the user terminal 120x is equipped with N ut,x Each antenna ranges from 252xa to 252xu. Access point 110 is a transmitting entity for the downlink and a receiving entity for the uplink. Each user terminal 120 is a transmitting entity for the uplink and a receiving entity for the downlink. As used herein, a “transmitting entity” is an independently operating device or apparatus capable of transmitting data via a frequency channel, and a “receiving entity” is an independently operating device or apparatus capable of receiving data via a frequency channel. In the following description, the subscript “dn” denotes the downlink, the subscript “up” denotes the uplink, and N... up N user terminals are selected for simultaneous transmission on the uplink. dn N user terminals are selected for simultaneous transmission on the downlink. up It may or may not be equal to N dn And N up and N dn It can be a static value or it can be changed for each scheduling interval. Beam control, beamforming, or some other spatial processing technique can be used at the access point and user terminal.

[0026] On the uplink, at each user terminal 120 selected for uplink transmission, the transmitter (TX) data processor 288 receives service data from the data source 286 and control data from the controller 280. The TX data processor 288 processes the service data {d} for that user terminal based on a decoding and modulation scheme associated with the selected rate for that user terminal. up} to perform processing (e.g., encoding, interleaving, and modulation), and for Nut,m One of the N antennas provides a data symbol stream {s up}. A transceiver front-end (TX / RX) 254 (also referred to as a radio frequency front-end (RFFE)) receives and processes (e.g., converts to analog, amplifies, filters, and upconverts) the respective symbol streams to generate uplink signals. The transceiver front-end 254 can also route the uplink signals to one of the N ut,m antennas for transmit diversity via, for example, a radio frequency (RF) switch. A controller 280 can control the routing within the transceiver front-end 254. A memory 282 can store data and program codes for the user terminal 120 and can interface with the controller 280.

[0027] Multiple (N up ) user terminals 120 can be scheduled to transmit simultaneously on the uplink. Each of these user terminals transmits its set of processed symbol streams on the uplink to the access point.

[0028] At the access point 110, N ap antennas 224a through 224ap receive the uplink signals from all N up user terminals on the uplink. For receive diversity, the transceiver front-end 222 can select signals received from one of the antennas 224 for processing. Signals received from multiple antennas 224 can be combined to enhance receive diversity. The transceiver front-end 222 of the access point also performs processing complementary to that performed by the transceiver front-end 254 of the user terminals and provides recovered uplink data symbol streams. The recovered uplink data symbol streams are estimates of the data symbol streams {s up} transmitted by the user terminals. A receiver (RX) data processor 242 processes the recovered uplink data symbol streams (e.g., demodulates, deinterleaves, and decodes) in accordance with the rates used to recover the uplink data symbol streams to obtain decoded data. The decoded data for each user terminal can be provided to a data sink (e.g., data sink 272m or data sink 272x, and corresponding data sink 244 of the access point 110) for storage and / or to the controller 230 for further processing.

[0029] On the downlink, at the access point 110, a TX data processor 210 receives traffic data from a data source 208 for N dnservice data for one or more user terminals, control data from the controller 230, and possibly other data from the scheduler 234. The various types of data can be transmitted on different transport channels. The TX data processor 210 processes (e.g., encodes, interleaves, and modulates) the service data for each user terminal based on the rate selected for that user terminal. The TX data processor 210 can provide a downlink data symbol stream for one or more of the N dn user terminals to be transmitted from one of the N ap antennas. The transceiver front end 222 receives the symbol stream and processes (e.g., converts to analog, amplifies, filters, and frequency upconverts) the symbol stream to generate a downlink signal. The transceiver front end 222 can also route the downlink signal to one or more of the N ap antennas 224 via an RF switch for transmit diversity, for example. The controller 230 can control the routing within the transceiver front end 222. The memory 232 can store data and program codes for the access point 110 and can interface with the controller 230.

[0030] At each user terminal 120, the N ut,m antennas 252 receive the downlink signal from the access point 110. For receive diversity at the user terminal 120, the transceiver front end 254 can select signals received from one or more of the antennas 252 for processing. Signals received from multiple antennas 252 can be combined to enhance receive diversity. The transceiver front end 254 of the user terminal also performs processing complementary to that performed by the transceiver front end 222 of the access point and provides a recovered downlink data symbol stream. The RX data processor 270 processes (e.g., demodulates, deinterleaves, and decodes) the recovered downlink data symbol stream to obtain decoded data for the user terminal. In some aspects, the transceiver front end 254 or 222 can include a DAC with a current steering cell implemented with an architecture for reducing timing skew error, as described in greater detail herein.

[0031] FIG. 3 is a block diagram of an example transceiver front end 300, such as the transceiver front end 222, 254 in FIG. 2 aspects of the disclosure can be practiced. The transceiver front end 300 includes a transmit (TX) path 302 (also referred to as a “transmit chain”) for transmitting signals via one or more antennas and a receive (RX) path 304 (also referred to as a “receive chain”) for receiving signals via an antenna. When the TX path 302 and the RX path 304 share an antenna 303, the paths can interface with the antenna via an interface 306, which can include any of various suitable radio frequency (RF) devices, such as switches, duplexers, diplexers, multiplexers, etc.

[0032] The TX path 302 can include a baseband filter (BBF) 310, a mixer 312, a driver amplifier (DA) 314, and a power amplifier (PA) 316, which receive in-phase (I) or quadrature (Q) baseband analog signals from a digital-to-analog converter (DAC) 308. The BBF 310, the mixer 312, and the DA 314 can be included in a radio frequency integrated circuit (RFIC). In some cases, the PA 316 can be external to the RFIC.

[0033] The BBF 310 filters the baseband signal received from the DAC 308, and the mixer 312 mixes the filtered baseband signal with a transmit local oscillator (LO) signal to convert the baseband signal of interest to a different frequency (e.g., upconvert from baseband to RF). This frequency conversion process produces sum and difference frequencies of the LO frequency and the frequency of the signal of interest. The sum and difference frequencies are referred to as “beats.” The beats are typically in the RF range, such that the signal output by the mixer 312 is typically an RF signal, which can be amplified by the DA 314 and / or by the PA 316 before being transmitted by the antenna 303. Although one mixer 312 is illustrated, several mixers can be used to upconvert the filtered baseband signal to one or more intermediate frequencies and thereafter upconvert the intermediate frequency (IF) signal to the frequency used for transmission. In some aspects, the DAC 308 can include a current steering cell implemented with an architecture for reducing timing-skew error, as described in greater detail herein.

[0034] The RX path 304 includes a low noise amplifier (LNA) 322, a mixer 324, and a baseband filter (BBF) 326. The LNA 322, the mixer 324, and the BBF 326 can be included in a radio frequency integrated circuit (RFIC), which can or can not be the same RFIC that includes the TX path components. An RF signal received via the antenna 303 can be amplified by the LNA 322, and the mixer 324 mixes the amplified RF signal with a receive local oscillator (LO) signal to convert the RF signal of interest to a different baseband frequency (i.e., downconvert). The baseband signal output by the mixer 324 can be filtered by the BBF 326 before being converted to a digital I or Q signal by an analog-to-digital converter (ADC) 328 for digital signal processing.

[0035] While it is desirable for the output of the LO to remain stable in frequency, tuning the LO to different frequencies often requires the use of a frequency variable oscillator, which can involve a tradeoff between stability and tunability. Contemporary systems can employ a frequency synthesizer with a voltage controlled oscillator (VCO) to generate a stable, tunable LO with a particular tuning range. Thus, a transmit LO frequency can be generated by a TX frequency synthesizer 318, which can be buffered or amplified by an amplifier 320 before being mixed with a baseband signal in a mixer 312. Similarly, a receive LO frequency can be generated by a RX frequency synthesizer 330, which can be buffered or amplified by an amplifier 332 before being mixed with an RF signal in a mixer 324.

[0036] While FIGS. 1-3 Wireless communication is described as an example application in which certain aspects of the present disclosure can be implemented to facilitate understanding, certain aspects described herein can be used in digital-to-analog conversion in any of a variety of other suitable applications (e.g., high-speed serializer / deserializer (SerDes) systems).

[0037] Digital-to-analog conversion using current steering

[0038] Current steering digital-to-analog converters (DACs) are the preferred architecture for high performance digital-to-analog conversion in many wireless transmitters. Current steering DACs provide versatility in design, allow for high speed operation, and provide high performance. In some cases, a segmented DAC can have different current steering segments for processing the most significant bits (MSBs) and the least significant bits (LSBs) of a digital input code. Some segmented DACs can suffer from timing errors across the segment boundaries, resulting in short pulses in a drive signal that provides wide bandwidth signal content, causing increased noise floor and large out-of-band emissions. Certain aspects provide a DAC architecture that reduces timing mismatch across DAC segment boundaries.

[0039] FIG. 4 An example current steering DAC 400 according to certain aspects of the present disclosure is illustrated (e.g., corresponding to FIG. 3 DAC 308). Depending on a digital input code, each bit of the DAC 400 associated with a current steering cell can cause a positive current or a negative current to be provided to a respective output in accordance with a logic level of a respective bit of the digital input code. A “positive current” from a current steering cell generally refers to a current provided to a positive output node (e.g., positive output node 426), and a “negative current” from a current steering cell generally refers to a current provided to a negative output node (e.g., negative output node 428). Each of the current steering cells can include a switch (referred to herein as a current steering switch or transistor) to selectively provide a positive current or a negative current to the respective output node.

[0040] As shown, the DAC 400 includes a plurality of current steering cells, including MSB current steering cells 402 for processing the most significant bits (MSBs) of a digital input code of the DAC system, and LSB current steering cells 404 for processing the least significant bits (LSBs) of the digital input code. In some aspects, the DAC 400 can also include mid (MID) current steering cells (e.g., for bits having significance between the MSBs and the LSBs). The LSB current steering cells 404 can be coupled to a resistor ladder circuit 440. The resistor ladder circuit 440 provides different weights associated with the LSB bits processed via the LSB current steering cells 404. As shown, drivers 408 can drive the current steering transistors of the MSB current steering cells 402, drivers 410 can drive the current steering transistors of the current steering cells 406, and drivers 412 can drive the current steering transistors of the current steering cells 404.

[0041] As shown, each of the MSB current steering cells 402 includes two current sources (e.g., p-channel metal oxide semiconductor (PMOS) transistors 414, 416) coupled to at least two positive current steering transistors (e.g., PMOS transistors 418, 420 providing positive current to a positive output node 426) and at least two negative current steering transistors (e.g., PMOS transistors 422, 424 providing negative current to a negative output node 428). The sources of the PMOS transistors 418, 420, 422, 424 can be coupled together and to the drains of the PMOS transistors 414, 416. The PMOS transistors 418, 420, 422, 424 can be referred to herein as current steering transistors. As shown, the drains of the PMOS transistors 418, 420 are coupled to the positive output node 426, and the drains of the PMOS transistors 422, 424 are coupled to the negative output node 428.

[0042] Each of the LSB current steering cells 404 and the MID current steering cell 406 can include fewer positive current steering transistors and fewer negative current steering transistors as compared to each of the MSB current steering cells 402. For example, the MID current steering cell 406 can include a single positive current steering transistor (e.g., PMOS transistor 430) and a single negative current steering transistor (e.g., PMOS transistor 432) as opposed to the MSB current steering cells 402 each including two positive current steering transistors and two negative current steering transistors. The sources of the PMOS transistors 430, 432 can be coupled to the drain of a PMOS transistor 434 for implementing a current source for the current steering cell 406. Each of the LSB current steering cells 404 can be implemented similarly to the MID current steering cell 406. For example, the LSB current steering cell 450 can include a positive current steering transistor (e.g., PMOS transistor 460) and a negative current steering transistor (e.g., PMOS transistor 462). The sources of the PMOS transistors 460, 462 can be coupled to the drain of a PMOS transistor 464 for implementing a current source for the current steering cell 450.

[0043] As each of the MID and LSB current steering cells includes fewer positive current steering transistors and negative current steering transistors, the capacitive load of each of the drivers 408 can not match the capacitive load of each of the drivers 410 or 412, causing a timing mismatch when driving different current steering cells. This timing mismatch causes a timing skew error across the DAC segmentation boundary (e.g., a timing mismatch associated with the digital outputs for driving the current steering cell 402 and the current steering cell 406).

[0044] In some implementations, the switch drivers can be redesigned to have different output drive capabilities to match the timing of the driver outputs. However, this technique is difficult to track process, voltage, and temperature (PVT) variations and causes harmonic distortion and increased noise floor. In some aspects of the disclosure, a non-conducting dummy transistor coupled to the driver output can be used to match the capacitive load of the driver as described in more detail herein.

[0045] FIG. 5An example current steering cell 500 is illustrated in accordance with certain aspects of the present disclosure. The current steering cell 500 can correspond to the current steering cell 406, or any one of the current steering cells 404, such as the current steering cell 450. As shown, the current steering cell 500 includes a PMOS transistor 506 (e.g., corresponding to the PMOS transistor 430 of the current steering cell 406 or the PMOS transistor 460 of the current steering cell 450) and a PMOS transistor 508 (e.g., corresponding to the PMOS transistor 432 of the current steering cell 406 or the PMOS transistor 462 of the current steering cell 450).

[0046] The current steering cell 500 can also include a PMOS transistor 514 that can operate in a saturation regime. A cascaded current 516 (icas) can be provided to a node 520 coupled to the sources of the transistors 506, 508 through the PMOS transistor 514 (e.g., from the source to the drain of the PMOS transistor 514). The icas can be provided via a current source (e.g., the PMOS transistor 434 of the current steering cell 406 or the PMOS transistor 464 of the current steering cell 450). As shown, a driver 502 (e.g., corresponding to one of the drivers 412 or the drivers 410) can be used to drive the gates of the PMOS transistors 506, 508. For example, a digital output (q) can be used to drive the gate of the PMOS transistor 506, and a complementary digital output (qb) can be used to drive the gate of the PMOS transistor 508.

[0047] In some aspects, to match the load of the driver 502 to the load of each of the drivers 408, the driver 502 can also drive the gates of a PMOS transistor 504 and a PMOS transistor 510. The drains of the PMOS transistors 504, 510 are coupled to a reference potential node (e.g., electrical ground or vss, or any potential node that configures the transistors 504, 510 in a saturation regime). The sources of the PMOS transistors 504, 510 are coupled to the drain of a PMOS transistor 512. When the digital output (q) of the driver 502 is logic low, the PMOS transistor 504 is effectively configured as a diode-connected transistor (e.g., due to the gate and drain of the PMOS transistor 504 being at the same voltage potential), and when the complementary digital output (qb) of the driver 502 is logic low, the PMOS transistor 510 is effectively configured as a diode-connected transistor (e.g., due to the gate and drain of the PMOS transistor 510 being at the same voltage potential).

[0048] As shown, a cascaded voltage (vcas) biases the gates of PMOS transistors 512, 514. PMOS transistors 512, 514 can operate in saturation. A source current 518 (isource) can be provided to a node 522 coupled to the sources of PMOS transistors 504, 510. Source current 518 can also be referred to as a bleeder current. As such, current steering cell 500 can be referred to as a current bleeder-based steering cell. Source current 518 (e.g., from the source to the drain of transistor 512) can be provided through transistor 512. Source current 518 can be provided via a current source 540. PMOS transistor 512 reduces the effect of line capacitance on the source side of PMOS transistor 512 on the capacitance on the drain side of PMOS transistor 512.

[0049] As shown, current source 540 can also provide source current to one or more other current steering cells. The input impedance seen into the gates of transistors 504, 510 can be fairly constant over a wide range of bias currents (e.g., when transistors 504, 510 are in saturation). Current steering cells can be insensitive to small variations in bias current across the steering cell, allowing a single current source 540 to be used to provide bias current for multiple current steering cells, as described.

[0050] With PMOS transistors 504, 510, a relatively small amount of increase in static power consumption of DAC 400 can be utilized to reduce load mismatch across the driver. Further, the techniques described herein for reducing load mismatch provide improved noise floor as compared to conventional implementations.

[0051] FIG. 6An example current steering cell 600 is illustrated in accordance with certain aspects of the present disclosure. The current steering cell 600 can correspond to any one of the MSB current steering cells 402. As shown, a cascaded current 616 (icasl) and a cascaded current 618 (icas2) are provided via respective current sources (e.g., PMOS transistor 414 and PMOS transistor 416). The current steering cell 600 can include PMOS transistor 612 and PMOS transistor 614. The cascaded current 616 can be received at the source of PMOS transistor 614, and the cascaded current 618 can be received at the source of PMOS transistor 612. The drains of PMOS transistor 612 and PMOS transistor 614 can be coupled together and to the sources of PMOS transistors 418, 420, 422, 424. As shown, PMOS transistors 612, 614 can be biased in saturation using a cascaded voltage (vcas). The gates of PMOS transistors 418, 420, 422, 424 can be driven using driver 602. Driver 602 can correspond to one of drivers 408.

[0052] FIG. 7 is a flow diagram depicting example operations 700 for digital-to-analog conversion in accordance with certain aspects of the present disclosure. The operations 700 can be performed, for example, by a DAC such as DAC 400.

[0053] The operations 700 begin, at block 702, where the DAC receives, via an input path of the DAC, a first digital input at a first driver of the DAC (e.g., driver 502 corresponding to driver 410 or driver 412). At block 704, the DAC generates, by controlling, based on the first digital input, a first current steering transistor (e.g., PMOS transistor 504) and a second current steering transistor (e.g., PMOS transistor 508) of a first current steering cell (e.g., current steering cell 500 corresponding to current steering cell 406 or current steering cell 450) of a plurality of current steering cells via the first driver based on the first digital input, an analog output signal based on the first digital input. The first current steering cell can have a first current source (e.g., PMOS transistor 434 or PMOS transistor 464) coupled to the first current steering transistor and the second current steering transistor.

[0054] In some aspects of the disclosure, the first current steering cell can further include a first transistor (e.g., PMOS transistor 504) having a source coupled to a current source path (e.g., a path providing source current 518), a drain coupled to a reference potential node (e.g., vss), and a gate coupled to the first driver. The first current steering cell can further include a second transistor (e.g., transistor 510) having a source coupled to the current source path, a drain coupled to the reference potential node, and a gate coupled to the first driver.

[0055] In some aspects, the DAC further receives, via a third transistor (e.g., transistor 512) of the current source path, a first current (e.g., source current 518) at a source of the third transistor, a drain of the third transistor being coupled to sources of the first and second transistors. The DAC can provide a second current via a second current source (e.g., current source 540). The first current can include a first portion of the second current, a second portion of the second current being provided to a second current steering cell of the plurality of current steering cells. In some aspects, the first current steering cell can further include a fourth transistor (e.g., transistor 514) coupled between the first current source and a current steering node (e.g., node 520), the current steering node being coupled to sources of the first and second current steering transistors. A gate of the fourth transistor can be coupled to a gate of the third transistor.

[0056] In some aspects, the DAC can further provide, via a first current steering transistor, a first output current to a first output terminal (e.g., positive output node 426) of the DAC, a drain of the first current steering transistor being coupled to the first output terminal of the DAC. The DAC can provide, via a second current steering transistor, a second output current to a second output terminal (e.g., negative output node 428) of the DAC, a drain of the second current steering transistor being coupled to the second output terminal of the DAC.

[0057] In some aspects, the DAC can receive, at a second driver (e.g., driver 408) of the DAC, a second digital input via an input path of the DAC. The DAC can generate an analog output signal based on the second digital input by controlling, based on the second digital input, a third current steering transistor (e.g., PMOS transistor 420) and a fourth current steering transistor (e.g., PMOS transistor 422) of a second current steering cell (e.g., current steering cell 402) of the plurality of current steering cells via the second driver. The second current steering cell can include a second current source (e.g., PMOS transistor 414 or PMOS transistor 416) coupled to the third current steering transistor and the fourth current steering transistor. In some aspects, the second current steering cell can include a fifth current steering transistor (e.g., PMOS transistor 418) having a source coupled to the second current source and a sixth current steering transistor (e.g., PMOS transistor 424) having a source coupled to the second current source. Gates of the fifth current steering transistor and the sixth current steering transistor can be coupled to a first output and a second output, respectively, of the second driver. In some aspects, the first digital input (e.g., LSB or one of the bits processed by current steering cell 406) has a lower significance than the second digital input (e.g., MSB). A first load impedance of the first driver can be configured to match a second load impedance of the second driver. The first load impedance can be associated with the first current steering cell and the second load impedance is associated with the second current steering cell.

[0058] In some aspects, drains of the first current steering transistor and the second current steering transistor can be coupled to a resistive ladder circuit (e.g., resistive ladder circuit 440). The first current steering transistor, the second current steering transistor, the first transistor, and the second transistor can include PMOS transistors.

[0059] Example Aspects

[0060] In addition to the various aspects described above, specific combinations of aspects are within the scope of the present disclosure, details of some of which are as follows:

[0061] Aspect 1. A digital-to-analog converter (DAC) system comprising: a first driver; and a plurality of current steering cells, a first current steering cell of the plurality of current steering cells comprising: a first current source coupled to a first current steering transistor and a second current steering transistor, wherein gates of the first current steering transistor and the second current steering transistor are coupled to first and second output terminals of the first driver, respectively; a first transistor having a source coupled to a current source path, a drain coupled to a reference potential node, and a gate coupled to the first output terminal of the first driver; and a second transistor having a source coupled to the current source path, a drain coupled to the reference potential node, and a gate coupled to the second output terminal of the first driver.

[0062] Aspect 2. The DAC system of aspect 1, wherein the current source path comprises a third transistor configured to receive a first current at a source of the third transistor, a drain of the third transistor coupled to the sources of the first and second transistors.

[0063] Aspect 3. The DAC system of aspect 2, further comprising a second current source configured to provide a second current, wherein the first current comprises a first portion of the second current, a second portion of the second current provided to a second current steering cell of the plurality of current steering cells.

[0064] Aspect 4. The DAC system of any one of aspects 2-3, wherein the first current steering cell further comprises a fourth transistor coupled between the first current source and a current steering node, the current steering node coupled to sources of the first and second current steering transistors.

[0065] Aspect 5. The DAC system of aspect 4, wherein a gate of the fourth transistor is coupled to a gate of the third transistor.

[0066] Aspect 6. The DAC system of any one of aspects 1-5, wherein: a drain of the first current steering transistor is coupled to a first output terminal of the DAC system; and a drain of the second current steering transistor is coupled to a second output terminal of the DAC system.

[0067] Aspect 7. The DAC system of any one of aspects 1-6, wherein a second current steering cell of the plurality of current steering cells comprises: a second current source; a third current steering transistor having a source coupled to the second current source; and a fourth current steering transistor having a source coupled to the second current source, wherein gates of the third and fourth current steering transistors are coupled to first and second output terminals, respectively, of a second driver.

[0068] Aspect 8. The DAC system of aspect 7, wherein the second current steering cell further comprises: a fifth current steering transistor having a source coupled to the second current source; and a sixth current steering transistor having a source coupled to the second current source, wherein gates of the fifth and sixth current steering transistors are coupled to the first and second output terminals, respectively, of the second driver.

[0069] Aspect 9. The DAC system of any one of aspects 7-8, wherein: the first current steering cell is configured to process a first bit of a digital input code of the DAC system; and the second current steering cell is configured to process a second bit of the digital input code of the DAC system, the first bit having a lower significance than the second bit.

[0070] Aspect 10. The DAC system of any one of aspects 7-9, wherein: a first load impedance of the first driver is configured to match a second load impedance of the second driver; the first load impedance is associated with the first current steering cell; and the second load impedance is associated with the second current steering cell.

[0071] Aspect 11. The DAC system of any one of aspects 1-10, wherein drains of the first and second current steering transistors are coupled to a resistive ladder circuit.

[0072] Aspect 12. The DAC system of any one of aspects 1-11, wherein the first and second current steering transistors, the first transistor, and the second transistor comprise p-channel metal-oxide-semiconductor (PMOS) transistors.

[0073] Aspect 13. A method for digital-to-analog conversion, the method comprising: receiving, at a first driver of a digital-to-analog converter (DAC), a first digital input via an input path of the DAC; generating, by controlling a first current steering transistor and a second current steering transistor of a first current steering cell of a plurality of current steering cells via the first driver based on the first digital input, an analog output signal based on the first digital input, the first current steering cell having a first current source coupled to the first current steering transistor and the second current steering transistor, wherein the first current steering cell further comprises: a first transistor having a source coupled to a current source path, a drain coupled to a reference potential node, and a gate coupled to the first driver; and a second transistor having a source coupled to the current source path, a drain coupled to the reference potential node, and a gate coupled to the first driver.

[0074] Aspect 14. The method of aspect 13, further comprising: receiving, via a third transistor of the current source path, a first current at a source of the third transistor, a drain of the third transistor coupled to the sources of the first transistor and the second transistor.

[0075] Aspect 15. The method of aspect 14, further comprising: providing a second current via a second current source, wherein the first current comprises a first portion of the second current, a second portion of the second current provided to a second current steering cell of the plurality of current steering cells.

[0076] Aspect 16. The method of any of aspects 14-15, wherein the first current steering cell further comprises a fourth transistor coupled between the first current source and a current steering node, the current steering node coupled to sources of the first current steering transistor and the second current steering transistor.

[0077] Aspect 17. The method of aspect 16, wherein a gate of the fourth transistor is coupled to a gate of the third transistor.

[0078] Aspect 18. The method of any of aspects 13-17, further comprising: providing, via the first current steering transistor, a first output current to a first output terminal of the DAC, a drain of the first current steering transistor coupled to the first output terminal of the DAC; and providing, via the second current steering transistor, a second output current to a second output terminal of the DAC, a drain of the second current steering transistor coupled to the second output terminal of the DAC.

[0079] Aspect 19. The method of any one of aspects 13-18, further comprising: receiving, at a second driver of the DAC, a second digital input via the input path of the DAC; and generating the analog output signal based on the second digital input by controlling, based on the second digital input, a third current steering transistor and a fourth current steering transistor of a second current steering cell of the plurality of current steering cells via the second driver, the second current steering cell having a second current source coupled to the third current steering transistor and the fourth current steering transistor.

[0080] Aspect 20. The method of aspect 19, wherein the second current steering cell comprises: a fifth current steering transistor having a source coupled to the second current source; and a sixth current steering transistor having a source coupled to the second current source, wherein gates of the fifth current steering transistor and the sixth current steering transistor are coupled to first and second output terminals of the second driver, respectively.

[0081] Aspect 21. The method of any one of aspects 19-20, wherein the first digital input has a lower significance than the second digital input.

[0082] Aspect 22. The method of any one of aspects 19-21, wherein: a first load impedance of the first driver is configured to match a second load impedance of the second driver; the first load impedance is associated with the first current steering cell; and the second load impedance is associated with the second current steering cell.

[0083] Aspect 23. The method of any one of aspects 13-22, wherein drains of the first current steering transistor and the second current steering transistor are coupled to a resistive ladder circuit.

[0084] Aspect 24. The method of any one of aspects 13-23, wherein the first current steering transistor, the second current steering transistor, the first transistor, and the second transistor comprise p-channel metal-oxide-semiconductor (PMOS) transistors.

[0085] Aspect 25. An apparatus for digital-to-analog conversion, the apparatus comprising: means for receiving a first digital input; and a first current steering cell of a plurality of current steering cells coupled to the means for receiving, wherein the means for receiving comprises means for controlling a first current steering transistor and a second current steering transistor of the first current steering cell based on the first digital input, the first current steering cell having a first current source coupled to the first current steering transistor and the second current steering transistor, wherein the first current steering cell further comprises: a first transistor having a source coupled to a current source path, a drain coupled to a reference potential node, and a gate coupled to the means for controlling; and a second transistor having a source coupled to the current source path, a drain coupled to the reference potential node, and a gate coupled to the means for controlling.

[0086] Additional Considerations

[0087] Within the disclosure, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term "coupled" is used herein to refer to the direct or indirect coupling between two objects. For example, if object A physically touches object B, and object B touches object C, then objects A and C can still be considered coupled to one another — even if objects A and C do not directly physically touch each other — as objects A and C can still be coupled to each other through objects B. As used herein, the term "circuitry" broadly refers to a combination of hardware and / or software that is configured to provide the functionality described herein, without regard to the specific hardware or software type that is used to implement the functionality. For example, a processing element can include a combination of a processor and / or controller with software that is loaded and executed by the processor and / or controller.

[0088] As used herein, the term "determining" encompasses a wide variety of actions. For example, "determining" can include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database or another data structure), ascertaining and the like. Additionally, "determining" can include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory) and the like. Furthermore, "determining" can include resolving, selecting, choosing, establishing and the like.

[0089] The apparatus and methods described in the detailed description are illustrated by way of various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively referred to as “elements”). Various operations or methods described above can be performed by any suitable means capable of performing the corresponding functions. The means can include various hardware and / or software component(s) and / or module(s), including, but not limited to a circuit, an application specific integrated circuit (ASIC), or processor. Generally, where there are operations illustrated in figures, those operations can have corresponding counterpart means-plus-function components with similar numbering. For example, means for receiving and means for controlling can include drivers, such as driver 410 or driver 412.

[0090] One or more of the components, steps, features and / or functions illustrated herein can be rearranged and / or combined into a single component, step, feature or function or embodied in several components, steps, or functions. Additional elements, components, steps, and / or functions can also be added or made optional without departing from the disclosed subject matter. The apparatus, devices, and / or components illustrated herein can be configured to perform one or more of the methods, features, or steps described herein.

[0091] It should be understood that the particular order in which the steps of the disclosed methods have been discussed is merely exemplary. It should be understood that the particular order in which the steps of these methods have been discussed is merely an example and that the steps of the methods can be rearranged or otherwise re-sequenced without departing from the disclosed subject matter. The method claims set forth in the appended claims are presented in the example order in which the steps are presented, but the steps of the various claims can be rearranged or otherwise re-sequenced without departing from the disclosed subject matter.

[0092] The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other aspects. Thus, the claims are not intended to be limited to the aspects presented herein, but are to be accorded the full scope consistent with the language of the claims, wherein reference to an element in the singular is not intended to mean "one and only one" unless specifically so stated, but rather "one or more." Unless specifically stated otherwise, the term "some" refers to one or more. Phrases such as "at least one of' or "one or more of' or "one or more' are to be understood as meaning that a selection of one or more of the referenced items can be made based on the specific example example, "at least one of a, b, or c" is intended to cover: a, b, c, a-b, a-c, b-c, and a-b-c, as well as any of the possible combinations of the elements, multiple identical elements, multiple different elements, and so forth. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. No claim element is to be construed under the provisions of 35 U.S.C. § 112(f) unless the element is expressly recited in the claim as "means plus function."

[0093] It is to be understood that the claims are not limited to the precise arrangements and components exemplified above. Various modifications, changes and variations can be made to the arrangements, operation and details of the methods and apparatus described herein without departing from the scope of the claims.

Claims

1. A digital-to-analog converter (DAC) system comprising: a first driver; and a plurality of current steering cells, wherein a first current steering cell of the plurality of current steering cells comprises: a first current source coupled to a first current steering transistor and a second current steering transistor, wherein gates of the first current steering transistor and the second current steering transistor are coupled to first and second outputs of the first driver, respectively; a first transistor having a source coupled to a current source path, a drain coupled to a reference potential node, and a gate coupled to the first output of the first driver; and a second transistor having a source coupled to the current source path, a drain coupled to the reference potential node, and a gate coupled to the second output of the first driver.

2. The DAC system of claim 1, wherein the current source path comprises a third transistor configured to receive a first current at a source of the third transistor, a drain of the third transistor coupled to the sources of the first and second transistors.

3. The DAC system of claim 2, further comprising a second current source configured to provide a second current, wherein the first current comprises a first portion of the second current, a second portion of the second current provided to a second current steering cell of the plurality of current steering cells.

4. The DAC system of claim 2, wherein the first current steering cell further comprises a fourth transistor coupled between the first current source and a current steering node, the current steering node coupled to sources of the first and second current steering transistors.

5. The DAC system of claim 4, wherein a gate of the fourth transistor is coupled to a gate of the third transistor.

6. The DAC system of claim 1, wherein: a drain of the first current steering transistor is coupled to a first output of the DAC system; and a drain of the second current steering transistor is coupled to a second output of the DAC system.

7. The DAC system of claim 1, wherein a second current steering cell of the plurality of current steering cells comprises: a second current source; a third current steering transistor having a source coupled to the second current source; and a fourth current steering transistor having a source coupled to the second current source, wherein gates of the third and fourth current steering transistors are coupled to first and second outputs of a second driver, respectively.

8. The DAC system of claim 7, wherein the second current steering cell further comprises: a fifth current steering transistor having a source coupled to the second current source; and a sixth current steering transistor having a source coupled to the second current source. a sixth current steering transistor having a source coupled to the second current source, wherein gates of the fifth current steering transistor and the sixth current steering transistor are coupled to the first output and the second output of the second driver, respectively.

9. The DAC system of claim 7, wherein: the first current steering unit is configured to process first bits of a digital input code of the DAC system; and the second current steering unit is configured to process second bits of the digital input code of the DAC system, the first bits having a lower significance than the second bits.

10. The DAC system of claim 7, wherein: a first load impedance of the first driver is configured to match a second load impedance of the second driver; the first load impedance is associated with the first current steering unit; and the second load impedance is associated with the second current steering unit.

11. The DAC system of claim 1, wherein drains of the first current steering transistor and the second current steering transistor are coupled to a resistive ladder circuit.

12. The DAC system of claim 1, wherein the first current steering transistor, the second current steering transistor, the first transistor, and the second transistor comprise p-channel metal-oxide-semiconductor (PMOS) transistors.

13. A method for digital-to-analog conversion, the method comprising: receiving, at a first driver of a digital-to-analog converter (DAC), a first digital input via an input path of the DAC; generating, by controlling first and second current steering transistors of a first current steering unit of a plurality of current steering units based on the first digital input via the first driver, an analog output signal based on the first digital input, the first current steering unit having a first current source coupled to the first and second current steering transistors, wherein the first current steering unit further comprises: a first transistor having a source coupled to a current source path, a drain coupled to a reference potential node, and a gate coupled to the first driver; and a second transistor having a source coupled to the current source path, a drain coupled to the reference potential node, and a gate coupled to the first driver. receiving, via a third transistor of the current source path, a first current at a source of the third transistor, a drain of the third transistor being coupled to the sources of the first and second transistors.

14. The method of claim 13, further comprising: providing a second current via a second current source, wherein the first current comprises a first portion of the second current, a second portion of the second current being provided to a second current steering unit of the plurality of current steering units.

15. The method of claim 14, further comprising: ​ 16. The method of claim 14, wherein the first current steering cell further comprises a fourth transistor coupled between the first current source and a current steering node, the current steering node coupled to sources of the first current steering transistor and the second current steering transistor.

17. The method of claim 16, wherein a gate of the fourth transistor is coupled to a gate of the third transistor.

18. The method of claim 13, the method further comprising: providing a first output current to a first output terminal of the DAC via the first current steering transistor, a drain of the first current steering transistor coupled to the first output terminal of the DAC; and providing a second output current to a second output terminal of the DAC via the second current steering transistor, a drain of the second current steering transistor coupled to the second output terminal of the DAC.

19. The method of claim 13, the method further comprising: receiving a second digital input at a second driver of the DAC via the input path of the DAC; and generating the analog output signal based on the second digital input by controlling a third current steering transistor and a fourth current steering transistor of a second current steering cell of the plurality of current steering cells based on the second digital input via the second driver, the second current steering cell having a second current source coupled to the third current steering transistor and the fourth current steering transistor.

20. The method of claim 19, wherein the second current steering cell comprises: a fifth current steering transistor having a source coupled to the second current source; and a sixth current steering transistor having a source coupled to the second current source, wherein gates of the fifth current steering transistor and the sixth current steering transistor are coupled to first and second output terminals of the second driver, respectively.

21. The method of claim 19, wherein the first digital input has a lower significance than the second digital input.

22. The method of claim 19, wherein: a first load impedance of the first driver is configured to match a second load impedance of the second driver; the first load impedance is associated with the first current steering cell; and the second load impedance is associated with the second current steering cell.

23. The method of claim 13, wherein drains of the first current steering transistor and the second current steering transistor are coupled to a resistive ladder circuit.

24. The method of claim 13, wherein the first current steering transistor, the second current steering transistor, the first transistor, and the second transistor comprise p-channel metal-oxide-semiconductor (PMOS) transistors.

25. An apparatus for digital-to-analog conversion, the apparatus comprising: means for receiving a first digital input; and means for generating an analog output signal based on the first digital input by controlling a first current steering transistor and a second current steering transistor of a first current steering cell of the plurality of current steering cells based on the first digital input via the first driver, the first current steering cell having a first current source coupled to the first current steering transistor and the second current steering transistor. ​ a first current steering unit of the plurality of current steering units coupled to the means for receiving, wherein the means for receiving comprises means for controlling a first current steering transistor and a second current steering transistor based on the first digital input, the first current steering unit having a first current source coupled to the first current steering transistor and the second current steering transistor, wherein the first current steering unit further comprises: a first transistor having a source coupled to a current source path, a drain coupled to a reference potential node, and a gate coupled to the means for controlling; and a second transistor having a source coupled to the current source path, a drain coupled to the reference potential node, and a gate coupled to the means for controlling. ​

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