Circuit board

Abstract

A circuit board of the present invention includes a first laminated ceramic electronic component and a second laminated ceramic electronic component. Each of the laminated ceramic electronic components has a height dimension that is 1.3 times or more of a width dimension, and the first laminated ceramic electronic component and the second laminated ceramic electronic component are orthogonal in respective longitudinal directions. The first laminated ceramic electronic component and the second laminated ceramic electronic component are disposed adjacent to each other on the mounting surface in a state in which a region, in which a region occupied in the width direction of the first laminated ceramic electronic component extends in the longitudinal direction of the first laminated ceramic electronic component, overlaps one of the first external electrode and the second external electrode of the second laminated ceramic electronic component.

Description

TECHNICAL FIELD

[0001] The present application relates to a circuit board. BACKGROUND

[0002] In recent years, various electronic devices are being increasingly downsized and high-functionalized, and electronic components including a multilayer ceramic electronic component have a tendency to be reduced in mounting area on a circuit board. On the other hand, for the multilayer ceramic electronic component, further large capacitance is required. In order to cope with such a requirement, a component structure for realizing further high-density mounting and large capacitance has been proposed (for example, refer to Patent Literature 1). In the multilayer ceramic electronic component, the mounting area on the circuit board can be specified by the length direction dimension and the width direction dimension of the multilayer ceramic electronic component. In Patent Literature 1, a technology of increasing the height direction dimension, that is, the dimension in the direction perpendicular to the mounting surface of the circuit board, compared to the length direction dimension or the width direction dimension of the multilayer ceramic electronic component, and becoming a high-back type has been proposed. The high-back type multilayer ceramic electronic component is suitable for large capacitance.

[0003] PRIOR ART DOCUMENTS

[0004] PATENT LITERATURE

[0005] Patent Literature 1: Japanese Patent Application Publication No. 2020-031152 SUMMARY

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] However, if the dimension in the height direction is large, and the multilayer ceramic electronic component mounted with high density is tilted, it is likely to come into contact with other electronic components mounted around it and short-circuit.

[0008] Therefore, the technical problem of the present application is to suppress short-circuiting when the high-back type multilayer ceramic electronic component is tilted in a circuit board in which the high-back type multilayer ceramic electronic component is mounted with high density.

[0009] MEANS FOR SOLVING THE PROBLEMS

[0010] To solve the above-described technical problem, the circuit board disclosed in the present specification includes: a substrate provided with a first axis perpendicular to a mounting surface, and a second axis and a third axis each orthogonal to the first axis and orthogonal to each other; and a plurality of multilayer ceramic electronic components mounted to the mounting surface, a first multilayer ceramic electronic component included in the plurality of multilayer ceramic electronic components is mounted to the mounting surface in a state in which a height direction coincides with a direction along the first axis, a width direction coincides with a direction along the second axis, and a length direction coincides with a direction along the third axis, and has a first external electrode having a prescribed length in the length direction at one end portion in the length direction and a second external electrode having a prescribed length in the length direction at the other end portion in the length direction, a second multilayer ceramic electronic component included in the plurality of multilayer ceramic electronic components is mounted to the mounting surface in a manner in which a height direction coincides with a direction along the first axis, a length direction coincides with a direction along the second axis, and a width direction coincides with a direction along the third axis, and has a first external electrode having a prescribed length in the length direction at one end portion in the length direction and a second external electrode having a prescribed length in the length direction at the other end portion in the length direction, a height dimension of the first multilayer ceramic electronic component is 1.3 times or more of a width dimension or a length dimension of the first multilayer ceramic electronic component, and a height dimension of the second multilayer ceramic electronic component is 1.3 times or more of a width dimension of the second multilayer ceramic electronic component, the first multilayer ceramic electronic component and the second multilayer ceramic electronic component are arranged adjacent to each other in a state in which a region in which a region occupied in a width direction of the first multilayer ceramic electronic component is extended in a length direction of the first multilayer ceramic electronic component overlaps with one of the first external electrode and the second external electrode of the second multilayer ceramic electronic component.

[0011] In the circuit board of the above-described structure, the following can be adopted: a distance in a direction along the second axis of the first external electrode and the second external electrode of the first multilayer ceramic electronic component from the other of the first external electrode and the second external electrode of the second multilayer ceramic electronic component is greater than 0.5 times a height dimension of the first multilayer ceramic electronic component.

[0012] In the circuit board of the above-described structure, the following can be adopted: in a region in a direction along the second axis of the first multilayer ceramic electronic component and in a direction along the third axis of the second multilayer ceramic electronic component, other electronic components that are arranged adjacent to the first multilayer ceramic electronic component and the second multilayer ceramic electronic component and are covered by an insulating cover are mounted.

[0013] Further, in the circuit board described above, the following configuration can be adopted: in a region of the second multilayer ceramic electronic component in a direction along the second axis and on a side of the first multilayer ceramic electronic component in a direction along the third axis, another electronic component is mounted which is disposed adjacent to the first multilayer ceramic electronic component and the second multilayer ceramic electronic component and is covered by an insulating cover.

[0014] Further, in the circuit board described above, the following configuration can be adopted: at least one of a height dimension of the first multilayer ceramic electronic component and a height dimension of the second multilayer ceramic electronic component is 1.5 times or more of a respective width dimension or length dimension.

[0015] In the circuit board described above, the following configuration can be adopted: at least one of an internal electrode provided inside a ceramic main body of the first multilayer ceramic electronic component and an internal electrode provided inside a ceramic main body of the second multilayer ceramic electronic component is stacked in opposition in a direction along a respective height direction.

[0016] Further, in the circuit board described above, the following configuration can be adopted: the internal electrodes stacked in the direction along the height direction include: a first internal electrode connected to the first external electrode; and a second internal electrode connected to the second external electrode, the first internal electrode has a connection end portion connected to the first external electrode and an open end portion on an opposite side of the connection end portion, the connection end portion has a narrow portion in which a dimension in the width direction is smaller than a dimension of the open end portion in the width direction, the second internal electrode has a connection end portion connected to the second external electrode and an open end portion on an opposite side of the connection end portion, the connection end portion has a narrow portion in which a dimension in the width direction is smaller than a dimension of the open end portion in the width direction.

[0017] Further, in the circuit board described above, the following configuration can be adopted: at least one of an internal electrode provided inside a ceramic main body of the first multilayer ceramic electronic component and an internal electrode provided inside a ceramic main body of the second multilayer ceramic electronic component is stacked in opposition in a direction along a respective width direction.

[0018] Further, in the circuit board described above, the following can be adopted: the internal electrode stacked in the direction of the width described above includes a first internal electrode connected to the first external electrode, and a second internal electrode connected to the second external electrode, the first internal electrode has a connection end portion connected to the first external electrode, and an open end portion on the opposite side of the connection end portion, the connection end portion has a narrow portion in which the dimension in the height direction is smaller than the dimension of the open end portion in the height direction, the second internal electrode has a connection end portion connected to the second external electrode, and an open end portion on the opposite side of the connection end portion, the connection end portion has a narrow portion in which the dimension in the height direction is smaller than the dimension of the open end portion in the height direction.

[0019] Further, in the circuit board described above, the following can be adopted: the internal electrode or the dielectric layer formed between the internal electrodes contains a low-melting metal.

[0020] Effects of Invention

[0021] According to the invention disclosed in the present specification, in a circuit board in which a high-back type multilayer ceramic electronic component is mounted at high density, short circuiting can be suppressed in the case where the multilayer ceramic electronic component has tilted. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 (A) of FIG. 1 is a front view of a circuit board of a first embodiment, Figure 1 (B) thereof is a plan view. Figure 1 (C) of FIG. 1 is a cross-sectional view taken along line A1-A1 of Figure 1 (A) and Figure 1 (B) of FIG. 1 are equivalent circuit diagrams of the circuit board shown in

[0023] Figure 2 (A) of FIG. 2 is a perspective view of a first and a second multilayer ceramic capacitor used for the circuit board of the first embodiment.

[0024] Figure 3 (B) of FIG. 2 is a 4-face view of the first and the second multilayer ceramic capacitor used for the circuit board of the first embodiment. Figure 3 (A) of FIG. 3 is a plan view, Figure 3 (B) of FIG. 3 is a bottom view, Figure 3 (C) of FIG. 3 is a front view, Figure 3 (D) of FIG. 3 is a rear view.

[0025] Figure 4 (A) of FIG. 4 is a cross-sectional view taken along line A1-A1 of Figure 2 of FIG. 4 is a cross-sectional view taken along line A1-A1 of

[0026] Figure 5(A) is a cross-sectional view of the first multilayer ceramic capacitor used for the circuit board of the first embodiment in FIG. 1, Figure 2 (A2-A2) is a cross-sectional view of the first multilayer ceramic capacitor used for the circuit board of the first embodiment in FIG. 2, Figure 5 (B) is a cross-sectional view of the first multilayer ceramic capacitor used for the circuit board of the first embodiment in FIG. 3, Figure 2 (A3-A3) is a cross-sectional view of the first multilayer ceramic capacitor used for the circuit board of the first embodiment in FIG. 4.

[0027] Figure 6 (A) is an explanatory view showing the positional relationship between the first multilayer ceramic capacitor and the second multilayer ceramic capacitor in the first embodiment, Figure 6 (B) is an explanatory view showing the positional relationship between the first multilayer ceramic capacitor and the second multilayer ceramic capacitor in the first modification of the first embodiment. Figure 6 (C) is an explanatory view showing the positional relationship between the first multilayer ceramic capacitor and the second multilayer ceramic capacitor in the second modification of the first embodiment, Figure 6 (D) is an explanatory view showing the positional relationship between the first multilayer ceramic capacitor and the second multilayer ceramic capacitor in the third modification of the first embodiment.

[0028] Figure 7 (A) is a side view of the circuit board of the second embodiment in FIG. 5, Figure 7 (B) is a plan view of the circuit board of the second embodiment in FIG. 6. Figure 7 (C) is a plan view of the circuit board of the third embodiment in FIG. 7.

[0029] Figure 8 is a cross-sectional view of the first multilayer ceramic capacitor used for the circuit board of the fourth embodiment in FIG. 8, which is cut along a line segment corresponding to Figure 2 (A1-A1) in FIG. 9.

[0030] Figure 9 (A) is a cross-sectional view of the first multilayer ceramic capacitor used for the circuit board of the fourth embodiment in FIG. 10, which is cut along a line segment corresponding to Figure 2 (A2-A2) in FIG. 11, Figure 9 (B) is a cross-sectional view of the first multilayer ceramic capacitor used for the circuit board of the fourth embodiment in FIG. 12, which is cut along a line segment corresponding to Figure 2 (A3-A3) in FIG. 13.

[0031] Figure 10 is a view showing the ceramic main body portion of the first multilayer ceramic capacitor in the fifth embodiment, which is shown by being disassembled.

[0032] Figure 11 is a view showing the ceramic main body portion of the first multilayer ceramic capacitor in the modification of the fifth embodiment, which is shown by being disassembled.

[0033] Figure 12This is a perspective view of the circuit board showing a partial cross-section of the first-layer ceramic capacitor of a modified example of the fifth embodiment.

[0034] Figure 13 (A) is a side view of the circuit board of the comparative example. Figure 13 (B) is its top view.

[0035] Figure 14 This diagram schematically illustrates the tilted state of the first-layer ceramic capacitor in the comparative example. Figure 14 (A) is a side view. Figure 14 (B) is the top view. Detailed Implementation

[0036] Hereinafter, a circuit board according to an embodiment of the present invention will be described with reference to the accompanying drawings. In the drawings, the dimensions, ratios, etc., of various parts are sometimes not shown to be exactly the same as the actual dimensions and ratios. Furthermore, for ease of description, details or constituent elements themselves are sometimes omitted from the drawings. Additionally, mutually orthogonal X-axis, Y-axis, and Z-axis are appropriately shown in the drawings. The X-axis, Y-axis, and Z-axis define a fixed coordinate system relative to the circuit board 110. In the following description, the Z-axis direction corresponds to the direction along the first axis, and the Y-axis direction corresponds to the direction along the second axis. Furthermore, the X-axis direction corresponds to the direction along the third axis.

[0037] (First Implementation)

[0038] [Circuit Board]

[0039] First, refer to Figure 1 (A) Figure 1 (C) will describe the general structure of the circuit board 110 of the first embodiment. Figure 1 (A) is a front view of the circuit board 110 of the first embodiment. Figure 1 (B) is a top view of circuit board 110. Figure 1 (C) is an equivalent circuit diagram of the circuit board 110 according to the first embodiment. The circuit board 110 has a printed wiring board 1 as a substrate, a first multilayer ceramic capacitor (MLCC) 10, and a second multilayer ceramic capacitor 30. In this embodiment, the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 are the same items, but different reference numerals are used for ease of explanation. The first multilayer ceramic capacitor 10 has a first external electrode 14 and a second external electrode 15. The second multilayer ceramic capacitor 30 also has a first external electrode 34 and a second external electrode 35.

[0040] In the circuit board 110, short-circuiting of the first external electrode 14 or the second external electrode 15 of the first multilayer ceramic capacitor 10 with the first external electrode 34 and the second external electrode 35 of the second multilayer ceramic capacitor 30 is required to be avoided. Specifically, for example, short-circuiting of the second external electrode 15 of the first multilayer ceramic capacitor 10 with the first external electrode 34 and the second external electrode 35 of the second multilayer ceramic capacitor 30 is required to be avoided.

[0041] In the circuit structure of the present embodiment, as shown in the equivalent circuit 5 of (C), Figure 1 one external electrode of the first multilayer ceramic capacitor 10 is grounded, and the other external electrode is input via the first terminal 4a. In addition, one external electrode of the second multilayer ceramic capacitor 30 is grounded, and the other external electrode is input via the second terminal 4b. Thus, in the present embodiment, contact of either external electrode of the first multilayer ceramic capacitor 10 with both external electrodes of the second multilayer ceramic capacitor 30 is required to be avoided. However, this circuit structure is one example, and the combination of external electrodes to be avoided from contacting differs depending on the circuit structure.

[0042] The first land 2a, the second land 2b, the third land 2c, and the fourth land 2d are provided in the printed wiring board 1. The second land 2b and the fourth land 2d are grounded. The first terminal 4a is provided in the first land 2a. The second terminal 4b is provided in the third land 2c.

[0043] The first external electrode 14 of the first multilayer ceramic capacitor 10 is disposed on the first land 2a in which the first terminal 4a is provided. The second external electrode 15 of the first multilayer ceramic capacitor 10 is disposed on the second land 2b which is grounded. In addition, the second external electrode 35 of the second multilayer ceramic capacitor 30 is disposed on the third land 2c in which the second terminal 4b is provided. The first external electrode 34 of the second multilayer ceramic capacitor 30 is disposed on the fourth land 2d which is grounded.

[0044] Thus, in the present embodiment, contact of the second external electrode 15 of the first multilayer ceramic capacitor 10 with the first external electrode 34 and the second external electrode 35 of the second multilayer ceramic capacitor 30 is required to be avoided.

[0045] Further, each external electrode is fixed to the disposed respective land by a solder fillet 3. Thus, the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 are mounted to the mounting surface la of the printed wiring board 1.

[0046] The first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 are mounted to the printed wiring board 1 in a manner that the respective height directions thereof are perpendicular to the mounting surface la.

[0047] The first multilayer ceramic capacitor 10 is mounted on the mounting surface 1a with its width direction aligned with the Y-axis direction and its length direction aligned with the X-axis direction. A first external electrode 14 is disposed at one end of the first multilayer ceramic capacitor 10 along the X-axis direction, and a second external electrode 15 is disposed at the other end.

[0048] The second-layer ceramic capacitor 30 is mounted on the mounting surface 1a with its length direction aligned with the Y-axis direction and its width direction aligned with the X-axis direction. The first external electrode 34 is disposed at one end of the second-layer ceramic capacitor 30 along the Y-axis direction, and the second external electrode 35 is disposed at the other end.

[0049] Reference Figure 1 In (B), the first-layer ceramic capacitor 10 and the second-layer ceramic capacitor 30 are configured to be orthogonal in their respective length directions. Furthermore, the first-layer ceramic capacitor 10 and the second-layer ceramic capacitor 30 are positioned such that... Figure 1 The region Ar shown in (B) is arranged adjacent to the first external electrode 34 of the second laminated ceramic capacitor 30 in a manner that overlaps with it. Here, region Ar is as follows: Figure 1 As indicated by the shaded line in (B), this refers to the region where the width of the first multilayer ceramic capacitor 10 extends along the length of the first multilayer ceramic capacitor 10. In this specification, "adjacent state" refers to a state where no other components are installed between the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30.

[0050] Furthermore, the first-layer ceramic capacitor 10 and the second-layer ceramic capacitor 30 can also be installed with each layer rotated 180°. The positional relationship between the first-layer ceramic capacitor 10 and the second-layer ceramic capacitor 30 will be explained in more detail later.

[0051] <Dimensioning of the first and second laminated ceramic capacitors>

[0052] Here, referring to the perspective view of the first-layer ceramic capacitor 10, i.e. Figure 2The dimensions of the first multilayer ceramic capacitor 10 are described. The X-axis direction dimension, i.e., the length, of the first multilayer ceramic capacitor 10 is denoted by L

[10] , and the Y-axis direction dimension, i.e., the width, is denoted by W

[10] . The Z-axis direction dimension, i.e., the height, is denoted by T

[10] . Further, the X-axis direction dimension, i.e., the length, of the first external electrode 14 is denoted by L

[14] . Similarly, the X-axis direction dimension, i.e., the length, of the second external electrode 15 is denoted by L

[15] . Further, the gap between the first external electrode 14 and the second external electrode 15 in the X-axis direction is denoted by G

[10] . Further, between the first external electrode 14 and the second external electrode 15, the ceramic main body 11 described later is exposed.

[0053] The second multilayer ceramic capacitor 30 is also similarly denoted. However, the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 are disposed in a state in which the respective length directions are orthogonal. Therefore, in the second multilayer ceramic capacitor 30, the Y-axis direction dimension becomes the length dimension, which is denoted by L

[30] , and the X-axis direction dimension becomes the width dimension, which is denoted by W

[30] . As for the Z-axis direction dimension, as with the first multilayer ceramic capacitor 10, it becomes the height dimension, which is denoted by T

[30] . Further, the Y-axis direction dimension, i.e., the length, of the first external electrode 34 is denoted by L

[34] . Similarly, the Y-axis direction dimension, i.e., the length, of the second external electrode 35 is denoted by L

[35] . Further, the gap between the first external electrode 34 and the second external electrode 35 in the Y-axis direction is denoted by G

[30] . Further, between the first external electrode 34 and the second external electrode 35, the ceramic main body 31 described later is exposed.

[0054] <First Multilayer Ceramic Capacitor>

[0055] Next, the first multilayer ceramic capacitor 10 is described in detail with reference to Figure 2 and Figure 3 (A) to Figure 3 (D) of FIG. 10. Figure 3 (A) to Figure 3 (D) of FIG. 10 are plan views of the first multilayer ceramic capacitor 10. Further, the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 are the same article, and their appearance shapes are also substantially the same. Therefore, in Figure 2 and Figure 3 (A) to Figure 3 (D) of FIG. 10, the reference numerals indicating the constituent elements of both are shown. The following description regarding the X-axis, the Y-axis, and the Z-axis is based on the state in which the first multilayer ceramic capacitor 10 is mounted on the substrate 1. That is, the description is based on the coordinate system set in the substrate.

[0056] <<Appearance Shape>>

[0057] First, the outer shape of the first multilayer ceramic capacitor 10 will be described.

[0058] The first multilayer ceramic capacitor 10 has a ceramic main body 11, a first external electrode 14, and a second external electrode 15. The ceramic main body 11 is configured as a hexahedron having a first main face M11 and a second main face M12 orthogonal to the Z-axis, a first end face E11 and a second end face E12 orthogonal to the X-axis, and a first side face S11 and a second side face S12 orthogonal to the Y-axis. Further, the "hexahedron" can be substantially hexahedron-shaped, and for example, the edges connecting the respective faces of the ceramic main body 11 can have rounded corners.

[0059] The main faces M11, M12, the end faces E11, E12, and the side faces S11, S12 of the ceramic main body 11 are each configured as a flat face. The flat face of the present embodiment can be a face that is recognized as flat when viewed as a whole, and can not be a strict plane, and for example, includes a face having a minute uneven shape of a surface, a gentle curved shape existing in a prescribed range, or the like.

[0060] The first multilayer ceramic capacitor 10 is a high-back type in which the height T

[10] is as large as 1.3 times or more of the width W

[10] . In the first multilayer ceramic capacitor 10, large-capacitance is achieved by increasing the height T

[10] . In addition, it is preferable that the height T

[10] be 1.5 times or more of the width W

[10] . The height T

[10] can be, for example, 1.6 times, 1.7 times, or more of the width W

[10] . Thereby, the first multilayer ceramic capacitor 10 can be further large-capacitance.

[0061] Further, in the present embodiment, the condition of the height T

[10] is prescribed in terms of the ratio to the width W

[10] , but the condition of the height T

[10] can be set in terms of the relationship to the length L

[10] instead of the width W

[10] . That is, the first multilayer ceramic capacitor 10 can be a high-back type in which the height T

[10] is as large as 1.3 times or more of the length W

[10] . In addition, the height T

[10] can be 1.5 times or more of the length L

[10] .

[0062] In the first multilayer ceramic capacitor 10, the size of the ceramic main body 11 in the X-axis direction can be larger than the size in the Y-axis direction, or can be smaller than the size in the Z-axis direction. In the first multilayer ceramic capacitor 10, the sizes of the ceramic main body 11 in the three-axis directions can be arbitrarily determined within a range satisfying the above conditions.

[0063] In the first multilayer ceramic capacitor 10 of the present embodiment, for example, the length L

[10] can be 0.2 mm or more and 1.2 mm or less, and the width W

[10] can be 0.1 mm or more and 0.7 mm or less. In addition, the height T

[10] can be 0.15 mm or more and 1.0 mm or less. The height T

[10] , the width W

[10] , and the length L

[10] are each the largest dimension in the respective directions of the first multilayer ceramic capacitor 10.

[0064] The first external electrode 14 has a first face portion 14a that covers the end face E11 of the ceramic main body 11. The first external electrode 14 has a second face portion 14b that extends from the first face portion 14a toward the side face S11, and a third face portion 14c that extends toward the side face S12. The first external electrode 14 also has a fourth face portion 14d that extends from the first face portion 14a toward the main face M11, and a fifth face portion 14e that extends toward the main face M12.

[0065] The second external electrode 15 has a first face portion 15a that covers the end face E12 of the ceramic main body 11. The second external electrode 15 has a second face portion 15b that extends from the first face portion 15a toward the side face S11, and a third face portion 15c that extends toward the side face S12. The second external electrode 15 also has a fourth face portion 15d that extends from the first face portion 15a toward the main face M11, and a fifth face portion 15e that extends toward the main face M12.

[0066] Here, the second face portions 14b, 15b, the third face portions 14c, 15c, the fourth face portions 14d, 15d, and the fifth face portions 14e, 15e correspond to the extension portions.

[0067] In the external electrodes 14, 15, both the cross section parallel to the X-Z plane and the cross section parallel to the X-Y plane are U-shaped. The shape of the external electrodes 14, 15 is not limited to the example shown in the drawing.

[0068] Further, the external electrodes 14, 15 contain a metal material as a main component. As the metal material that constitutes the external electrodes 14, 15, for example, copper (Cu), nickel (Ni), tin (Sn), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), and alloys thereof, and the like can be given. In the present embodiment, the main component refers to the component having the highest proportion.

[0069] <<Internal Structure>>

[0070] Next, the internal structure of the first multilayer ceramic capacitor 10 will be described with reference to Figures 4-5 (B). Figure 4 is a view of the cross section of the first multilayer ceramic capacitor 10 taken along the A1-A1 line in Figure 2 Figure 5 ​(A) of FIG. 1 is a cross-sectional view of the first multilayer ceramic capacitor 10 taken along the line A1-A1 in FIG. 1. Figure 2 (A) of FIG. 1 is a cross-sectional view of the first multilayer ceramic capacitor 10 taken along the line A1-A1 in FIG. 1. Figure 5 (A) of FIG. 1 is a cross-sectional view of the first multilayer ceramic capacitor 10 taken along the line A1-A1 in FIG. 1. Figure 2 (A) of FIG. 1 is a cross-sectional view of the first multilayer ceramic capacitor 10 taken along the line A1-A1 in FIG. 1. Figure 5 (A) of FIG. 1 is a cross-sectional view of the first multilayer ceramic capacitor 10 taken along the line A1-A1 in FIG. 1.

[0071] The ceramic main body 11 has a laminated portion 20 and a pair of margin portions 18. The laminated portion 20 has a capacitance forming portion 16 and a pair of cover portions 17. The capacitance forming portion 16 includes a plurality of first and second internal electrodes 12, 13 alternately laminated along the Z-axis direction with a plurality of ceramic layers 19. In the present embodiment, the first internal electrode 12, the second internal electrode 13, and the ceramic layer 19 are each configured in a sheet shape extending along the X-Y plane. Further, the number of layers of the first and second internal electrodes 12, 13 in each drawing does not represent the actual number of layers.

[0072] The first and second internal electrodes 12, 13 are alternately arranged along the Z-axis direction in a manner of facing each other in the Z-axis direction. The first and second internal electrodes 12, 13 face each other in the Z-axis direction in a central region of the X-axis direction and the Y-axis direction. The first internal electrode 12 corresponds to a first group, and is drawn out from the central region to one end surface E11 to be connected to the first external electrode 14. The second internal electrode 13 corresponds to a second group, and is drawn out from the central region to the other end surface E12 to be connected to the second external electrode 15.

[0073] The first and second internal electrodes 12, 13 contain a metal material as a main component. As the metal material, nickel (Ni) can be typically cited, and in addition to this, copper (Cu), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), and alloys thereof, and the like can be cited. Further, the metal material forming the internal electrodes 12, 13 can contain a low-melting-point metal having a lower melting point than nickel (Ni) as a main component as an additive element. Such a low-melting-point metal is, for example, tin (Sn), zinc (Zn), aluminum (Al), gallium (Ga), germanium (Ge), and the like. The internal electrodes 12, 13 can contain at least one of these low-melting-point metals. By adding such a low-melting-point metal, it is possible to improve the sinterability of the inside of the ceramic main body 11, and to improve the insulation between the internal electrodes 12, 13.

[0074] With such a structure, in the first multilayer ceramic capacitor 10, if a voltage is applied between the external electrodes 14, 15, a voltage is applied to the plurality of ceramic layers 19 between the internal electrodes 12, 13 in the central region. Thus, in the first multilayer ceramic capacitor 10, an electric charge corresponding to the voltage between the external electrodes 14, 15 is accumulated.

[0075] In the stack portion 20, in order to increase the electrostatic capacitance of each ceramic layer 19 between the first and second internal electrodes 12, 13, a dielectric ceramic having a high dielectric constant is used. As the dielectric ceramic having a high dielectric constant, for example, a material having a perovskite structure containing barium (Ba) and titanium (Ti) typified by barium titanate (BaTiO3) can be cited.

[0076] In addition, the dielectric ceramic can also be of a composition system of strontium titanate (SrTiO3), calcium titanate (CaTiO3), magnesium titanate (MgTiO3), calcium zirconate (CaZrO3), calcium zirconate titanate (Ca(Zr,Ti)O3), barium calcium zirconate titanate ((Ba,Ca)(Zr,Ti)O3), barium zirconate (BaZrO3), titanium oxide (TiO2), or the like. In this case, instead of adding a low-melting-point metal to the above-described first and second internal electrodes 12, 13, a low-melting-point metal can be added to the dielectric ceramic, or a low-melting-point metal can be added to the first and second internal electrodes 12, 13 and a low-melting-point metal can be added to the dielectric ceramic. The content of the low-melting-point metal and the effects of adding the low-melting-point metal are as described above, and thus a detailed description thereof is omitted here.

[0077] A pair of cover portions 17 covers the capacitance forming portion 16 from both sides in the stacking direction, that is, the Z-axis direction. The cover portion 17 is also sometimes referred to as a protective layer in the height direction. The cover portion 17 is composed of, for example, a laminate of ceramic sheets extending along the X-Y plane. From the viewpoint of suppressing internal stress and the like, the dielectric ceramic constituting the cover portion 17 is preferably of the same composition system as the ceramic layer 19.

[0078] A pair of edge portions 18 is formed along the Z-axis direction and covers the stack portion 20 from the Y-axis direction. The edge portion 18 is also sometimes referred to as a protective layer in the width direction. The edge portion 18 is mounted on the surface of the stack portion 20 perpendicular to the Y-axis. For example, the edge portion 18 is formed of a ceramic sheet and is composed of a sheet shape extending along the X-Z plane. From the viewpoint of suppressing internal stress and the like, the dielectric ceramic constituting the edge portion 18 is preferably of the same composition system as the ceramic layer 19.

[0079] <Second Stacked Ceramic Capacitor>

[0080] The second stacked ceramic capacitor 30 is the same article as the first stacked ceramic capacitor 10. Therefore, the above-described description of the first stacked ceramic capacitor 10 is generally applicable to the description of the second stacked ceramic capacitor 30. However, the description of the first stacked ceramic capacitor 10 regarding the X-axis, the Y-axis, and the Z-axis is based on the state in which the first stacked ceramic capacitor 10 is mounted on the substrate 1. That is, the description is based on the coordinate system set on the substrate. Therefore, in the description of the second stacked ceramic capacitor 30, the X-axis is replaced with the Y-axis.

[0081] The second multilayer ceramic capacitor 30 has a ceramic main body 31, a first external electrode 34, and a second external electrode 35. The ceramic main body 31 is configured as a hexahedron having a first main face M31 and a second main face M32 orthogonal to the Z-axis, a first end face E31 and a second end face E32 orthogonal to the Y-axis, and a first side face S31 and a second side face S32 orthogonal to the X-axis.

[0082] In addition, the ceramic main body 31 is not labeled with a reference numeral, but has a stack portion and a pair of edge portions similarly to the ceramic main body 11. The stack portion has a capacitance forming portion and a pair of cover portions 17. The capacitance forming portion includes a plurality of first and second internal electrodes alternately stacked along the Z-axis direction. The respective constituent elements of the second multilayer ceramic capacitor 30 having the same names as those of the first multilayer ceramic capacitor 10 are the same, and thus detailed description thereof is omitted here.

[0083] <Size relationship and positional relationship of first and second multilayer ceramic capacitors>

[0084] Here, returning again to Figure 1 (A) and Figure 1 (B) of the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 will be described.

[0085] The first multilayer ceramic capacitor 10 is mounted to the substrate 1 in such a manner that the length direction thereof coincides with the X-axis direction of the substrate 1. On the other hand, the second multilayer ceramic capacitor 30 is mounted to the substrate 1 in such a manner that the length direction thereof coincides with the Y-axis direction of the substrate 1. Thus, the second multilayer ceramic capacitor 30 is mounted in such a manner that the first external electrode 34 overlaps the region Ar.

[0086] Here, a gap S1 is provided between the second external electrode 15 of the first multilayer ceramic capacitor 10 and the first external electrode 34 of the second multilayer ceramic capacitor 30. The gap S1 is the shortest distance between the second external electrode 15 of the first multilayer ceramic capacitor 10 and the first external electrode 34 of the second multilayer ceramic capacitor 30 along the X-axis direction of the substrate 1. No other component is mounted between the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30. Therefore, from the viewpoint of high-density mounting, the gap S1 is preferably 0.3 mm or less, more preferably 0.2 mm or less.

[0087] In addition, a gap S2 is provided between the first and second external electrodes 14 and 15 of the first multilayer ceramic capacitor 10 and the second external electrode 35 of the second multilayer ceramic capacitor 30. The gap S2 is set to be greater than 0.5 times the height T

[10] of the first multilayer ceramic capacitor 10. The gap S2 can be set taking into account the inclination that can occur in the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30.

[0088] The first-layer ceramic capacitor 10 sometimes... Figure 1 As shown in (A), it is tilted in the Y-axis direction, i.e., the width direction. For example, it can be envisioned that the upper edge (upper edge) of the first multilayer ceramic capacitor 10 is tilted close to the second external electrode 35 of the second multilayer ceramic capacitor 30. In this case, it is assumed that the maximum tilt angle is 30°. In this case, as Figure 1 As shown in (A), the mounting surface 1a and the side surface S11 of the first laminated ceramic capacitor 10 (see Figure 1) Figure 2 The angle θ is 60°. When θ = 60°, the upper edge of the first layered ceramic capacitor 10 approaches the second external electrode 35 of the second layered ceramic capacitor 30 at a distance of T

[10] × cos60°. In this way, when the upper edge of the first layered ceramic capacitor 10 approaches the second external electrode 35 of the second layered ceramic capacitor 30, it is necessary to avoid contact between the second external electrode 15 of the first layered ceramic capacitor 10 and the second external electrode 35 of the second layered ceramic capacitor 30. Therefore, the interval S2 is set to be greater than 0.5 times cos60° of the height T

[10] of the first layered ceramic capacitor 10.

[0089] Therefore, when T

[10] is 0.4 mm, the interval S2 is set to be greater than 0.2 mm; when T

[10] is 0.6 mm, the interval S2 is set to be greater than 0.3 mm. Additionally, when T

[10] is 0.8 mm, it is set to be greater than 0.4 mm. Furthermore, as described above, in this embodiment, it is required to avoid contact between the second external electrode 15 of the first stacked ceramic capacitor 10 and the first external electrode 34 and the second external electrode 35 of the second stacked ceramic capacitor 30. Assuming that an appropriate interval S2 is not set, and the first stacked ceramic capacitor 10 is in… Figure 1 (B) tilts to the right, and the second-layer ceramic capacitor 30 is in Figure 1 If (B) is tilted downwards, contact as described above may occur. However, in this embodiment, an appropriate interval S2 is provided. Therefore, even if both stacked ceramic capacitors are tilted, contact between the second external electrode 15 of the first stacked ceramic capacitor 10 and the first external electrode 34 and the second external electrode 35 of the second stacked ceramic capacitor 30 can be avoided.

[0090] Here, refer to Figure 6 (A) Figure 6 (D) illustrates the various changes in the positional relationship between the first-layer ceramic capacitor 10 and the second-layer ceramic capacitors 30, 40, and 40'.

[0091] Figure 6(A) of FIG. 1 shows the positional relationship of the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 in the first embodiment. The interval S2 between the second external electrode 15 of the first multilayer ceramic capacitor 10 and the second external electrode 35 of the second multilayer ceramic capacitor 30 is greater than 0.5 x T

[10] .

[0092] ((First Modification))

[0093] Figure 6 (B) of FIG. 1 is an explanatory view showing the positional relationship of the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 in the first modification of the first embodiment. Figure 6 The position in the left-right direction of the second multilayer ceramic capacitor 30 in (A) of FIG. 1 is a position at which the inner edge (inner margin) of the first external electrode 34 of the second multilayer ceramic capacitor 30 is substantially aligned with the right end edge (right end margin) of the region Ar. In this regard, the second multilayer ceramic capacitor 30 can be positioned as shown in (B) of FIG. 1. Figure 6 In (B) of FIG. 1, the second multilayer ceramic capacitor 30 is positioned at a position that has relatively moved in the range in which the first external electrode 34 of the second multilayer ceramic capacitor 30 overlaps the region Ar, as indicated by the arrow 6a. Thus, the interval between the second external electrode 15 of the first multilayer ceramic capacitor 10 and the second external electrode 35 of the second multilayer ceramic capacitor 30 is S2. Figure 6 The interval S2 shown in (A) of FIG. 1 is an interval that is greater than 0.5 x T

[10] , and that is an interval in which contact between the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 is avoided.

[0094] ((Second Modification))

[0095] Figure 6 (C) of FIG. 1 is an explanatory view showing the positional relationship of the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 40 in the second modification of the first embodiment. In the second modification, the second multilayer ceramic capacitor 40 is employed in place of the second multilayer ceramic capacitor 30. The second multilayer ceramic capacitor 40 has a first external electrode 44 and a second external electrode 45, but the length thereof is longer than that of the second multilayer ceramic capacitor 30. The first external electrode 44 of the second modification is moved in the direction indicated by the arrow 6b, and is in a state in which it is positioned within the region Ar, as shown in (A) of FIG. 1. Figure 6 However, in the second modification, by lengthening the length of the second multilayer ceramic capacitor 40, an interval S is ensured between the second external electrode 15 of the first multilayer ceramic capacitor 10 and the second external electrode 45.

[0096] ((Third Modification))

[0097] Figure 6(D) is an explanatory view showing the positional relationship between the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 40' in the third modification of the first embodiment. In the third modification, the second multilayer ceramic capacitor 40' is employed instead of the second multilayer ceramic capacitor 30. The second multilayer ceramic capacitor 40' has the first external electrode 44' and the second external electrode 45', but its length is longer than that of the second multilayer ceramic capacitor 30. In addition, the length of the second multilayer ceramic capacitor 40' is longer than that of the second multilayer ceramic capacitor 40 of the second modification. This avoids occurrence of short circuit.

[0098] The first external electrode 44' of the third modification is further moved in the direction indicated by the arrow 6c than the first external electrode 44 shown in (C), and its outer end edge (outer end edge) is located to the left of the left end edge (left end edge) of the region Ar. However, in the third modification, by lengthening the length of the second multilayer ceramic capacitor 40', it is ensured that there is a gap S between the second external electrode 15 of the first multilayer ceramic capacitor 10 and the second external electrode 45', thereby avoiding occurrence of short circuit. Figure 6

[0099] In addition, in the third modification and the fourth modification, although the gap S2 is ensured by lengthening the length of the second multilayer ceramic capacitor, it is also possible to ensure the gap S2 by shortening the length of the external electrode.

[0100] [Effects]

[0101] In the present embodiment, even if the first multilayer ceramic capacitor 10 is tilted in either direction along the Y-axis direction, or the second multilayer ceramic capacitor 30 is tilted in either direction along the X-axis direction, it is possible to avoid contact between the two.

[0102] Thus, it is possible to set the height T

[10] of the first multilayer ceramic capacitor 10 and the height T

[30] of the second multilayer ceramic capacitor 30 to be large. In addition, it is possible to set the height of the second multilayer ceramic capacitor 40 of the third modification and the second multilayer ceramic capacitor 40' of the fourth modification to be large.

[0103] In the present embodiment, the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 are the same article, but the two are not necessarily the same article.

[0104] (Second Embodiment)

[0105] Next, referring to (A) and (B) of FIG. 10, the second embodiment will be described. Figure 7 Figure 7 ​​(B) to explain the second embodiment. The circuit board 120 of the second embodiment has the first multilayer ceramic capacitor 10, the second multilayer ceramic capacitor 30, and the flip-chip mounted electronic component 70. In addition, in the second embodiment, two second multilayer ceramic capacitors 30 are provided. The two second multilayer ceramic capacitors 30 are arranged in a state of being aligned in the length direction.

[0106] The electronic component 70 is arranged in a region of the second multilayer ceramic capacitor 30 along the width direction (X-axis direction) and in a region of the first multilayer ceramic capacitor 10 along the width direction (Y-axis direction). The electronic component 70 is arranged adjacent to the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30.

[0107] The electronic component 70 is covered with the insulating cover member. Therefore, even in a case where the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 are tilted toward the electronic component 70 on the side thereof, a short circuit does not occur between the first multilayer ceramic capacitor 10, the second multilayer ceramic capacitor 30, and the electronic component 70.

[0108] Therefore, it is possible to narrow the interval S3 between the first multilayer ceramic capacitor 10 and the electronic component 70 and the interval S4 between the second multilayer ceramic capacitor 30 and the electronic component 70. In addition, it is possible to set the height of the first multilayer ceramic capacitor 10 and the height of the second multilayer ceramic capacitor 30 to be higher. Further, from the viewpoint of high-density mounting, the intervals S3 and S4 are preferably 0.3 mm or less, and more preferably 0.2 mm or less.

[0109] (Third Embodiment)

[0110] Next, the third embodiment will be explained with reference to Figure 7 (C). The circuit board 130 of the third embodiment has the first multilayer ceramic capacitor 10, the second multilayer ceramic capacitor 30, and the electronic components 71, 72, and 73. The point that the two second multilayer ceramic capacitors 30 are arranged in a state of being aligned in the length direction is the same as in the second embodiment. The electronic component 71 is provided instead of the electronic component 70 of the second embodiment. In addition, the electronic component 72 is arranged in a region across the first multilayer ceramic capacitor 10 and one second multilayer ceramic capacitor 30, that is, in a region on the upper left side of the electronic component 71 in (C) of the second embodiment, with respect to the electronic component 71. The electronic component 73 is arranged in a region across the first multilayer ceramic capacitor 10, that is, in a region on the left side of the first multilayer ceramic capacitor 10 in (C) of the second embodiment, with respect to the electronic component 71. Figure 7 Figure 7

[0111] ​​As with the electronic component 70 of the embodiment, the electronic components 71, 72, 73 are covered with the insulating cover. Therefore, even in the case where the first stacked ceramic capacitor 10, the second stacked ceramic capacitor 30 are tilted toward the electronic component 71 side, the electronic component 72 side, and the electronic component 73 side located in the respective lateral directions, short-circuiting does not occur between the first stacked ceramic capacitor 10, the second stacked ceramic capacitor 30, and the electronic components 71, 72, 73.

[0112] Therefore, in Figure 7 (C) of FIG. 8, it is possible to reduce the interval S5 between the outer electrode of the second stacked ceramic capacitor 30 located on the left side and the electronic component 72, and the interval S6 between the two second stacked ceramic capacitors 30 and the electronic component 71. In addition, it is possible to reduce the interval S7 between the first stacked ceramic capacitor 10 and the electronic component 71, the interval S8 between the first stacked ceramic capacitor 10 and the electronic component 73, and the interval S9 between the first stacked ceramic capacitor 10 and the electronic component 72. Thus, it is possible to set the height of the first stacked ceramic capacitor 10 and the height of the second stacked ceramic capacitor 30 to be higher.

[0113] Further, the intervals S6 to S9 are preferably 0.3 mm or less, and more preferably 0.2 mm or less from the viewpoint of high-density mounting, as with the intervals S3, S4 in the second embodiment.

[0114] (Fourth Embodiment)

[0115] Next, the fourth embodiment will be described with reference to Figure 8 and Figure 9 In the fourth embodiment, the first stacked ceramic capacitor 50 is provided instead of the first stacked ceramic capacitor 10 of the first embodiment. In addition, although not shown, the second stacked ceramic capacitor 30 is also changed to a stacked ceramic capacitor similar to the first stacked ceramic capacitor 50. Hereinafter, the first stacked ceramic capacitor 50 will be mainly described.

[0116] Figure 8 is a view of the first stacked ceramic capacitor 50 cut along a line segment corresponding to the A1-A1 line in Figure 2 . That is, it is a view corresponding to the cross-sectional view of the first stacked ceramic capacitor 10 of the first embodiment cut at the A1-A1 line. Figure 9 (A) of FIG. 10 is a cross-sectional view of the first stacked ceramic capacitor 50 cut along a line segment corresponding to the A2-A2 line in Figure 2 . That is, it is a cross-sectional view corresponding to the A2-A2 cross-sectional view of the first stacked ceramic capacitor 10 of the first embodiment. Figure 9 (B) of FIG. 10 is a cross-sectional view of the first stacked ceramic capacitor 50 cut along a line segment corresponding to the A3-A3 line in Figure 2A3-A3 line in FIG. 6 is cut and a cross-sectional view is obtained. That is, a cross-sectional view corresponding to the A3-A3 cross-sectional view of the first multilayer ceramic capacitor 10 of the first embodiment. Further, in Figure 9 (B) of FIG. 6, the second external electrode 55 is omitted.

[0117] <Appearance>

[0118] The appearance of the first multilayer ceramic capacitor 50 is substantially the same as that of the first multilayer ceramic capacitor 10 of the first embodiment. That is, the first multilayer ceramic capacitor 50 has the ceramic main body 51, the first external electrode 54, and the second external electrode 55. The first external electrode 54 has the first face portion 54a, the second face portion (not shown), the third face portion (not shown), the fourth face portion 54d, and the fifth face portion 54e. The second external electrode 55 has the first face portion 55a, the second face portion (not shown), the third face portion (not shown), the fourth face portion 55d, and the fifth face portion 55e. In addition, the first multilayer ceramic capacitor 50 has the first main face M51, the first side face S51, and the like. These constituent elements are the same as the corresponding portions of the first multilayer ceramic capacitor 10 of the first embodiment, and thus detailed description thereof is omitted here.

[0119] The length, the width, and the height of the first multilayer ceramic capacitor 50 are not shown, but are respectively denoted as the length L

[50] , the width W

[50] , and the height T

[50] , as with the first multilayer ceramic capacitor 10 of the first embodiment. Moreover, the first multilayer ceramic capacitor 50 is a high back type in which the height T

[50] is greater than 1.3 times the width W

[50] . This is also the same as the first multilayer ceramic capacitor 10 of the first embodiment.

[0120] <Internal Structure>

[0121] Next, the internal structure of the first multilayer ceramic capacitor 50 in the second embodiment is described with reference to Figures 8-9 (B) of FIG. 6.

[0122] The ceramic main body 51 has a stacked portion 56 and a pair of cover portions 57. The stacked portion 56 has a capacitance forming portion 60 and a pair of edge portions 58. The capacitance forming portion 60 includes a plurality of first and second internal electrodes 52, 53 alternately stacked along the Y-axis direction with a plurality of ceramic layers 59. In the present embodiment, the internal electrodes 52, 53 and the ceramic layers 59 are each configured in a sheet shape extending along the X-Z plane. The internal electrodes 52, 53 are stacked along the Y-axis direction and face each other in a direction parallel to the mounting surface la, and thus the bonding area of each first internal electrode 52 with the first external electrode 54 and the bonding area of each second internal electrode 53 with the second external electrode 55 can be increased. Thus, a decrease in capacitance, so-called capacitance loss, caused by poor contact is suppressed. Note that the number of layers of the first internal electrodes 52 and the second internal electrodes 53 in each figure does not represent the actual number of layers.

[0123] The internal electrodes 52, 53 are alternately arranged along the Y-axis direction so as to face each other in the Y-axis direction. The internal electrodes 52 and 53 face each other in the Y-axis direction in a central region of the X-axis direction and the Z-axis direction. The first internal electrodes 52 correspond to a first group and are drawn out from the central region to one end surface E51 to be connected to the first external electrode 54. The second internal electrodes 53 correspond to a second group and are drawn out from the central region to the other end surface E52 to be connected to the second external electrode 55.

[0124] The internal electrodes 52, 53 contain a metal material as a main component. As the metal material, nickel (Ni) can be typically given, and in addition to this, copper (Cu), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), and alloys thereof, and the like can be given. The internal electrodes 52, 53 can contain a low-melting metal as in the internal electrodes 12, 13 in the first embodiment.

[0125] With such a structure, in the first stacked ceramic capacitor 50, if a voltage is applied between the external electrodes 54, 55, a voltage is applied to the plurality of ceramic layers 59 between the internal electrodes 52, 53 in the central region. Thus, in the second stacked ceramic capacitor 30, an electric charge corresponding to the voltage between the external electrodes 54, 55 is accumulated.

[0126] In the stacked portion 56, a dielectric ceramic having a high dielectric constant is used in order to increase the electrostatic capacitance of each ceramic layer 59 between the internal electrodes 52, 53. As the dielectric ceramic having a high dielectric constant, a material having a perovskite structure containing barium (Ba) and titanium (Ti), represented by barium titanate (BaTi03), can be given, for example.

[0127] In addition, the dielectric ceramic can also be a composition system of strontium titanate (SrTiO3), calcium titanate (CaTiO3), magnesium titanate (MgTiO3), calcium zirconate (CaZrO3), calcium zirconate titanate (Ca(Zr,Ti)O3), calcium barium zirconate titanate ((Ba,Ca)(Zr,Ti)O3), barium zirconate (BaZrO3), titanium oxide (TiO2), and the like. As with the first embodiment, a low-melting metal can be added to the dielectric ceramic.

[0128] A pair of covering portions 57 are formed along the Y-axis direction, covering the laminated portion 56 from the Z-axis direction. The covering portion 57 is also sometimes referred to as a protection layer in the height direction. The covering portion 57 is mounted on the surface of the laminated portion 56 that is perpendicular to the Z-axis. The covering portion 57 is composed of, for example, a laminate of ceramic sheets that extend along the X-Y plane. From the viewpoint of suppressing internal stress and the like, the dielectric ceramic that constitutes the covering portion 57 is preferably the same composition system as the ceramic layer 59.

[0129] A pair of edge portions 58 are formed along the Z-axis direction, covering the capacitance forming portion 60 from the Y-axis direction. The edge portion 58 is also sometimes referred to as a protection layer in the width direction. The edge portion 58 is formed of, for example, a ceramic sheet, and is composed of a sheet shape that extends along the X-Z plane. From the viewpoint of suppressing internal stress and the like, the dielectric ceramic that constitutes the edge portion 58 is preferably the same composition system as the ceramic layer 59.

[0130] In addition, the second laminated ceramic capacitor that is employed instead of the second laminated ceramic capacitor 30 is the same article as the first laminated ceramic capacitor 50, and thus detailed explanation thereof is omitted.

[0131] The first laminated ceramic capacitor 50 and the second laminated ceramic capacitor (not shown) described above are mounted on the substrate 1 in the same manner as the first laminated ceramic capacitor 10 and the second laminated ceramic capacitor 30 of the first embodiment shown in (A) and (B) of FIG. 1. Figure 1 Figure 1 The first laminated ceramic capacitor 10 and the second laminated ceramic capacitor 30 of the first embodiment shown in (A) and (B) of FIG. 1 are mounted on the substrate 1 in the same manner as the first laminated ceramic capacitor 50 and the second laminated ceramic capacitor (not shown) described above.

[0132] Thus, even if the first laminated ceramic capacitor 50 and the second laminated ceramic capacitor are tilted, contact of the external electrodes with each other can be avoided.

[0133] In addition, an electrostriction phenomenon sometimes occurs in the first laminated ceramic capacitor 50. The electrostriction phenomenon is a cause of so-called ringing (whistling). However, the laminated direction of the internal electrodes 52, 53 in the first laminated ceramic capacitor 50 is the width direction, which is a direction orthogonal to the mounting direction, i.e., the Z-axis direction. Thus, ringing is suppressed in the first laminated ceramic capacitor 50. The ringing caused by the electrostriction phenomenon is also similarly suppressed in the second laminated ceramic capacitor.

[0134] ​In the present embodiment, the first stacked ceramic capacitor 50 and the second stacked ceramic capacitor are used as the same components, but one of them can be replaced with, for example, the first stacked ceramic capacitor 10 of the first embodiment.

[0135] (Fifth Embodiment)

[0136] Next, the fifth embodiment will be described. The fifth embodiment differs from the first embodiment in the following aspects. Referring to Figure 10 , a state in which the ceramic main body portion of the first stacked ceramic capacitor is disassembled is shown. The fifth embodiment has the first internal electrode 12 and the second internal electrode 13 as in the first embodiment, but the shapes thereof are different. Further, the other portions are not different from those of the first embodiment, and thus the fifth embodiment will be described with appropriate reference to the drawings used for the description of the first embodiment in the following description. In addition, in the description, the same reference numerals are used for the constituent elements common to the first embodiment.

[0137] As shown in (A) of FIG. 10, Figure 5 the first internal electrode 12 included in the first group is connected to the first external electrode 14, and the second internal electrode 13 included in the second group is connected to the second external electrode 15.

[0138] Returning again to Figure 10 , the first internal electrode 12 of the present embodiment has a connection end portion 12a connected to the first external electrode 14, and an open end portion 12b located on the opposite side of the connection end portion 12a. A cutout portion 12a2 is provided at the connection end portion 12a, thereby forming a narrow portion 12al. The width of the narrow portion 12al is smaller than the width dimension on the side closer to the open end portion 12b than the connection end portion 12a. That is, the dimension of the narrow portion 12al in the direction of the width direction of the first stacked ceramic capacitor 10 is smaller than the dimension of the open end portion 12b in the direction of the width direction of the first stacked ceramic capacitor 10. The same is true in the second stacked ceramic capacitor 30.

[0139] Similarly, the second internal electrode 13 of the present embodiment has a connection end portion 13a connected to the second external electrode 15, and an open end portion 13b located on the opposite side of the connection end portion 13a. A cutout portion 13a2 is provided at the connection end portion 13a, thereby forming a narrow portion 13al. The width of the narrow portion 13al is smaller than the width dimension on the side closer to the open end portion 13b than the connection end portion 13a. That is, the dimension of the narrow portion 13al in the direction of the width direction of the first stacked ceramic capacitor 10 is smaller than the dimension of the open end portion 13b in the direction of the width direction of the first stacked ceramic capacitor 10. The same is true in the second stacked ceramic capacitor 30.

[0140] By adopting such a structure, for example, in the case where the internal electrodes 12, 13 are composed of Ni and the external electrodes 14, 15 are composed of Cu, it is possible to suppress the expansion of the internal electrodes 12, 13 due to the diffusion of Cu of the external electrodes 14, 15, and the generation of cracks at the corner portions of the first multilayer ceramic capacitor. In particular, even in the case where a low-melting metal is added to the internal electrodes 12, 13, the dielectric ceramic as explained in the first embodiment, it is possible to avoid the expansion of the internal electrodes 12, 13 and suppress the generation of cracks.

[0141] In such a fifth embodiment, the external appearance shape, the dimensional relationship and the positional relationship of the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 in the first embodiment are also maintained. Therefore, in the fifth embodiment, it is also possible to suppress the short circuit between the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 as in the first embodiment.

[0142] In addition, in the present embodiment, the first multilayer ceramic capacitor and the second multilayer ceramic capacitor are the same article. That is, the internal electrodes of both ceramic capacitors have the narrow-width portions. In contrast, it is also possible that only one of the internal electrodes of the first multilayer ceramic capacitor and the second multilayer ceramic capacitor has the narrow-width portion.

[0143] ((Modified Example))

[0144] Next, a modified example of the fifth embodiment will be explained. The fifth embodiment is an embodiment that maintains the basic form of the first embodiment and changes the shape of the internal electrodes 12, 13. In contrast, the modified example is an embodiment that maintains the basic form of the fourth embodiment and changes the shape of the internal electrodes 52, 53.

[0145] Referring to Figure 11 , a state in which the ceramic main body portion of the first multilayer ceramic capacitor 80 (refer to Figure 12 ) is disassembled is shown. The first multilayer ceramic capacitor 80 corresponds to the first multilayer ceramic capacitor 50 in the fourth embodiment. In the modified example, the second multilayer ceramic capacitor also adopts the same multilayer ceramic capacitor as the first multilayer ceramic capacitor 80.

[0146] The modified example has the first internal electrode 52 and the second internal electrode 53 as in the fourth embodiment, but the shapes thereof are different. Further, the other portions are not different from those of the fourth embodiment, and therefore, in the following explanation, the modified example of the fifth embodiment will be explained with appropriate reference to the drawings used for explaining the fourth embodiment. In addition, in the explanation, the same reference numerals are used for the constituent elements common to the fourth embodiment.

[0147] Although not shown, the first internal electrode 52 included in the first group is connected to the first external electrode 54. Also, as shown in (A) of FIG. 10, the second internal electrode 53 included in the second group is connected to the second external electrode 55. Figure 9

[0148] Returning again to FIG. 10, Figure 11 The first internal electrode 52 of this modification example has a connection end portion 52a connected to the first external electrode 54 and an open end portion 52b located on the opposite side of the connection end portion 52a. A cutout portion 52a2 is provided at the connection end portion 52a, thereby forming a narrow portion 52al. The width of the narrow portion 52al is smaller than the width dimension on the side closer to the open end portion 52b than the connection end portion 52a. That is, the dimension of the narrow portion 52al in the direction of the height of the first multilayer ceramic capacitor 80 is smaller than the dimension of the open end portion 52b in the direction of the height of the first multilayer ceramic capacitor 80. Further, the width dimension of the first internal electrode 52 is the dimension in the Z-axis direction.

[0149] Similarly, the second internal electrode 53 of this modification example has a connection end portion 53a connected to the second external electrode 55 and an open end portion 53b located on the opposite side of the connection end portion 53a. A cutout portion 53a2 is provided at the connection end portion 53a, thereby forming a narrow portion 53al. The width of the narrow portion 53al is smaller than the width dimension on the side closer to the open end portion 53b than the connection end portion 53a. That is, the dimension of the narrow portion 53al in the direction of the height of the first multilayer ceramic capacitor 80 is smaller than the dimension of the open end portion 53b in the direction of the height of the first multilayer ceramic capacitor 80. The width dimension of the second internal electrode 53 is also the dimension in the Z-axis direction.

[0150] By adopting such a structure, for example, in the case where the internal electrodes 52, 53 are composed of Ni and the external electrodes 54, 55 are composed of Cu, it is possible to suppress the expansion of the internal electrodes 52, 53 due to the diffusion of Cu of the external electrodes 54, 55, and the generation of cracks at the corners of the first multilayer ceramic capacitor 90. In particular, even in the case where a low-melting-point metal is added to the internal electrodes 52, 53 or the dielectric ceramic as explained in the third embodiment, it is possible to avoid the expansion of the internal electrodes 12, 13 and suppress the generation of cracks.

[0151] In this modification example, the external appearance shape of the first multilayer ceramic capacitor 50, the dimensional and positional relationships thereof in the fourth embodiment are also maintained. Therefore, in the modification example, as well as in the fourth embodiment, the short circuit between the first multilayer ceramic capacitor and the second multilayer ceramic capacitor is suppressed.

[0152] ​In addition, in the present embodiment, the first multilayer ceramic capacitor and the second multilayer ceramic capacitor are the same article. That is, the internal electrodes of both ceramic capacitors have the narrow-width portions. In contrast, only one of the internal electrodes of the first multilayer ceramic capacitor and the second multilayer ceramic capacitor can have the narrow-width portion.

[0153] In addition, the present specification discloses various multilayer ceramic capacitors in which the stacking direction of the internal electrodes and the shape of the internal electrodes are different. These multilayer ceramic capacitors can be appropriately combined and used.

[0154] Embodiment

[0155] (Embodiment)

[0156] Next, the embodiment is described together with the comparative example. In the circuit board 110 of the first embodiment, the dimensions of each part of the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 are set to the values shown below. As for the combination of the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30, five types, Modes 1 to 5, are prepared.

[0157] The comparative example is described below. Figure 13 (A) and Figure 13 (B) of FIG. 10 are a mode in which the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 are arranged along the Y-axis direction. At this time, the positions of the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 along the X-axis direction are identical. That is, the first external electrode 14 of the first multilayer ceramic capacitor 10 and the first external electrode 34 of the second multilayer ceramic capacitor 30 become adjacent in the Y-axis direction. The second external electrode 15 of the first multilayer ceramic capacitor 10 and the second external electrode 35 of the second multilayer ceramic capacitor 30 become adjacent in the Y-axis direction. The interval S is provided between the first external electrode 14 and the first external electrode 34 and between the second external electrode 15 and the second external electrode 35.

[0158] <Mode 1>

[0159] First multilayer ceramic capacitor 10:

[0160] Length L

[10] : 0.6 mm, width W

[10] : 0.3 mm, height T

[10] : 0.4 mm

[0161] Second multilayer ceramic capacitor 30:

[0162] The first multilayer ceramic capacitor and the second multilayer ceramic capacitor are the same article, and the dimensions are also the same.

[0163] Interval S1:

[0164] 0.1 mm

[0165] When the first stacked ceramic capacitor 10 is tilted by 30°, the distance by which the upper edge thereof approaches the second external electrode 35 of the second stacked ceramic capacitor 30:

[0166] Height T

[10] x cos 60° = 0.4 mm x 0.5 = 0.2 mm

[0167] Interval S2:

[0168] 0.3 mm

[0169] T

[10] / W

[10] in Mode 1 is approximately 1.33, satisfying the condition of the first stacked ceramic capacitor 10 of the first embodiment that T

[10] is more than 1.3 times W

[10] . The second stacked ceramic capacitor 30 also satisfies the condition. In addition, the interval S2 is greater than the height T

[10] x cos 60° = 0.2 mm.

[0170] <Mode 2>

[0171] First stacked ceramic capacitor 10:

[0172] Length L

[10] : 0.4 mm, width W

[10] : 0.2 mm, height T

[10] : 0.3 mm

[0173] Second stacked ceramic capacitor 30:

[0174] The same as in Mode 1.

[0175] Interval S1:

[0176] The same as in Mode 1.

[0177] When the first stacked ceramic capacitor 10 is tilted by 30°, the distance by which the upper edge thereof approaches the second external electrode 35 of the second stacked ceramic capacitor 30:

[0178] Height T

[10] x cos 60° = 0.3 mm x 0.5 = 0.15 mm

[0179] Interval S2:

[0180] 0.2 mm.

[0181] T

[10] / W

[10] in Mode 2 is 1.5, satisfying the condition of the first stacked ceramic capacitor 10 that T

[10] is more than 1.3 times W

[10] , and further more than 1.5 times. The second stacked ceramic capacitor 30 satisfies the condition of the second stacked ceramic capacitor 30 of the first embodiment that T

[30] is more than 1.3 times W

[30] . In addition, the interval S2 is greater than the height T

[10] x cos 60° = 0.15 mm.

[0182] <Mode 3>

[0183] First stacked ceramic capacitor 10:

[0184] Length L

[10] : 0.6 mm, width W

[10] : 0.3 mm, height T

[10] : 0.5 mm

[0185] Second stacked ceramic capacitor 30:

[0186] Same as Mode 1.

[0187] Interval S1:

[0188] Same as Mode 1.

[0189] Distance by which the upper edge of the first stacked ceramic capacitor 10 approaches the second external electrode 35 of the second stacked ceramic capacitor 30 when the first stacked ceramic capacitor 10 is tilted by 30°:

[0190] Height T

[10] x cos 60° = 0.5 mm x 0.5 = 0.25 mm

[0191] Interval S2:

[0192] Same as Mode 1.

[0193] T

[10] / W

[10] in Mode 3 is approximately 1.67, satisfying the condition of the first stacked ceramic capacitor 10 in which T

[10] is 1.3 times or more, and further 1.5 times or more of W

[10] . The second stacked ceramic capacitor 30 satisfies the condition of the second stacked ceramic capacitor 30 of the first embodiment in which T

[30] is 1.3 times or more of W

[30] . In addition, the interval S2 is greater than the height T

[10] x cos 60° = 0.25 mm.

[0194] <Mode 4>

[0195] First stacked ceramic capacitor 10:

[0196] Length L

[10] : 1.0 mm, width W

[10] : 0.5 mm, height T

[10] : 0.7 mm

[0197] Second stacked ceramic capacitor 30:

[0198] Same as Mode 1.

[0199] Interval S1:

[0200] Same as Mode 1.

[0201] Distance by which the upper edge of the first stacked ceramic capacitor 10 approaches the second external electrode 35 of the second stacked ceramic capacitor 30 when the first stacked ceramic capacitor 10 is tilted by 30°:

[0202] Height T

[10] x cos 60° = 0.7 mm x 0.5 = 0.35 mm

[0203] Interval S2:

[0204] 0.5 mm

[0205] T

[10] / W

[10] in Mode 4 is approximately 1.4, satisfying the condition of the first stacked ceramic capacitor 10 that T

[10] is 1.3 times or more of W

[10] . The second stacked ceramic capacitor 30 satisfies the condition of the second stacked ceramic capacitor 30 of the first embodiment that T

[30] is 1.3 times or more of W

[30] . In addition, the interval S2 is greater than the height T

[10] x cos 60° = 0.35 mm.

[0206] <Mode 5>

[0207] First stacked ceramic capacitor 10:

[0208] Length L

[10] : 1.0 mm, width W

[10] : 0.5 mm, height T

[10] : 0.8 mm

[0209] Second stacked ceramic capacitor 30:

[0210] The same as the first stacked ceramic capacitor, and the dimensions are also the same.

[0211] Interval S1:

[0212] The same as Mode 1.

[0213] When the first stacked ceramic capacitor 10 is inclined by 30°, the distance by which the upper edge thereof approaches the second external electrode 35 of the second stacked ceramic capacitor 30:

[0214] Height T

[10] x cos 60° = 0.8 mm x 0.5 = 0.4 mm

[0215] Interval S2:

[0216] 0.5 mm

[0217] T

[10] / W

[10] in Mode 4 is 1.6, satisfying the condition of the first stacked ceramic capacitor 10 that T

[10] is 1.3 times or more, and further 1.5 times or more, of W

[10] . The second stacked ceramic capacitor 30 satisfies the condition of the second stacked ceramic capacitor 30 of the first embodiment that T

[30] is 1.3 times or more of W

[30] . In addition, the interval S2 is greater than the height T

[10] x cos 60° = 0.4 mm.

[0218] <Comparative Example>

[0219] First stacked ceramic capacitor 10:

[0220] Length L

[10] : 0.6mm, Width W

[10] : 0.3mm, Height T

[10] : 0.4mm

[0221] Interval S:

[0222] 0.1mm

[0223] In the comparative example, T

[10] / W

[10] is approximately 1.33, which satisfies the condition that T

[10] is more than 1.3 times W

[10] of the first stacked ceramic capacitor 10 of the first embodiment.

[0224] [Experimental Methods]

[0225] For Examples 1-5 and Comparative Examples, a predetermined number of samples were prepared. Then, samples from which it was determined that the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 were tilted were extracted. For the extracted samples, a voltage was applied between the first terminal 4a and the second terminal 4b for testing to confirm whether a short circuit had occurred.

[0226] [Experimental Results]

[0227] In all four of the embodiments, no short circuit was detected in any of the samples.

[0228] In the comparative examples, samples exhibiting short circuits were confirmed. In such samples, tilting of the first-layer ceramic capacitor 10 was confirmed. In the comparative examples, such as... Figure 14 (A) and Figure 14 As shown in (B), if at least one of the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 is tilted close to each other, the first external electrode 14 contacts the first external electrode 34, and the second external electrode 15 contacts the second external electrode 35. This results in a short circuit.

[0229] Thus, according to this embodiment, when T

[10] is 1.3 times or more than W

[10] , and even when T

[10] is 1.5 times or more than W

[10] , the occurrence of short circuits can be suppressed.

[0230] Regarding the second to fifth embodiments and their variations, the external shape of the first multilayer ceramic capacitor 10, its dimensional relationship with the second multilayer ceramic capacitor 30, and their positional relationship are maintained in the first embodiment. Therefore, it is believed that short circuits can be suppressed in the same way in any embodiment.

[0231] Furthermore, the above embodiments have been described as examples of multilayer ceramic electronic components, but are not limited thereto. For example, the structures of the above embodiments can also be applied to other multilayer ceramic electronic components such as rheostats and thermistors.

[0232] The above embodiments are merely examples for implementing the present invention, and the present invention is not limited thereto. Various modifications to these embodiments are within the scope of the present invention, and other various embodiments can be implemented within the scope of the present invention, as is evident from the foregoing description.

[0233] Explanation of reference numerals in the attached figures

[0234] 1……Printed wiring board, 2a……First pad, 2b……Second pad, 2c……Third pad, 2d……Fourth pad, 3……Solder seam, 10, 50, 80……First layer ceramic capacitor, 11, 31, 51……Ceramic body, M11, M51……First main surface, M12……Second main surface, E11……First end face, E12……Second end face, S11, S51……First side face, S12……Second side face, 12, 13, 52, 53, 92, 93……Internal electrode, 14, 34, 54……First external electrode, 15, 35, 55……Second external electrode, 16, 60……Capacitor forming part, 17, 57……Covering part, 18, 58……Edge part, 19, 59……Ceramic layer, 20, 56……Layer part, 30, 40, 40'……Second layer ceramic capacitor, 110, 120, 130……Circuit board.

Claims

1. A circuit board, characterized by, Comprising: a substrate provided with a first axis perpendicular to a mounting surface, and a second axis and a third axis each orthogonal to the first axis and to each other; and a plurality of multilayer ceramic electronic components mounted to the mounting surface, a first multilayer ceramic electronic component included in the plurality of multilayer ceramic electronic components is mounted to the mounting surface in a state in which a height direction coincides with a direction along the first axis, a width direction coincides with a direction along the second axis, and a length direction coincides with a direction along the third axis, and has a first external electrode having a prescribed length in the length direction at one end portion in the length direction, and a second external electrode having a prescribed length in the length direction at the other end portion in the length direction, a second multilayer ceramic electronic component included in the plurality of multilayer ceramic electronic components is mounted to the mounting surface in a manner in which a height direction coincides with a direction along the first axis, and a length direction coincides with a direction along the second axis, and a width direction coincides with a direction along the third axis, and has a first external electrode having a prescribed length in the length direction at one end portion in the length direction, and a second external electrode having a prescribed length in the length direction at the other end portion in the length direction, a height dimension of the first multilayer ceramic electronic component is 1.3 times or more of a width dimension or a length dimension of the first multilayer ceramic electronic component, and a height dimension of the second multilayer ceramic electronic component is 1.3 times or more of a width dimension of the second multilayer ceramic electronic component, the first multilayer ceramic electronic component and the second multilayer ceramic electronic component are arranged adjacent to the mounting surface in a state in which the length directions thereof are orthogonal, and a region in which a range occupied in the width direction of the first multilayer ceramic electronic component extends in the length direction of the first multilayer ceramic electronic component overlaps with one of the first external electrode and the second external electrode possessed by the second multilayer ceramic electronic component.

2. The circuit board according to claim 1, characterized in that: a separation in a direction along the second axis of the first external electrode and the second external electrode of the first multilayer ceramic electronic component from the other of the first external electrode and the second external electrode possessed by the second multilayer ceramic electronic component is greater than 0.5 times a height dimension of the first multilayer ceramic electronic component.

3. The circuit board according to claim 1, characterized in that: in a region located laterally along the second axis direction of the first multilayer ceramic electronic component, and in the third axis direction of the second multilayer ceramic electronic component, other electronic components are mounted which are arranged adjacent to the first multilayer ceramic electronic component and the second multilayer ceramic electronic component, and are covered by an insulating cover.

4. The circuit board according to claim 1, characterized in that: In a region of the second multilayer ceramic electronic component in the direction of the second axis, and on a side of the first multilayer ceramic electronic component in the direction of the third axis, other electronic components are mounted which are arranged adjacent to the first and second multilayer ceramic electronic components and are covered by an insulating cover.

5. The circuit board according to any one of claims 1 to 4, characterized in that: at least one of a height dimension of the first multilayer ceramic electronic component and a height dimension of the second multilayer ceramic electronic component is 1.5 times or more of a respective width dimension or length dimension.

6. The circuit board according to claim 1, characterized in that: at least one of an internal electrode provided in a ceramic main body of the first multilayer ceramic electronic component and an internal electrode provided in a ceramic main body of the second multilayer ceramic electronic component is laminated in a direction opposite in a respective height direction.

7. The circuit board according to claim 6, characterized in that: the internal electrodes laminated in the direction of the height direction include a first internal electrode connected to the first external electrode, and a second internal electrode connected to the second external electrode, the first internal electrode has a connection end portion connected to the first external electrode and an open end portion on an opposite side of the connection end portion, the connection end portion having a narrow portion with a dimension in the width direction smaller than a dimension of the open end portion in the width direction, the second internal electrode has a connection end portion connected to the second external electrode and an open end portion on an opposite side of the connection end portion, the connection end portion having a narrow portion with a dimension in the width direction smaller than a dimension of the open end portion in the width direction.

8. The circuit board according to claim 1, characterized in that: at least one of an internal electrode provided in a ceramic main body of the first multilayer ceramic electronic component and an internal electrode provided in a ceramic main body of the second multilayer ceramic electronic component is laminated in a direction opposite in a respective width direction.

9. The circuit board according to claim 8, characterized in that: the internal electrodes laminated in the direction of the width direction include a first internal electrode connected to the first external electrode, and a second internal electrode connected to the second external electrode, the first internal electrode has a connection end portion connected to the first external electrode and an open end portion on an opposite side of the connection end portion, the connection end portion having a narrow portion with a dimension in the height direction smaller than a dimension of the open end portion in the height direction, the second internal electrode has a connection end portion connected to the second external electrode and an open end portion on an opposite side of the connection end portion, the connection end portion having a narrow portion with a dimension in the height direction smaller than a dimension of the open end portion in the height direction.

10. The circuit board according to claim 7 or 9, characterized in that: a low-melting metal is contained in the internal electrode or a dielectric layer formed between the internal electrodes.

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