Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a transistor having low parasitic capacitance. Also provided is a semiconductor device having excellent electrical characteristics. The semiconductor device includes a transistor in which a source electrode and a drain electrode are located at different heights, and an insulating layer disposed between the source electrode and the drain electrode, the insulating layer having a first opening to one of the source electrode and the drain electrode, the other one of the source electrode and the drain electrode is arranged on the insulating layer and provided with a second opening overlapped with the first opening, the semiconductor layer is provided with an area arranged in the first opening, a gate insulating layer and a gate electrode are sequentially arranged on the semiconductor layer, and the gate electrode is of a two-layer structure. An end portion of a lower layer of the gate electrode overlaps the other one of the source electrode and the drain electrode, an upper layer of the gate electrode has a first region extending outside the end portion of the lower layer, and a gap is provided between the first region and the other one of the source electrode and the drain electrode.

Description

TECHNICAL FIELD

[0001] One embodiment of the present application relates to a semiconductor device, a memory device, a display device, and an electronic device. Note that one embodiment of the present application relates to a method for manufacturing a semiconductor device.

[0002] Note that one embodiment of the present application is not limited to the technical field described above. Examples of a technical field to which one embodiment of the present application pertains are a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (e.g., a touch sensor), an input-output device (e.g., a touch panel), and a driving method or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device generally means a device that utilizes semiconductor characteristics and includes a circuit including a semiconductor element (a transistor, a diode, a photodiode, and the like) and a device including the circuit. Furthermore, a semiconductor device means all devices that can function by utilizing semiconductor characteristics. For example, a semiconductor device includes an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is mounted in a package. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device themselves are semiconductor devices, and each include a semiconductor device in some cases. BACKGROUND

[0004] In recent years, development of semiconductor devices has been advanced, and LSIs, CPUs, memories, and the like are mainly used for semiconductor devices. A CPU is a collection of semiconductor integrated circuits (at least including transistors and memories) and semiconductor elements each of which is formed with an electrode serving as a connection terminal, which are processed into chips from semiconductor wafers.

[0005] Semiconductor circuits (IC chips) of LSIs, CPUs, memories, and the like are mounted on circuit boards, e.g., printed wiring boards, and used as one of components of various electronic devices.

[0006] Furthermore, a technique for forming a transistor using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. The transistor is widely applied to electronic devices such as integrated circuits (ICs), display devices, and the like. As a semiconductor thin film which can be used for a transistor, a silicon-based semiconductor material is widely known. As another material, an oxide semiconductor has attracted attention.

[0007] In addition, it is known that a transistor using an oxide semiconductor has extremely small off-state current. For example, Patent Document 1 has disclosed a low-power CPU and the like which utilizes the characteristic of small off-state current of a transistor using an oxide semiconductor. In addition, for example, Patent Document 2 has disclosed a memory device and the like which utilizes the characteristic of small off-state current of a transistor using an oxide semiconductor to achieve long-term retention of stored contents.

[0008] In recent years, with the miniaturization and weight reduction of electronic devices, further high-density integration of integrated circuits is required. In addition, productivity of semiconductor devices including integrated circuits is required to be improved. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique in which a plurality of memory cells are provided in a stacked manner by using a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film, whereby the density of an integrated circuit is increased. In addition, in Patent Document 4, a technique in which channels of transistors using an oxide semiconductor film are arranged in a longitudinal direction to achieve high-density integration of integrated circuits is also disclosed. [Prior Art Documents] [Patent Documents]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187 [Patent Document 2] Japanese Patent Application Publication No. 2011-151383 [Patent Document 3] International Patent Application Publication No. 2021 / 053473 [Patent Document 4] Japanese Patent Application Publication No. 2013-211537 [Non-Patent Documents]

[0010] [Non-Patent Document 1] M. Oota et. al, “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72 nm”, IEDM Tech. Dig., 2019, pp. 50-53 SUMMARY PROBLEMS TO BE SOLVED BY THE INVENTION

[0011] One of objects of one embodiment of the present application is to provide a transistor with small parasitic capacitance. Furthermore, one of objects of one embodiment of the present application is to provide a transistor with good electric characteristics. Furthermore, one of objects of one embodiment of the present application is to provide a transistor with large on-state current. Furthermore, one of objects of one embodiment of the present application is to provide a transistor, a semiconductor device, or a memory device which can be miniaturized or highly integrated. Furthermore, one of objects of one embodiment of the present application is to provide a display device with high definition or high aperture ratio. Furthermore, one of objects of one embodiment of the present application is to provide a transistor, a semiconductor device, a display device, or a memory device with high reliability. Furthermore, one of objects of one embodiment of the present application is to provide a semiconductor device, a display device, or a memory device with low power consumption. Furthermore, one of objects of one embodiment of the present application is to provide a memory device with high operation speed. Furthermore, one of objects of one embodiment of the present application is to provide a method for manufacturing the above transistor, semiconductor device, display device, or memory device.

[0012] Note that the description of these objects does not preclude the existence of other objects. One embodiment of the present application does not necessarily achieve all the above objects. An object other than the above objects can be extracted from the description of the specification, the attached drawings, and the claims. Means for solving the technical problem

[0013] One embodiment of the present application is a semiconductor device including a first transistor and a first insulating layer, the first transistor including a first conductive layer, a second conductive layer, a semiconductor layer, a gate insulating layer, and a gate electrode, the first conductive layer being one of a source electrode and a drain electrode of the first transistor, the second conductive layer being the other of the source electrode and the drain electrode of the first transistor, the first conductive layer and the second conductive layer being located at different levels, the first insulating layer being provided between the first conductive layer and the second conductive layer and having a first opening reaching the first conductive layer, the second conductive layer having a second opening overlapping with the first opening, the second conductive layer being provided over the first insulating layer, the semiconductor layer having a region in contact with a top surface of the first conductive layer in the first opening, a side surface of the first insulating layer in the first opening, a side surface of the second conductive layer in the second opening, and a top surface of the second conductive layer, the gate insulating layer being provided in contact with the semiconductor layer, the gate electrode being provided over the gate insulating layer so as to have a region overlapping with the semiconductor layer, the gate electrode including a third conductive layer and a fourth conductive layer stacked over the third conductive layer, an end portion of the third conductive layer being located in the region overlapping with the second conductive layer, the fourth conductive layer having a region extending outside the end portion of the third conductive layer, and a gap being formed between the region of the fourth conductive layer extending outside the end portion of the third conductive layer and the second conductive layer.

[0014] In the above structure, the relative dielectric constant of the gap is preferably greater than or equal to 0.8 and less than or equal to 1.2.

[0015] In addition, one embodiment of the present application is a semiconductor device including a first transistor, a first insulating layer, and a second insulating layer, the first transistor including a first conductive layer, a second conductive layer, a semiconductor layer, a gate insulating layer, and a gate electrode, the first conductive layer being one of a source electrode and a drain electrode of the first transistor, the second conductive layer being the other of the source electrode and the drain electrode of the first transistor, the first conductive layer and the second conductive layer being positioned at different levels, the first insulating layer being provided between the first conductive layer and the second conductive layer and having a first opening reaching the first conductive layer, the second conductive layer having a second opening overlapping with the first opening, the second conductive layer being provided over the first insulating layer, the semiconductor layer having a region in contact with a top surface of the first conductive layer in the first opening, a side surface of the first insulating layer in the first opening, a side surface of the second conductive layer in the second opening, and a top surface of the second conductive layer, the gate insulating layer being provided in contact with the semiconductor layer, the gate electrode being provided over the gate insulating layer so as to have a region overlapping with the semiconductor layer, the gate electrode including a third conductive layer and a fourth conductive layer stacked over the third conductive layer, an end portion of the third conductive layer being positioned in the region overlapping with the second conductive layer, the fourth conductive layer having a region extending outside the end portion of the third conductive layer, the second insulating layer covering a top surface and a side surface of the fourth conductive layer, and the second insulating layer having a region covering a bottom surface of the fourth conductive layer in the region where the fourth conductive layer extends outside the end portion of the third conductive layer.

[0016] In the above structure, it is preferable that the fourth conductive layer have the region extending outside the end portion of the third conductive layer between the second conductive layer and the second insulating layer. Alternatively, in the above structure, the third conductive layer is preferably one selected from the group consisting of tantalum nitride, titanium nitride, ruthenium nitride, a nitride containing molybdenum, a nitride containing tungsten, titanium, and aluminum, and a nitride containing tantalum and aluminum.

[0017] In the above structure, it is preferable that the third conductive layer be one selected from the group consisting of tantalum nitride, titanium nitride, ruthenium nitride, a nitride containing molybdenum, a nitride containing tungsten, titanium, and aluminum, and a nitride containing tantalum and aluminum, and that the fourth conductive layer be tungsten.

[0018] Further, one embodiment of the present application is a method for manufacturing a semiconductor device, including the steps of: forming a first insulating layer over a first conductive layer; forming a second conductive layer over the first insulating layer; forming a first opening reaching the first conductive layer by removing part of the second conductive layer and part of the first insulating layer, exposing a top surface of the first conductive layer; forming a first semiconductor layer so as to be in contact with a top surface of the first semiconductor layer and a top surface of the first insulating layer; forming a second insulating layer over the second insulating layer; sequentially stacking a third conductive layer and a fourth conductive layer over the second insulating layer; forming a first mask by a photolithography method; removing part of the fourth conductive layer using the first mask to form a fifth conductive layer; forming a sixth conductive layer by removing part of the third conductive layer using the fifth conductive layer as a mask; removing part of the third conductive layer by wet etching; and removing part of the fourth conductive layer by dry etching.

[0019] Further, in the above structure, it is preferable that a region of the fifth conductive layer which extends outside an end portion of the sixth conductive layer be formed by removing part of the third conductive layer, that a third insulating layer be formed after formation of the sixth conductive layer so as to be in contact with a top surface of the fifth conductive layer, a side surface of the fifth conductive layer, and a top surface of the second insulating layer, and that the third insulating layer be provided in the region of the fifth conductive layer which extends outside the end portion of the sixth conductive layer so as to have a region in contact with a bottom surface of the fifth conductive layer. Effects of Invention

[0020] According to one embodiment of the present application, a transistor with small parasitic capacitance can be provided. Further, according to one embodiment of the present application, a transistor with favorable electrical characteristics can be provided. Further, according to one embodiment of the present application, a transistor with large on-state current can be provided. Further, according to one embodiment of the present application, a transistor, a semiconductor device, or a memory device which can be miniaturized or highly integrated can be provided. Further, according to one embodiment of the present application, a display device with high definition or high aperture ratio can be provided. Further, according to one embodiment of the present application, a transistor, a semiconductor device, a display device, or a memory device with high reliability can be provided. Further, according to one embodiment of the present application, a semiconductor device, a display device, or a memory device with low power consumption can be provided. Further, according to one embodiment of the present application, a memory device with high operation speed can be provided. Further, according to one embodiment of the present application, a method for manufacturing a transistor, a semiconductor device, a display device, or a memory device can be provided.

[0021] Note that the description of these effects does not preclude the presence of other effects. One embodiment of the present application does not necessarily achieve all of the effects described above. Other effects inherent to the present application can be extracted from the description, the drawings, and the like. BRIEF DESCRIPTION OF DRAWINGS

[0022] FIG. 1A is a plan view showing one example of a semiconductor device. FIG. 1B and FIG. 1C is a cross-sectional view showing one example of a semiconductor device. FIG. 2A and FIG. 2C is a cross-sectional view showing one example of a semiconductor device. FIG. 2B is a plan view showing one example of a semiconductor device. FIG. 3A and FIG. 3B is a cross-sectional view showing one example of a semiconductor device. FIG. 4A and FIG. 4B is a cross-sectional view showing one example of a semiconductor device. FIG. 5A to FIG. 5C is a cross-sectional view showing one example of a manufacturing method of a semiconductor device. FIG. 6A to FIG. 6C is a cross-sectional view showing one example of a manufacturing method of a semiconductor device. FIG. 7A to FIG. 7C is a cross-sectional view showing one example of a manufacturing method of a semiconductor device. FIG. 8A and FIG. 8B is a cross-sectional view showing one example of a semiconductor device. FIG. 9A and FIG. 9B is a cross-sectional view showing one example of a semiconductor device. FIG. 10A is a plan view showing one example of a storage device. FIG. 10B and FIG. 10C is a cross-sectional view showing one example of a storage device. FIG. 11A is a plan view showing one example of a storage device. FIG. 11B is a cross-sectional view showing one example of a storage device. FIG. 12 is a cross-sectional view showing one example of a storage device. FIG. 13 is a cross-sectional view showing one example of a storage device. FIG. 14 is a block diagram showing one example of a structure of a semiconductor device. FIG. 15A to FIG. 15H is a diagram showing one example of a circuit structure of a memory cell. FIG. 16A and FIG. 16B is a perspective view showing one example of a structure of a semiconductor device. FIG. 17is a block diagram illustrating a CPU. FIG. 18A and FIG. 18B is a perspective view of a semiconductor device. FIG. 19A and FIG. 19B is a perspective view of a semiconductor device. FIG. 20A and FIG. 20B is a diagram showing a hierarchy of various storage devices. FIG. 21A and FIG. 21B is a perspective view showing one example of a display device. FIG. 22 is a cross-sectional view showing one example of a display device. FIG. 23 is a cross-sectional view showing one example of a display device. FIG. 24A to FIG. 24C is a diagram showing a structure example of a display device. FIG. 25A and FIG. 25B is a diagram showing one example of an electronic component. FIG. 26A to FIG. 26C is a diagram showing one example of a large computer. FIG. 26D is a diagram showing one example of a space device. FIG. 26E is a diagram showing one example of a storage system which can be used for a data center. FIG. 27A to FIG. 27F is a diagram showing one example of an electronic device. FIG. 28A to FIG. 28G is a diagram showing one example of an electronic device. FIG. 29A to FIG. 29F is a diagram showing one example of an electronic device. FIG. 30 is a cross-sectional view showing one example of a display device. Embodiment of Invention

[0023] Embodiments are described in detail with reference to the accompanying drawings. Note that the present application is not limited to the following description, and it is readily apparent to those skilled in the art that the present application can be carried out in various changes and modifications of the embodiments. Therefore, the present application should not be construed as being limited to the following examples.

[0024] Note that, in the structure of the present application described below, the same symbols are used to show the same parts or parts having the same function in different drawings, and repeated description is omitted. Further, the same hatching pattern is used when indicating parts having the same function, and a reference numeral is not particularly added.

[0025] For ease of understanding, the positions, sizes, ranges, and the like of the respective components shown in the drawings are not necessarily to scale. Therefore, the disclosed application is not necessarily limited to the positions, sizes, ranges, and the like disclosed in the drawings.

[0026] Note that in this specification and the like, the terms "first" and "second" are used, and thus do not limit the number of the components or the order in which the components are mentioned (e.g., the order of the steps or the order of layers). In addition, the terms "first" and "second" attached to a component in one part of this specification or like do not mean to be limited to the same in another part of this specification or like.

[0027] A transistor is one of semiconductor elements, and can achieve a function of amplifying current or voltage, a switching operation of controlling on or off, and the like. The transistor in this specification includes an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT).

[0028] In this specification and the like, a transistor in which an oxide semiconductor or a metal oxide is used for a semiconductor layer and a transistor including an oxide semiconductor or a metal oxide in a channel formation region is referred to as an OS transistor. Further, a transistor including silicon in a channel formation region is referred to as an Si transistor.

[0029] In this specification and the like, a transistor refers to an element including at least a gate, a drain, and a source. A transistor has a region (also referred to as a channel formation region) in which a channel is formed between a drain (a drain terminal, a drain region, or a drain electrode) and a source (a source terminal, a source region, or a source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region where a current flows.

[0030] In addition, the functions of the source and the drain are sometimes interchanged with each other in the case of using transistors of different polarities or in the case where the direction of current flowing in a circuit operation is changed, for example. Therefore, the source and the drain can be interchanged with each other in this specification.

[0031] Note that an impurity of a semiconductor refers to, for example, an element other than the main component of a semiconductor. For example, an element with a concentration lower than 0.1 atomic% can be regarded as an impurity. In the case where an impurity is contained, for example, an increase in the defect state density of a semiconductor or a decrease in crystallinity, or the like, is sometimes caused. When a semiconductor is an oxide semiconductor, as an impurity which changes the characteristics of a semiconductor, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component of the oxide semiconductor are given. Specifically, for example, hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen are given. In addition, water is sometimes given as an impurity. Furthermore, for example, the mixture of an impurity causes formation of an oxygen vacancy (also referred to as V O ) in an oxide semiconductor.

[0032] Note that in this specification and the like, an oxynitride refers to a material whose composition contains oxygen more than nitrogen. A nitride oxide refers to a material whose composition contains nitrogen more than oxygen.

[0033] For example, the content of hydrogen, oxygen, carbon, nitrogen, or the like in a film can be analyzed by secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS). XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., 0.5 atomic% or less or 1 atomic% or less). In comparison of the content of an element, it is more preferable to perform composite analysis using both SIMS and XPS analysis techniques.

[0034] Note that "film" and "layer" can be interchanged depending on the situation or state. For example, a "conductive layer" can be changed into a "conductive film". In addition, an "insulating film" can be changed into an "insulating layer".

[0035] In this specification and the like, "parallel" indicates a state in which the angle formed between two straight lines is greater than or equal to -10 degrees and less than or equal to 10 degrees. Thus, a state in which the angle is greater than or equal to -5 degrees and less than or equal to 5 degrees is also included. "Substantially parallel" indicates a state in which the angle formed between two straight lines is greater than or equal to -30 degrees and less than or equal to 30 degrees. In addition, "perpendicular" indicates a state in which the angle formed between two straight lines is greater than or equal to 80 degrees and less than or equal to 100 degrees. Thus, a state in which the angle is greater than or equal to 85 degrees and less than or equal to 95 degrees is also included. "Substantially perpendicular" indicates a state in which the angle formed between two straight lines is greater than or equal to 60 degrees and less than or equal to 120 degrees.

[0036] In this specification and the like, "electrically connected" includes the case where "an element having some kind of electric action" is connected. Here, "an element having some kind of electric action" is not particularly limited as long as it can transmit and receive an electric signal between connection objects. For example, "an element having some kind of electric action" includes, in addition to an electrode or a wiring, a switching element such as a transistor, a resistor, a coil, an element having a variety of functions, and the like.

[0037] Further, in this specification and the like, an off-state current refers to a leakage current between a source and a drain when a transistor is in an off state (also referred to as a non-conduction state, a blocking state) unless otherwise specified. In the case of an n-channel transistor, the off state refers to a state where a voltage V gs is lower than a threshold voltage V th ( V gs is higher than V th ).

[0038] In this specification and the like, a normally-on characteristic refers to a state where a channel exists even when no voltage is applied to a gate, and a current flows through a transistor. Further, a normally-off characteristic refers to a state where no current flows through a transistor when no voltage is applied to a gate or a ground potential is supplied to the gate.

[0039] In this specification and the like, a top surface shape of a component refers to an edge shape of the component when viewed from above. Note that viewing from above refers to a case where the component is viewed from the direction of the normal line of a surface on which the component is formed or a surface of a support (e.g., a substrate) on which the component is formed.

[0040] In this specification and the like, "top surface shapes are substantially uniform" refers to a case where at least a part of edges of each layer in a stack is overlapped. For example, a case where an upper layer and a lower layer are processed by the same mask pattern or a part of the same mask pattern is included. However, strictly speaking, there are cases where edges are not overlapped and the upper layer is positioned inside the lower layer or the upper layer is positioned outside the lower layer, and these cases can also be said to be "top surface shapes are substantially uniform". When the top surface shapes are uniform or substantially uniform, it can also be said that end portions are aligned or substantially aligned, or side end portions are aligned or substantially aligned.

[0041] In this specification and the like, a tapered shape refers to a shape in which at least a part of a side surface of a component is provided to be inclined with respect to a substrate surface or a formed surface. For example, a region in which an angle (also referred to as a taper angle) formed by an inclined side surface and a substrate surface or a formed surface is greater than 0 degrees and less than 90 degrees is preferably included. Here, the side surface of the component, the substrate surface, and the formed surface do not necessarily have to be completely flat, and can be an approximately planar shape with a fine curvature or an approximately planar shape with a fine unevenness.

[0042] In the present specification and the like, in the case where there is a description of "A and B being in contact", at least a part of A is in contact with B. Therefore, for example, it can be called that A includes a region in contact with B.

[0043] In the present specification and the like, in the case where there is a description of "A being on B", at least a part of A is on B. Therefore, for example, it can be called that A includes a region on B.

[0044] In the present specification and the like, in the case where there is a description of "A covering B", at least a part of A covers B. Therefore, for example, it can be called that A includes a region covering B.

[0045] In the present specification and the like, in the case where there is a description of "A and B overlapping", at least a part of A overlaps with B. Therefore, for example, it can be called that A includes a region overlapping with B.

[0046] In the present specification and the like, a device manufactured using a metal mask or an FMM (Fine Metal Mask) is sometimes referred to as a device having an MM (Metal Mask) structure. In addition, in the present specification and the like, a device manufactured without using a metal mask or an FMM is sometimes referred to as a device having an MML (Metal Mask Less) structure.

[0047] In the present specification and the like, a structure in which light emitting layers are respectively manufactured in light emitting elements (also referred to as light emitting devices) in which light emitting wavelengths are different is sometimes referred to as an SBS (Side By Side) structure. The SBS structure can optimize materials and structures for each light emitting element, and the degree of freedom in the selection of materials and structures is improved, and improvement in luminance and reliability can be easily achieved.

[0048] In the present specification and the like, a hole or an electron is sometimes referred to as a "carrier". Specifically, a hole injection layer or an electron injection layer is sometimes referred to as a "carrier injection layer", a hole transport layer or an electron transport layer is sometimes referred to as a "carrier transport layer", and a hole blocking layer or an electron blocking layer is sometimes referred to as a "carrier blocking layer". Note that the above-described carrier injection layer, carrier transport layer, and carrier blocking layer cannot be clearly distinguished at times. In addition, one layer sometimes has the functions of two or all of the carrier injection layer, the carrier transport layer, and the carrier blocking layer.

[0049] In this specification and the like, a light-emitting element includes, in a pair of electrodes, an EL layer. The EL layer includes at least a light-emitting layer. Here, as a layer included in the EL layer (also referred to as a functional layer), a light-emitting layer, a carrier injecting layer (a hole injecting layer and an electron injecting layer), a carrier transporting layer (a hole transporting layer and an electron transporting layer), and a carrier blocking layer (a hole blocking layer and an electron blocking layer) can be given. In this specification and the like, a light-receiving element (also referred to as a light-receiving device) includes, in a pair of electrodes, at least an active layer serving as a photoelectric conversion layer. In this specification and the like, one of a pair of electrodes is referred to as a pixel electrode, and the other is referred to as a common electrode.

[0050] In this specification and the like, a sacrificial layer (also referred to as a mask layer) is at least positioned over a light-emitting layer (more specifically, a layer included in an EL layer and processed into an island shape) and has a function of protecting the light-emitting layer in a manufacturing process.

[0051] In this specification and the like, disconnection refers to a phenomenon in which a layer, a film, or an electrode is disconnected due to the shape of a formed surface (e.g., a step or the like).

[0052] Note that in some cases, an arrowhead representing an X direction, a Y direction, and a Z direction is attached to a drawing in this specification and the like. Note that in this specification and the like, the "X direction" refers to the direction along the X axis, and the forward and reverse directions thereof are sometimes not distinguished unless explicitly indicated. The same applies to the "Y direction" and the "Z direction". Further, the X direction, the Y direction, and the Z direction are perpendicular to each other. For example, the X direction, the Y direction, and the Z direction are orthogonal to each other.

[0053] (Embodiment 1) In this embodiment, a semiconductor device of one embodiment of the present application is described.

[0054] A semiconductor device of one embodiment of the present application includes a first conductive layer, a second conductive layer, a third conductive layer, an oxide semiconductor layer, a first insulating layer, and a second insulating layer.

[0055] The first insulating layer is positioned over the first conductive layer, and the second conductive layer is positioned over the first insulating layer. The first insulating layer and the second conductive layer include an opening reaching the first conductive layer. The oxide semiconductor layer is in contact with at least a top surface of the first conductive layer, a side surface of the first insulating layer, and a side surface of the second conductive layer in the opening. The second insulating layer is positioned over the oxide semiconductor layer in the opening. The third conductive layer overlaps with the oxide semiconductor layer with the second insulating layer positioned therebetween in the opening.

[0056] The first conductive layer is used as one of a source electrode and a drain electrode of a transistor. The second conductive layer is used as the other of the source electrode and the drain electrode of the transistor. The third conductive layer is used as a gate electrode of the transistor, and the second insulating layer is used as a gate insulating layer.

[0057] In this specification and the like, a cross section indicated by a plane including an imaginary straight line parallel to a bottom surface (or parallel to a top surface) of the layer to be cut, and a cross section indicated by a plane including an imaginary straight line perpendicular to the bottom surface (or perpendicular to the top surface) of the layer to be cut is simply referred to as a "cross section" or a "cross-sectional view". In addition, a cross section indicated by a plane including an imaginary straight line oblique to the bottom surface (or the top surface) of the layer to be cut is simply referred to as a "cross section" or a "cross-sectional view".

[0058] The source electrode and the drain electrode of one embodiment of a transistor according to the present application are located at different levels, and thus current flowing through a semiconductor layer flows in the direction of the levels. In other words, the channel length direction has a component in the direction of the levels (the vertical direction), and thus one embodiment of a transistor according to the present application can also be referred to as a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel type transistor, or the like.

[0059] Since the source electrode, the semiconductor layer, and the drain electrode can be provided to be stacked, the area occupancy of one embodiment of a transistor according to the present application can be much smaller than that of a so-called planar transistor in which a semiconductor layer is provided in a planar shape.

[0060] Note that in this specification and the like, "end portions coincide" means a case where at least a part of the edge of each layer in the stack overlaps when viewed from the top. For example, a case where an upper layer and a lower layer are processed by the same mask pattern or a mask pattern which is a part of the same mask pattern is included. However, strictly speaking, there are cases where the edges do not overlap and the edge of the upper layer is positioned inside the edge of the lower layer or the edge of the upper layer is positioned outside the edge of the lower layer, and these cases can also be said to be "end portions coincide".

[0061] Note that generally, it is sometimes difficult to clearly distinguish between "completely coincide" and "approximately coincide". Thus, in this specification and the like, "coincide" includes both the case of complete coincidence and the case of approximate coincidence.

[0062] <Structure Example 1 of Semiconductor Device> Reference FIG. 1A to FIG. 3B A structure of a semiconductor device of one embodiment of the present application is described below. FIG. 1A is a plan view of a semiconductor device including a transistor 200. FIG. 1B is a cross-sectional view taken along a dotted line A1-A2 in FIG. 1A . FIG. 1C is a cross-sectional view taken along a dotted line A3-A4 in FIG. 1A . FIG. 2A is an enlarged view of a region surrounded by a dotted line in FIG. 1B . Note that in the plan view of FIG. 1A , part of the components is omitted for clarity. Part of the components is also omitted in the plan views shown below in some cases.

[0063] FIG. 1A to FIG. 1C , FIG. 2A and FIG. 2B The semiconductor device shown includes an insulating layer 210 on a substrate (not shown), a transistor 200 on the insulating layer 210, an insulating layer 280 on the insulating layer 210, and an insulating layer 283 on the transistor 200. The insulating layers 210, 280, and 283 are used as interlayer films.

[0064] Transistor 200 includes a conductive layer 220, a conductive layer 240 on an insulating layer 280, an oxide semiconductor layer 230, an insulating layer 250 on the oxide semiconductor layer 230, and a conductive layer 260 on the insulating layer 250. Conductive layer 260 includes conductive layer 260a and conductive layer 260b stacked on conductive layer 260a. Conductive layers 220 and 240 are located at different heights. Insulating layer 283 covers the top and side surfaces of conductive layer 260b.

[0065] like FIG. 1B and FIG. 1C As shown, the insulating layer 280 and the conductive layer 240 are provided with openings 290 leading to the conductive layer 220. Here, the bottom of the opening 290 is the top surface of the conductive layer 220, and the sidewalls of the opening 290 are the sidewalls of the insulating layer 280 and the conductive layer 240. The opening 290 includes the openings of both the insulating layer 280 and the conductive layer 240. In other words, the opening in the region of the insulating layer 280 that overlaps with the conductive layer 220 is part of the opening 290, and the opening in the region of the conductive layer 240 that overlaps with the conductive layer 220 is the remaining part of the opening 290. Note that the opening 290 in the insulating layer 280 is referred to as opening 290a, and the opening 290 in the conductive layer 240 is referred to as opening 290b.

[0066] At least a portion of the constituent elements of transistor 200 are disposed within opening 290. Specifically, at least a portion of each of oxide semiconductor layer 230, insulating layer 250, and conductive layer 260 is located within opening 290. Oxide semiconductor layer 230 is in contact with the top surface of conductive layer 220, the side surface of insulating layer 280, and the side surface of conductive layer 240 within opening 290.

[0067] Furthermore, the arrangement of the oxide semiconductor layer 230 and the insulating layer 250 within the opening 290 reflects the shape of the opening 290. Specifically, the oxide semiconductor layer 230 is disposed to cover the bottom and sidewalls of the opening 290, and the insulating layer 250 is disposed to cover the oxide semiconductor layer 230. Additionally, the conductive layer 260 is disposed to be embedded in a recess of the insulating layer 250 that reflects the shape of the opening 290.

[0068] The transistor of one embodiment of the present application can increase the withstand voltage of the insulating layer 250 by including a region 277 between the conductive layer 260b and the insulating layer 250. The region 277 is, for example, a void. By providing a void, the conductive layer 260b can be separated from the conductive layer 240, and the leakage current flowing through the insulating layer 250 between the conductive layer 260b and the conductive layer 240 can be suppressed. Furthermore, as described later, the void can be embedded with the insulating layer 283. FIG. 4A and FIG. 4B The void can be embedded with the insulating layer 283.

[0069] The width of the opening 290 is a width D. The width D is sometimes varied in the depth direction. For example, it can be the width of the upper end of the opening 290 of the insulating layer 280. Alternatively, it can be the width of the lower end thereof. Alternatively, it can be the width of half the depth of the opening 290 in the insulating layer 280. Alternatively, the width of the opening 290 in the conductive layer 240 can be used.

[0070] The region of the oxide semiconductor layer 230 in contact with the conductive layer 240 is sometimes used as a low-resistance region.

[0071] In the transistor 200, the oxide semiconductor layer 230 is used as a semiconductor layer, the conductive layer 260 is used as a gate electrode, the insulating layer 250 is used as a gate insulating layer, the conductive layer 220 is used as one of a source electrode and a drain electrode, and the conductive layer 240 is used as the other of the source electrode and the drain electrode.

[0072] As described above, the oxide semiconductor layer 230 is provided inside the opening 290 of the insulating layer 280. Furthermore, one of the source electrode and the drain electrode in the transistor 200 (here, the conductive layer 220) is below and the other of the source electrode and the drain electrode (here, the conductive layer 240) is above, so that the transistor 200 has a structure in which current flows in the up-down direction. That is, a channel is formed along the side surface of the opening of the insulating layer 280.

[0073] The oxide semiconductor layer 230 is in contact with the top surface of the conductive layer 220 and the side surface of the conductive layer 240 in the opening 290. The oxide semiconductor layer 230 is also in contact with part of the top surface of the conductive layer 240. Thus, by making the oxide semiconductor layer 230 in contact with not only the side surface but also the top surface of the conductive layer 240, the area of the oxide semiconductor layer 230 in contact with the conductive layer 240 can be increased, for example, as compared to the case where the oxide semiconductor layer 230 is in contact with the side surface of the conductive layer 240 and not in contact with the top surface. Thus, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be reduced.

[0074] The sidewalls of the opening 290 are preferably perpendicular to the top surface of the insulating layer 210. This structure allows for miniaturization or high integration of the semiconductor device. In this case, the films disposed inside the opening 290 are preferably formed using atomic layer deposition (ALD). ALD deposits atoms layer by layer, resulting in the ability to deposit very thin films, deposit structures with high aspect ratios, deposit with fewer defects such as pinholes, achieve high coverage, and deposit at low temperatures. Therefore, the film can be deposited with high coverage on the sides of the opening 290. For example, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 can all be formed using ALD. Here, for example, in conductive layers 260a and 260b, conductive layer 260a is particularly preferably formed using ALD.

[0075] Note that in FIG. 1B and FIG. 1C The opening 290 is provided such that the sidewall of the opening 290 is perpendicular to the top surface of the insulating layer 210, but the present invention is not limited thereto. For example, the sidewall of the opening 290 may also have a tapered shape. FIG. 2C It is shown FIG. 1B The example shown is an opening 290 with a tapered sidewall. By making the sidewall of the opening 290 tapered, the coverage of the oxide semiconductor layer 230, insulating layer 250, etc., can be improved, thereby reducing defects such as voids. When the sidewall of the opening 290 is tapered, for example, the angle θ formed by the side surface of the insulating layer 280 and the top surface of the insulating layer 210 in the opening 290 is preferably 45 degrees or more and less than 90 degrees. Specifically, when the angle is 80 degrees or more and less than 90 degrees, as described above, miniaturization or high integration of the semiconductor device can be achieved, so it is preferred. Furthermore, when the angle is 45 degrees or more and less than 60 degrees, the coverage of the film formed in the opening 290 is improved, so it is preferred. Specifically, for example, it is preferred to be 45 degrees or more or 50 degrees or more and less than 80 degrees, 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less.

[0076] Alternatively, for example, the sidewalls of opening 290 may sometimes have an inverted conical shape. In other words, the angle formed by the side surface of insulating layer 280 and the top surface of insulating layer 210 in opening 290 may sometimes be greater than 90 degrees.

[0077] The conductive layer 240 has an opening in a region overlapping with the conductive layer 220. Further, the conductive layer 240 is preferably not provided in the inside of the opening of the insulating layer 280. That is, the conductive layer 240 preferably has no region in contact with the side surface of the insulating layer 280 in the opening 290. By employing such a structure, the opening of the conductive layer 240 and the opening of the insulating layer 280 can be formed at the same time. Further, by employing a structure in which the side surface of the conductive layer 240 in the opening 290 coincides or substantially coincides with the side surface of the insulating layer 280 in the opening 290, the thickness distribution of the oxide semiconductor layer 230 provided in the inside of the opening 290 can be made uniform. Further, separation of the oxide semiconductor layer 230 due to a step between the conductive layer 240 and the insulating layer 280 can be suppressed.

[0078] Although the side surface of the conductive layer 240 in the opening 290 coincides or substantially coincides with the side surface of the insulating layer 280 in the opening 290 is described in FIG. 1B and FIG. 1C , the present invention is not limited thereto. For example, the side surface of the conductive layer 240 in the opening 290 and the side surface of the insulating layer 280 in the opening 290 can not be continuous. Alternatively, the inclination of the side surface of the conductive layer 240 in the opening 290 and the inclination of the side surface of the insulating layer 280 in the opening 290 can be different from each other. At this time, for example, the angle formed by the side surface of the conductive layer 240 in the opening 290 and the top surface of the insulating layer 210 is preferably smaller than the angle formed by the side surface of the insulating layer 280 in the opening 290 and the top surface of the insulating layer 210. By employing such a structure, the coverage of the oxide semiconductor layer 230 over the side surface of the conductive layer 240 in the opening 290 is improved, and thus defects such as a void can be reduced.

[0079] Here, FIG. 1B and FIG. 1C describe a structure in which the end portion of the oxide semiconductor layer 230 on the outside of the opening 290 is positioned on the inside of the end portion of the conductive layer 240. Note that the present invention is not limited thereto. For example, in the X direction, the end portion of the oxide semiconductor layer 230 and the end portion of the conductive layer 240 can coincide with each other at times. Alternatively, the end portion of the oxide semiconductor layer 230 can be positioned on the outside of the end portion of the conductive layer 240 at times.

[0080] Further, FIG. 1B describes a structure in which the end portion of the conductive layer 240 on the outside of the opening 290 is positioned on the outside of the end portion of the conductive layer 260. By employing such a structure, a plug or the like can be provided in a region of the conductive layer 240 extending on the outside of the conductive layer 260, and electrically connected to a conductive layer such as a wiring or an electrode provided in a layer above the conductive layer 240 and the conductive layer 260.

[0081] The insulating layer 250 is provided in contact with a top surface of the oxide semiconductor layer 230. The insulating layer 250 includes a region in contact with a top surface of the conductive layer 240, a region in contact with a side surface of the conductive layer 240, and a region in contact with the insulating layer 280.

[0082] As FIG. 1B and FIG. 1C shown, a part of the insulating layer 250 is positioned outside the opening 290, i.e., on the conductive layer 240 and the insulating layer 280. At this time, the insulating layer 250 preferably covers an end portion of the oxide semiconductor layer 230. By this means, the conductive layer 260 can be prevented from short-circuiting with the oxide semiconductor layer 230. Further, the insulating layer 250 preferably covers an end portion of the conductive layer 240. By this means, the conductive layer 260 can be prevented from short-circuiting with the conductive layer 240.

[0083] In the insulating layer 250, a region outside the end portion of the conductive layer 260 is exposed to an etching atmosphere at the time of formation of the conductive layer 260, and thus there is a concern that the region is damaged by etching. Since the etching damage has a concern that the withstand voltage of the insulating layer 250 decreases. In particular, when dry etching is used in the formation process of the conductive layer 260, the etching damage is sometimes more significant.

[0084] Further, in the formation process of the conductive layer 260, the thickness of the insulating layer 250 is sometimes reduced in a region outside the end portion of the conductive layer 260 due to over-etching. In particular, when dry etching is used in the formation process of the conductive layer 260, the reduction in the thickness of the insulating layer 250 due to over-etching is sometimes more significant. The region in the insulating layer 250 where the thickness is reduced has a concern that the withstand voltage decreases.

[0085] The region in the insulating layer 250 where the withstand voltage decreases has a concern that, for example, the gate current flowing due to an electric field between the conductive layer 260 and the conductive layer 240 increases. Further, when the damage or the reduction in the thickness of the insulating layer 250 is significant, there is also a concern that, for example, a short circuit occurs between the conductive layer 260 and the conductive layer 240.

[0086] Here, in the semiconductor device of one embodiment of the present application, as FIG. 1B and FIG. 2A shown, the conductive layer 260 includes the conductive layer 260a and the conductive layer 260b, and the conductive layer 260b has a region extending outside the end portion of the conductive layer 260a.

[0087] Further, the end portion of the conductive layer 260b is positioned outside the end portion of the conductive layer 260a. Further, in FIG. 1BIn the cross section, the conductive layer 260b and the conductive layer 260a extend from the opening 290 in both the positive direction and the negative direction of X, respectively. It can also be said that, from the opening 290, the side of the conductive layer 260b extending in the positive direction (negative direction) of X is positioned outside the side of the conductive layer 260a extending in the positive direction (negative direction) of X.

[0088] Further, in the plan view illustrated in FIG. 1A, the edge of the conductive layer 260b is positioned outside the edge of the conductive layer 260a. FIG. 1A

[0089] As described above, the conductive layer 260a can be formed by wet etching. FIG. 1B FIG. 2A The structure of the conductive layer 260a illustrated in FIG. 1A can be formed, for example, by wet etching.

[0090] By using isotropic etching as a wet etching condition, the end portion of the conductive layer 260a can be positioned inside the end portion of the conductive layer 260b when the conductive layer 260b is used as a mask to form the conductive layer 260a.

[0091] Further, by increasing the selectivity ratio of the etching rate of the conductive layer 260 with respect to the insulating layer 250 using wet etching, the reduction in the thickness of the insulating layer 250 due to over-etching in the formation process of the conductive layer 260 can be suppressed. Further, wet etching is less likely to cause damage than dry etching and can reduce damage to the insulating layer 250. Increasing the selectivity ratio of the etching rate of the conductive layer 260 with respect to the insulating layer 250 here means making the etching rate of the conductive layer 260 higher than the etching rate of the insulating layer 250.

[0092] In the transistor 200 illustrated in FIG. 1A, the conductive layer 260a is positioned over the insulating layer 250, and the transistor 200 has a region 277 between the region of the conductive layer 260b extending outside the end portion of the conductive layer 260a and the insulating layer 250. The region 277 is, for example, a void. FIG. 1B FIG. 2A By providing the region 277 between the conductive layer 260b and the insulating layer 250, in the region of the conductive layer 260 in contact with the insulating layer 250, for example, the conductive layer 260a can not overlap with a region where damage is likely to occur in the insulating layer 250, and thus the withstand voltage of the insulating layer 250 can be increased. Alternatively, in the region of the conductive layer 260 in contact with the insulating layer 250, for example, the conductive layer 260a can not overlap with a region where a reduction in the thickness of the insulating layer 250 is likely to occur.

[0093]

[0094] ​​​​Region 277 is, for example, a void, i.e., an empty space. Region 277 contains, for example, one or more elements selected from air, nitrogen, oxygen, carbon dioxide, and Group 18 elements. Furthermore, region 277 has, for example, a relative permittivity approximately equal to that of air. When region 277 contains air, for example, the relative permittivity of region 277 has a value of 1 or near it. A value of 1 or near it is, for example, greater than 0.8 and less than 1.2. Alternatively, the relative permittivity of region 277 is greater than 1 and less than 1.2. Because region 277 is air, the void can be provided between conductive layer 260 and conductive layer 240 to suppress leakage current flowing through the insulating layer 250 between the conductive layers.

[0095] When region 277 is a void, for example, the relative permittivity of region 277 is smaller than that of insulating layer 250. Furthermore, for example, the relative permittivity of region 277 is smaller than that of insulating layer 283. Furthermore, for example, the film density of region 277 is smaller than that of insulating layer 250. Furthermore, for example, the film density of region 277 is smaller than that of insulating layer 283. By providing region 277 as a region with a low relative permittivity, the parasitic capacitance between conductive layer 260 and conductive layer 240 can be reduced, for example.

[0096] Alternatively, region 277 may be filled with an insulating layer 283 formed after the formation of the conductive layer 260. FIG. 4A Show FIG. 1B An example where region 277 is filled with insulating layer 283. Furthermore, FIG. 4B Shown in FIG. 4A An enlarged view of the area surrounded by double-dotted lines.

[0097] When region 277 is filled with insulating layer 283, for example, region 277 has a relative permittivity that is equal to or close to that of insulating layer 283. For example, the relative permittivity of region 277 is more than 0.8 times and less than 1.2 times the relative permittivity of insulating layer 283.

[0098] exist FIG. 4A and FIG. 4B In the middle, the insulating layer 283 has a region covering the bottom surface of the conductive layer 260b in the region where the conductive layer 260b extends to the outside of the conductive layer 260a.

[0099] The insulating layer 283 has a region located between the region extending outside the conductive layer 260a in the conductive layer 260b and the insulating layer 250.

[0100] Note that it is also possible for only a portion of region 277 to be filled with insulating layer 283.

[0101] Here, the width of the region where the end portion of the conductive layer 260b extends outward from the end portion of the conductive layer 260a is width R. For example, the width R corresponds to the distance between the end portion of the conductive layer 260b and the end portion of the conductive layer 260a. Further, it can be said that the edge of the conductive layer 260b in plan view is positioned outward of the edge of the conductive layer 260a, where the difference in the edges corresponds to the width R.

[0102] Further, the thickness of the insulating layer 250 is thickness T1. For example, the thickness T1 can be the thickness of the region covering the top surface of the conductive layer 240 in the insulating layer 250. Further, the thickness T1 can be the thickness of the region covering the top surface of the conductive layer 240 and covered with the conductive layer 260b. Further, for example, as the thickness T1, the thickness of the region sandwiched between the oxide semiconductor layer 230 and the conductive layer 260 can be used. Further, for example, as the thickness T1, the thickness of the region positioned in the opening 290 can be used.

[0103] The width R is, for example, preferably greater than or equal to 10 % and less than or equal to 25 % of the width D.

[0104] The thickness T1 is, for example, greater than or equal to 0.5 nm and less than or equal to 200 nm, for example, greater than or equal to 1 nm and less than or equal to 50 nm.

[0105] The width R is, for example, greater than or equal to 0.3 times and less than or equal to 10 times or greater than or equal to 0.5 times and less than or equal to 5 times the thickness T1.

[0106] The transistor 200 contains a metal oxide (also referred to as an oxide semiconductor) serving as a semiconductor in the oxide semiconductor layer 230 including a channel formation region. That is, the transistor 200 can be said to be an OS transistor.

[0107] In an OS transistor, when oxygen vacancies (V O ) and impurities exist in the channel formation region of the oxide semiconductor, the electrical characteristics easily fluctuate and the reliability can be decreased. Further, hydrogen in the vicinity of the oxygen vacancy forms a defect (hereinafter referred to as V O H) in which hydrogen enters the oxygen vacancy, and an electron serving as a carrier can be generated. Thus, in the case where the channel formation region in the oxide semiconductor contains oxygen vacancies, the OS transistor tends to have a normally-on characteristic. Thus, in the channel formation region in the oxide semiconductor, it is preferable to reduce oxygen vacancies and impurities as much as possible. In other words, it is preferable that the carrier concentration of the channel formation region in the oxide semiconductor be reduced and be i-type (intrinsic) or substantially i-type.

[0108] On the other hand, the source region and the drain region of the OS transistor are preferably regions in which oxygen vacancies are more than in the channel formation region, V OH is high and the carrier concentration increases, whereby the resistance is lowered. That is, the source region and the drain region of the OS transistor are preferably n-type regions having a high carrier concentration and a low resistance, as compared to the channel formation region.

[0109] The region of the oxide semiconductor layer 230 in contact with the insulating layer 280 and its vicinity is used as the channel formation region of the transistor 200. One of the region of the oxide semiconductor layer 230 in contact with the conductive layer 220 and the region of the oxide semiconductor layer 230 in contact with the conductive layer 240 is used as a source region, and the other is used as a drain region. That is, the channel formation region is interposed between the source region and the drain region.

[0110] When the oxide semiconductor layer 230 is in contact with the conductive layer 220, a metal compound or an oxygen vacancy is formed, and the region of the oxide semiconductor layer 230 in contact with the conductive layer 220 is low-resistance. Thus, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220 can be reduced. Similarly, when the oxide semiconductor layer 230 is in contact with the conductive layer 240, the region of the oxide semiconductor layer 230 in contact with the conductive layer 240 is low-resistance. Thus, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be reduced.

[0111] As FIG. 2B illustrated in FIG. 6A, the insulating layer 280 is in contact with the edge of the oxide semiconductor layer 230 as a whole. Thus, the channel formation region of the transistor 200 can be formed in the entire outer periphery of the portion of the oxide semiconductor layer 230 formed in the same layer as the insulating layer 280. Further, as FIG. 2B illustrated in FIG. 6B, the cross-sectional view of the XY plane including the channel formation region of the oxide semiconductor layer 230 can be obtained.

[0112] The channel length of the transistor 200 is the distance between the source region and the drain region. That is, it can be said that the channel length of the transistor 200 is determined depending on the thickness of the insulating layer 280 over the conductive layer 220. In FIG. 1C FIG. 6C, the channel length L of the transistor 200 is indicated by a double-headed arrow in a dashed line. In a cross-sectional view, the channel length L is the distance between the end of the region where the oxide semiconductor layer 230 and the conductive layer 220 are in contact and the end of the region where the oxide semiconductor layer 230 and the conductive layer 240 are in contact. That is, the channel length L corresponds to the length of the side of the opening 290 side of the insulating layer 280 in a cross-sectional view.

[0113] In a transistor in the related art, such as a planar transistor, the channel length is limited by the exposure limit of photolithography, and further miniaturization is difficult, but in the present application, the channel length can be set in accordance with the thickness of the insulating layer 280. Thus, the channel length of the transistor 200 can be set to a very fine structure (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less and 0.1 nm or more, 1 nm or more, or 5 nm or more) below the exposure limit of photolithography. Thus, the on-state current of the transistor 200 is increased, and thus the frequency characteristics can be improved.

[0114] Further, as described above, the channel formation region, the source region, and the drain region can be formed in the opening 290. Thus, the transistor 200 can have a smaller area than a lateral transistor in which a channel formation region, a source region, and a drain region are provided separately in a XY plane. Thus, high integration of a semiconductor device can be achieved. Further, when the semiconductor device of one embodiment of the present application is used for a memory device, the memory capacity per unit area can be increased.

[0115] Further, as FIG. 2B indicated, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are provided in a concentric circular shape. Thus, the side surface of the conductive layer 260 provided at the center faces the side surface of the oxide semiconductor layer 230 with the insulating layer 250 interposed therebetween. In other words, the edge of the oxide semiconductor layer 230 as a whole is a channel formation region when viewed in plan view. At this time, for example, the channel width of the transistor 200 is determined in accordance with the length of the edge of the oxide semiconductor layer 230. In other words, the channel width of the transistor 200 is determined in accordance with the size of the width D of the opening 290 (in the case where the shape of the opening 290 in plan view is circular, the diameter). In FIG. 1C to FIG. 2B the width D of the opening 290 is indicated by a double-headed arrow with a two-dot chain line. In FIG. 2B the channel width W of the transistor 200 is indicated by a double-headed arrow with a one-dot chain line. By increasing the width D of the opening 290, the channel width per unit area can be increased, and thus the on-state current can be increased.

[0116] In the case where the opening 290 is formed by photolithography, the width D of the opening 290 is limited by the exposure limit of photolithography. Further, the width D of the opening 290 is determined in accordance with the thickness of each of the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 provided in the opening 290. The width D of the opening 290 is preferably, for example, 5 nm or more, 10 nm or more, or 20 nm or more and 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. Note that in the case where the opening 290 is circular when viewed in plan view, the width D of the opening 290 corresponds to the diameter of the opening 290, and the channel width W can be calculated as "D x π".

[0117] Further, the channel length L of the transistor 200 is preferably shorter than the channel width W of the transistor 200. The channel length L of the transistor 200 is preferably greater than or equal to 0.1 times and less than or equal to 0.99 times the channel width W of the transistor 200, further preferably greater than or equal to 0.5 times and less than or equal to 0.8 times the channel width W of the transistor 200. With such a structure, a transistor with good electrical characteristics and high reliability can be implemented.

[0118] Further, by forming the opening 290 in a circular shape in plan view, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are provided in a concentric circular shape. Thus, the distance between the conductive layer 260 and the oxide semiconductor layer 230 is substantially uniform, so that a gate electric field can be applied to the oxide semiconductor layer 230 substantially uniformly.

[0119] Note that this embodiment illustrates an example in which the shape of the opening 290 in plan view is circular, but the present application is not limited to this. For example, the shape of the opening 290 in plan view can be a substantially circular shape such as an elliptical shape, a polygonal shape such as a quadrangular shape, or a shape in which an angle of a polygonal shape such as a quadrangular shape is rounded.

[0120] <Structure material of semiconductor device> Hereinafter, a material used for the semiconductor device of this embodiment will be described. Note that a layer included in the semiconductor device of this embodiment can have a single-layer structure or a stacked-layer structure. In this embodiment, a case where the semiconductor device has a single-layer structure will be described. FIG. 1B and FIG. 1C An example in which the conductive layer 220, the oxide semiconductor layer 230, the conductive layer 240, and the insulating layer 250 each have a single-layer structure is described. Further, an example in which the conductive layer 220 and the conductive layer 240 have a stacked-layer structure is described. FIG. 3A and FIG. 3B An example in which the conductive layer 220 and the conductive layer 240 have a stacked-layer structure is described.

[0121] [Oxide semiconductor layer 230] As described above, the oxide semiconductor layer 230 has a channel formation region. The channel formation region is i-type (intrinsic) or substantially i-type. The oxide semiconductor layer 230 also has a source region and a drain region. The source region and the drain region are n-type regions (low-resistance regions) with higher carrier concentration than the channel formation region.

[0122] There is no particular limitation on the crystallinity of the semiconductor material used for the oxide semiconductor layer 230, and an amorphous semiconductor, a single-crystal semiconductor, or a semiconductor having crystallinity other than single-crystal (microcrystalline semiconductor, polycrystalline semiconductor, or a semiconductor in which part of the semiconductor has a crystalline region) can be used. The use of a single-crystal semiconductor or a semiconductor having crystallinity can suppress deterioration of the characteristics of the transistor, and is thus preferable.

[0123] The metal oxide used as a semiconductor preferably has a band gap of 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide having a wide band gap, the off-state current of the transistor can be reduced. Since the off-state current of the OS transistor is small, the power consumption of the semiconductor device can be sufficiently reduced. Furthermore, since the OS transistor has high frequency characteristics, the semiconductor device can operate at high speed.

[0124] As the metal oxide that can be used for the oxide semiconductor layer 230, for example, an indium oxide, a gallium oxide, an aluminum oxide, a zinc oxide, or a tin oxide can be given. The metal oxide preferably contains at least indium (In) or zinc (Zn). Further, the metal oxide preferably contains two or more kinds selected from indium, an element M, and zinc. Note that the element M is a metal element or a semi-metal element having high bonding energy to oxygen, such as a metal element or a semi-metal element having higher bonding energy to oxygen than indium. Specifically, as the element M, an aluminum, a gallium, a tin, a yttrium, a titanium, a vanadium, a chromium, a manganese, an iron, a cobalt, a nickel, a zirconium, a molybdenum, a hafnium, a tantalum, a tungsten, a lanthanum, a cerium, a neodymium, a magnesium, a calcium, a strontium, a barium, a boron, a silicon, a germanium, an antimony, or the like can be given. The element M contained in the metal oxide is preferably one or more kinds selected from the above elements, more preferably one or more kinds selected from an aluminum, a gallium, a tin, and a yttrium, and further preferably a gallium. Note that in this specification and the like, a metal element and a semi-metal element are sometimes collectively referred to as a "metal element", and the "metal element" described in this specification and the like sometimes includes a semi-metal element.

[0125] The oxide semiconductor layer 230 can be formed using, for example, an indium oxide, an indium-zinc oxide (also referred to as IZO (registered trademark)), an indium-tin oxide, an indium-titanium oxide, an indium-gallium oxide, an indium-gallium-aluminum oxide, an indium-gallium-tin oxide (also referred to as IGTO), a gallium-zinc oxide (also referred to as GZO), an aluminum-zinc oxide (also referred to as AZO), an indium-aluminum-zinc oxide (also referred to as IAZO), an indium-tin-zinc oxide (also referred to as ITZO (registered trademark)), an indium-titanium-zinc oxide, an indium-gallium-zinc oxide (also referred to as IGZO), an indium-gallium-tin-zinc oxide (also referred to as IGZTO), an indium-gallium-aluminum-zinc oxide (also referred to as IGAZO, IGZAO, or IAGZO), or the like. Alternatively, an indium-tin oxide including silicon, a gallium-tin oxide (Ga-Sn oxide), an aluminum-tin oxide (Al-Sn oxide), or the like can be used.

[0126] By increasing the ratio of the number of atoms of indium to the sum of the number of atoms of all metal elements in the metal oxide, the field-effect mobility of the transistor can be increased. Furthermore, a transistor with a large on-state current can be realized.

[0127] Note that the metal oxide can also contain one or plural kinds of metal elements with a large number of periods instead of or in addition to indium. There is a tendency that the larger the orbital overlap of the metal elements, the larger the carrier conduction in the metal oxide. Thus, by containing a metal element with a large number of periods, the field-effect mobility of the transistor can be increased in some cases. As the metal element with a large number of periods, a metal element belonging to the 5th period and a metal element belonging to the 6th period, and the like can be given. Specifically, as the metal element, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium, and the like can be given. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare-earth elements.

[0128] The metal oxide can also contain one or plural kinds of non-metal elements. When the metal oxide contains a non-metal element, the field-effect mobility of the transistor can be increased in some cases due to an increase in carrier concentration or a narrowing of a band gap, or the like. As the non-metal element, carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, hydrogen, and the like can be given.

[0129] Furthermore, by increasing the ratio of the number of atoms of zinc to the sum of the number of atoms of all metal elements in the metal oxide, the crystallinity of the metal oxide is increased, whereby diffusion of impurities in the metal oxide can be suppressed. Thus, fluctuation in electrical characteristics of the transistor is suppressed, whereby reliability can be increased.

[0130] Furthermore, by increasing the ratio of the number of atoms of the element M to the sum of the number of atoms of all metal elements in the metal oxide, a metal oxide with a wide band gap can be obtained. Furthermore, formation of an oxygen vacancy in the metal oxide can be suppressed. Thus, generation of carriers due to the oxygen vacancy is suppressed, whereby a transistor with a small off-state current can be realized. Furthermore, drift of the threshold voltage of the transistor can be suppressed. Furthermore, fluctuation in electrical characteristics of the transistor is suppressed, whereby reliability can be increased.

[0131] The electrical characteristics and the reliability of the transistor differ depending on the composition of the metal oxide used for the oxide semiconductor layer 230. Thus, by making the composition of the metal oxide different in accordance with the electrical characteristics and the reliability required for the transistor, a semiconductor device with excellent electrical characteristics and high reliability can be realized.

[0132] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably higher than or equal to the atomic ratio of M. As the atomic ratio of metal elements of such an In-M-Zn oxide, for example, In:M:Zn = 1:1:0.5, In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 1:1:2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:1, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, and the like, or compositions in the vicinity thereof can be given. Further, the composition in the vicinity includes a range of ±30 % of the desired atomic ratio. By increasing the atomic ratio of indium in the metal oxide, the on-state current or the field-effect mobility of the transistor, or the like can be increased.

[0133] The atomic ratio of In in the In-M-Zn oxide can also be lower than the atomic ratio of M. As the atomic ratio of metal elements of such an In-M-Zn oxide, for example, In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4, and the like, or compositions in the vicinity thereof can be given. By increasing the proportion of the atomic number of M in the metal oxide, generation of oxygen vacancies can be suppressed.

[0134] Note that when a plurality of metal elements are included as the element M, the total of the proportions of the atomic numbers of the metal elements can be the proportion of the atomic number of the element M.

[0135] In this specification and the like, the proportion of the atomic number of indium with respect to the total of the atomic numbers of all the metal elements contained is sometimes referred to as the indium content. The same applies to other metal elements.

[0136] Further, when the metal oxide is an In-Zn oxide, as the atomic ratio of metal elements of such an In-Zn oxide, for example, In:Zn = 1:1, In:Zn = 2:1, In:Zn = 4:1, and the like, or compositions in the vicinity thereof can be given. Further, the In-Zn oxide can include a small amount of the element M. For example, when Sn is included as the element M, as the atomic ratio of metal elements of such a metal oxide, for example, In:Sn:Zn = 2:0.1:1, In:Sn:Zn = 4:0.1:1, and the like, or compositions in the vicinity thereof can be given.

[0137] As analysis of the composition of the metal oxide serving as the oxide semiconductor layer 230, for example, an energy dispersive X-ray spectrometry (EDX), an X-ray photoelectron spectrometry (XPS), an inductively coupled plasma-mass spectrometry (ICP-MS), or an inductively coupled plasma-atomic emission spectrometry (ICP-AES) can be used. Alternatively, a plurality of the above methods can be combined and used for analysis. Note that the content rate of an element with a low content rate is sometimes affected by the analysis accuracy, and the actual content rate is different from the content rate obtained by analysis. For example, when the content rate of the element M is low, the content rate of the element M obtained by analysis is sometimes lower than the actual content rate.

[0138] The metal oxide can be formed by a sputtering method or an ALD method as appropriate. Note that in the case where the metal oxide is formed by a sputtering method, the composition of the metal oxide after deposition is sometimes different from that of the target. In particular, the content rate of zinc in the metal oxide after deposition is sometimes reduced to about 50 % of that in the target. Further, when the metal oxide is deposited, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, or the like can be used.

[0139] The oxide semiconductor layer 230 can have a stacked structure including two or more metal oxide layers. The composition of the two or more metal oxide layers included in the oxide semiconductor layer 230 can be the same or substantially the same. By using a stacked structure of metal oxide layers having the same composition, the same sputtering target can be used, for example, so that the manufacturing cost can be reduced.

[0140] The composition of the two or more metal oxide layers included in the oxide semiconductor layer 230 can be different from each other.

[0141] The oxide semiconductor layer 230 can have a two-layer structure, for example. FIG. 9A An example FIG. 1B The oxide semiconductor layer 230 illustrated in FIG. 1A has a two-layer structure of an oxide layer 230a and an oxide layer 230b over the oxide layer 230a.

[0142] For example, the oxide layer 230a preferably uses a material with higher conductivity than the oxide layer 230b. By using a material with higher conductivity for the oxide layer 230a in contact with the source electrode and the drain electrode (the conductive layer 220 and the conductive layer 240), the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220 and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be reduced, and thus a transistor with a large on-state current can be implemented.

[0143] In this case, in the case where a material with higher conductivity is used for the oxide layer 230b provided on the side of the conductive layer 260 serving as a gate electrode, the threshold voltage of the transistor 200 is sometimes shifted, so that the drain current flowing when the gate voltage is 0 V (hereinafter also referred to as off-state current) is increased. Specifically, in the case where the transistor 200 is an n-channel transistor, the threshold voltage is sometimes decreased. Thus, the oxide layer 230b preferably uses a material with lower conductivity than the oxide layer 230a. With this structure, in the case where the transistor 200 is an n-channel transistor, the threshold voltage can be increased, and a transistor with a small off-state current can be implemented. Note that a state where the off-state current is small is also referred to as always off.

[0144] By making the oxide semiconductor layer 230 have a stacked-layer structure as described above and using a material with higher conductivity than the oxide layer 230b for the oxide layer 230a, a transistor that is always off and has a large on-state current can be implemented. With this structure, a semiconductor device that has both low power consumption and high performance can be implemented.

[0145] Further, the carrier concentration of the oxide layer 230a is preferably higher than that of the oxide layer 230b. By increasing the carrier concentration of the oxide layer 230a, the conductivity is increased, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220 and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be reduced, and thus a transistor with a large on-state current can be implemented. Further, by decreasing the carrier concentration of the oxide layer 230b, the conductivity is decreased, and thus a transistor that is always off can be implemented.

[0146] Note that the oxide semiconductor layer 230 is not limited to the above structure, and a material with lower conductivity than the oxide layer 230b can be used for the oxide layer 230a. Further, the carrier concentration of the oxide layer 230a can be lower than that of the oxide layer 230b.

[0147] Further, the band gap of the first metal oxide used for the oxide layer 230a is preferably different from that of the second metal oxide used for the oxide layer 230b. For example, the difference between the band gap of the first metal oxide and that of the second metal oxide is preferably 0.1 eV or more, further preferably 0.2 eV or more, and still further preferably 0.3 eV or more.

[0148] The band gap of the first metal oxide used for the oxide layer 230a is preferably smaller than the band gap of the second metal oxide used for the oxide layer 230b. By this means, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220 and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be reduced, and thus a transistor with high on-state current can be achieved. Furthermore, in the case where the transistor 200 is an n-channel transistor, the threshold voltage can be increased, and thus a normally-off transistor can be achieved. Moreover, since the band gap of the second metal oxide is large, generation and induction of carriers in the oxide layer 230b and at the interface between the oxide layer 230b and the insulating layer 250 can be suppressed. Thus, the reliability of the transistor can be improved.

[0149] For example, the content of the element M of the first metal oxide is preferably lower than that of the second metal oxide. Specifically, for example, a metal oxide with a composition of In:M:Zn = 1:1:1 [atomic ratio] or its neighborhood is used as the oxide layer 230a, and a metal oxide with a composition of In:M:Zn = 1:3:2 [atomic ratio] or its neighborhood is used as the oxide layer 230b. At this time, as the element M, one or more of gallium, aluminum, and tin is / are particularly preferably used.

[0150] Note that the oxide semiconductor layer 230 is not limited to the above structure, and the band gap of the first metal oxide can be larger than that of the second metal oxide.

[0151] Furthermore, the content of the element M of the first metal oxide is preferably lower than that of the second metal oxide. The first metal oxide can contain a small amount of the element M or can not contain the element M. For example, the first metal oxide used for the oxide layer 230a is preferably an In-Zn oxide, and the second metal oxide used for the oxide layer 230b is preferably an In-M-Zn oxide. Specifically, the first metal oxide can be an In-Zn oxide, and the second metal oxide can be an In-Ga-Zn oxide.

[0152] For example, as the oxide layer 230a, a metal oxide having a composition of In:Zn = 1 : 1 [atomic ratio] or its neighborhood, a metal oxide having a composition of In:Zn = 2: 1 [atomic ratio] or its neighborhood, a metal oxide having a composition of In:Sn:Zn = 2:0.1: 1 [atomic ratio] or its neighborhood, a metal oxide having a composition of In:Zn = 4: 1 [atomic ratio] or its neighborhood, a metal oxide having a composition of In:Sn:Zn = 4:0.1: 1 [atomic ratio] or its neighborhood, or an indium oxide is preferably used. Further, as the oxide layer 230b, a metal oxide having a composition of In:Ga:Zn = 1 : 1 : 1 [atomic ratio] or its neighborhood, a metal oxide having a composition of In:Ga:Zn = 1 :3:2 [atomic ratio] or its neighborhood, or a metal oxide having a composition of In:Ga:Zn = 1 :3:4 [atomic ratio] or its neighborhood is preferably used. With this, the on-state current of the transistor 200 can be increased, and thus a transistor structure with low unevenness and high reliability can be achieved.

[0153] The oxide semiconductor layer 230 is not limited to the above structure, and the proportion of the element M of the first metal oxide can be higher than that of the second metal oxide.

[0154] The oxide semiconductor layer 230 preferably includes a metal oxide layer having crystallinity. As a structure of a metal oxide having crystallinity, a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, and a microcrystalline (nc: nano-crystal) structure can be given, for example. By using a metal oxide layer having crystallinity for the oxide semiconductor layer 230, the density of defect states in the oxide semiconductor layer 230 can be reduced, and thus a semiconductor device with high reliability can be achieved.

[0155] The higher the crystallinity of the metal oxide layer used for the oxide semiconductor layer 230 is, the lower the density of defect states in the oxide semiconductor layer 230 can be. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of flowing a large current can be achieved.

[0156] When a metal oxide layer is formed by a sputtering method, the higher the substrate temperature (stage temperature) at the time of formation is, the higher the crystallinity of the metal oxide layer can be. Further, the higher the flow rate ratio of an oxygen gas (hereinafter also referred to as an oxygen flow rate) to the entire deposition gas used at the time of formation is, the higher the crystallinity of the metal oxide layer can be.

[0157] The crystallinity of the oxide semiconductor layer 230 can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of the above methods can be used for analysis.

[0158] The oxide semiconductor layer 230 may also have a stacked structure of two or more metal oxide layers with different crystallinity. For example, it may have a stacked structure of a first metal oxide layer and a second metal oxide layer disposed on the first metal oxide layer, wherein the second metal oxide layer may have a region with higher crystallinity than the first metal oxide layer. Alternatively, the second metal oxide layer may have a region with lower crystallinity than the first metal oxide layer. In this case, the compositions of the first metal oxide layer and the second metal oxide layer may be different, the same, or substantially the same.

[0159] For example, as oxide layer 230a, a metal oxide with an In:M:Zn ratio of 1:3:2 or similar, or an In:M:Zn ratio of 1:3:4 or similar, is preferably used. As oxide layer 230b, a metal oxide with an In:M:Zn ratio of 1:1:1 or similar, is preferably used. By using a metal oxide with a high Zn:In ratio as oxide layer 230a, the crystallinity of oxide layer 230a can be improved. Furthermore, by forming oxide layer 230b on the highly crystallinity oxide layer 230a, the crystallinity of oxide layer 230b is easily improved. Therefore, the overall crystallinity of oxide semiconductor layer 230 can be improved, which is preferred. In this case, gallium, aluminum, or tin is particularly preferred as element M. For example, two IGZOs with different compositions can also be stacked. For example, a stacked structure selected from any one of indium oxide, indium gallium oxide and IGZO and any one of IAZO, IAGZO and ITZO (registered trademarks) can also be used.

[0160] In addition, such as FIG. 9B As shown, the oxide semiconductor layer 230 can have a three-layer structure consisting of an oxide layer 230c, an oxide layer 230a on the oxide layer 230c, and an oxide layer 230b on the oxide layer 230a.

[0161] Oxide layer 230a and oxide layer 230b can adopt the structure described above. Oxide layer 230c can adopt the same structure as that used in oxide layer 230b.

[0162] For example, as the oxide layer 230a, a metal oxide of In:Zn = 1:1 [atomic ratio] or a neighborhood thereof, a metal oxide of In:Zn = 2:1 [atomic ratio] or a neighborhood thereof, a metal oxide of In:Sn:Zn = 2:0.1:1 [atomic ratio] or a neighborhood thereof, a metal oxide of In:Zn = 4:1 [atomic ratio] or a neighborhood thereof, a metal oxide of In:Sn:Zn = 4:0.1:1 [atomic ratio] or a neighborhood thereof, or an indium oxide is preferably used. Further, as the oxide layer 230b and the oxide layer 230c, a metal oxide of In:Ga:Zn = 1:1:1 [atomic ratio] or a neighborhood thereof, a metal oxide of In:Ga:Zn = 1:3:2 [atomic ratio] or a neighborhood thereof, or a metal oxide of In:Ga:Zn = 1:3:4 [atomic ratio] or a neighborhood thereof is preferably used.

[0163] The band gap of the oxide layer 230b and the oxide layer 230c is preferably larger than that of the oxide layer 230a. Thus, the oxide layer 230a is sandwiched by the oxide layers 230b and 230c with a large band gap, and the oxide layer 230a is mainly used as a current path (channel). By sandwiching the oxide layer 230a with the oxide layers 230b and 230c, the trap level at the interface of the oxide layer 230a and its vicinity can be reduced. Thus, an embedded channel type transistor in which the channel is away from the interface of the insulating layer can be implemented, and thus the field-effect mobility can be increased. Further, the influence of the interface state which can be formed on the back channel side can be reduced to suppress the photo degradation (e.g., photo negative bias temperature instability) of the transistor, and thus the reliability of the transistor can be increased.

[0164] The thickness of the oxide semiconductor layer 230 is preferably greater than or equal to 3 nm and less than or equal to 200 nm, preferably greater than or equal to 3 nm and less than or equal to 100 nm, more preferably greater than or equal to 5 nm and less than or equal to 100 nm, further preferably greater than or equal to 10 nm and less than or equal to 100 nm, still further preferably greater than or equal to 10 nm and less than or equal to 70 nm, yet further preferably greater than or equal to 15 nm and less than or equal to 70 nm, furthermore preferably greater than or equal to 15 nm and less than or equal to 50 nm, and still furthermore preferably greater than or equal to 20 nm and less than or equal to 50 nm. In a transistor used for a more miniaturized semiconductor device, the thickness of the oxide semiconductor layer 230 is preferably greater than or equal to 1 nm, greater than or equal to 3 nm, or greater than or equal to 5 nm and less than or equal to 20 nm, less than or equal to 15 nm, less than or equal to 12 nm, or less than or equal to 10 nm.

[0165] Hydrogen included in the oxide semiconductor reacts with oxygen bonded to a metal atom to generate water in some cases, and thus an oxygen vacancy (V O ) is formed in the oxide semiconductor. Further, hydrogen enters a defect (hereinafter referred to as a hydrogen atom) in the oxygen vacancy in some cases. OH) is used as a donor to generate an electron which is a carrier. Furthermore, at times, an electron which is a carrier is generated due to a part of hydrogen bonding with oxygen bonded to a metal atom. Thus, a transistor using an oxide semiconductor containing a large amount of hydrogen easily has a normally-on characteristic (i.e., a threshold voltage is negative). Furthermore, because hydrogen in an oxide semiconductor easily moves due to heat, an electric field, or the like, the reliability of a transistor can be reduced when an oxide semiconductor contains a large amount of hydrogen.

[0166] That is, it is preferable to reduce V O H in the oxide semiconductor layer 230 as much as possible so that the oxide semiconductor layer 230 is high-purity intrinsic or substantially high-purity intrinsic. In order to obtain such V O H in the oxide semiconductor, it is important to remove impurities such as water and hydrogen from the oxide semiconductor (sometimes referred to as dehydration or dehydrogenation treatment) and to supply oxygen to the oxide semiconductor to repair oxygen vacancies. By reducing V O H and the like in the oxide semiconductor to a sufficient extent, the oxide semiconductor is used for a channel formation region of a transistor, which can impart stable electrical characteristics. Note that a process in which oxygen is supplied to the oxide semiconductor to repair oxygen vacancies is referred to as oxidation treatment.

[0167] The carrier concentration of the oxide semiconductor used for the region serving as the channel formation region is preferably 1 x 10 18 cm -3 The carrier concentration of the oxide semiconductor used for the region serving as the channel formation region is preferably 1 x 10 17 cm -3 The carrier concentration of the oxide semiconductor used for the region serving as the channel formation region is preferably 1 x 10 16 cm -3 The carrier concentration of the oxide semiconductor used for the region serving as the channel formation region is preferably 1 x 10 13 cm -3 The carrier concentration of the oxide semiconductor used for the region serving as the channel formation region is preferably 1 x 10 12 cm -3 The carrier concentration of the oxide semiconductor used for the region serving as the channel formation region is preferably 1 x 10 -9 cm -3

[0168] Here, the effects of each impurity in a metal oxide (oxide semiconductor) are described.

[0169] When the oxide semiconductor contains silicon or carbon which is one of Group 14 elements, a defect state is formed in the oxide semiconductor. Thus, the carbon concentration in the channel formation region of the oxide semiconductor is set to be lower than or equal to 1 x 10 20 atoms / cm 3 The carbon concentration in the channel formation region of the oxide semiconductor is preferably lower than or equal to 5 x 10 19 atoms / cm 3 The carbon concentration in the channel formation region of the oxide semiconductor is more preferably lower than or equal to 3 x 10​19 atoms / cm 3 atoms / cm 19 atoms / cm 3 atoms / cm 18 atoms / cm 3 atoms / cm 18 atoms / cm 3 atoms / cm 20 atoms / cm 3 atoms / cm 19 atoms / cm 3 atoms / cm 19 atoms / cm 3 atoms / cm 19 atoms / cm 3 atoms / cm 18 atoms / cm 3 atoms / cm 18 atoms / cm 3 atoms / cm

[0170] Further, when the oxide semiconductor contains nitrogen, electrons serving as carriers are generated, so that the carrier concentration is increased, and the oxide semiconductor is easily n- doped. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor easily has an always-on characteristic. Alternatively, when the oxide semiconductor contains nitrogen, a trap state is sometimes formed. As a result, the electric characteristics of the transistor are sometimes unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor is set to be lower than or equal to 1 x 10 20 atoms / cm 3 atoms / cm 19 atoms / cm 3 atoms / cm 19 atoms / cm 3 atoms / cm 18 atoms / cm 3 atoms / cm 18 atoms / cm 3 atoms / cm 17 atoms / cm 3 atoms / cm

[0171] Further, hydrogen included in the oxide semiconductor reacts with oxygen bonded to a metal atom to generate water, and thus an oxygen vacancy is sometimes formed. When hydrogen enters the oxygen vacancy, an electron serving as a carrier is sometimes generated. Further, an electron serving as a carrier is sometimes generated because a part of hydrogen is bonded to oxygen bonded to a metal atom. Thus, a transistor using an oxide semiconductor including hydrogen tends to have a normally-on characteristic. Thus, it is preferable to reduce hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor is set to be lower than or equal to 1 x 10 20 atoms / cm 3 , preferably lower than or equal to 5 x 10 19 atoms / cm 3 , more preferably lower than or equal to 1 x 10 19 atoms / cm 3 , further more preferably lower than or equal to 5 x 10 18 atoms / cm 3 , and still further more preferably lower than or equal to 1 x 10 18 atoms / cm 3 .

[0172] Further, when the oxide semiconductor includes an alkali metal or an alkaline earth metal, a defect state is sometimes formed to generate a carrier. Thus, a transistor using an oxide semiconductor including an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Thus, the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor is set to be lower than or equal to 1 x 10 18 atoms / cm 3 , preferably lower than or equal to 2 x 10 16 atoms / cm 3 .

[0173] By using an oxide semiconductor in which impurities are sufficiently reduced for the channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0174] Further, a transistor using another semiconductor material in the channel formation region can be used for the semiconductor device of this embodiment. As the other semiconductor material, for example, a semiconductor composed of a single element or a compound semiconductor can be given. As the semiconductor composed of a single element, for example, silicon or germanium can be given. As the compound semiconductor, for example, gallium arsenide and silicon germanium can be given. Further, as the compound semiconductor, for example, an organic semiconductor and a nitride semiconductor can be given. The above oxide semiconductor is one of compound semiconductors. These semiconductor materials can include impurities as dopants.

[0175] As a semiconductor material that can be used as a transistor, single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon can be given. As polycrystalline silicon, for example, low-temperature polysilicon (LTPS: Low Temperature Poly Silicon) can be given.

[0176] Further, the semiconductor layer of the transistor can also include a layered substance that is used as a semiconductor. The layered substance is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked by bonds such as van der Waals force, which are weaker than covalent bonds or ionic bonds. The layered substance has high conductivity in a unit layer, i.e., has high two-dimensional conductivity. By using a material that is used as a semiconductor and has high two-dimensional conductivity for a channel formation region, a transistor with a large on-state current can be provided.

[0177] As the above layered substance, for example, graphene, silicene, chalcogenide, and the like can be given. The chalcogenide is a compound including an oxygen group element (a group 16 element). Further, as the chalcogenide, a transition metal chalcogenide, a group 13 chalcogenide, and the like can be given. As the transition metal chalcogenide that can be used as a semiconductor layer of a transistor, specifically, molybdenum sulfide (typically, MoS2), molybdenum selenide (typically, MoSe2), molybdenum telluride (typically, MoTe2), tungsten sulfide (typically, WS2), tungsten selenide (typically, WSe2), tungsten telluride (typically, WTe2), hafnium sulfide (typically, HfS2), hafnium selenide (typically, HfSe2), zirconium sulfide (typically, ZrS2), zirconium selenide (typically, ZrSe2), and the like can be given.

[0178] [Insulating layer] As the insulating layer included in the semiconductor device (the insulating layer 210, the insulating layer 250, the insulating layer 280, the insulating layer 283, the insulating layer 285, and the like), an inorganic insulating film is preferably used. As the inorganic insulating film, for example, an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film can be given. As the oxide insulating film, for example, a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, a yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminum oxide film can be given. As the nitride insulating film, for example, a silicon nitride film and an aluminum nitride film can be given. As the oxynitride insulating film, for example, a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, a yttrium oxynitride film, and a hafnium oxynitride film can be given. As the nitride oxide insulating film, for example, a silicon nitride oxide film and an aluminum nitride oxide film can be given. Further, as the insulating layer included in the semiconductor device, an organic insulating film can also be used.

[0179] For example, with the progress of miniaturization and high integration of transistors, problems such as leakage current sometimes occur due to thinning of the gate insulating layer. By using a high-k material for the gate insulating layer, it is possible to achieve low voltage during transistor operation while maintaining the physical thickness. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the gate insulating layer. On the other hand, by using a material with a low relative dielectric constant for the insulating layer serving as an interlayer film, it is possible to reduce the parasitic capacitance generated between wirings. Therefore, it is preferable to select the material in accordance with the function of the insulating layer. In addition, a material with a low relative dielectric constant is also a material with a large dielectric strength.

[0180] As a material with a high relative dielectric constant (high-k), for example, there can be mentioned aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium, and the like.

[0181] As a material with a low relative dielectric constant, for example, there can be mentioned inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, resins such as polyester, polyolefin, polyamide (nylon, aromatic polyamide, and the like), polyimide, polycarbonate, and acrylic resin. In addition, as an inorganic insulating material with a low relative dielectric constant other than the above, for example, there can be mentioned silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and the like. In addition, there can be mentioned porous silicon oxide. In addition, these silicon oxides can also contain nitrogen.

[0182] In addition, as the insulating layer included in the semiconductor device, a material that can have ferroelectricity can also be used. As a material that can have ferroelectricity, there can be mentioned hafnium oxide, zirconium oxide, HfZrO X (X is a real number greater than 0) and the like. In addition, as a material that can have ferroelectricity, there can be mentioned a material to which an element J1 (here, the element J1 is one or a plurality of elements selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, and the like) is added to hafnium oxide. Here, the ratio of the number of atoms of hafnium atoms to the number of atoms of the element J1 can be appropriately set, and for example, the ratio of the number of atoms of hafnium atoms to the number of atoms of the element J1 can be set to 1:1 or the vicinity thereof. In addition, as a material that can have ferroelectricity, there can be mentioned a material to which an element J2 (here, the element J2 is one or a plurality of elements selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, and the like) is added to zirconium oxide, and the like. In addition, the ratio of the number of atoms of zirconium atoms to the number of atoms of the element J2 can be appropriately set, and for example, the ratio of the number of atoms of zirconium atoms to the number of atoms of the element J2 can be set to 1:1 or the vicinity thereof. In addition, as a material that can have ferroelectricity, lead titanate (PbTiO X), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), barium titanate, and the like having a perovskite structure.

[0183] Further, as a material that can have ferroelectricity, a metal nitride containing an element M1, an element M2, and nitrogen can be given. Here, the element M1 is one or more selected from aluminum, gallium, indium, and the like. Further, the element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, and the like. Further, the atomic ratio of the element M1 and the element M2 can be appropriately set. Further, a metal oxide containing the element M1 and nitrogen sometimes has ferroelectricity even if the element M2 is not contained. Further, as a material that can have ferroelectricity, a material to which an element M3 is added to the above metal nitride can be given. Note that the element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, and the like. Here, the atomic ratio of the element M1, the element M2, and the element M3 can be appropriately set.

[0184] Further, as a material that can have ferroelectricity, a perovskite-type oxynitride such as SrTaO2N, BaTaO2N, and the like, GaFeO3 which is a κ-type aluminum oxide, and the like can be given.

[0185] Note that examples of the metal oxide and the metal nitride are shown in the above description, but not limited thereto. For example, a metal oxynitride to which nitrogen is added to the above metal oxide or a metal nitride oxide to which oxygen is added to the above metal nitride, or the like can be used.

[0186] Further, as a material that can have ferroelectricity, for example, a mixture or a compound composed of a plurality of materials selected from the above materials can be used. Further, the insulating layer can have a stacked structure composed of a plurality of materials selected from the above materials. Note that the crystal structure (property) of the above listed materials and the like can be changed not only depending on deposition conditions but also depending on various processes and the like, and thus in this specification and the like, a material exhibiting ferroelectricity is not only referred to as a ferroelectric but also as a material that can have ferroelectricity.

[0187] A metal oxide containing one or both of hafnium and zirconium can have ferroelectricity even if it is processed into a thin film of several nm. Further, a metal oxide containing one or both of hafnium and zirconium can have ferroelectricity even if its area is small. Thus, by using a metal oxide containing one or both of hafnium and zirconium, miniaturization of a semiconductor device can be achieved.

[0188] Note that in this specification and the like, a material that can have ferroelectricity formed in a layered shape is sometimes referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Further, in this specification and the like, a device including a ferroelectric layer, a metal oxide film, or a metal nitride film is sometimes referred to as a ferroelectric device.

[0189] Further, the ferroelectricity is considered to be exhibited because oxygen or nitrogen of the crystal included in the ferroelectric layer is displaced by an external electric field. Further, the exhibition of the ferroelectricity is presumed to depend on the crystal structure of the crystal included in the ferroelectric layer. Thus, in order for the insulating layer to exhibit the ferroelectricity, the insulating layer needs to include a crystal. In particular, the insulating layer preferably has a crystal having an orthorhombic crystal structure, whereby the ferroelectricity is exhibited. The crystal structure of the crystal included in the insulating layer can be any one or a plurality of selected from the isometric system, the tetragonal system, the orthorhombic system, the monoclinic system, and the hexagonal system. Further, the insulating layer can also have an amorphous structure. At this time, the insulating layer can also have a composite structure of an amorphous structure and a crystal structure.

[0190] Further, by surrounding the transistor using a metal oxide with an insulating layer having a function of suppressing the penetration of impurities and oxygen, the electric characteristics of the transistor can be stabilized. As the insulating layer having a function of suppressing the penetration of impurities and oxygen, for example, a single layer or a stack of an insulating layer including one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used. Specifically, as the material of the insulating layer having a function of suppressing the penetration of impurities and oxygen, a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, an aluminum nitride, silicon oxynitride, a silicon nitride, or the like can be used.

[0191] Specifically, as the insulating layer having a function of suppressing the penetration of impurities such as water and hydrogen and oxygen, for example, a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide can be given. Further, as the insulating layer having a function of suppressing the penetration of impurities such as water and hydrogen and oxygen, for example, an oxide including aluminum and hafnium (hafnium aluminate) can be given. In addition, as the insulating layer having a function of suppressing the penetration of impurities such as water and hydrogen and oxygen, for example, a metal nitride such as aluminum nitride, silicon oxynitride, and silicon nitride can be given.

[0192] Further, the insulating layer in contact with the oxide semiconductor layer such as a gate insulating layer or the insulating layer provided in the vicinity of the oxide semiconductor layer preferably has a region including oxygen which is separated by heating (hereinafter referred to as excess oxygen). For example, by bringing the insulating layer having a region including excess oxygen into contact with or in the vicinity of the oxide semiconductor layer, the oxygen vacancy in the oxide semiconductor layer can be reduced. As the insulating layer in which a region including excess oxygen is easily formed, silicon oxide, silicon oxynitride, or porous silicon oxide, or the like can be given.

[0193] The insulating layer 210 is used as an interlayer film, and thus its relative dielectric constant is preferably low. By using a material with a low relative dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced. Since silicon oxide and silicon oxynitride have thermal stability, they are suitable for use as the insulating layer 210.

[0194] Further, the impurity concentration of water, hydrogen, or the like in the insulating layer 210 is preferably reduced. By this, the mixing of impurities such as water and hydrogen into the channel formation region of the oxide semiconductor layer 230 can be inhibited.

[0195] As the insulating layer 210, a hydrogen-blocking insulating layer is preferably used. By providing the insulating layer 210 which has a hydrogen-blocking property outside the oxide semiconductor layer 230, the diffusion of hydrogen into the oxide semiconductor layer 230 can be inhibited.

[0196] As a material of the hydrogen-blocking insulating layer, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be given.

[0197] In this specification and the like, a blocking insulating layer refers to an insulating layer having a blocking property. Further, the blocking property refers to a property that a corresponding substance is not easily diffused (a property that a corresponding substance is not easily permeated, a property that the permeability of a corresponding substance is low, or a function of inhibiting the diffusion of a corresponding substance). Further, hydrogen which is a corresponding substance refers to at least one of a hydrogen atom, a hydrogen molecule, a water molecule, and a substance which is bonded to hydrogen, for example. Further, unless otherwise specified, an impurity which is a corresponding substance refers to an impurity in a channel formation region or in a semiconductor layer, and refers to at least one of a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N2O, NO, NO2, or the like), a copper atom, and the like, for example. Further, oxygen which is a corresponding substance refers to at least one of an oxygen atom and an oxygen molecule, for example. -

[0198] For example, as the insulating layer 210, a silicon nitride film is preferably used.

[0199] The insulating layer 280 is preferably a hydrogen-blocking insulating layer described above. The insulating layer 280 is provided so as to surround the oxide semiconductor layer 230. By providing the insulating layer 280 which has a hydrogen-blocking property outside the oxide semiconductor layer 230, the diffusion of hydrogen into the oxide semiconductor layer 230 can be inhibited. For example, the insulating layer 280 preferably includes a silicon nitride film.

[0200] Further, silicon nitride has an oxygen-blocking property. Thus, by using silicon nitride for the insulating layer 280, the formation of excess oxygen vacancies in the oxide semiconductor layer 230 due to the detachment of oxygen from the oxide semiconductor layer 230 can be inhibited.

[0201] ​Further, by using silicon nitride for the insulating layer 280, excess oxygen can be prevented from being supplied to the oxide semiconductor layer 230. Thus, the channel formation region of the oxide semiconductor layer 230 can be prevented from being excess-oxygen, and the reliability of the transistor 200 can be improved.

[0202] Further, the insulating layer 280 preferably includes the above-described insulating film including excess oxygen, the insulating film including excess oxygen and nitrogen, or the insulating layer including a region including excess oxygen.

[0203] For example, the insulating layer including a region including excess oxygen can be formed by a sputtering method in an atmosphere containing oxygen. By using a sputtering method which does not need to use a molecule containing hydrogen as a deposition gas, the hydrogen concentration in the insulating layer 280 can be reduced. Thus, by depositing the insulating layer 280, oxygen can be supplied from the insulating layer 280 to the channel formation region of the oxide semiconductor layer 230, and oxygen vacancies and VoH can be reduced.

[0204] Further, the impurity concentration of water, hydrogen, or the like in the insulating layer 280 is preferably reduced. Thus, the entry of impurities such as water and hydrogen into the channel formation region of the oxide semiconductor layer 230 can be suppressed.

[0205] Note that the thickness of the insulating layer 280 over the conductive layer 220 corresponds to the channel length of the transistor 200, and is thus set to an appropriate value in accordance with the design value of the channel length of the transistor 200.

[0206] For example, as the insulating layer 280, a single-layer structure of a silicon nitride film is preferably used. Alternatively, for example, as the insulating layer 280, a three-layer structure in which a silicon nitride film, a silicon oxide film, and a silicon nitride film are sequentially stacked is preferably used.

[0207] The insulating layer 250 preferably has a function of trapping and fixing hydrogen. Thus, the hydrogen concentration of the oxide semiconductor layer 230 (particularly, the hydrogen concentration in the channel formation region of the transistor) can be reduced. Accordingly, the V O H in the channel formation region can be reduced to make the channel formation region i-type or substantially i-type.

[0208] Materials used as insulating layers with the function of trapping or fixing hydrogen include metal oxides such as hafnium oxides, magnesium oxides, aluminum oxides, and oxides containing both aluminum and hafnium (hafnium aluminate). Furthermore, these metal oxides may also contain zirconium; for example, oxides containing both hafnium and zirconium can be cited. In metal oxides with amorphous structures, the ability to trap or fix hydrogen is high because some oxygen atoms have dangling bonds. Therefore, these metal oxides preferably have an amorphous structure. For example, an amorphous structure can be achieved by including silicon in these oxides. For example, oxides containing both hafnium and silicon (hafnium silicate) are preferred. Furthermore, sometimes a portion of the metal oxide has one or both of a crystalline region and a grain boundary.

[0209] Furthermore, the function of capturing or fixing the corresponding substance can also be described as possessing the property that the corresponding substance is not easily diffused. Therefore, the function of capturing or fixing the corresponding substance can also be referred to as barrier property.

[0210] The insulation layer 250 can be a two-layer structure. FIG. 9A and FIG. 9B Show FIG. 1B The example shown is an example of a two-layer structure of insulating layer 250 having insulating layer 250a and insulating layer 250b on insulating layer 250a.

[0211] When the insulating layer 250 has a stacked structure, the layer in contact with the oxide semiconductor layer 230 preferably has the function of trapping and fixing hydrogen. That is, in FIG. 2A and FIG. 2B In this process, insulating layer 250a preferably has the function of capturing and fixing hydrogen. Furthermore, as insulating layer 250b, the aforementioned hydrogen-blocking insulating layer is preferably used.

[0212] By utilizing the hydrogen-trapping or fixing function of the insulating layer 250a, hydrogen contained in the oxide semiconductor layer 230 can be trapped or fixed more effectively. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced. Hafnium silicate is preferably used as the insulating layer 250a, for example. Furthermore, the insulating layer 250a preferably has an amorphous structure.

[0213] By giving the insulating layer 250a an amorphous structure, the formation of grain boundaries can be suppressed. Suppressing grain boundary formation improves the flatness of the insulating layer 250a film. Consequently, the thickness distribution of the insulating layer 250a becomes more uniform, reducing extremely thin sections and thus improving the withstand voltage of the insulating layer 250a. Furthermore, it allows for a more uniform thickness distribution of the film disposed on the insulating layer 250a.

[0214] Further, by inhibiting formation of grain boundaries in the insulating layer 250a, a leakage current due to a defect state of the grain boundaries can be reduced. Thus, the insulating layer 250a can be used as an insulating film with a small leakage current.

[0215] Further, since hafnium oxide is a high-k material, hafnium silicate becomes a high-k material depending on the silicon content. Thus, when the insulating layer 250a is used as a gate insulating layer, the gate potential applied at the time of transistor operation can be reduced while the physical thickness of the gate insulating layer is maintained. Further, the equivalent oxide thickness (EOT) of the gate insulating layer can be reduced.

[0216] By using a hydrogen barrier insulating layer as the insulating layer 250b, diffusion of impurities contained in the conductive layer 260 to the oxide semiconductor layer 230 can be inhibited. Silicon nitride has high hydrogen barrier properties, and is thus suitable for use as the insulating layer 250b.

[0217] By employing the above structure, a semiconductor device with good electrical characteristics can be provided. Further, a semiconductor device with high reliability can be provided. Further, a semiconductor device in which the electrical characteristics of transistors are less likely to be non-uniform can be provided. Further, a semiconductor device with a large on-state current can be provided.

[0218] In addition, the insulating layer 250 preferably uses a high-k material. Further, as one example of the high-k material, there is an oxide containing one or both of aluminum and hafnium. When a high-k material is used as the insulating layer 250, the gate potential applied at the time of transistor operation can be reduced while the physical thickness of the gate insulating layer is maintained. Further, the equivalent oxide thickness (EOT) of the insulating layer used as the gate insulating layer can be reduced.

[0219] Thus, as the insulating layer 250a, an oxide containing one or both of aluminum and hafnium is preferably used, an oxide having an amorphous structure and containing one or both of aluminum and hafnium is more preferably used, and an aluminum oxide having an amorphous structure is further preferably used.

[0220] Further, the insulating layer 250 can include an insulating layer having a structure stable to heat, such as a silicon oxide or a silicon oxynitride.

[0221] In addition, the insulating layer 250 can include an insulating layer having a thermally stable structure between a pair of insulating layers having a function of trapping and fixing hydrogen.

[0222] In addition, the insulating layer 250 preferably includes an oxygen barrier insulating layer. Thus, oxidation of the conductive layer 240, the conductive layer 260, and the like can be inhibited. When the insulating layer 250 has a stacked structure, the layer in contact with the conductive layer 240 and the layer in contact with the conductive layer 260 are preferably both oxygen barrier insulating layers.

[0223] For example, by using a barrier insulating layer of hydrogen and oxygen as the insulating layer 250b described above, oxidation of the conductive layer 260 can be suppressed. Further, diffusion of oxygen contained in the oxide semiconductor layer 230 to the conductive layer 260 can be suppressed, so that oxygen vacancies can be formed in the oxide semiconductor layer 230.

[0224] As the oxygen barrier insulating layer, for example, an oxide containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium-zinc oxide, indium-gallium-zinc oxide, silicon nitride, and silicon oxynitride can be given. As the oxide containing one or both of aluminum and hafnium, for example, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate) can be given.

[0225] The layer of the insulating layer 250 which is in contact with the conductive layer 240 is preferably less likely to transmit oxygen than the insulating layer 280. When the layer has an oxygen barrier property, the side surface of the conductive layer 240 can be prevented from being oxidized and an oxide film can be formed on the side surface. Thus, a decrease in on-state current or a decrease in field-effect mobility of the transistor 200 can be suppressed.

[0226] The thickness of the insulating layer 250 is preferably greater than or equal to 0.1 nm and less than or equal to 30 nm, preferably greater than or equal to 0.1 nm and less than or equal to 20 nm, preferably greater than or equal to 0.1 nm and less than or equal to 10 nm, more preferably greater than or equal to 0.1 nm and less than or equal to 5.0 nm, still more preferably greater than or equal to 0.5 nm and less than or equal to 5.0 nm, further more preferably greater than or equal to 1.0 nm and less than 5.0 nm, and even more preferably greater than or equal to 1.0 nm and less than or equal to 3.0 nm.

[0227] Further, as the insulating layer 250, a three-layer structure in which a first insulating layer containing a material with a low relative dielectric constant, a second insulating layer having a function of trapping or fixing hydrogen, and a third insulating layer having an oxygen and hydrogen barrier property are sequentially stacked from the oxide semiconductor layer 230 side is preferably used. As the material with a low relative dielectric constant contained in the first insulating layer, silicon oxide or silicon oxynitride is preferably used. The first insulating layer is in contact with the oxide semiconductor layer 230. By using an oxide as the first insulating layer, oxygen can be supplied to the oxide semiconductor layer 230. Further, by providing the third insulating layer, diffusion of oxygen contained in the first insulating layer to the conductive layer 260 can be suppressed, so that oxidation of the conductive layer 260 can be suppressed. Further, the amount of oxygen supplied from the first insulating layer to the oxide semiconductor layer 230 can be reduced.

[0228] As the insulating layer 250, a four-layer structure in which a fourth insulating layer having oxygen blocking properties, a first insulating layer containing a material with low relative dielectric constant, a second insulating layer having a function of trapping or fixing hydrogen, and a third insulating layer having hydrogen and oxygen blocking properties are sequentially stacked from the oxide semiconductor layer 230 side is preferably used. The first insulating layer to the third insulating layer can have the same structure as that of the layers used for the above three-layer structure. The fourth insulating layer is a layer in contact with the oxide semiconductor layer 230. When the fourth insulating layer has oxygen blocking properties, separation of oxygen from the oxide semiconductor layer 230 can be inhibited. As the fourth insulating layer, for example, aluminum oxide is preferably used. Since aluminum oxide has a function of trapping or fixing hydrogen, it is suitable as the fourth insulating layer in contact with the oxide semiconductor layer 230.

[0229] In order to achieve miniaturization of a transistor, the thickness of each layer forming the insulating layer 250 is preferably small. The thickness of each layer forming the insulating layer 250 is preferably greater than or equal to 0.1 nm and less than or equal to 10 nm, more preferably greater than or equal to 0.1 nm and less than or equal to 5 nm, further preferably greater than or equal to 0.5 nm and less than or equal to 5 nm, still further preferably greater than or equal to 1 nm and less than 5 nm, and still further preferably greater than or equal to 1 nm and less than or equal to 3 nm. Note that at least a part of each layer forming the insulating layer 250 can have a region with the above thickness.

[0230] Typically, the thicknesses of the fourth insulating layer, the first insulating layer, the second insulating layer, and the third insulating layer are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. With such a structure, a transistor can have good electrical characteristics even when the transistor is miniaturized or highly integrated.

[0231] As the insulating layer 283, a hydrogen-blocking insulating layer is preferably used. With this structure, hydrogen can be inhibited from diffusing into the oxide semiconductor layer 230 from above the insulating layer 283. Since both a silicon nitride film and a silicon oxynitride film have characteristics that impurities (e.g., water and hydrogen) released from themselves are small and oxygen and hydrogen are not easily permeable, they can be suitably used for the insulating layer 283.

[0232] As the insulating layer 283, a silicon nitride deposited by a sputtering method is particularly preferably used. Since the sputtering method does not need to use a molecule containing hydrogen for deposition gas, the hydrogen concentration of the insulating layer 283 can be reduced. By depositing the insulating layer 283 using a sputtering method, a silicon nitride with high density can be formed.

[0233] Further, as the insulating layer 283, an insulating layer having a function of trapping or fixing hydrogen can be used. With such a structure, hydrogen can be inhibited from diffusing into the oxide semiconductor layer 230 from above the insulating layer 283, and hydrogen contained in the oxide semiconductor layer 230 can be trapped or fixed. Thus, the hydrogen concentration of the oxide semiconductor layer 230 can be reduced. As the insulating layer 283, hafnium silicate or the like can be used.

[0234] Further, as the insulating layer 283, a stacked structure of an insulating layer having a function of trapping or fixing hydrogen and a hydrogen barrier insulating layer can be used. For example, as the insulating layer 283, a stacked film of aluminum oxide and silicon nitride over the aluminum oxide can be used.

[0235] [Conductive layer] As the conductive layer included in the semiconductor device (the conductive layer 220, the conductive layer 240, the conductive layer 260, and the like), a metal element selected from tungsten, copper, aluminum, chromium, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, and the like, an alloy including the above metal element, or an alloy combining the above metal elements, and the like is preferably used. As the alloy including the above metal element, a nitride of the alloy or an oxide of the alloy can be used. For example, tantalum nitride, titanium nitride, ruthenium nitride, a nitride including molybdenum, a nitride including tungsten, titanium, and aluminum, a nitride including tantalum and aluminum, ruthenium oxide, an oxide including strontium and ruthenium, an oxide including lanthanum and nickel, and the like are preferably used. Further, a semiconductor having high conductivity typified by polysilicon including an impurity element such as phosphorus and a silicide such as nickel silicide can be used.

[0236] Further, a conductive material including nitrogen such as a nitride including tantalum, a nitride including titanium, a nitride including molybdenum, a nitride including tungsten, a nitride including ruthenium, a nitride including tantalum and aluminum, or a nitride including titanium and aluminum, a conductive material including oxygen such as ruthenium oxide, an oxide including strontium and ruthenium, or an oxide including lanthanum and nickel, a material including a metal element such as titanium, tantalum, or ruthenium, which is not easily oxidized, a conductive material having a function of inhibiting diffusion of oxygen, or a material which absorbs oxygen and maintains conductivity is preferable. As the conductive material including oxygen, indium oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide (also referred to as ITO), indium tin oxide including titanium oxide, indium tin oxide to which silicon is added (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), indium zinc oxide including tungsten oxide, and the like can be given. In this specification and the like, a conductive film deposited using a conductive material including oxygen is sometimes referred to as an oxide conductive film.

[0237] A conductive material whose main component is tungsten, copper, or aluminum has high conductivity and is therefore preferable.

[0238] Further, a plurality of conductive layers formed of the above-described materials can be stacked. For example, a stacked structure combining a material including the above metal element and a conductive material including oxygen can be used. Further, a stacked structure combining a material including the above metal element and a conductive material including nitrogen can be used. Further, a stacked structure combining a material including the above metal element, a conductive material including oxygen, and a conductive material including nitrogen can be used.

[0239] Further, in the case where a metal oxide is used for the channel formation region of the transistor, a stacked-layer structure in which a material containing the above metal element and a conductive material containing oxygen are combined is preferably employed as the conductive layer used as the gate electrode. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0240] As the conductive layer 260, the above metal element, an alloy containing the above metal element, an alloy in which the above metal elements are combined, or the like can be used. For example, a material with high conductivity such as tungsten is preferably used. Further, as the conductive layer 260, a conductive material which is not easily oxidized or a conductive material having a function of inhibiting diffusion of oxygen, or the like is preferably used. As the conductive material, a conductive material containing nitrogen and a conductive material containing oxygen, or the like can be given as described above. Thus, the conductivity of the conductive layer 260 can be inhibited from decreasing.

[0241] The conductive layer 260 preferably uses a conductive material containing a metal element and oxygen included in the metal oxide forming the channel. Further, one or a plurality of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide to which silicon is added can be used. Further, indium gallium zinc oxide containing nitrogen can be used. By using the above material, hydrogen included in the metal oxide forming the channel can be sometimes trapped. Alternatively, hydrogen mixed from the outside from an insulating layer or the like can be sometimes trapped.

[0242] The conductive layer 260 can be, for example, greater than or equal to 3 nm and less than or equal to 500 nm. The thickness of the conductive layer 260 can be, for example, greater than or equal to the thickness of the insulating layer 250. By increasing the thickness of the conductive layer 260, the resistance of the conductive layer 260 can be reduced.

[0243] In the semiconductor device of one embodiment of the present application, a two-layer structure of the conductive layer 260a and the conductive layer 260b over the conductive layer 260a is preferably employed as the conductive layer 260.

[0244] A material which can be processed by wet etching is preferably used as the conductive layer 260a. Further, the conductive layer 260a is preferably a material with a high selectivity to the conductive layer 260b in wet etching. That is, the etching rate of the conductive layer 260a is preferably sufficiently higher than that of the conductive layer 260b. Further, the conductive layer 260a is preferably a material with a high selectivity to the insulating layer 250 in wet etching. That is, the etching rate of the conductive layer 260a is preferably sufficiently higher than that of the insulating layer 250.

[0245] Further, by using a conductive material having a function of suppressing diffusion of oxygen as the conductive layer 260a, for example, release of oxygen from the oxide semiconductor layer 230 can be suppressed, and formation of oxygen vacancies in the oxide semiconductor layer 230 can be suppressed.

[0246] Further, by using a conductive material which is not easily oxidized as the conductive layer 260a, for example, oxidation of the conductive layer 260a due to release of oxygen from the oxide semiconductor layer 230 or release of oxygen from the insulating layer 250, which leads to a decrease in conductivity, can be suppressed.

[0247] The material used for the conductive layer 260b is preferably, for example, higher in conductivity than the material used for the conductive layer 260a. Further, by increasing the thickness of the conductive layer 260b, the current flowing through the conductive layer 260b can be further increased.

[0248] The conductive layer 260a is preferably isotropically etched by a wet etching method or the like. In this specification, etching in which the end portion of the conductive layer 260a enters the inside of the end portion of the conductive layer 260b is referred to as side etching. When isotropic etching is used, the thicker the thickness of the conductive layer to be etched, the larger the width of the end portion of the conductive layer 260a which enters the inside of the end portion of the conductive layer 260b by side etching. When the width of side etching is increased, there is a possibility that coverage of the insulating layer 283 is decreased or the like. Further, when the region 277 is too large, there is a possibility that the end portion of the conductive layer 260b directly contacts the insulating layer 250, and the effect of increasing the insulating resistance of the insulating layer 250 is decreased. Thus, the conductive layer 260a is preferably appropriately thin.

[0249] Thus, for example, the thickness of the conductive layer 260b is preferably thicker than the thickness of the conductive layer 260a. The thickness of the conductive layer 260a is preferably, for example, 50 % or less, further preferably 30 % or less, of the total of the thickness of the conductive layer 260a and the thickness of the conductive layer 260b. By thinning the thickness of the conductive layer 260a, the width R can be made fine. Further, the region 277 can be formed by isotropic etching. The width R of the region 277 is formed depending on the thickness of the conductive layer 260a. By forming the conductive layer 260a to be thicker than or equal to a desired thickness, the leakage current between the conductive layer 260 and the conductive layer 240 can be appropriately reduced. The thickness of the conductive layer 260a can be, for example, 5 % or more or 10 % or more of the total of the thickness of the conductive layer 260a and the thickness of the conductive layer 260b.

[0250] Alternatively, the material used for the conductive layer 260a can have higher conductivity than the material used for the conductive layer 260b.

[0251] The conductive layer 260 can be embedded in the opening 290 by increasing the sum of the thickness of the conductive layer 260a and the thickness of the conductive layer 260b (i.e., the thickness of the conductive layer 260). By embedding the conductive layer 260 in the opening 290, the conductive layer (e.g., a plug, an electrode, a wiring, or the like) of the upper layer of the conductive layer 260 can be formed in the region of the conductive layer 260 overlapping with the opening 290.

[0252] The conductive layer 260 can be embedded in the opening 290 by the sum of the thickness of the conductive layer 260a and the thickness of the conductive layer 260b being 50% or more of the width D of the opening 290.

[0253] The conductive layer 260a can be appropriately formed along the side wall of the opening 290 by using a deposition method having high coverage as the conductive layer 260a.

[0254] As the conductive layer 260a, for example, a conductive material containing nitrogen, a conductive material containing oxygen, or the like can be used. Further, as the conductive layer 260a, for example, a conductive material containing a metal element contained in a metal oxide formed in a channel and oxygen can be used.

[0255] As the conductive layer 260a, for example, a conductive material containing the above metal element and nitrogen can be used, and for example, tantalum nitride, titanium nitride, ruthenium nitride, a nitride containing molybdenum, a nitride containing tungsten, titanium, and aluminum, a nitride containing tantalum and aluminum, or the like can be used.

[0256] Further, as the conductive layer 260a, for example, a conductive material containing the above metal element and oxygen can be used, and for example, ruthenium oxide, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like can be used.

[0257] Further, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide to which silicon is added can be used. Further, indium gallium zinc oxide containing nitrogen can be used.

[0258] As the conductive layer 260a, titanium, tantalum, ruthenium, and a material containing one or more of these metal elements are a conductive material that is not easily oxidized, a conductive material having a function of suppressing diffusion of oxygen, or a material that can maintain conductivity even if oxygen is absorbed, and thus are preferable.

[0259] As the conductive layer 260b, for example, the above metal element, an alloy containing the above metal element as a component, or an alloy in which the above metal elements are combined, or the like can be used. For example, tungsten can be used. Tungsten is sometimes highly resistant to a chemical solution used at the time of wet etching, and thus is preferable.

[0260] Furthermore, conductive layer 260a may also have a stacked structure. Furthermore, conductive layer 260b may also have a stacked structure. When conductive layer 260a has a stacked structure, for example, multiple materials suitable for conductive layer 260a can be stacked. Alternatively, multiple materials selected from those suitable for a conductive layer in one aspect of the present invention can be stacked. When conductive layer 260b has a stacked structure, for example, multiple materials suitable for use as conductive layer 260b can be stacked. Alternatively, multiple materials selected from those suitable for a conductive layer in one aspect of the present invention can be stacked.

[0261] Conductive layers 220 and 240 are conductive layers in contact with the oxide semiconductor layer 230, so it is preferable to use conductive materials that are not easily oxidized, conductive materials that maintain low resistance even when oxidized, oxide conductive materials, or conductive materials that have the function of inhibiting oxygen diffusion. Examples of such conductive materials include nitrogen-containing conductive materials and oxygen-containing conductive materials. As a result, the decrease in conductivity of conductive layers 220 and 240 can be suppressed.

[0262] By using an oxygen-containing conductive material as conductive layer 220 or conductive layer 240, conductivity can be maintained even if conductive layer 220 or conductive layer 240 absorbs oxygen. Furthermore, when an oxygen-containing insulating layer such as hafnium oxide is used as insulating layer 210, conductive layer 220 can also maintain conductivity, which is therefore preferred. For example, ITO, ITSO, and IZO (registered trademark) are preferred as conductive layers 220 and 240.

[0263] FIG. 3A and FIG. 3B Shown in FIG. 1B and FIG. 1C The conductive layer 220 has a three-layer structure consisting of a conductive layer 220a, a conductive layer 220b on the conductive layer 220a, and a conductive layer 220c on the conductive layer 220b; the conductive layer 240 has a two-layer structure consisting of a conductive layer 240a and a conductive layer 240b on the conductive layer 240a; and the insulating layer 280 has a three-layer structure consisting of an insulating layer 280a, an insulating layer 280b on the insulating layer 280a, and an insulating layer 280c on the insulating layer 280b. Furthermore, FIG. 3A and FIG. 3B and FIG. 1B and FIG. 1C The difference is that the former includes an insulating layer 222.

[0264] For example, it is preferable to use a conductive material that is not easily oxidized or a conductive material having a function of inhibiting diffusion of oxygen as the conductive layer 220a, to use a material with high conductivity as the conductive layer 220b, and to use a conductive material containing oxygen as the conductive layer 220c. Specifically, for example, it is preferable to use titanium nitride as the conductive layer 220a, to use tungsten as the conductive layer 220b, and to use ITO or ITSO as the conductive layer 220c. In this case, the titanium nitride is in contact with the insulating layer 210, and the ITO or ITSO is in contact with the oxide semiconductor layer 230. With such a structure, even when the conductive layer 220 is in contact with the oxide semiconductor layer 230, the conductivity can be maintained. Further, in the case where the insulating layer 210 is an oxide insulating layer, the conductive layer 220 can be inhibited from being excessively oxidized by the insulating layer 210. Furthermore, by using tungsten, which has high conductivity, as the conductive layer 220b, the conductivity of the conductive layer 220 can be increased.

[0265] In addition, FIG. 1B and FIG. 1C A structure in which the top surface of the conductive layer 220 is flat is shown, but the present application is not limited thereto. For example, as shown in FIG. 6A, a recessed portion overlapping with the opening 290 can be formed in the top surface of the conductive layer 220. By forming at least part of the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 in such a manner as to be embedded in the recessed portion, the gate electric field of the conductive layer 260 can be easily applied to the vicinity of the conductive layer 220 of the oxide semiconductor layer 230. FIG. 3A FIG. 3B In addition,

[0266] Further, in FIG. 3A and FIG. 3B , the conductive layer 240 has a two-layer structure of the conductive layer 240a and the conductive layer 240b over the conductive layer 240a. At this time, for example, it is preferable to use a material with higher conductivity than the conductive layer 240b as the conductive layer 240a, and to use a conductive material containing oxygen as the conductive layer 240b. Specifically, for example, it is preferable to use ruthenium, tungsten, titanium nitride, or tantalum nitride as the conductive layer 240a, and to use ITO or ITSO as the conductive layer 240b. In this case, the ITO or ITSO is in contact with the oxide semiconductor layer 230. With such a structure, even when the conductive layer 240 is in contact with the oxide semiconductor layer 230, the conductivity can be maintained. Further, by using a material with higher conductivity than the conductive layer 240b as the conductive layer 240a, the conductivity of the conductive layer 240 can be increased.

[0267] [Substrate] ​As a substrate for forming a transistor, an insulator substrate, a semiconductor substrate, or a conductor substrate can be used, for example. As an insulator substrate, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (a yttria-stabilized zirconia substrate or the like), a resin substrate, or the like can be given. Further, as a semiconductor substrate, a semiconductor substrate using silicon or germanium as a material, or a compound semiconductor substrate formed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or the like can be given. Further, a semiconductor substrate having an insulator region in the above-described semiconductor substrate, such as an SOI (Silicon On Insulator) substrate or the like can be given. As a conductor substrate, a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, or the like can be given. Alternatively, a substrate containing a metal nitride, a substrate containing a metal oxide, or the like can be given. Further, an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, a conductor substrate provided with a semiconductor or an insulator, or the like can be given. Alternatively, a substrate provided with an element over a substrate can be used. As an element provided over a substrate, a capacitor, a resistor, a switching element, a light-emitting element, a memory element, or the like can be given.

[0268] In the semiconductor device illustrated in FIG. 1A, the insulating layer 210 is provided with the insulating layer 222, the conductive layer 220, and the insulating layer 280. FIG. 3A FIG. 3B In the semiconductor device illustrated in FIG. 1A, the insulating layer 210 is provided with the insulating layer 222, the conductive layer 220, and the insulating layer 280.

[0269] As the insulating layer 222, an insulating layer having a function of trapping or fixing hydrogen is preferably used. By this means, hydrogen in the oxide semiconductor layer 230 is diffused through the conductive layer 220 to the insulating layer 222, and can be trapped or fixed. Thus, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced.

[0270] For example, it is preferable that a silicon nitride film be used as the insulating layer 210 and an oxide film containing hafnium and silicon (a hafnium silicate film) be used as the insulating layer 222.

[0271] In the semiconductor device illustrated in FIG. 1A, the insulating layer 210 is provided with the insulating layer 222, the conductive layer 220, and the insulating layer 280. FIG. 3A FIG. 3B In the semiconductor device illustrated in FIG. 1A, the insulating layer 210 is provided with the insulating layer 222, the conductive layer 220, and the insulating layer 280.

[0272] The insulating layer 280a has a region in contact with the top surface of the insulating layer 222, a region in contact with the side surface of the conductive layer 220, and a region in contact with the top surface of the conductive layer 220. The insulating layer 280c has a region in contact with the bottom surface of the conductive layer 240.

[0273] ​​The insulating layer 280b is in contact with the channel formation region of the oxide semiconductor layer 230. By using an insulating layer containing oxygen as the insulating layer 280b, oxygen can be supplied to the oxide semiconductor layer 230.

[0274] The insulating layer 280b preferably has a region with a higher oxygen content than at least one of the insulating layer 280a and the insulating layer 280c. In particular, the insulating layer 280b preferably has a region with a higher oxygen content than each of the insulating layer 280a and the insulating layer 280c. By increasing the oxygen content of the insulating layer 280b, an i-type region can be easily formed in the oxide semiconductor layer 230 in the vicinity of the insulating layer 280b.

[0275] As the insulating layer 280b, a film that releases oxygen by heating is more preferably used. Since the insulating layer 280b releases oxygen by heating in the manufacturing process of the transistor 200, oxygen can be supplied to the oxide semiconductor layer 230. By supplying oxygen from the insulating layer 280b to the oxide semiconductor layer 230, particularly to the channel formation region of the oxide semiconductor layer 230, oxygen vacancies and V O H, a transistor with good electrical characteristics and high reliability can be achieved.

[0276] Furthermore, in order to improve the electrical characteristics and reliability of the OS transistor, it is important to optimize the amount of oxygen supplied to the oxide semiconductor in a state where the hydrogen concentration in the oxide semiconductor is sufficiently reduced.

[0277] As one example, the amount of oxygen molecules released from the insulating layer 280b is preferably 1.0 x 10 14 molecules / cm 2 or less and less than 1.0 x 10 15 molecules / cm 2 Note that the amount of oxygen molecules released can be measured by thermal desorption spectroscopy.

[0278] In particular, in the case of a transistor 200 with a short channel length, the influence of oxygen vacancies and V O H on electrical characteristics and reliability is particularly large. Thus, by optimizing the amount of oxygen supplied to the oxide semiconductor layer 230 in a state where the hydrogen concentration in the oxide semiconductor layer 230 is sufficiently reduced, a short-channel-length transistor with good electrical characteristics and high reliability can be achieved.

[0279] The insulating layer 280b is preferably formed by a deposition method such as a sputtering method or a plasma-enhanced chemical vapor deposition (PECVD) method. In particular, when a sputtering method is used, hydrogen gas does not need to be used as a deposition gas, whereby a film with a small amount of hydrogen can be obtained. Thus, the supply of hydrogen to the oxide semiconductor layer 230 can be suppressed, leading to stabilization of the electric characteristics of the transistor 200.

[0280] In the case where the amount of oxygen supplied to the oxide semiconductor layer 230 is increased, for example, heat treatment in an oxygen atmosphere or plasma treatment in an oxygen atmosphere is preferably performed after the formation of the insulating layer 280b. Alternatively, an oxide film can be deposited on the top surface of the insulating layer 280b by a sputtering method in an oxygen atmosphere to supply oxygen. Then, the oxide film can be removed. By such a process, oxygen can be supplied to the insulating layer 280b to increase the amount of oxygen supplied to the oxide semiconductor layer 230.

[0281] Further, in the oxide semiconductor layer 230, the amount of oxygen supplied to a region in contact with the insulating layer 280a and a region in contact with the insulating layer 280c is smaller than that of a region in contact with the insulating layer 280b. Thus, the region in contact with the insulating layer 280a and the region in contact with the insulating layer 280c of the oxide semiconductor layer 230 are sometimes low-resistance. That is, by adjusting the thickness of the insulating layer 280a, the range of the region serving as one of the source region and the drain region can be controlled. Similarly, by adjusting the thickness of the insulating layer 280c, the range of the region serving as the other of the source region and the drain region can be controlled. In this manner, the thickness of the insulating layer 280a and the thickness of the insulating layer 280c can be appropriately set in accordance with the characteristics required for the transistor.

[0282] Further, as the insulating layer 280b, a material with a low relative dielectric constant is preferably used. By this means, the parasitic capacitance generated between wirings can be reduced. As the insulating layer 280b, for example, silicon oxide or silicon oxynitride can be used.

[0283] As the insulating layer 280a and the insulating layer 280c, an oxygen barrier insulating layer is preferably used. By providing the insulating layer 280a between the insulating layer 280b and the conductive layer 220, the resistance of the conductive layer 220 can be prevented from increasing due to oxidation of the conductive layer 220. Further, by providing the insulating layer 280c between the insulating layer 280b and the conductive layer 240, the resistance of the conductive layer 240 can be prevented from increasing due to oxidation of the conductive layer 240.

[0284] Further, as the insulating layer 280a, an insulating layer having a function of trapping or fixing hydrogen can be used. With such a structure, diffusion of hydrogen from below the insulating layer 280a to the oxide semiconductor layer 230 can be suppressed, and hydrogen contained in the oxide semiconductor layer 230 can be trapped or fixed. Thus, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced. As the insulating layer 280a, magnesium oxide, aluminum oxide, hafnium oxide, or an oxide containing hafnium and silicon, or the like can be used. Further, for example, as the insulating layer 280a, a stacked film of aluminum oxide and silicon nitride over the aluminum oxide can be used. Similarly, as the insulating layer 280c, an insulating layer having a function of trapping or fixing hydrogen can be used.

[0285] For example, silicon nitride can be used for the insulating layer 280a and the insulating layer 280c, and silicon oxide can be used for the insulating layer 280b.

[0286] <Example 1 of method for manufacturing semiconductor device> Next, a method for manufacturing a semiconductor device of one embodiment of the present application will be described with reference to FIGS. 5 to 8. Note that the materials and formation methods of the components are sometimes omitted in the description of the same as those already described.

[0287] The thin films (insulating films, semiconductor films, and conductive films, etc.) included in the semiconductor device can be formed by a sputtering method, a CVD method, a vacuum evaporation method, a PLD method, an ALD method, or the like.

[0288] As the sputtering method, an RF sputtering method in which a high-frequency power source is used as a sputtering power source, a DC sputtering method in which a direct-current power source is used, and a pulse DC sputtering method in which a voltage applied to a sputtering target is changed in a pulse manner can be given. The RF sputtering method is mainly used for deposition of an insulating film, and the DC sputtering method is mainly used for deposition of a metal conductive film. Further, the pulse DC sputtering method is mainly used for deposition of a compound such as an oxide, a nitride, or a carbide by a reactive sputtering method.

[0289] Further, the CVD method can be classified into a plasma CVD (PECVD) method using plasma, a thermal CVD (TCVD) method using heat, a photo CVD method using light, and the like. Further, the CVD method can be classified into a metal CVD (MCVD) method, a metal organic CVD (MOCVD) method, depending on a source gas used.

[0290] By utilizing the plasma CVD method, a high-quality film can be obtained at a low temperature. Further, because no plasma is used, the thermal CVD method is a deposition method that can reduce plasma damage to a processed object. For example, a wiring, an electrode, an element (transistor, capacitor, etc.), or the like included in a semiconductor device sometimes generates charge accumulation due to receiving a charge from plasma. At this time, the wiring, the electrode, the element, or the like included in the semiconductor device is sometimes damaged due to the accumulated charge. On the other hand, because the above-described plasma damage does not occur in the case of the thermal CVD method that does not use plasma, the yield of the semiconductor device can be improved. Further, in the thermal CVD method, plasma damage at the time of deposition does not occur, and thus a film with few defects can be obtained.

[0291] Further, as the ALD method, a thermal ALD method that causes only a precursor and a reactant to react by using thermal energy, a PEALD method that uses a reactant excited by plasma, or the like is employed.

[0292] The CVD method and the ALD method are different from a sputtering method in which particles released from a target or the like are deposited. Thus, the CVD method and the ALD method are deposition methods that are less likely to be affected by the shape of a processed object and have high step coverage. In particular, the ALD method has good step coverage and thickness uniformity, and thus the ALD method is suitable for use in a case where a surface of an opening with a high aspect ratio is covered, or the like. However, the deposition rate of the ALD method is relatively slow, and thus the ALD method is sometimes preferably used in combination with another deposition method such as the CVD method that has a fast deposition rate.

[0293] Further, when the CVD method is used, a film with an arbitrary composition can be deposited in accordance with the flow ratio of source gases. For example, when the CVD method is used, a film whose composition continuously changes can be deposited by changing the flow ratio of source gases while deposition is performed. When deposition is performed while the flow ratio of source gases is changed, because time required for transfer or adjustment of pressure is not needed, the deposition time can be shortened as compared with a case where deposition is performed using a plurality of deposition chambers. Thus, the productivity of a semiconductor device can be improved in some cases.

[0294] When the ALD method is used, a film with an arbitrary composition can be deposited by simultaneously introducing different kinds of precursors. Alternatively, when different kinds of precursors are introduced, a film with an arbitrary composition can be deposited by controlling the number of cycles of each precursor.

[0295] A thin film (insulating film, semiconductor film, and conductive film, etc.) that constitutes a semiconductor device can be formed using a wet deposition method such as a spin coating method, an immersion method, a spray coating method, an inkjet method, a dispenser method, a screen printing method, an offset printing method, a doctor knife method, a slit coating method, a roll coating method, a curtain coating method, or a blade coating method.

[0296] Furthermore, when the thin film constituting the semiconductor device is processed, photolithography or the like can be used. Alternatively, the thin film can be processed by nanoimprint, sandblasting, peeling, or the like. Furthermore, the thin film can be formed in an island shape by a deposition method using a metal mask or the like as a shielding mask.

[0297] Photolithography typically has two methods. One is a method in which a resist mask is formed on a thin film to be processed, the thin film is processed by etching or the like, and the resist mask is removed. The other is a method in which a thin film having photosensitivity is deposited, and then exposed to light, developed, and processed into a desired shape.

[0298] In photolithography, as light for exposure, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or light mixed with these rays can be used, for example. Furthermore, ultraviolet light, KrF laser light, ArF laser light, or the like can be used. Furthermore, exposure can be performed by liquid immersion exposure technology. Furthermore, as light for exposure, extreme ultraviolet (EUV) light or X-rays can be used. Furthermore, instead of light for exposure, an electron beam can be used. When extreme ultraviolet light, X-rays, or an electron beam is used, extremely fine processing can be performed, and thus is preferable. Note that when exposure is performed by scanning with a light beam such as an electron beam, a photomask is not needed.

[0299] As an etching method of the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0300] First, the conductive layer 220 is formed over the insulating layer 210, the insulating layer 280 is formed over the conductive layer 220, and the conductive layer 240 is formed over the insulating layer 280.

[0301] Note that it is preferable to perform planarization treatment (also referred to as CMP treatment) by a chemical mechanical polishing (CMP) method to planarize the top surface of the insulating layer 280 after the insulating layer 280 is deposited. By performing the planarization treatment of the insulating layer 280, the surface on which the conductive layer 240 serving as a wiring is formed can be planarized, and thus disconnection of the conductive layer 240 can be prevented. Alternatively, the planarization treatment can not be performed, in which case manufacturing cost can be reduced.

[0302] Next, the opening 290 is formed in the conductive layer 240 and the insulating layer 280 at a position overlapping with the conductive layer 220. FIG. 5A ).

[0303] Since the aspect ratio of the opening 290 is high, it is preferable to use anisotropic etching to process a part of the conductive layer 240 and a part of the insulating layer 280. In particular, processing using a dry etching method is suitable for fine processing and is therefore preferable. Furthermore, the processing can be performed under different conditions for each. Note that depending on the processing conditions of the conductive layer 240 and the insulating layer 280, the inclination of the side surface of the conductive layer 240 in the opening 290 and the inclination of the side surface of the insulating layer 280 can be different from each other.

[0304] Next, heat treatment can also be performed. As the heat treatment, for example, heat treatment at 250 °C or higher and 650 °C or lower, preferably, at 300 °C or higher and 500 °C or lower, further preferably, at 320 °C or higher and 450 °C or lower can be performed.

[0305] Further, the heat treatment is performed in an atmosphere of a nitrogen gas or an inert gas or an atmosphere containing 10 ppm or more, 1 % or more, or 10 % or more of an oxidizing gas. For example, when heat treatment is performed in a mixed atmosphere of a nitrogen gas and an oxygen gas, the proportion of the oxygen gas is preferably about 20 %. The heat treatment can also be performed in a reduced pressure state. Alternatively, the heat treatment can be performed in an atmosphere of a nitrogen gas or an inert gas, and then heat treatment can be performed in an atmosphere containing 10 ppm or more, 1 % or more, or 10 % or more of an oxidizing gas in order to compensate for the released oxygen. By performing the above heat treatment, impurities such as water contained in the insulating layer 280 and the like can be reduced before deposition of the oxide semiconductor layer 230 which will be described later.

[0306] Further, the gas used in the above heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the above heat treatment is preferably 1 ppb or lower, further preferably 0.1 ppb or lower, and still further preferably 0.05 ppb or lower. By performing heat treatment using a gas that is highly purified, moisture and the like can be prevented from being absorbed by the insulating layer 280 and the like as much as possible.

[0307] Next, the conductive layer 240 is processed into an island shape. The step of processing the conductive layer 240 into an island shape and the step of providing the opening 290 in the conductive layer 240 can be performed independently of each other, and there is no limitation on the order of the steps. Alternatively, etching can be performed after exposure using a mask for processing into a square island shape and exposure using a mask for providing a circular opening, whereby processing into an island shape and formation of an opening can be performed at one time. Further, exposure using a multi-tone mask (typically, a half tone mask or a gray tone mask) can be used. Furthermore, the same mask can be used to form openings in the conductive layer 240 and the insulating layer 280, or different masks can be used to form openings in the conductive layer 240 and the insulating layer 280.

[0308] Next, the oxide semiconductor layer 230 is formed so as to cover the opening 290. Then, the insulating layer 250 is formed over the oxide semiconductor layer 230. FIG. 5B The oxide semiconductor layer 230 is provided so as to be in contact with the top surface of the conductive layer 220, the side surface of the insulating layer 280, and the top surface and the side surface of the conductive layer 240. The insulating layer 250 is formed so as to be in contact with the oxide semiconductor layer 230.

[0309] The oxide semiconductor layer 230 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method, for example.

[0310] The oxide semiconductor layer 230 is preferably formed into a film with a thickness as uniform as possible along the top surface of the conductive layer 220, the side surface of the insulating layer 280, and the side surface of the conductive layer 240 within the opening 290. A thin film can be deposited with high controllability by deposition with an ALD method. Thus, the oxide semiconductor layer 230 is preferably deposited by an ALD method.

[0311] Further, when the crystallinity of the oxide semiconductor layer 230 is high, diffusion of impurities in the oxide semiconductor layer 230 is inhibited, and thus the electric characteristics of the transistor are less likely to vary, which can improve the reliability. When the oxide semiconductor layer 230 is deposited by a sputtering method, a layer with high crystallinity is easily formed compared to the case of an ALD method, and is thus preferable.

[0312] For example, in the case of forming the oxide semiconductor layer 230 by a sputtering method, oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas. By increasing the proportion of oxygen included in the sputtering gas, excess oxygen in a deposited oxide film can be increased. Further, in the case of depositing the above oxide film by a sputtering method, an In-M-Zn oxide target or the like can be used.

[0313] In the case of forming the oxide semiconductor layer 230 by a sputtering method, when deposition is performed at a proportion of oxygen included in a sputtering gas of more than 30 % and 100 % or less, preferably 70 % or more and 100 % or less, an oxygen-excess oxide semiconductor is formed. A transistor in which an oxygen-excess oxide semiconductor is used for a channel formation region can have relatively high reliability. Note that one embodiment of the present application is not limited to this. At this time, when the proportion of oxygen included in a sputtering gas is set to be 1 % or more and 30 % or less, preferably 5 % or more and 20 % or less, an oxygen-deficient oxide semiconductor is formed. A transistor in which an oxygen-deficient oxide semiconductor is used for a channel formation region can have high field-effect mobility. Further, by performing deposition while heating a substrate, the crystallinity of the oxide semiconductor layer can be improved.

[0314] Next, heat treatment is preferably performed. The heat treatment is preferably performed at a temperature at which the oxide semiconductor layer 230 is not crystallized. The temperature of the heat treatment is preferably higher than or equal to 100 °C, higher than or equal to 250 °C, or higher than or equal to 350 °C, and lower than or equal to 650 °C, lower than or equal to 600 °C, or lower than or equal to 550 °C. The details of the heat treatment can be referred to the above description.

[0315] Further, a gas used in the above heat treatment is preferably high-purity. By performing the heat treatment using a high-purity gas, moisture and the like can be prevented from being absorbed by the oxide semiconductor layer 230 as much as possible.

[0316] In this embodiment, as the heat treatment, a treatment is performed for one hour at a temperature of 450 °C in a condition where the flow ratio of nitrogen gas to oxygen gas is 4: 1. By such heat treatment including oxygen gas, impurities such as carbon, water, and hydrogen in the oxide semiconductor layer 230 can be reduced. Thus, by reducing impurities in the film, the crystallinity of the oxide semiconductor layer 230 is improved, and a denser structure with higher density can be obtained. Thus, the crystalline region in the oxide semiconductor layer 230 can be increased, and the in-plane unevenness of the crystalline region in the oxide semiconductor layer 230 can be reduced. Thus, the in-plane unevenness of the electrical characteristics of the transistor can be reduced.

[0317] Further, in the case where the insulating layer 280 contains oxygen, it is preferable that oxygen be supplied from the insulating layer 280 to the channel formation region of the oxide semiconductor layer 230 by heat treatment. By this means, oxygen vacancies and VoH can be reduced.

[0318] Here, the insulating layer 250 is preferably formed so as to be in contact with the oxide semiconductor layer 230 provided in the high-aspect-ratio opening 290. Thus, a deposition method with high coverage is preferably used when the insulating layer 250 is deposited, and a CVD method or an ALD method or the like is more preferably used.

[0319] By depositing the insulating layer 250 after the oxide semiconductor layer 230 is processed into an island shape, the side end portion of the oxide semiconductor layer 230 is covered with the insulating layer 250. Thus, the oxide semiconductor layer 230 can be prevented from being short-circuited with the conductive layer 260. Further, by employing the above structure, the side end portion of the conductive layer 240 is covered with the insulating layer 250. Thus, the conductive layer 240 can be prevented from being short-circuited with the conductive layer 260.

[0320] Next, the conductive layer 260af is formed over the insulating layer 250, and the conductive layer 260bf is formed so as to be stacked over the conductive layer 260af. FIG. 5C )。

[0321] The conductive layer 260af is formed in contact with the insulating layer 250 provided in the high aspect ratio opening 290. Thus, a deposition method with good coverage is preferably used when depositing the conductive layer 260af, and a CVD method or an ALD method or the like is more preferably used.

[0322] Further, as deposition of the conductive layer 260bf, a sputtering method or a CVD method or the like is used, for example, and a film with a large thickness can be formed at a high deposition rate as appropriate, which can achieve efficiency in manufacturing steps.

[0323] Next, a mask 278 is formed over the conductive layer 260bf. As the mask 278, a resist mask can be used. Further, as the mask 278, a structure in which a spin on carbon (SOC) film, a spin on glass (SOG) film, and a resist mask are sequentially stacked over the conductive layer 260bf can be employed.

[0324] Next, a portion of the conductive layer 260bf is removed using the mask 278 to form a conductive layer 260b( FIG. 6A ). Note that, as FIG. 6A indicated in FIG. 2B, a portion of the conductive layer 260af is sometimes removed when the conductive layer 260b is formed, and the thickness of the conductive layer 260af is thinned in a region not covered with the conductive layer 260bf.

[0325] When a portion of the conductive layer 260bf is removed, a dry etching method suitable for fine processing is preferably used.

[0326] Next, a portion of the conductive layer 260af is removed to form a conductive layer 260a( FIG. 6B ). Here, the conductive layer 260b is used as a mask to remove a portion of the conductive layer 260af. Here, the mask 278 can remain when the conductive layer 260a is formed. In the case where the mask 278 remains, the mask 278 and the conductive layer 260b are used as masks to remove a portion of the conductive layer 260af. Further, in the case where the mask 278 remains, the mask 278 is removed, for example, after the conductive layer 260a is formed.

[0327] Note that, in processing of the conductive layer 260a, a region in the conductive layer 260af not covered with the conductive layer 260b is removed. Further, at this time, as FIG. 6B indicated in FIG. 2C, a region covered with the conductive layer 260b, e.g., a region inside the end portion of the conductive layer 260b is also removed. In the manufacturing method of the semiconductor device of one embodiment of the present application, the conductive layer 260a is preferably formed so that the end portion thereof is positioned inside the end portion of the conductive layer 260b.

[0328] Isotropic etching conditions are preferably used when forming the conductive layer 260a. Wet etching is preferred because it can perform isotropic etching appropriately. Furthermore, by using wet etching, damage to the surface of the insulating layer 250 can be reduced when it is exposed.

[0329] As a wet etching solution, a solution containing hydrogen peroxide can be used, for example. For example, a mixture of ammonia, hydrogen peroxide, and water can be used.

[0330] In addition, for example, a solution containing one or more of sulfuric acid and hydrochloric acid, as well as hydrogen peroxide, can be used.

[0331] In addition, as a wet etching solution, a developer, a tetramethylammonium hydroxide (TMAH) aqueous solution, etc. can be used.

[0332] In addition, as a wet etching solution, oxalic acid, phosphoric acid, acetic acid, nitric acid, or a solution containing one or more of these can be used.

[0333] Next, an insulating layer 283 is formed on the insulating layer 250 and the conductive layer 260. FIG. 6C By forming an insulating layer 283, for example, a void is formed as region 277.

[0334] Alternatively, when an insulating layer 283 is embedded in region 277 by forming an insulating layer 283, it can be formed FIG. 4A and FIG. 4B The semiconductor device shown has the following structure.

[0335] When forming the insulating layer 283 using methods such as sputtering or PECVD, region 277 may easily become a void. Furthermore, when forming the insulating layer 283 using the high-coverage ALD method, region 277 may easily be embedded by the insulating layer 283.

[0336] The semiconductor device of one aspect of the present invention can be manufactured through the above-described process.

[0337] <Example 2 of Semiconductor Device Manufacturing Methods> The manufacturing method examples shown in Figures 5 and 6 illustrate an example of wet etching when forming the conductive layer 260a, but the method for forming the conductive layer 260a is not limited to this. An example of combining dry etching and wet etching will be described below.

[0338] First, refer to FIG. 5A to FIG. 6A The process shown forms conductive layers 220, 280, 240, oxide semiconductor layer 230, 250, 260af, and 260b on insulating layer 210.

[0339] Next, the mask 278 and the conductive layer 260b are used as masks, and a portion of the conductive layer 260af is removed, so that a conductive layer 260ae is formed. FIG. 7A Note that dry etching is used to form the conductive layer 260ae.

[0340] Note that the dry etching for forming the conductive layer 260ae and the dry etching for forming the conductive layer 260b can be performed continuously.

[0341] Note that, as illustrated in FIG. 2B, a portion of the insulating layer 250 is removed when the conductive layer 260ae is formed, and the thickness of the insulating layer 250 is sometimes reduced in a region which is not covered with the conductive layer 260ae. FIG. 7A

[0342] Further, as illustrated in FIG. 2B, a portion of the conductive layer 260af is removed to such an extent that the insulating layer 250 is not exposed, and reduction in the thickness of the insulating layer 250 can be suppressed. FIG. 7B

[0343] Next, a portion of the conductive layer 260ae is removed by wet etching, so that a conductive layer 260a is formed. FIG. 7C Here, a portion of the conductive layer 260ae is removed with the conductive layer 260b used as a mask. Here, the mask 278 can be left when the conductive layer 260a is formed. When the mask 278 is left, the mask 278 and the conductive layer 260b are used as masks to remove a portion of the conductive layer 260ae. Further, when the mask 278 is left, the mask 278 is removed, for example, after the conductive layer 260a is formed.

[0344] The conditions of the wet etching can be referred to the above conditions. Note that when the etching rate of the conductive layer 260af in the wet etching is low, the combination of the dry etching and the wet etching can be used when a portion of the conductive layer 260af is removed, so that efficiency of the manufacturing process can be improved.

[0345] Next, by forming an insulating layer 283 over the insulating layer 250 and the conductive layer 260, a semiconductor device of one embodiment of the present application can be manufactured. FIG. 8A FIG. 8B An enlarged view of a region surrounded by a two-dot chain line in FIG. 2D is illustrated. FIG. 8A

[0346] Note that in the examples illustrated in FIGS. 2D and 2E, the thickness of a region in the insulating layer 250 which does not overlap with the conductive layer 260b (e.g., a region on the outer side of a region overlapping with the conductive layer 260b) is thinner than the thickness of a region overlapping with the conductive layer 260b. FIG. 8A FIG. 8B

[0347] ​​​​​​This embodiment mode can be combined as appropriate with other embodiment modes. Furthermore, in this specification, in the case where a plurality of structural examples are shown in one embodiment mode, the structural examples can be combined as appropriate.

[0348] (Embodiment 2) In this embodiment mode, reference is made to FIG. 10 to FIG. 12. FIG. 13 A storage device of one embodiment of the present application is described. The storage device of one embodiment of the present application includes a storage unit. The storage unit includes a transistor and a capacitor.

[0349] <Structure Example 1 of Storage Device> Reference is made to FIG. 1. FIG. 10A to FIG. 10C The structure of a storage device including a transistor and a capacitor is described. FIG. 10A is a plan view of a storage device including a transistor 200 and a capacitor 100. FIG. 10B is a cross-sectional view taken along a dotted line A1-A2 indicated in FIG. 10A . FIG. 10C is a cross-sectional view taken along a dotted line A3-A4 indicated in FIG. 10A .

[0350] FIG. 10A to FIG. 10C The storage device illustrated in FIG. 1 includes an insulating layer 140 over a substrate (not shown), a conductive layer 110 over the insulating layer 140, a storage unit 150 over the conductive layer 110, an insulating layer 180 over the conductive layer 110, an insulating layer 280, and an insulating layer 283 over the storage unit 150. The insulating layer 140, the insulating layer 180, the insulating layer 280, and the insulating layer 283 are used as interlayer films. The conductive layer 110 is used as a wiring.

[0351] The storage unit 150 includes a capacitor 100 over the conductive layer 110 and a transistor 200 over the capacitor 100.

[0352] The capacitor 100 includes a conductive layer 115 over the conductive layer 110, an insulating layer 130 over the conductive layer 115, and a conductive layer 120 over the insulating layer 130. The conductive layer 120 is used as one of a pair of electrodes (sometimes referred to as an upper electrode), the conductive layer 115 is used as the other of the pair of electrodes (sometimes referred to as a lower electrode), and the insulating layer 130 is used as a dielectric. That is, the capacitor 100 constitutes an MIM (Metal-Insulator-Metal) capacitor.

[0353] As described above, FIG. 10B and FIG. 10CAs shown, the insulating layer 180 is provided with an opening 190 reaching the conductive layer 110. At least a portion of the conductive layer 115 is disposed in the opening 190. Note that the conductive layer 115 has a region in contact with the top surface of the conductive layer 110 in the opening 190, a region in contact with the side surface of the insulating layer 180 in the opening 190, and a region in contact with at least a portion of the top surface of the insulating layer 180. The insulating layer 130 is disposed so that at least a portion thereof is in the opening 190. The conductive layer 120 is disposed so that at least a portion thereof is in the opening 190. Furthermore, as shown in FIG. 1B, the conductive layer 120 is preferably provided so as to be embedded in the opening 190. Furthermore, the films provided inside the opening 190 are preferably formed using the ALD method. By so doing, the films have good coverage. For example, the conductive layer 115, the insulating layer 130, and the conductive layer 120 are preferably formed using the ALD method. FIG. 10B and FIG. 10C As shown, the conductive layer 120 is preferably provided so as to be embedded in the opening 190. Furthermore, the films provided inside the opening 190 are preferably formed using the ALD method. By so doing, the films have good coverage. For example, the conductive layer 115, the insulating layer 130, and the conductive layer 120 are preferably formed using the ALD method.

[0354] The capacitor 100 has a structure in which the upper electrode and the lower electrode face each other with the dielectric therebetween not only on the bottom surface but also on the side surface in the opening 190, and thus the electrostatic capacitance per unit area can be increased. By so doing, the deeper the depth of the opening 190, the greater the electrostatic capacitance of the capacitor 100 can be. Thus, by increasing the electrostatic capacitance per unit area of the capacitor 100, the readout operation of the storage device can be stabilized. Furthermore, the miniaturization or high integration of the storage device can be promoted.

[0355] FIG. 10B and FIG. 10C An example in which the side wall of the opening 190 is perpendicular to the top surface of the conductive layer 110 is shown. At this time, the opening 190 has a cylindrical shape. By adopting such a structure, the miniaturization or high integration of the storage device can be achieved.

[0356] The conductive layer 115 and the insulating layer 130 are disposed in layers along the side wall of the opening 190 and the top surface of the conductive layer 110. Furthermore, the conductive layer 120 is provided on the insulating layer 130 so as to be embedded in the opening 190. The capacitor 100 having such a structure can be referred to as a trench-type capacitor or a trench capacitor.

[0357] The insulating layer 280 is disposed on the capacitor 100. That is, the insulating layer 280 is disposed on the conductive layer 115, the insulating layer 130, and the conductive layer 120. In other words, the conductive layer 120 is disposed under the insulating layer 280.

[0358] The transistor 200 includes the conductive layer 120 (corresponding to FIG. 1BThe conductive layer 220, conductive layer 240 on insulating layer 280, oxide semiconductor layer 230, insulating layer 250 on oxide semiconductor layer 230, and conductive layer 260 on insulating layer 250 are used as semiconductor layers, conductive layer 260 is used as gate electrode, insulating layer 250 is used as gate insulating layer, conductive layer 120 is used as one of source electrode and drain electrode, and conductive layer 240 is used as the other of source electrode and drain electrode.

[0359] Regarding transistor 200, please refer to the description in Embodiment 1 (Figures 1 and 2), so detailed description is omitted. Furthermore, the transistors included in the memory cell 150 are not limited to transistor 200, and any of the transistors shown in Embodiment 1 may also be used.

[0360] like FIG. 10A to FIG. 10C As shown, transistor 200 overlaps with capacitor 100. Furthermore, the opening 290 where a portion of the transistor 200 is disposed has a region overlapping with the opening 190 where a portion of the capacitor 100 is disposed. Specifically, conductive layer 120 is used as one of the source and drain electrodes of transistor 200 and as the upper electrode of capacitor 100, so transistor 200 and capacitor 100 share a common structure. By employing this structure, transistor 200 and capacitor 100 can be disposed in a manner that does not significantly increase the occupied area when viewed from above. Therefore, the occupied area of ​​memory cell 150 can be reduced, and the storage capacity of the memory device can be increased by arranging memory cells 150 at a high density. In other words, high integration of the memory device can be achieved.

[0361] Furthermore, by placing the transistor 200 above the capacitor 100, the transistor 200 is not affected by the heat treatment during the manufacture of the capacitor 100. Therefore, it is possible to suppress the degradation of the electrical characteristics of the transistor 200, such as threshold voltage fluctuations and increased parasitic resistance, as well as the increase in uneven electrical characteristics caused by such degradation.

[0362] FIG. 15A A circuit diagram of the storage device shown in this embodiment is illustrated. FIG. 15A As shown, FIG. 10A to FIG. 10C The structure shown is used as a storage cell. Storage cell 951 includes transistor M1 and capacitor CA. Here, transistor M1 corresponds to transistor 200, and capacitor CA corresponds to capacitor 100.

[0363] One of the source and drain terminals of transistor M1 is connected to one of the electrodes of capacitor CA. The other of the source and drain terminals of transistor M1 is connected to wiring BIL. The gate of transistor M1 is connected to wiring WOL. The other of the electrodes of capacitor CA is connected to wiring CAL.

[0364] Here, the wiring BIL corresponds to the conductive layer 240, the wiring WOL corresponds to the conductive layer 260, and the wiring CAL corresponds to the conductive layer 110. As shown in the drawing, it is preferable that the conductive layer 260 be provided so as to extend in the X direction and the conductive layer 240 be provided so as to extend in the Y direction. By adopting this structure, the wiring BIL and the wiring WOL cross each other. In addition, in the drawing, the wiring CAL (the conductive layer 110) is provided in a planar shape, but the present application is not limited to this. For example, the wiring CAL can also be parallel to the wiring WOL (the conductive layer 260) or the wiring BIL (the conductive layer 240). FIG. 10A to FIG. 10C FIG. 10A

[0365] Note that the storage unit will be described in detail in later embodiments.

[0366] [Capacitor 100] The capacitor 100 includes the conductive layer 115, the insulating layer 130, and the conductive layer 120. Further, the conductive layer 115 is provided with the conductive layer 110 below. The conductive layer 115 has a region in contact with the conductive layer 110.

[0367] The conductive layer 110 is provided on the insulating layer 140. The conductive layer 110 is used as the wiring CAL and can be provided in a planar shape, for example. As the conductive layer 110, a single layer or a stack of the conductive materials described in [Conductive layer] of Embodiment 1 can be used. As the conductive layer 110, a conductive material with high conductivity such as tungsten can be used, for example. By using a conductive material with high conductivity in this way, the conductivity of the conductive layer 110 can be improved so that the conductive layer 110 sufficiently functions as the wiring CAL.

[0368] Further, as the conductive layer 115, a conductive material that is not easily oxidized or a conductive material that has a function of suppressing diffusion of oxygen, or the like is preferably used in a single layer or a stack. For example, titanium nitride or indium tin oxide to which silicon is added, or the like can be used. Alternatively, for example, a structure in which tungsten is stacked with titanium nitride thereon can be provided. Alternatively, for example, a structure in which first titanium nitride, tungsten, and second titanium nitride are sequentially stacked can be provided. By adopting such a structure, oxidation of the conductive layer 110 by the insulating layer 130 when the insulating layer 130 is made of an oxide can be suppressed. Further, oxidation of the conductive layer 110 by the insulating layer 180 when the insulating layer 180 is made of an oxide can be suppressed.

[0369] The insulating layer 130 is provided on the conductive layer 115. The insulating layer 130 is provided so as to contact the top surface and the side surface of the conductive layer 115. That is, the insulating layer 130 preferably covers the side end portion of the conductive layer 115. By this, short-circuiting of the conductive layer 115 and the conductive layer 120 can be prevented.

[0370] ​​Further, a structure in which the side end portion of the insulating layer 130 is aligned with the side end portion of the conductive layer 115 can also be employed. By employing such a structure, the insulating layer 130 and the conductive layer 115 can be formed using the same mask, and thus the manufacturing process of the storage device can be simplified.

[0371] A material having a high relative dielectric constant (high-k) is preferably used as the insulating layer 130. By using a high-k material for the insulating layer 130, the thickness of the insulating layer 130 can be increased to a degree at which leakage current can be suppressed and the electrostatic capacitance of the capacitor 100 can be sufficiently ensured.

[0372] Further, as the insulating layer 130, a structure in which an insulator composed of a high-k material is stacked is preferably used, and a structure in which a material having a high relative dielectric constant (high-k) and a material having a larger dielectric strength than the high-k material are stacked is preferably used. For example, as the insulating layer 130, an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are sequentially stacked can be used. Further, for example, an insulating film in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are sequentially stacked can be used. Further, for example, an insulating film in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are sequentially stacked can be used. By using an insulating layer having a large dielectric strength such as aluminum oxide, the dielectric strength can be increased and the electrostatic breakdown of the capacitor 100 can be suppressed.

[0373] Further, as the insulating layer 130, a material having ferroelectricity can also be used. Details of the material having ferroelectricity can be found in the description of Embodiment 1.

[0374] A metal oxide containing one or both of hafnium and zirconium has ferroelectricity even when it is processed into a thin film of several nm, and thus is preferably used for the insulating layer 130. The thickness of the insulating layer 130 is preferably 100 nm or less, more preferably 50 nm or less, further preferably 20 nm or less, and still further preferably 10 nm or less (typically, 2 nm or more and 9 nm or less). Further, for example, the thickness is preferably 8 nm or more and 12 nm or less. By using a ferroelectric layer that can be thinned, a semiconductor device can be formed by combining the capacitor 100 and a semiconductor element such as a transistor that has been miniaturized.

[0375] Further, a metal oxide containing one or both of hafnium and zirconium has ferroelectricity even when its area is small, and thus is preferably used for the insulating layer 130. For example, a ferroelectric layer has ferroelectricity even when the area (occupied area) thereof in plan view is 100 μm 2 Hereinafter, 10 μm 2 Hereinafter, 1 μm 2 Hereinafter, 0.1 μm 2The following can also have ferroelectricity. Furthermore, sometimes the ferroelectric layer has an area (occupied area) of 10000 nm 2 The following or 1000 nm 2 The following also has ferroelectricity. By making the area of the ferroelectric layer small, the occupied area of the capacitor 100 can be reduced.

[0376] A ferroelectric is an insulator that has a property of being polarized inside by an applied electric field and retaining the polarization even when the electric field is 0. Thus, by using a capacitor in which such a material is used as a dielectric (hereinafter, sometimes referred to as a ferroelectric capacitor), a nonvolatile memory element can be formed. A nonvolatile memory element using a ferroelectric capacitor is sometimes referred to as a FeRAM (Ferroelectric Random Access Memory), a ferroelectric memory, or the like. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one of a source and a drain of the transistor is electrically connected to one terminal of the ferroelectric capacitor. Thus, in the case where the ferroelectric capacitor is used as the capacitor 100, the storage device described in this embodiment mode is used as a ferroelectric memory.

[0377] The conductive layer 120 is provided so as to be in contact with part of the top surface of the insulating layer 130. Furthermore, the side end portion of the conductive layer 120 is preferably positioned inside the side end portion of the conductive layer 115 in both the X direction and the Y direction. Note that in the case where the insulating layer 130 covers the side end portion of the conductive layer 115, the side end portion of the conductive layer 120 can also be positioned outside the side end portion of the conductive layer 115.

[0378] The conductive layer 120 can use a single layer or a stack of the conductive materials described in [Conductive layer] in Embodiment Mode 1. As the conductive layer 120, a conductive material which is not easily oxidized or a conductive material having a function of suppressing diffusion of oxygen, or the like is preferably used. For example, titanium nitride or tantalum nitride, or the like can be used. Furthermore, for example, a structure in which tantalum nitride is stacked over titanium nitride can be employed. In this case, the titanium nitride is in contact with the insulating layer 130 and the tantalum nitride is in contact with the oxide semiconductor layer 230. By employing such a structure, over-oxidation of the conductive layer 120 due to the oxide semiconductor layer 230 can be suppressed. Furthermore, in the case where the insulating layer 130 uses an oxide, over-oxidation of the conductive layer 120 due to the insulating layer 130 can be suppressed. Alternatively, the conductive layer 120 can have a structure in which tungsten is stacked over titanium nitride, for example.

[0379] Since the conductive layer 120 has a region in contact with the oxide semiconductor layer 230, a conductive material containing oxygen is preferably used. By using a conductive material containing oxygen as the conductive layer 120, the conductive property can be maintained even when the conductive layer 120 absorbs oxygen. Further, when an insulating layer containing oxygen such as zirconium oxide is used as the insulating layer 130, the conductive layer 120 can maintain the conductive property, and is thus preferable. As the conductive layer 120, a single layer or a stack of ITO, ITSO, IZO (registered trademark), or the like can be used, for example.

[0380] The insulating layer 180 is used as an interlayer film, and thus its relative dielectric constant is preferably low. By using a material with a low relative dielectric constant for the interlayer film, a parasitic capacitance generated between wirings can be reduced. As the insulating layer 180, a single layer or a stack of insulating layers containing a material with a low relative dielectric constant can be used. Silicon oxide and silicon oxynitride have thermal stability, and are thus preferable.

[0381] Note that in this embodiment, the insulating layer 180 is formed to have a single-layer structure, but the present application is not limited to this. The insulating layer 180 can have a two-layer structure, or can have a stack structure of three or more layers. FIG. 10B FIG. 10C A structure in which the insulating layer 180 is a single layer is illustrated, but the present application is not limited to this. The insulating layer 180 can have a two-layer structure, or can have a stack structure of three or more layers.

[0382] <Structure Example 2 of Storage Device> The storage unit 150 including the transistor 200 and the capacitor 100 described in this embodiment can be used as a storage unit of a storage device. The transistor 200 is a transistor whose channel is formed in a semiconductor layer containing an oxide semiconductor. Since the off-state current of the transistor 200 is small, the storage content can be held for a long period of time by using it for a storage device. In other words, since a refresh operation is not needed or the frequency of the refresh operation is extremely low, the power consumption of the storage device can be sufficiently reduced. Further, since the frequency characteristics of the transistor 200 are high, high-speed reading and writing of a storage device can be performed.

[0383] By arranging the storage units 150 in a three-dimensional manner and in a matrix, a storage unit array can be formed.

[0384] FIG. 11A is a plan view of a storage device. FIG. 11A An example in which 2 x 2 storage units (the storage unit 150a to the storage unit 150d) are arranged in the X direction and the Y direction is illustrated.

[0385] FIG. 11B is a cross-sectional view along the dotted line A3-A4 illustrated in FIG. 11A In the storage units 150a and 150b in FIG. 11A and FIG. 11B , two storage units (the storage unit 150a and the storage unit 150b in FIG. 11B ) are connected to a common wiring (the conductive layer 246).​

[0386] In this case, FIG. 11A and FIG. 11B The storage unit 150a and the storage unit 150b each have the same structure as the storage unit 150. The storage unit 150a includes the capacitor 100a and the transistor 200a, and the storage unit 150b includes the capacitor 100b and the transistor 200b. Further, FIG. 11A The storage unit 150c and the storage unit 150d each have the same structure as the storage unit 150. Thus, in the storage device, FIG. 11A and FIG. 11B The same reference numerals are given to components having the same functions as those of the storage device illustrated in FIG. 10. Further, the detailed description of the storage units 150a to 150d can be referred to the description of the storage unit 150 in <Structure Example 1 of Storage Device>.

[0387] As illustrated in FIG. 11A and FIG. 11B The conductive layer 260 serving as the wiring WOL is provided in each of the storage unit 150a and the storage unit 150b. Further, as illustrated in FIG. 11A One conductive layer 260 is provided in common between the storage unit 150a and the storage unit 150c, and another conductive layer 260 is provided in common between the storage unit 150b and the storage unit 150d. Further, one conductive layer 240 serving as part of the wiring BIL is provided in common between the storage unit 150a and the storage unit 150b. In other words, the conductive layer 240 is in contact with the oxide semiconductor layer 230 of the storage unit 150a and the oxide semiconductor layer 230 of the storage unit 150b. Further, another conductive layer 240 is provided in common between the storage unit 150c and the storage unit 150d.

[0388] In this case, FIG. 11A and FIG. 11B The storage device includes the conductive layer 245 and the conductive layer 246 serving as a plug (which can be referred to as a connection electrode) electrically connected to the storage unit 150a and the storage unit 150b. The conductive layer 245 is provided in contact with the bottom surface of the conductive layer 240 in an opening formed in the insulating layer 140, the insulating layer 180, the insulating layer 130, and the insulating layer 280. Further, the conductive layer 246 is provided in contact with the top surface of the conductive layer 240 in an opening formed in the insulating layer 285, the insulating layer 283, and the insulating layer 250. As the conductive layer 245 and the conductive layer 246, a conductive material or the like that can be used for the conductive layer 240 can be used.

[0389] Insulating layer 285 is used as an interlayer film, so its relative permittivity is preferably low. By using a material with a low relative permittivity for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0390] Furthermore, the concentration of impurities such as water and hydrogen in the insulating layer 285 is preferably reduced. This can suppress the mixing of impurities such as water and hydrogen into the channel formation region of the oxide semiconductor layer 230.

[0391] Conductive layers 245 and 246 are used as plugs or wiring for electrically connecting circuit elements such as switches, transistors, capacitors, inductors, resistors, and diodes, as well as for wiring, electrodes, or terminals, to memory cells 150a and 150b. For example, a structure can be adopted where conductive layer 245 is connected to the plug or wiring of memory cells 150a and 150b. FIG. 11B The read amplifier (not shown) under the storage device is electrically connected, and the conductive layer 246 is disposed with the read amplifier (not shown) under the storage device. FIG. 11B The same storage device (not shown) is electrically connected to the storage device shown. In this case, conductive layers 245 and 246 are used as part of the wiring BIL. Thus, by... FIG. 11B By placing storage devices on top of or below the storage device shown, the storage capacity per unit area can be increased.

[0392] Furthermore, memory cells 150a and 150b are linearly symmetrical about the perpendicular bisector of the dashed line A3-A4. Therefore, transistors 200a and 200b are also arranged linearly symmetrically, sandwiching conductive layers 245 and 246. Here, conductive layer 240 serves as one of the source and drain electrodes of transistor 200a and another of the source and drain electrodes of transistor 200b. Moreover, transistors 200a and 200b share conductive layers 245 and 246, which act as a connector. Thus, by employing the above structure as a connection between two transistors and a connector, a memory device capable of miniaturization or high integration can be provided.

[0393] Furthermore, the conductive layer 110 used for wiring CAL can be disposed separately in memory cells 150a and 150b, or it can be disposed together in memory cells 150a and 150b. Note that, as FIG. 12 As shown, the conductive layer 110 is disposed separately from the conductive layer 245 to prevent short circuit between the conductive layer 110 and the conductive layer 245.

[0394] also, FIG. 11A This shows n layers (n is an integer greater than or equal to 3) stacked along the Z direction. FIG. 12 The example shown is of four storage units. FIG. 11A It is along FIG. 12 The cross-sectional view shown is the dotted-dash line A3-A4.

[0395] FIG. 12 The storage device shown includes n layers of storage layers 160. Specifically, the storage layer 160[1] is provided with the storage layer 160[2], and the storage layer 160[2] is further provided with (n-2) layers of storage layers, and the storage layer 160[n] is provided as the uppermost layer. The number of storage units included in one layer of storage layers 160 is not particularly limited, and can include two or more storage units. The storage units included in the n layers of storage layers 160 are electrically connected to a sense amplifier (not shown) provided below the n layers of storage layers 160, through the conductive layers 245, 246, 247, and 248.

[0396] As shown in FIG. 13 , by stacking a plurality of storage units, the units can be integrally configured without increasing the area occupied by the storage unit array. That is, a 3D storage unit array can be formed.

[0397] FIG. 13 A cross-sectional structure example of a storage device in which a layer provided with a drive circuit including a sense amplifier is stacked on a layer including a storage unit is shown.

[0398] In FIG. 13 , the storage unit 150 (transistor 200 and capacitor 100) is provided above the transistor 300.

[0399] The transistor 300 is one of the transistors included in the sense amplifier.

[0400] Regarding the storage unit 150 shown in FIG. 13 , reference can be made to the description of the storage unit 150 in <Structure Example 1 of Storage Device>.

[0401] As shown in FIG. 13 , by adopting a structure in which the sense amplifier is provided in a manner overlapping the storage unit 150, the bit line can be shortened. Thus, the bit line capacitance is reduced, and the storage unit holding capacitance can be reduced. Therefore, high-speed driving of the storage device can be achieved.

[0402] FIG. 13 The storage device shown can correspond to the semiconductor device 900 described in Embodiment 3. Specifically, the transistor 300 corresponds to the transistor included in the sense amplifier 927 in the semiconductor device 900. In addition, the storage unit 150 corresponds to the storage unit 950.

[0403] The transistor 300 is provided over a substrate 311 and includes a conductive layer 316 serving as a gate electrode, an insulating layer 315 serving as a gate insulator, a semiconductor region 313 formed of a portion of the substrate 311, and low-resistance regions 314a and 314b serving as source or drain regions. The transistor 300 can be of a p-channel type or an n-channel type.

[0404] In this embodiment, in the transistor 300 illustrated in FIG. 1A, the semiconductor region 313 (a portion of the substrate 311) in which a channel is formed has a convex shape. Further, the conductive layer 316 is provided so as to cover side surfaces and a top surface of the semiconductor region 313 with the insulating layer 315 interposed therebetween. Further, the conductive layer 316 can also use a material for adjusting a work function. Since the convex portion of the semiconductor substrate is used, such a transistor 300 is also referred to as a FIN type transistor. Further, the insulating layer which is a mask for forming the convex portion can be provided so as to be in contact with an upper surface of the convex portion. Further, although the case where the convex portion is formed by processing a portion of the semiconductor substrate is described here, a semiconductor film having a convex portion can be formed by processing an SOI substrate. FIG. 13 Note that, in the transistor 300 illustrated in FIG. 1A, the semiconductor region 313 (a portion of the substrate 311) in which a channel is formed has a convex shape. Further, the conductive layer 316 is provided so as to cover side surfaces and a top surface of the semiconductor region 313 with the insulating layer 315 interposed therebetween. Further, the conductive layer 316 can also use a material for adjusting a work function. Since the convex portion of the semiconductor substrate is used, such a transistor 300 is also referred to as a FIN type transistor. Further, the insulating layer which is a mask for forming the convex portion can be provided so as to be in contact with an upper surface of the convex portion. Further, although the case where the convex portion is formed by processing a portion of the semiconductor substrate is described here, a semiconductor film having a convex portion can be formed by processing an SOI substrate.

[0405] FIG. 13 Note that, in the transistor 300 illustrated in FIG. 1A, the semiconductor region 313 (a portion of the substrate 311) in which a channel is formed has a convex shape. Further, the conductive layer 316 is provided so as to cover side surfaces and a top surface of the semiconductor region 313 with the insulating layer 315 interposed therebetween. Further, the conductive layer 316 can also use a material for adjusting a work function. Since the convex portion of the semiconductor substrate is used, such a transistor 300 is also referred to as a FIN type transistor. Further, the insulating layer which is a mask for forming the convex portion can be provided so as to be in contact with an upper surface of the convex portion. Further, although the case where the convex portion is formed by processing a portion of the semiconductor substrate is described here, a semiconductor film having a convex portion can be formed by processing an SOI substrate.

[0406] A wiring layer including an interlayer film, a wiring, and a plug, and the like can be provided between the structures. Further, the wiring layer can be provided in a plurality of layers depending on design. In the conductive layer having a function of a plug or a wiring, the same reference numeral is used to denote a plurality of structures in some cases. Further, in this specification and the like, a wiring and a plug electrically connected to a wiring can be one component. That is, part of a conductive layer is used as a wiring in some cases, and part of a conductive layer is used as a plug in some cases.

[0407] For example, over the transistor 300, the insulating layer 320, the insulating layer 322, the insulating layer 324, and the insulating layer 326 are provided in this order as an interlayer film. Further, the conductive layer 328 is embedded in the insulating layer 320 and the insulating layer 322, and the conductive layer 330 is embedded in the insulating layer 324 and the insulating layer 326. Further, the conductive layer 328 and the conductive layer 330 are used as a plug or a wiring.

[0408] Further, the insulating layer serving as an interlayer film can be used as a planarization film for covering a concavo-convex shape of the lower portion. For example, in order to improve planarity of a top surface of the insulating layer 322, the top surface thereof can be planarized by a planarization treatment such as a CMP method.

[0409] Further, a wiring layer can be formed over the insulating layer 326 and the conductive layer 330. For example, in the case where the conductive layer 330 is used as a plug, a wiring layer can be formed over the conductive layer 330.​FIG. 14 In this case, the insulating layer 350, the insulating layer 352, and the insulating layer 354 are sequentially stacked. Further, the conductive layer 356 is formed in the insulating layer 350, the insulating layer 352, and the insulating layer 354. The conductive layer 356 is used as a plug or a wiring.

[0410] As the insulating layer 352 and the insulating layer 354 used as an interlayer film, the above-described insulating layer used for a semiconductor device or a storage device can be used.

[0411] As the conductive layer used as a plug or a wiring, for example, the conductive layer 328, the conductive layer 330, and the conductive layer 356, the conductive material used for the conductive layer 240 can be used. A high melting point material such as tungsten or molybdenum having heat resistance and conductivity is preferably used, and tungsten is particularly preferably used. Alternatively, a low-resistance conductive material such as aluminum or copper is preferably used. By using a low-resistance conductive material, the wiring resistance can be reduced.

[0412] The conductive layer 240 included in the transistor 200 is electrically connected to the low-resistance region 314b serving as a source region or a drain region of the transistor 300 through the conductive layer 643, the conductive layer 642, the conductive layer 644, the conductive layer 645, the conductive layer 646, the conductive layer 356, the conductive layer 330, and the conductive layer 328.

[0413] The conductive layer 643 is embedded in the insulating layer 280. The conductive layer 642 is provided over the insulating layer 130 and embedded in the insulating layer 641. The conductive layer 642 can be manufactured using the same material and process as the conductive layer 120. The conductive layer 644 is embedded in the insulating layer 180 and the insulating layer 130. The conductive layer 645 is embedded in the insulating layer 647. The conductive layer 645 can be manufactured using the same material and process as the conductive layer 110. The conductive layer 646 is embedded in the insulating layer 648. The transistor 300 and the conductive layer 110 are electrically insulated from each other by the insulating layer 648.

[0414] As described above, the storage device of this embodiment includes a transistor in which a parasitic capacitance is reduced, and thus the operation speed can be increased. Further, in the storage device of this embodiment, a capacitor and a transistor are stacked, and thus the area occupied by a storage unit in plan view can be reduced, and a storage device with high integration can be achieved.

[0415] This embodiment can be combined with other embodiments as appropriate.

[0416] (Embodiment 3) In this embodiment, a semiconductor device 900 of a semiconductor device according to one embodiment of the present application is described. The semiconductor device 900 can be used as a storage device.

[0417] FIG. 14 is a block diagram illustrating a structure example of the semiconductor device 900. FIG. 14The illustrated semiconductor device 900 includes a drive circuit 910 and a memory array 920. The memory array 920 includes one or more memory cells 950. FIG. 14 The memory array 920 is illustrated as including a plurality of memory cells 950 configured in a matrix shape.

[0418] As the memory cell 950, the memory device (the memory cell 150 or the like) described in Embodiment 2 can be used.

[0419] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0420] In the semiconductor device 900, each of the above-described circuits, signals, and voltages can be appropriately selected as needed. Alternatively, other circuits or other signals can be added. The signal BW, the signal CE, the signal GW, the signal CLK, the signal WAKE, the signal ADDR, the signal WDA, the signal PON1, and the signal PON2 are signals input from the outside, and the signal RDA is a signal output to the outside. The signal CLK is a clock signal.

[0421] Further, the signal BW, the signal CE, and the signal GW are control signals. The signal CE is a chip enable signal, the signal GW is a global write enable signal, and the signal BW is a byte write enable signal. The signal ADDR is an address signal. The signal WDA is write data, and the signal RDA is read data. The signal PON1 and the signal PON2 are power gate control signals. Further, the signal PON1 and the signal PON2 can be generated in the control circuit 912.

[0422] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 logically operates the signal CE, the signal GW, and the signal BW to determine the operation mode (for example, a write operation, a read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal of the peripheral circuit 911 to perform the above-described operation mode.

[0423] The voltage generation circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 928. For example, when the signal WAKE is applied with an H-level signal, the signal CLK is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates a negative voltage.

[0424] The peripheral circuit 911 is used to write and read data from the storage unit 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0425] Row decoder 941 and column decoder 942 are used to decode the signal ADDR. Row decoder 941 is used to specify the row to be accessed, and column decoder 942 is used to specify the column to be accessed. Row driver 923 is used to select the row to be connected to by row decoder 941. Column driver 924 has the following functions: writing data to memory cell 950; reading data from memory cell 950; and storing the read data.

[0426] Input circuit 925 has the function of holding signal WDA. The data held in input circuit 925 is output to column driver 924. The output data of input circuit 925 is the data written to memory cell 950 (Din). The data read from memory cell 950 by column driver 924 (Dout) is output to output circuit 926. Output circuit 926 has the function of holding Dout. In addition, output circuit 926 has the function of outputting Dout to the outside of semiconductor device 900. The data signal output from output circuit 926 is signal RDA.

[0427] PSW931 controls the supply of V to the external circuit 915. DD The PSW932 has the function of controlling the supply of V to the line driver 923. HM The function of the semiconductor device 900. Here, the high supply voltage of the semiconductor device 900 is V. DD The low supply voltage is GND (ground potential). Additionally, V HM It is a high power supply voltage used to make the word line high, which is higher than V. DD The PSW931 is controlled to turn on / off using signal PON1, and the PSW932 is controlled to turn on / off using signal PON2. FIG. 15A to FIG. 15H In the middle, the peripheral circuit 915 is supplied with V DD The number of power domains can be 1, but it can also be multiple. In this case, a power switch can be set for each power domain.

[0428] Reference FIG. 15A This section describes an example of the structure of a storage cell that can be used in storage cell 950.

[0429] Hereinafter, in the case where two constitutional elements are connected, the case where they are electrically connected through a circuit element (transistor, switch, diode, resistor, or the like) is included. Electrical connection means that a state where current can flow between the two constitutional elements. Further, in the case where two constitutional elements are connected through a switch or a transistor, a state where current can flow when the switch or the transistor is in an on state is also included in the category of electrical connection.

[0430] [DOS RAM] FIG. 15B A circuit structure example of a DRAM-type memory cell is shown. In this specification and the like, a DRAM using an OS transistor is referred to as a DOS RAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 951 includes a transistor Ml and a capacitor CA.

[0431] The transistor Ml can include a front gate (sometimes simply referred to as a gate) and a back gate. At this time, the back gate can be connected to a wiring to which a constant potential or a signal is supplied, and the front gate can be connected to the back gate.

[0432] The first terminal of the transistor Ml is connected to the first terminal of the capacitor CA, the second terminal of the transistor Ml is connected to a wiring BIL, and the gate of the transistor Ml is connected to a wiring WOL. The second terminal of the capacitor CA is connected to a wiring CAL.

[0433] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL is used as a wiring for applying a designated potential to the second terminal of the capacitor CA. At the time of writing and reading of data, a low-level potential (sometimes referred to as a reference potential) is preferably applied to the wiring CAL.

[0434] Writing and reading of data are performed by applying a high-level potential to the wiring WOL to make the transistor Ml an on state and making the wiring BIL and the first terminal of the capacitor CA a conduction state (current can flow) between them.

[0435] Further, the memory cell used for the memory cell 950 is not limited to the memory cell 951, and the circuit structure can be changed. For example, the memory cell 952 shown in FIG. 9B can be used. The memory cell 952 is an example in which the capacitor CA and the wiring CAL are not included. The first terminal of the transistor Ml is in an electrically floating state. FIG. 15C

[0436] ​In the storage unit 952, the potential written through the transistor Ml is held in a capacitance (also referred to as a parasitic capacitance) between the first terminal and the gate shown by a dashed line. By employing such a structure, the structure of the storage unit can be greatly simplified.

[0437] As the transistor Ml, an OS transistor is preferably used. The OS transistor has a characteristic of having a very small off-state current. By using the OS transistor as the transistor Ml, the leakage current of the transistor Ml can be made very low. That is, the data written can be held by the transistor Ml for a long time, and thus the refresh frequency of the storage unit can be reduced. Further, the refresh operation of the storage unit can be omitted. Furthermore, since the leakage current is very low, multi-value data or analog data can be held in the storage unit 951 and the storage unit 952.

[0438] [NOSRAM] FIG. 15D A circuit structure example of a storage unit of a gain cell type including two transistors and one capacitor is shown. The storage unit 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and the like, a storage device including a gain cell type storage unit in which an OS transistor is used for the transistor M2 is sometimes referred to as an NOSRAM (Nonvolatile Oxide Semiconductor RAM).

[0439] The first terminal of the transistor M2 is connected to the first terminal of the capacitor CB, the second terminal of the transistor M2 is connected to a wiring WBL, and the gate of the transistor M2 is connected to a wiring WOL. The second terminal of the capacitor CB is connected to a wiring CAL. The first terminal of the transistor M3 is connected to a wiring RBL, the second terminal of the transistor M3 is connected to a wiring SL, and the gate of the transistor M3 is connected to the first terminal of the capacitor CB.

[0440] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CB. At the time of data writing, at the time of data retention, and at the time of data reading, a low-level potential (sometimes referred to as a reference potential) is preferably applied to the wiring CAL.

[0441] Writing of data is performed by bringing the transistor M2 into an on state by applying a high potential to the wiring WOL, and bringing the wiring WBL and the first terminal of the capacitor CB into a conduction state. Specifically, when the transistor M2 is in an on state, a potential corresponding to information to be recorded is applied to the wiring WBL to write the potential to the first terminal of the capacitor CB and the gate of the transistor M3. Then, the transistor M2 is brought into an off state by applying a low potential to the wiring WOL, whereby the potential of the first terminal of the capacitor CB and the potential of the gate of the transistor M3 are held.

[0442] Reading of data is performed by applying a predetermined potential to the wiring SL. Since the current flowing between the source and the drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. That is, information written in the memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0443] For example, a structure in which the wiring WBL and the wiring RBL are combined into one wiring BIL can be employed. FIG. 15E A circuit structure example of the memory cell in this case is shown. In the memory cell 954, the wiring WBL and the wiring RBL of the memory cell 953 are combined into one wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. That is, the memory cell 954 operates with the write bit line and the read bit line combined into one wiring BIL.

[0444] FIG. 15F The memory cell 955 shown is an example in which the capacitor CB and the wiring CAL in the memory cell 953 are omitted. Furthermore, FIG. 15G The memory cell 956 shown is an example in which the capacitor CB and the wiring CAL in the memory cell 954 are omitted. By employing such a structure, the degree of integration of the memory cell can be increased.

[0445] Note that it is preferable to use an OS transistor at least for the transistor M2. In particular, it is preferable to use an OS transistor for the transistor M2 and the transistor M3.

[0446] Since an OS transistor has a characteristic of having a very small off-state current, the transistor M2 can hold written data for a long time, whereby the refresh frequency of the memory cell can be reduced. Furthermore, the refresh operation of the memory cell can be omitted. Furthermore, since the leakage current is very low, the memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956 can hold multi-value data or analog data.

[0447] The memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956 each using an OS transistor as the transistor M2 are one embodiment of an NOSRAM.

[0448] An Si transistor can also be used as the transistor M3. An Si transistor can increase field-effect mobility and can be a p-channel transistor, and thus can increase the degree of freedom of circuit design.

[0449] Further, when an OS transistor is used as the transistor M3, the memory cell can be configured with unipolar circuits.

[0450] Further, FIG. 15H A gain cell type memory cell 957 including three transistors and one capacitor is shown. The memory cell 957 includes transistors M4 to M6 and a capacitor CC.

[0451] The first terminal of the transistor M4 is connected to the first terminal of the capacitor CC, the second terminal of the transistor M4 is connected to a wiring BIL, and the gate of the transistor M4 is connected to a wiring WOL. The second terminal of the capacitor CC is connected to the first terminal of the transistor M5 and a wiring GNDL. The second terminal of the transistor M5 is connected to the first terminal of the transistor M6, and the gate of the transistor M5 is connected to the first terminal of the capacitor CC. The second terminal of the transistor M6 is connected to the wiring BIL, and the gate of the transistor M6 is connected to a wiring RWL.

[0452] The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring supplying a low potential.

[0453] Writing of data is performed by making the transistor M4 an on state by applying a high potential to the wiring WOL and making the wiring BIL and the first terminal of the capacitor CC an on state. Specifically, when the transistor M4 is an on state, a potential corresponding to information to be recorded is applied to the wiring BIL to write the potential to the first terminal of the capacitor CC and the gate of the transistor M5. Then, the transistor M4 is made an off state by applying a low potential to the wiring WOL, whereby the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5 are held.

[0454] Data readout is performed by pre-charging the wiring BIL to a predetermined potential, then making the wiring BIL electrically floating and applying a high-level potential to the wiring RWL. By making the wiring RWL high, transistor M6 is turned on, and the wiring BIL and the second terminal of transistor M5 are connected. At this time, the potential of the wiring BIL is applied to the second terminal of transistor M5, but the potential of the second terminal of transistor M5 and the potential of the wiring BIL will change correspondingly to the potential held by the first terminal of capacitor CC (or the gate of transistor M5). Here, the potential held by the first terminal of capacitor CC (or the gate of transistor M5) can be read by reading the potential of the wiring BIL. In other words, the information written to the memory cell can be read from the potential held by the first terminal of capacitor CC (or the gate of transistor M5).

[0455] Note that it is preferable to use the OS transistor as at least transistor M4.

[0456] Si transistors can also be used as transistors M5 and M6. As mentioned above, the field-effect mobility of Si transistors is sometimes higher than that of OS transistors, depending on factors such as the crystallization state of the silicon used in the semiconductor layer.

[0457] Furthermore, when OS transistors are used as transistors M5 and M6, the memory cell can be constructed from unipolar circuits.

[0458] [OS-SRAM] FIG. 15H An example of SRAM (Static Random Access Memory) using OS transistors is shown. In this specification, etc., SRAM using OS transistors will be referred to as OS-SRAM (Oxide Semiconductor-SRAM). Furthermore, FIG. 16A The storage unit 958 shown is an SRAM-type storage unit capable of backup.

[0459] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, capacitor CD1, and capacitor CD2. Transistors MS1 and MS2 are p-channel transistors, and transistors MS3 and MS4 are n-channel transistors.

[0460] The first terminal of the transistor M7 is connected to the wiring BIL, and the second terminal of the transistor M7 is connected to the first terminal of the transistor MS1, the first terminal of the transistor MS3, the gate of the transistor MS2, the gate of the transistor MS4, and the first terminal of the transistor M10. The gate of the transistor M7 is connected to the wiring WOL. The first terminal of the transistor M8 is connected to the wiring BILB, and the second terminal of the transistor M8 is connected to the first terminal of the transistor MS2, the first terminal of the transistor MS4, the gate of the transistor MS1, the gate of the transistor MS3, and the first terminal of the transistor M9. The gate of the transistor M8 is connected to the wiring WOL.

[0461] The second terminal of the transistor MS1 is connected to the wiring VDL. The second terminal of the transistor MS2 is connected to the wiring VDL. The second terminal of the transistor MS3 is connected to the wiring GNDL. The second terminal of the transistor MS4 is connected to the wiring GNDL.

[0462] The second terminal of the transistor M9 is connected to the first terminal of the capacitor CD1, and the gate of the transistor M9 is connected to the wiring BRL. The second terminal of the transistor M10 is connected to the first terminal of the capacitor CD2, and the gate of the transistor M10 is connected to the wiring BRL.

[0463] The second terminal of the capacitor CD1 is connected to the wiring GNDL, and the second terminal of the capacitor CD2 is connected to the wiring GNDL.

[0464] The wiring BIL and the wiring BILB function as bit lines, the wiring WOL functions as a word line, and the wiring BRL is a wiring for controlling the on state and the off state of the transistor M9 and the transistor M10.

[0465] The wiring VDL is a wiring for supplying a high-level potential, and the wiring GNDL is a wiring for supplying a low-level potential.

[0466] The writing of data is performed by applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is in the on state, a potential corresponding to information to be recorded is applied to the wiring BIL, and the potential is written to the side of the second terminal of the transistor M10.

[0467] The storage unit 958 is configured with the transistors MS1 to MS2 as an inverter loop, so an inverted signal of the data signal corresponding to the potential is input to the second terminal side of the transistor M8. Since the transistor M8 is in an on state, the potential applied to the wiring BIL, that is, the inverted signal of the signal input to the wiring BIL is output to the wiring BILB. Further, since the transistors M9 and M10 are in an on state, the potential of the second terminal of the transistor M7 and the potential of the second terminal of the transistor M8 are held by the first terminal of the capacitor CD2 and the first terminal of the capacitor CD1, respectively. Then, the potential of the first terminal of the capacitor CD1 and the potential of the first terminal of the capacitor CD2 are held by making the transistors M7 to M10 into an off state by applying a low potential to the wiring WOL and a low potential to the wiring BRL.

[0468] The readout of the data is performed by the following method: first, the wiring BIL and the wiring BILB are precharged to predetermined potentials, and then a high potential is applied to the wiring WOL and a high potential is applied to the wiring BRL, whereby the potential of the first terminal of the capacitor CD1 is refreshed by the inverter loop of the storage unit 958 and output to the wiring BILB. Further, the potential of the first terminal of the capacitor CD2 is refreshed by the inverter loop of the storage unit 958 and output to the wiring BIL. Since the wiring BIL and the wiring BILB change from the precharged potentials to the potential of the first terminal of the capacitor CD2 and the potential of the first terminal of the capacitor CD1, respectively, the potential held by the storage unit can be read out from the potential of the wiring BIL or the potential of the wiring BILB.

[0469] The transistors M7 to M10 are preferably OS transistors. By this, the data written can be held for a long time by the transistors M7 to M10, so the refresh frequency of the storage unit can be reduced. Alternatively, the refresh operation of the storage unit can be omitted.

[0470] Further, Si transistors are preferably used as the transistors MS1 to MS4.

[0471] The driving circuit 910 and the memory array 920 included in the semiconductor device 900 are provided on the same plane. Further, as shown in FIG. 9B, the driving circuit 910 and the memory array 920 can also overlap. By overlapping the driving circuit 910 and the memory array 920, the signal transmission distance can be shortened. FIG. 16B As shown in FIG. 9C, a plurality of memory arrays 920 can also be stacked on the driving circuit 910. FIG. 17

[0472] Next, one example of an arithmetic processing device which can include the above-described storage device and the like will be described.

[0473] FIG. 17 ​is a block diagram of the arithmetic device 960. FIG. 17 The arithmetic device 960 illustrated is, for example, used for a CPU (Central Processing Unit). In addition, the arithmetic device 960 can also be used for a GPU (Graphics Processing Unit) including a plurality of (tens to hundreds) processor cores capable of parallel processing, a TPU (Tensor Processing Unit), an NPU (Neural Processing Unit), and the like, which are more than a CPU.

[0474] FIG. 17 The arithmetic device 960 illustrated has, on a substrate 990, an ALU 991 (ALU: Arithmetic logic unit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989. As the substrate 990, a semiconductor substrate, an SOI substrate, a glass substrate, and the like are used. A rewritable ROM and a ROM interface can also be included. The cache 999 and the cache interface 989 can also be provided on different chips.

[0475] The cache 999 is connected to a main memory provided on a different chip through the cache interface 989. The cache interface 989 has a function of supplying a part of data stored in the main memory to the cache 999. In addition, the cache interface 989 has a function of outputting a part of data held in the cache 999 to the ALU 991, the register 996, or the like through the bus interface 998.

[0476] As described later, the memory array 920 can be provided in a manner of being stacked on the arithmetic device 960. The memory array 920 can be used as a cache. At this time, the cache interface 989 can have a function of supplying data held in the memory array 920 to the cache 999. In addition, at this time, it is preferable that a part of the cache interface 989 include the drive circuit 910.

[0477] Note that the cache 999 can also not be provided and only the memory array 920 can be used as a cache.

[0478] FIG. 17 The arithmetic device 960 illustrated is only one example of a simplified structure thereof, and an actual arithmetic device 960 has various structures according to its use. For example, it is preferable to adopt a structure including FIG. 17The computing device 960 shown has a multi-core structure, which consists of a single core and multiple cores that operate simultaneously. The more cores, the better the computing performance. More cores are preferred; for example, two cores are preferred, four cores are more preferred, eight cores are even more preferred, twelve cores are still more preferred, and sixteen cores or more are even more preferred. Furthermore, when used in servers or other applications requiring very high computing performance, a multi-core structure with 16 or more cores is preferred, more preferably 32 or more cores, and more preferably 64 or more cores. Additionally, the number of bits that can be processed in the internal computing circuitry, data bus, etc., of the computing device 960 can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0479] Instructions input to the arithmetic unit 960 via the bus interface 998 are input to the instruction decoder 993 and, after being decoded, are input to the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995.

[0480] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals to control the operation of the ALU 991. Furthermore, when executing the program of the arithmetic unit 960, the interrupt controller 994 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc., based on their priority and mask state. The register controller 997 generates the address of register 996 and reads and writes register 996 according to the state of the arithmetic unit 960.

[0481] Furthermore, the timing controller 995 generates signals to control the operating timing of the ALU 991, ALU controller 992, instruction decoder 993, interrupt controller 994, and register controller 997. For example, the timing controller 995 has an internal clock generator that generates an internal clock signal based on a reference clock signal and supplies the internal clock signal to the aforementioned circuits.

[0482] exist FIG. 18A In the arithmetic unit 960 shown, the register controller 997 selects the holding operation of register 996 according to instructions from ALU 991. In other words, the register controller 997 selects whether data is held in the memory cells of register 996 by flip-flops or by capacitors. When data is held by flip-flops, a power supply potential is supplied to the memory cells in register 996. When data is held by capacitors, the data is overwritten to the capacitors, and the power supply potential to the memory cells in register 996 can be stopped.

[0483] The memory array 920 and the arithmetic device 960 can be arranged so as to overlap. FIG. 18B and FIG. 18B is a perspective view of the semiconductor device 970A. The semiconductor device 970A includes the layer 930 provided with the memory array on the arithmetic device 960. The layer 930 is provided with the memory array 920L1, the memory array 920L2, and the memory array 920L3. The arithmetic device 960 and each of the memory arrays have regions that overlap each other. In order to easily understand the structure of the semiconductor device 970A, the arithmetic device 960 and the layer 930 are separately shown in FIG. 18B .

[0484] By arranging the layer 930 including the memory array and the arithmetic device 960 so as to overlap, the connection distance between the two can be shortened. Thus, the communication speed between the two can be increased. Further, because the connection distance is short, power consumption can be reduced.

[0485] As a method of laminating the layer 930 including the memory array and the arithmetic device 960, a method in which the layer 930 including the memory array is directly laminated on the arithmetic device 960 (also referred to as monolithic lamination) or a method in which the arithmetic device 960 and the layer 930 are formed on different substrates, respectively, the two substrates are bonded together, and the substrates are electrically connected using a through-hole or a conductive film bonding technique (Cu-Cu bonding or the like) can be employed. In the former method, misalignment at the time of bonding does not need to be considered, and thus not only the chip size can be reduced but also the manufacturing cost can be reduced.

[0486] Here, the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 and not including the cache 999 in the arithmetic device 960 can all be used as a cache. At this time, for example, the memory array 920L1, the memory array 920L2, and the memory array 920L3 can be used as an L1 cache (also referred to as a level 1 cache), an L2 cache (also referred to as a level 2 cache), and an L3 cache (also referred to as a level 3 cache), respectively. Among the three memory arrays, the memory array 920L3 has the largest capacity and the lowest access frequency. Further, the memory array 920L1 has the smallest capacity and the highest access frequency.

[0487] Note that, when the cache 999 provided in the arithmetic device 960 is used as an L1 cache, each of the memory arrays provided in the layer 930 can be used as a lower-level cache or a main memory. The main memory is a memory having a larger capacity and a lower access frequency than a cache.

[0488] Further, as shown in FIG. 19AAs shown, the drive circuit 910L1, the drive circuit 910L2, and the drive circuit 910L3 are provided. The drive circuit 910L1 is connected to the memory array 920L1 through the connection electrode 940L1. Similarly, the drive circuit 910L2 is connected to the memory array 920L2 through the connection electrode 940L2, and the drive circuit 910L3 is connected to the memory array 920L3 through the connection electrode 940L3.

[0489] Note that although the case where the memory arrays serving as the cache are three is described here, one, two, or more than four can be used.

[0490] When the memory array 920L1 is used as the cache, the drive circuit 910L1 can also be used as part of the cache interface 989, and the drive circuit 910L1 can also be connected to the cache interface 989. Similarly, the drive circuit 910L2 and the drive circuit 910L3 can also be used as or connected to part of the cache interface 989.

[0491] Whether the memory array 920 is used as the cache or as the main memory depends on the control circuit 912 included in each drive circuit 910. The control circuit 912 can use part of the plurality of memory cells 950 included in the semiconductor device 900 as RAM in accordance with a signal supplied from the arithmetic device 960.

[0492] In the semiconductor device 900, part of the plurality of memory cells 950 can be used as the cache and another part can be used as the main memory. That is, the semiconductor device 900 can have a function as the cache and a function as the main memory. The semiconductor device 900 according to one embodiment of the present application can be used as a general-purpose memory, for example.

[0493] Further, the layer 930 including one memory array 920 can be provided in a manner overlapping with the arithmetic device 960. FIG. 19A is a perspective view of the semiconductor device 970B.

[0494] In the semiconductor device 970B, one memory array 920 can be divided into a plurality of regions and used with different functions. FIG. 19B An example in which the region L1, the region L2, and the region L3 are used as an L1 cache, an L2 cache, and an L3 cache, respectively, is shown.

[0495] Further, in the semiconductor device 970B, the capacity of each of the regions L1 to L3 can be changed depending on a situation. For example, an increase in the capacity of the L1 cache is achieved by increasing the area of the region L1. With such a structure, high efficiency of an arithmetic process can be achieved, which improves the processing speed.

[0496] Furthermore, a plurality of memory arrays can be stacked. FIG. 20A is a perspective view of the semiconductor device 970C.

[0497] The semiconductor device 970C has stacked thereon a layer 930L1 including a memory array 920L1, a layer 930L2 including a memory array 920L2 thereon, and a layer 930L3 including a memory array 920L3 thereon. The memory array 920L1 physically closest to the arithmetic device 960 can be used as an upper cache and the memory array 920L3 farthest from the arithmetic device 960 can be used as a lower cache or a main memory. By employing such a structure, the capacity of each memory array can be increased, and thus the processing capability can be further improved.

[0498] The present embodiment can be appropriately combined with other embodiments.

[0499] (Embodiment 4) An application example of a storage device of one embodiment of the present application is described in this embodiment.

[0500] Generally, in a semiconductor device such as a computer, various storage devices are used according to their uses. FIG. 20A Various storage devices for a semiconductor device are shown in a hierarchy. The higher the storage device is in the hierarchy, the faster the operation speed is required, and the lower the storage device is in the hierarchy, the larger the storage capacity and the higher the recording density are required. In the FIG. 20A In the hierarchy, a memory installed as a register in an arithmetic processing device such as a CPU, an L1 cache, an L2 cache, an L3 cache, a main memory, a storage, and the like are included in order from the top. Note that although an example including an L3 cache is shown here, a cache at a lower level can be included.

[0501] Since the memory installed as a register in an arithmetic processing device such as a CPU is used for temporary storage of an operation result or the like, the frequency of access from the arithmetic processing device is high. Thus, the operation speed is required to be faster than the storage capacity. Furthermore, the register has a function of holding setting information of the arithmetic processing device or the like.

[0502] The cache has a function of copying and holding a part of information held in the main memory. By copying data with a high frequency of use to the cache, the speed of access to the data can be improved. The storage capacity required for the cache is smaller than that required for the main memory, and the operation speed required for the cache is higher than that required for the main memory. Furthermore, data to be rewritten in the cache is copied and supplied to the main memory.

[0503] The main memory has a function of holding a program, data, or the like read out from a storage.

[0504] The storage stores functions of holding data that needs to be kept for a long time and various programs and the like used by the arithmetic processing device. Thus, a larger storage capacity and a higher recording density are required in comparison with a faster operation speed. For example, a large-capacity nonvolatile storage device such as 3D NAND can be used.

[0505] The storage device according to one embodiment of the present application using an oxide semiconductor (OS memory) is fast in operation and can hold data for a long period. Thus, as illustrated in FIG. 1, the storage device according to one embodiment of the present application can be used for both a hierarchy including a cache and a hierarchy including a main memory. Further, the storage device according to one embodiment of the present application can also be used for a hierarchy including storage. FIG. 20B

[0506] Further, as illustrated in FIG. 2, the storage device according to one embodiment of the present application can be used for a hierarchy including a cache. FIG. 20B An example of a case where SRAM is used for part of a cache and the OS memory according to one embodiment of the present application is used for the other part is shown.

[0507] The cache at the lowest level can be referred to as LLC (Last Level Cache). The LLC does not need to be faster in operation than the cache at the upper level, but is required to have a larger storage capacity. The OS memory according to one embodiment of the present application is fast in operation and can hold data for a long period, and thus can be suitably used for the LLC. Note that the OS memory according to one embodiment of the present application can also be used for FLC (Final Level Cache).

[0508] For example, as illustrated in FIG. 3, SRAM can be used for the cache at the upper level (L1 cache, L2 cache, or the like) and the OS memory according to one embodiment of the present application can be used for the LLC. FIG. 20B FIG. 21A In the main memory, DRAM can be used in addition to the OS memory, as illustrated in FIG. 4.

[0509] The present embodiment can be combined as appropriate with other embodiments.

[0510] (Embodiment 5) A display device according to one embodiment of the present application is described in this embodiment.

[0511] ​​The semiconductor device of one embodiment of the present application can be used for a display device or a module including the display device. As a module including the display device, a module to which a flexible printed circuit (FPC) or a tape carrier package (TCP) or the like is attached can be given, a module having an integrated circuit (IC) mounted thereon by chip on glass (COG) or chip on film (COF) can be given, and the like.

[0512] Further, the display device of this embodiment can have a function of a touch panel. For example, various detection elements (which can be referred to as sensor elements) capable of detecting proximity or contact of a detection object such as a finger can be used for the display device.

[0513] For example, as a method of a sensor, an electrostatic capacity method, a resistance film method, a surface acoustic wave method, an infrared method, an optical method, and a pressure-sensitive method can be given.

[0514] As the electrostatic capacity method, for example, a surface type electrostatic capacity method, a projection type electrostatic capacity method, and the like can be given. Further, as the projection type electrostatic capacity method, for example, a self-capacitance method, a mutual-capacitance method, and the like can be given. The mutual-capacitance method is preferably used, whereby multi-point detection can be performed at the same time.

[0515] As the touch panel, for example, an Out-Cell type, an On-Cell type, and an In-Cell type can be given. Note that the In-Cell type touch panel refers to a structure in which an electrode included in a detection element is provided in one or both of a substrate and a counter substrate which support a display element.

[0516] [Display Module] FIG. 21B A perspective view of a display module 170 is shown. The display module 170 includes a display device 600A and an FPC 298. Note that the display device included in the display module 170 is not limited to the display device 600A, and can be the display device 600B described later.

[0517] The display module 170 includes a substrate 291 and a substrate 299. The display module 170 includes a display portion 297. The display portion 297 is an image display region in the display module 170, and light from each pixel provided in a pixel portion 294 described below can be seen.

[0518] FIG. 21Bis a perspective view of a structure on one side of the substrate 291. The substrate 291 has the circuit portion 292, the pixel circuit portion 293 over the circuit portion 292, and the pixel portion 294 over the pixel circuit portion 293 stacked thereover. Further, a terminal portion 295 to be connected to an FPC 298 is provided over a portion of the substrate 291 which does not overlap with the pixel portion 294. The terminal portion 295 is electrically connected to the circuit portion 292 through a wiring portion 296 formed with a plurality of wires.

[0519] The semiconductor device of one embodiment of the present application can be applied to one or both of the circuit portion 292 and the pixel circuit portion 293.

[0520] The pixel portion 294 includes a plurality of pixels 294a arranged periodically. FIG. 21B An enlarged view of one pixel 294a is shown on the right side. FIG. 21B An example is shown in which one pixel 294a includes a sub-pixel 130R which emits red light, a sub-pixel 130G which emits green light, and a sub-pixel 130B which emits blue light.

[0521] The sub-pixel includes a display element. As the display element, a variety of elements can be used, for example, a liquid crystal element and a light-emitting element can be given. In addition to the above, a MEMS (Micro Electro Mechanical Systems) element of a shutter type or a light interference type, a display element using a microcapsule, an electrophoretic type, an electro-wetting type, an electronic ink type, or the like, and the like can be used. In addition, a QLED (Quantum-dot LED) using a light source and a color conversion technology using a quantum dot material can be used.

[0522] As the light-emitting element, for example, a LED (Light Emitting Diode), an OLED (Organic LED), a semiconductor laser, or the like can be given. As the LED, a Mini LED, a Micro LED, or the like can be used.

[0523] There is no particular limitation on the arrangement of pixels in the display device of this embodiment, and various methods can be employed. As the arrangement of pixels, for example, a stripe arrangement, an S stripe arrangement, a matrix arrangement, a Delta arrangement, a Bayer arrangement, and a Pentile arrangement can be given. FIG. 22 An example is shown in which the arrangement of pixels employs a stripe arrangement.

[0524] The pixel circuit portion 293 includes a plurality of pixel circuits 293a arranged periodically.

[0525] A pixel circuit 293a controls driving of the elements included in a pixel 294a. Three circuits that control light emission of a light emitting element can be provided in a pixel circuit 293a. For example, the pixel circuit 293a can have a structure in which at least a selection transistor, a transistor for current control (a driver transistor), and a capacitor are provided for a light emitting element. In this case, the gate of the selection transistor is input with a gate signal, and the source is input with a source signal. Thus, an active matrix display device is realized.

[0526] The circuit portion 292 includes a circuit that drives each pixel circuit 293a of the pixel circuit portion 293. For example, one or both of a gate line drive circuit and a source line drive circuit are preferably included. In addition, at least one of an arithmetic circuit, a storage circuit, and a power supply circuit, and the like can be included.

[0527] The FPC 298 functions as a wiring that supplies a video signal or a power supply potential, and the like from the outside to the circuit portion 292. In addition, an IC can be mounted on the FPC 298.

[0528] The display module 170 can have a structure in which one or both of the pixel circuit portion 293 and the circuit portion 292 are provided on the lower side of the pixel portion 294, and thus the display portion 297 can have a very high aperture ratio (effective display area ratio). In addition, the pixels 294a can be arranged at a very high density, and thus the display portion 297 can have a very high definition.

[0529] Such a high-definition display module 170 is suitable for use in a VR device such as an HMD or an eyeglass-type AR device. For example, because the display module 170 has a display portion 297 with a very high definition, in a structure in which the display portion of the display module 170 is viewed through a lens, even if the display portion is enlarged by the lens, the user cannot see the pixels, and thus a display with a high sense of immersion can be realized. In addition, the display module 170 can also be applied to an electronic device having a relatively small display portion. For example, the display module 170 is suitable for use in a display portion of a wearable electronic device such as a watch-type device.

[0530] [Structure Example 1 of Display Device] FIG. 22 is a cross-sectional view of a display device 600A. The display device 600A is an example of a display device that employs an MML structure. That is, the display device 600A includes a light emitting element that is not manufactured using a high-precision metal mask.

[0531] The island-shaped light-emitting layer in the light-emitting element included in the display device having the MML structure is formed by processing after deposition of the light-emitting layer over the entire surface using photolithography. Thus, a display device of high definition or a display device of high aperture ratio, which has been difficult to achieve so far, can be realized. Furthermore, since the light-emitting layer can be formed separately for each color, a display device of extremely high vividness, high contrast, and high display quality can be realized. For example, in the case of using three kinds of light-emitting elements that emit blue light, green light, and red light to constitute a display device, three kinds of island-shaped light-emitting layers can be formed by repeating formation of the light-emitting layer and processing using photolithography three times.

[0532] Since the device having the MML structure can be manufactured without using a metal mask, the upper limit of the definition due to the alignment accuracy of the metal mask can be exceeded. Furthermore, in the case where the device is manufactured without using a metal mask, equipment related to the manufacture of the metal mask and a cleaning process of the metal mask can not be needed. Furthermore, in the processing using photolithography, the same equipment as or common equipment as that used when a transistor is manufactured can be used, so that a special equipment for manufacturing a device having the MML structure need not be introduced. Thus, by virtue of the MML structure, the manufacturing cost can be reduced, so that mass production of the device is suitable.

[0533] In the display device having the MML structure, for example, a special pixel arrangement such as a Pentile arrangement is not needed to improve the definition in a pseudo manner, so that a display device in which a so-called stripe arrangement in which sub-pixels of R, G, and B are arranged in one direction is adopted and the definition is high (e.g., 500 ppi or higher, 1000 ppi or higher, 2000 ppi or higher, 3000 ppi or higher, or 5000 ppi or higher) can be realized.

[0534] Furthermore, by providing a sacrificial layer over the light-emitting layer, damage to the light-emitting layer in the manufacturing process of the display device can be reduced, and the reliability of the light-emitting element can be improved. The sacrificial layer can be left in the completed display device or can be removed in the manufacturing process. For example, FIG. 23 , a sacrificial layer 618a described later FIG. 30 and FIG. 22 is a part of the sacrificial layer provided over the light-emitting layer.

[0535] Furthermore, by employing a deposition process using a range mask and a processing process using a resist mask, the light-emitting element can be manufactured with a simpler process.

[0536] FIG. 22 A display device 600A is a cross-sectional view of a display device (semiconductor device) of one embodiment of the present application. In the display device 600A, a pixel circuit, a driver circuit, and the like are provided over a substrate 410. In the display device 600A, a light-emitting element 420 having an MML structure is provided over the substrate 410.FIG. 22 In the display device 600A, a wiring layer 670 is illustrated in addition to the element layer 620, the element layer 630, and the element layer 660. The wiring layer 670 is a layer in which a wiring is provided.

[0537] In the element layer 630, a pixel circuit of the display device is preferably provided. In the element layer 620, a driver circuit (one or both of a gate driver and a source driver) of the display device is preferably provided. Furthermore, in the element layer 620, one or more of various circuits such as a calculation circuit, a storage circuit, and the like can be provided.

[0538] As one example, the element layer 620 includes a substrate 410 over which a transistor 400d is formed. Furthermore, a wiring layer 670 is provided over the transistor 400d, and the wiring layer 670 includes a wiring which electrically connects the transistor 400d and a conductive layer or a transistor (the conductive layer 514 in FIG. 6A) provided in the element layer 630. FIG. 22 Furthermore, the element layer 630 and the element layer 660 are provided over the wiring layer 670, and the element layer 630 includes, for example, a transistor MTCK and the like. The element layer 660 includes a light-emitting element 650 (the light-emitting element 650R, the light-emitting element 650G, and the light-emitting element 650B in FIG. 6A) and the like. FIG. 22

[0539] The transistor 400d is one example of a transistor included in the element layer 620. Furthermore, the transistor MTCK is one example of a transistor included in the element layer 630. Furthermore, the light-emitting element (the light-emitting element 650R, the light-emitting element 650G, and the light-emitting element 650B) is one example of a light-emitting element included in the element layer 660.

[0540] As the transistor MTCK, an OS transistor can be used, for example. FIG. 22 An example in which the transistor 200 described in the above embodiment is used as the transistor MTCK is illustrated.

[0541] As the substrate 410, a semiconductor substrate (e.g., a single crystal substrate in which silicon or germanium is used as a material) can be used, for example. Furthermore, as the substrate 410, a substrate other than a semiconductor substrate, such as an SOI (Silicon On Insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate including a stainless steel foil, a tungsten substrate, a substrate including a tungsten foil, a flexible substrate, a bonding film, paper or a base film including a fibrous material can be used, for example. In this embodiment, a case in which the substrate 410 is a semiconductor substrate including silicon as a material is described. Thus, the transistor in the element layer 620 can be a Si transistor.

[0542] ​The transistor 400d includes an element isolation layer 412, a conductive layer 416, an insulating layer 415, an insulating layer 417, a semiconductor region 413 formed of a portion of the substrate 410, a low-resistance region 414a serving as a source region or a drain region, and a low-resistance region 414b. Thus, the transistor 400d is an Si transistor. Although FIG. 22 Although a structure in which a source or a drain of the transistor 400d is electrically connected to the conductive layer 514 provided in the element layer 630 through the conductive layer 428, the conductive layer 430, and the conductive layer 456 is illustrated, the electrical connection structure of the display device of one embodiment of the present application is not limited thereto.

[0543] The transistor 400d can have a Fin structure, for example, by a structure in which the top surface and side surfaces in the channel width direction of the semiconductor region 413 are covered with the conductive layer 416 with the insulating layer 415 serving as a gate insulating layer. By forming the Fin transistor 400d, the effective channel width can be increased, so that the on-state characteristics of the transistor 400d can be improved. Furthermore, since the effect of the electric field of the gate electrode can be enhanced, the off-state characteristics of the transistor 400d can be improved. Alternatively, the transistor 400d can have a planar structure without the Fin structure.

[0544] Furthermore, the transistor 400d can be either a p-channel transistor or an n-channel transistor. Furthermore, a plurality of transistors 400d can be provided, and both a p-channel transistor and an n-channel transistor can be used.

[0545] The channel formation region of the semiconductor region 413, a region in the vicinity thereof, the low-resistance region 414a serving as a source region or a drain region, and the low-resistance region 414b preferably include a silicon-based semiconductor, specifically, single crystal silicon. Alternatively, each of the regions can be formed using germanium, silicon germanium, gallium arsenide, aluminum gallium arsenide, or gallium nitride, for example. Silicon in which the effective mass is controlled by applying stress to a lattice to change the interplanar spacing can be used. Furthermore, the transistor 400d can be a HEMT (High Electron Mobility Transistor) using gallium arsenide and aluminum gallium arsenide, for example.

[0546] As the conductive layer 416 serving as a gate electrode, a semiconductor material such as silicon including an element such as arsenic or phosphorus which imparts n-type conductivity or an element such as boron or aluminum which imparts p-type conductivity can be used. Alternatively, as the conductive layer 416, a conductive material such as a metal material, an alloy material, or a metal oxide material can be used, for example.

[0547] Further, since the material of the conductive layer determines the work function, the threshold voltage of the transistor can be adjusted by selecting the material of the conductive layer. Specifically, as the conductive layer, one or both of a material of titanium nitride and a material of tantalum nitride is preferably used. In order to have conductivity and embeddability, a stack of a metal material of one or both of tungsten and aluminum is preferably used as the conductive layer, and tungsten is particularly preferably used in terms of heat resistance.

[0548] The element isolation layer 412 is provided so as to separate the plurality of transistors formed over the substrate 410 from each other. The element isolation layer can be formed using, for example, a LOCOS (Local Oxidation of Silicon) method, an STI (Shallow Trench Isolation) method, or a mesa isolation method.

[0549] FIG. 22 The transistor 400d is provided with the insulating layer 420 and the insulating layer 422 stacked in this order from the substrate 410 side.

[0550] As the insulating layer 420 and the insulating layer 422, one or more selected from silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, and aluminum nitride, for example, can be used.

[0551] The insulating layer 422 can also be used as a planarization film for planarizing a step caused by the transistor 400d and the like covered with the insulating layer 420 and the insulating layer 422. For example, in order to improve planarity, the top surface of the insulating layer 422 can also be planarized by planarization treatment using a CMP method or the like.

[0552] The conductive layer 428 connected to the transistor MTCK and the like provided above the insulating layer 422 is embedded in the insulating layer 420 and the insulating layer 422. Further, the conductive layer 428 has a function of a plug or a wiring.

[0553] In the display device 600A, the wiring layer 670 is provided over the transistor 400d. The wiring layer 670 includes, for example, the insulating layer 424, the insulating layer 426, the conductive layer 430, the insulating layer 450, the insulating layer 452, the insulating layer 454, and the conductive layer 456.

[0554] The insulating layer 424 and the insulating layer 426 are stacked in this order over the insulating layer 422 and the conductive layer 428. Further, in a region overlapping with the conductive layer 428, an opening is formed in the insulating layer 424 and the insulating layer 426. Further, the conductive layer 430 is embedded in the opening.

[0555] Further, the insulating layer 426 and the conductive layer 430 are provided with the insulating layer 450, the insulating layer 452, and the insulating layer 454 in this order. Further, in a region overlapping with the conductive layer 430, openings are formed in the insulating layer 450, the insulating layer 452, and the insulating layer 454. Further, the openings are embedded with the conductive layer 456.

[0556] The conductive layer 430 and the conductive layer 456 have, for example, a function of a plug or a wiring connected to the transistor 400d.

[0557] For example, like the insulating layer 592 to be described later, the insulating layer 424 and the insulating layer 450 are preferably formed using an insulating layer having a barrier property against one or more selected from hydrogen, oxygen, and water. Further, like the insulating layer 594 to be described later, the insulating layer 426, the insulating layer 452, and the insulating layer 454 are preferably formed using an insulating layer having a low relative dielectric constant in order to reduce parasitic capacitance generated between wirings. Further, the insulating layer 426, the insulating layer 452, and the insulating layer 454 are used as an interlayer insulating film and a planarization film.

[0558] Further, the conductive layer 456 preferably includes a conductive layer having a barrier property against one or more selected from hydrogen, oxygen, and water.

[0559] Note that as the insulating layer having a hydrogen barrier property, for example, tantalum nitride is preferably used. Further, by stacking tantalum nitride and tungsten having high conductivity, it is possible to maintain the conductivity as a wiring and to suppress diffusion of hydrogen from the transistor 400d. At this time, the tantalum nitride layer having a hydrogen barrier property is preferably in contact with the insulating layer 450 having a hydrogen barrier property.

[0560] Further, the insulating layer 454 and the conductive layer 456 are provided with the insulating layer 513 thereover. Further, the insulating layer 513 is provided with the insulating layer IS1. Further, the insulating layer IS1 and the insulating layer 513 are embedded with a conductive layer serving as a plug or a wiring. Thus, the transistor 400d can be electrically connected to the conductive layer 514 provided in the element layer 630. Alternatively, one of a source and a drain of the transistor MTCK can be electrically connected to one of a source and a drain of the transistor 400d.

[0561] The insulating layer IS1 is provided with the transistor MTCK and the insulating layer IS2. The insulating layer IS2 includes an opening in which a semiconductor layer of the transistor MTCK, an insulating layer serving as a gate insulating layer, a conductive layer serving as a gate electrode, and the like are provided. Further, the transistor MTCK is provided with the insulating layer IS3, the insulating layer 574, and the insulating layer 581 in this order. Further, the insulating layer IS3, the insulating layer 574, and the insulating layer 581 are embedded with a conductive layer MPG serving as a plug or a wiring.

[0562] The insulating layer 574 preferably has a function of inhibiting diffusion of impurities such as water and hydrogen (one or both of hydrogen atoms and hydrogen molecules). In other words, the insulating layer 574 is preferably used as a barrier insulating film that inhibits the impurities from being mixed into the transistor MTCK. Furthermore, the insulating layer 574 preferably has a function of inhibiting diffusion of oxygen (one or both of oxygen atoms and oxygen molecules). For example, the oxygen permeability of the insulating layer 574 is preferably lower than that of the insulating layer IS2 and the insulating layer IS3.

[0563] Thus, the insulating layer 574 is preferably used as a barrier insulating film that inhibits diffusion of impurities such as water and hydrogen. Thus, the insulating layer 574 preferably uses an insulating material having a function of inhibiting diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., N20, NO, and NO2), and copper atoms (the above-described impurities are not easily permeated). Alternatively, an insulating material having a function of inhibiting diffusion of oxygen (one or both of oxygen atoms and oxygen molecules) (the above-described oxygen is not easily permeated) is preferably used.

[0564] As the insulating layer having a function of inhibiting permeation of impurities such as water and hydrogen and oxygen, a material that can be used for an insulating layer having a function of inhibiting permeation of impurities and oxygen, which is described in Embodiment Mode 1, can be used.

[0565] It is particularly preferable that aluminum oxide or silicon nitride be used as the insulating layer 574. By this means, diffusion of impurities such as water and hydrogen from above the insulating layer 574 to the transistor MTCK can be inhibited. Alternatively, diffusion of oxygen included in the insulating layer IS3 and the like to above the insulating layer 574 can be inhibited.

[0566] The insulating layer 581 is preferably used as an interlayer film and has a lower dielectric constant than the insulating layer 574. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced. For example, the relative dielectric constant of the insulating layer 581 is preferably lower than 4, more preferably lower than 3. For example, the relative dielectric constant of the insulating layer 581 is preferably 0.7 times or less, more preferably 0.6 times or less, of the relative dielectric constant of the insulating layer 574. By using an interlayer film of a material with a low dielectric constant as the insulating layer 581, parasitic capacitance generated between wirings can be reduced.

[0567] ​Further, the concentration of impurities such as water and hydrogen in the insulating layer 581 is preferably reduced. At this time, as the insulating layer 581, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride can be used. Further, as the insulating layer 581, for example, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or porous silicon oxide can be used. In particular, silicon oxide and silicon oxynitride have heat resistance, and are thus preferable. In particular, since a material such as silicon oxide, silicon oxynitride, or porous silicon oxide easily forms a region containing oxygen which is separated by heating, it is preferable. Further, as the insulating layer 581, a resin can be used. Further, as a material which can be used for the insulating layer 581, the above-described materials can be appropriately combined.

[0568] The insulating layer 574 and the insulating layer 581 have the insulating layer 592 and the insulating layer 594 stacked thereover in this order.

[0569] Further, the insulating layer 592 preferably uses a barrier insulating film (referred to as a barrier insulating film) which prevents impurities such as water and hydrogen from diffusing from the substrate 410 and the transistor MTCK to a region above the insulating layer 592 (e.g., a region in which the light emitting element 650R, the light emitting element 650G, and the light emitting element 650B, and the like are provided). Thus, the insulating layer 592 preferably uses an insulating material which has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, and water molecules (not easy to make the above-described oxygen permeate). Further, depending on the case, the insulating layer 592 preferably uses an insulating material which has a function of suppressing diffusion of impurities such as nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., N2O, NO, and NO2), and copper atoms (not easy to make the above-described impurities permeate). Alternatively, a function of suppressing diffusion of oxygen (e.g., one or both of oxygen atoms and oxygen molecules) is preferable.

[0570] As a film having a hydrogen barrier property, for example, silicon nitride formed by a CVD method can be used.

[0571] The amount of hydrogen desorption can be analyzed by, for example, a thermal desorption spectrometry (TDS). For example, in TDS, when the amount of desorption converted into hydrogen atoms is converted into the amount per unit area of the insulating layer 424, the amount of hydrogen desorption in the insulating layer 424 can be 10 x 10 15 atoms / cm 2 The following is preferable: 5 x 10 15 atoms / cm 2 or more.

[0572] Like the insulating layer 581, the insulating layer 594 is preferably an interlayer film with a low dielectric constant. Thus, the insulating layer 594 can use a material which can be used for the insulating layer 581.

[0573] Further, the dielectric constant of the insulating layer 594 is preferably lower than that of the insulating layer 592. For example, the relative dielectric constant of the insulating layer 594 is preferably lower than 4, more preferably lower than 3. Further, for example, the relative dielectric constant of the insulating layer 594 is preferably 0.7 times or less, more preferably 0.6 times or less, of the relative dielectric constant of the insulating layer 592. By using an interlayer film of a material having a low dielectric constant as the insulating layer 594, the parasitic capacitance generated between the wirings can be reduced.

[0574] Further, the conductive layer MPG and the conductive layer 596, which are used as plugs or wirings, are embedded in the insulating layer GI1 and the insulating layer IS3, and the insulating layer 592 and the insulating layer 594, respectively. In particular, the conductive layer MPG and the conductive layer 596 are electrically connected to the light emitting elements and the like provided above the insulating layer 594. Note that the same reference numerals are sometimes used to denote a plurality of conductive layers used as plugs or wirings. Further, in this specification and the like, a wiring and a plug connected to the wiring can be one constituent element. That is, a part of the conductive layer is sometimes used as a wiring, and a part of the conductive layer is sometimes used as a plug.

[0575] As a material of each of the plugs and the wirings (the conductive layer MPG, the conductive layer 428, the conductive layer 430, the conductive layer 456, the conductive layer 514, and the conductive layer 596), a single layer or a stack of one or more conductive materials selected from a metal material, an alloy material, a metal nitride material, and a metal oxide material can be used. A high melting point material such as tungsten or molybdenum, which has heat resistance and conductivity, is preferably used, and tungsten is particularly preferably used. Further, a low resistance conductive material such as aluminum or copper is preferably used. By using a low resistance conductive material, the wiring resistance can be reduced.

[0576] The insulating layer 598 and the insulating layer 599 are sequentially formed over the insulating layer 594 and the conductive layer 596.

[0577] As one example, the insulating layer 598 is preferably an insulating layer having a barrier property against one or more of hydrogen, oxygen, and water, like the insulating layer 592. Further, like the insulating layer 594, the insulating layer 599 is preferably an insulating layer having a low relative dielectric constant in order to reduce the parasitic capacitance generated between the wirings. Further, the insulating layer 599 is used as an interlayer insulating film and a planarization film.

[0578] The light emitting elements 650 and the connection portion 640 are formed over the insulating layer 599.

[0579] The connection portion 640 is sometimes referred to as a cathode contact portion, and is electrically connected to the cathode electrode of each of the light emitting elements 650R, 650G, and 650B. In FIG. 22In the connection portion 640, a conductive layer formed using the same process and material as the conductive layers 611a to 611c is electrically connected to the common electrode 615 described later. Although FIG. 22 Although an example is shown in which the conductive layer is electrically connected to the common electrode 615 through the common layer 614 described later, the conductive layer can also be in direct contact with the common electrode 615.

[0580] The connection portion 640 can be provided so as to surround the four sides of the display portion in plan view, or can be provided inside the display portion (e.g., between adjacent light emitting elements 650) (not shown).

[0581] The light emitting element 650R includes the conductive layer 611a as a pixel electrode. Similarly, the light emitting element 650G includes the conductive layer 611b as a pixel electrode, and the light emitting element 650B includes the conductive layer 611c as a pixel electrode.

[0582] The conductive layers 611a, 611b, and 611c are each connected to the conductive layer 596 embedded in the insulating layer 594 through a conductive layer (plug) embedded in the insulating layer 599.

[0583] The light emitting element 650R includes the layer 613a, the common layer 614 over the layer 613a, and the common electrode 615 over the common layer 614. Further, the light emitting element 650G includes the layer 613b, the common layer 614 over the layer 613b, and the common electrode 615 over the common layer 614. Further, the light emitting element 650B includes the layer 613c, the common layer 614 over the layer 613c, and the common electrode 615 over the common layer 614.

[0584] As a material of a pair of electrodes (pixel electrode and common electrode) forming a light emitting element, a metal, an alloy, a conductive compound, and a mixture thereof, or the like can be appropriately used. As the material, specifically, a metal such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, and an alloy appropriately combining them can be given. Further, as the material, indium tin oxide (In-Sn oxide, also referred to as ITO), In-Si-Sn oxide (also referred to as ITSO), indium zinc oxide (In-Zn oxide), In-W-Zn oxide, and the like can be given. Further, as the material, an aluminum-containing alloy (aluminum alloy) such as an alloy of aluminum, nickel, and lanthanum (Al-Ni-La), and an alloy of silver and magnesium, and an alloy of silver, palladium, and copper (Ag-Pd-Cu, also referred to as APC), and the like can be given. Further, as the material, an element belonging to Group 1 or Group 2 in the periodic table (e.g., lithium, cesium, calcium, strontium), a rare earth metal such as europium and ytterbium, an alloy appropriately combining them, graphene, and the like can be given.

[0585] The display device 600A employs an SBS structure. The SBS structure can optimize materials and structures for each light emitting element, and thus can improve the degree of freedom in selecting materials and structures, and can easily achieve improvements in luminance and reliability.

[0586] Further, the display device 600A employs a top emission type. In the top emission type, a transistor or the like can be arranged so as to overlap with a light emitting region of a light emitting element, and thus the aperture ratio of a pixel can be further improved as compared with a bottom emission type.

[0587] The layer 613a is formed so as to cover the top surface and side surface of the conductive layer 611a. Similarly, the layer 613b is formed so as to cover the top surface and side surface of the conductive layer 611b. Further, similarly, the layer 613c is formed so as to cover the top surface and side surface of the conductive layer 611c. Thus, the entire region where the conductive layer 611a, the conductive layer 611b, and the conductive layer 611c are provided can be used as a light emitting region of the light emitting element 650R, the light emitting element 650G, and the light emitting element 650B, and thus the aperture ratio of a pixel can be improved.

[0588] In the light emitting element 650R, the layer 613a and the common layer 614 can be collectively referred to as an EL layer. Further, similarly, in the light emitting element 650G, the layer 613b and the common layer 614 can be collectively referred to as an EL layer. Further, similarly, in the light emitting element 650B, the layer 613c and the common layer 614 can be collectively referred to as an EL layer.

[0589] The EL layer includes at least a light emitting layer. The light emitting layer contains one or more light emitting substances. As the light emitting substance, a substance that emits light of blue, violet, blue-violet, green, yellow-green, yellow, orange, or red color, or the like is appropriately used. Further, as the light emitting substance, a substance that emits near-infrared light can also be used.

[0590] As the light emitting substance contained in the light emitting element, for example, a substance that emits fluorescence (fluorescent material), a substance that emits phosphorescence (phosphorescent material), a substance that exhibits thermally activated delayed fluorescence (TADF material), and an inorganic compound (quantum dot material, or the like) can be given.

[0591] The light emitting layer can contain one or more organic compounds (host material, auxiliary material, or the like) in addition to the light emitting substance (guest material). As the one or more organic compounds, one or both of a substance having high hole-transporting property (hole-transporting material) and a substance having high electron-transporting property (electron-transporting material) can be used. Further, as the one or more organic compounds, a bipolar substance (a substance having high hole-transporting property and high electron-transporting property) or a TADF material can also be used.

[0592] The EL layer can include one or more of a layer containing a substance having a high hole-injection property (hole-injection layer), a layer containing a hole-transport material (hole-transport layer), a layer containing a substance having a high electron-blocking property (electron-blocking layer), a layer containing a substance having a high electron-injection property (electron-injection layer), a layer containing an electron-transport material (electron-transport layer), and a layer containing a substance having a high hole-blocking property (hole-blocking layer), in addition to the light-emitting layer. In addition to these, the EL layer can contain one or both of a bipolar substance and a TADF material.

[0593] The light-emitting element can use a low molecular compound or a high molecular compound, and can also contain an inorganic compound. The layers constituting the light-emitting element can be formed by a method such as an evaporation method (including a vacuum evaporation method), a transfer method, a printing method, an inkjet method, a coating method, or the like.

[0594] The light-emitting element can have a single structure in which one light-emitting unit is included, or can have a tandem structure in which a plurality of light-emitting units are connected in series. The light-emitting unit includes at least a light-emitting layer. The tandem structure has a structure in which a plurality of light-emitting units are connected in series through a charge generation layer. The charge generation layer has a function of injecting electrons into one of the two light-emitting units and injecting holes into the other when a voltage is applied between a pair of electrodes. By employing the tandem structure, a light-emitting element capable of emitting light with high luminance can be obtained. Furthermore, the tandem structure can improve reliability because the current needed to obtain the same luminance can be reduced as compared to the single structure. Furthermore, the tandem structure can be referred to as a stacked structure.

[0595] Furthermore, when the light-emitting element has a microcavity structure, color purity can be further improved.

[0596] The layer 613a, the layer 613b, and the layer 613c are processed into an island shape by photolithography. Thus, the layer 613a, the layer 613b, and the layer 613c have an angle formed by the top surface and the side surface at each end portion close to 90 degrees. On the other hand, for example, an organic film formed using an FMM (Fine Metal Mask) has a tendency that the thickness is reduced as the end portion is approached, and for example, the top surface is formed in a slope shape in a range of 1 μm or more and 10 μm or less from the end portion, so that it is difficult to distinguish the top surface and the side surface.

[0597] In the layer 613a, the layer 613b, and the layer 613c, the top surface and the side surface are clearly distinguished. Thus, in the adjacent layer 613a and the layer 613b, one side surface of the layer 613a and one side surface of the layer 613b face each other. The same applies to any combination of the layer 613a, the layer 613b, and the layer 613c.

[0598] The layers 613a, 613b, and 613c each include at least a light-emitting layer. For example, a structure in which the layers 613a, 613b, and 613c each include a light-emitting layer that emits red light, a light-emitting layer that emits green light, and a light-emitting layer that emits blue light, respectively, is preferable....

Claims

1. A semiconductor device comprising: a first transistor; a first insulating layer, wherein the first transistor includes a first conductive layer, a second conductive layer, a semiconductor layer, a gate insulating layer, and a gate electrode, the first conductive layer is one of a source electrode and a drain electrode of the first transistor, the second conductive layer is the other of the source electrode and the drain electrode of the first transistor, the first conductive layer and the second conductive layer are located at different levels, the first insulating layer is provided between the first conductive layer and the second conductive layer and has a first opening reaching the first conductive layer, the second conductive layer has a second opening overlapping the first opening, the second conductive layer is provided on the first insulating layer, the semiconductor layer has a region in contact with a top surface of the first conductive layer within the first opening, a side surface of the first insulating layer within the first opening, a side surface of the second conductive layer within the second opening, and a top surface of the second conductive layer, the gate insulating layer is provided in contact with the semiconductor layer, the gate electrode is provided on the gate insulating layer in a manner having a region overlapping the semiconductor layer, the gate electrode includes a third conductive layer and a fourth conductive layer stacked on the third conductive layer, an end portion of the third conductive layer is located in a region overlapping the second conductive layer, the fourth conductive layer has a region extending outside the end portion of the third conductive layer, and the region of the fourth conductive layer extending outside the end portion of the third conductive layer has a gap between the second conductive layer.

2. The semiconductor device according to claim 1, wherein a relative dielectric constant of the gap is 0.8 or more and 1.2 or less.

3. A semiconductor device comprising: a first transistor; a first insulating layer; and a second insulating layer, wherein the first transistor includes a first conductive layer, a second conductive layer, a semiconductor layer, a gate insulating layer, and a gate electrode, the first conductive layer is one of a source electrode and a drain electrode of the first transistor, the second conductive layer is the other of the source electrode and the drain electrode of the first transistor, the first conductive layer and the second conductive layer are located at different levels, the first insulating layer is provided between the first conductive layer and the second conductive layer and has a first opening reaching the first conductive layer, the second conductive layer has a second opening overlapping the first opening, the second conductive layer is provided on the first insulating layer, the semiconductor layer has a region in contact with a top surface of the first conductive layer within the first opening, a side surface of the first insulating layer within the first opening, a side surface of the second conductive layer within the second opening, and a top surface of the second conductive layer, the gate insulating layer is provided in contact with the semiconductor layer, the gate electrode is provided on the gate insulating layer in a manner having a region overlapping the semiconductor layer, the gate electrode includes a third conductive layer and a fourth conductive layer stacked on the third conductive layer, an end portion of the third conductive layer is located in a region overlapping the second conductive layer, the fourth conductive layer has a region extending outside the end portion of the third conductive layer, and the region of the fourth conductive layer extending outside the end portion of the third conductive layer has a gap between the second conductive layer. The fourth conductive layer has a region extending outside the end portion of the third conductive layer, The second insulating layer covers a top surface and a side surface of the fourth conductive layer, and the second insulating layer has a region covering a bottom surface of the fourth conductive layer in the region of the fourth conductive layer extending outside the end portion of the third conductive layer.

4. The semiconductor device according to claim 3, wherein the region of the fourth conductive layer extending outside the end portion of the third conductive layer has the second insulating layer between the second conductive layer.

5. The semiconductor device according to any one of claims 1 to 4, wherein the third conductive layer is one selected from the group consisting of tantalum nitride, titanium nitride, ruthenium nitride, a molybdenum-containing nitride, a tungsten-, titanium-, and aluminum-containing nitride, and a tantalum- and aluminum-containing nitride.

6. The semiconductor device according to any one of claims 1 to 4, wherein the third conductive layer is one selected from the group consisting of tantalum nitride, titanium nitride, ruthenium nitride, a molybdenum-containing nitride, a tungsten-, titanium-, and aluminum-containing nitride, and a tantalum- and aluminum-containing nitride, and the fourth conductive layer is tungsten.

7. A manufacturing method of a semiconductor device, comprising the steps of: forming a first insulating layer on a first conductive layer; forming a second conductive layer on the first insulating layer; forming a first opening reaching the first conductive layer by removing a portion of the second conductive layer and a portion of the first insulating layer, so as to expose a top surface of the first conductive layer, forming a first semiconductor layer so as to contact the top surface of the first conductive layer, a side surface within the first opening of the first insulating layer, a side surface within the first opening of the second conductive layer, and a top surface of the second conductive layer; forming a second insulating layer so as to contact a top surface of the first semiconductor layer and a top surface of the first insulating layer; stacking a third conductive layer and a fourth conductive layer on the second insulating layer in this order; forming a fifth conductive layer using a first mask formed by a photolithography method, by removing a portion of the fourth conductive layer using the first mask; forming a sixth conductive layer by removing a portion of the third conductive layer using the fifth conductive layer as a mask; the removal of the portion of the third conductive layer is performed using wet etching; and the removal of the portion of the fourth conductive layer is performed using dry etching.

8. The manufacturing method of a semiconductor device according to claim 7, wherein a region extending outside an end portion of the sixth conductive layer is formed in the fifth conductive layer by removing a portion of the third conductive layer, forming a third insulating layer so as to contact a top surface of the fifth conductive layer, a side surface of the fifth conductive layer, and a top surface of the second insulating layer after forming the sixth conductive layer, and the third insulating layer is provided so as to have a region contacting a bottom surface of the fifth conductive layer in the region of the fifth conductive layer extending outside the end portion of the sixth conductive layer.

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