Code generator circuit and local replica generator circuit

Abstract

The invention provides a code generator circuit and a local replica generator circuit. The code generator circuit comprises a control circuit and a code sequence processing circuit. The control circuit is configured to update an accumulated value by accumulating an incremental value per clock cycle, and to generate a control output per clock cycle with reference to the accumulated value, where the setting of the incremental value depends on one of a Doppler shift, a block size, and a local replica output sampling rate. The code sequence processing circuit is configured to generate a code generator output according to the control output of the control circuit.

Description

Technical Field

[0001] This invention relates to the generation of local replicas, and more particularly to a code generator circuit with code Doppler compensation and a local replica generator circuit using the code generator circuit. Background Technology

[0002] Global Navigation Satellite System (GNSS) is often described as an "invisible utility" that provides two essential services—time and position—accurately, reliably, and inexpensively, making it indispensable for many aspects of the modern world. Each GNSS satellite is equipped with a high-precision atomic clock. When four or more satellites are in the line of sight, a GNSS receiver can measure the distance to each satellite by estimating the signal transmission time delay from each satellite to the receiver. These measurements allow the device with embedded GNSS to determine its position and synchronize with the precise GNSS system time.

[0003] GNSS satellite signals are modulated using pseudo-random noise (PRN) codes, which are code sequences of randomly distributed 0s and 1s. Each satellite transmits a unique PRN code, allowing a GNSS receiver to identify any satellite. The unique PRN code repeats continuously, and the GNSS receiver can use a local copy of this unique PRN code to perform correlation operations with the received satellite signal for acquisition.

[0004] The Doppler shift of satellite signals is caused by the relative motion between the GNSS receiver and the GNSS satellite. Therefore, the GNSS baseband received signal is affected by the Doppler effect (including code Doppler and carrier Doppler). As a result, the GNSS receiver needs to process the Doppler effect to improve the extraction efficiency of satellite signals. Summary of the Invention

[0005] One of the objectives of this invention is to provide a code generator circuit with code Doppler compensation and a local copy generator circuit using the code generator circuit.

[0006] In one embodiment of the present invention, a code generator circuit is disclosed. The code generator circuit includes a control circuit and a code sequence processing circuit. The control circuit is configured to update an accumulated value by accumulating an increment value each clock cycle, and to generate a control output each clock cycle with reference to the accumulated value, wherein the increment value is set based on one of a Doppler shift, a block size, and a local replica output sampling rate. The code sequence processing circuit is configured to generate a code generator output based on the control output of the control circuit.

[0007] In one embodiment of the present invention, a local copy generator circuit is disclosed. The local copy generator circuit includes a code generator circuit, a Doppler shift generator circuit, and a multiplier circuit. The code generator circuit includes a first control circuit and a code sequence processing circuit. The first control circuit is configured to update a first accumulated value by accumulating a first increment value each clock cycle, and to generate a first control output each clock cycle with reference to the first accumulated value, wherein the first increment value is set based on one of a Doppler shift, a block size, and a local copy output sampling rate. The code sequence processing circuit is configured to generate a code generator output based on the first control output of the first control circuit. The Doppler shift generator circuit includes a second control circuit and a Doppler shift processing circuit. The second control circuit updates a second accumulated value by accumulating a second increment value each clock cycle, and generates a second control output each clock cycle with reference to the second accumulated value, wherein the setting of the second increment value depends on one of the Doppler shift, the block size, and the local replica output sampling rate. The Doppler shift processing circuit generates a Doppler shift generator output based on the second control output of the second control circuit. The multiplier circuit generates a local replica output of the local replica generator circuit by performing a multiplication operation between the code generator output and the Doppler shift generator output.

[0008] This invention proposes a local copy generator design that can simultaneously perform code Doppler compensation (whose compensation accuracy is not limited by the scale of the fast Fourier transform) and carrier Doppler compensation, upsample the local copy to an arbitrary sampling rate, and / or output all samples of a block in each clock cycle for subsequent block-related processing. Attached Figure Description

[0009] Figure 1 This is a block diagram of a local copy generator circuit according to an embodiment of the present invention.

[0010] Figure 2 This is an embodiment of the present invention. Figure 1 The block diagram of the code generator circuit is shown.

[0011] Figure 3 This is an embodiment of the present invention. Figure 1 The block diagram of the actual implementation of the code generator circuit is shown.

[0012] Figure 4 This is a schematic diagram of the implementation of the numerically controlled oscillator circuit and index generator used in a code generator circuit according to an embodiment of the present invention.

[0013] Figure 5 This is an embodiment of the present invention. Figure 1 The block diagram shows another implementation of the code generator circuit.

[0014] Figure 6 This is an embodiment of the present invention. Figure 1 The block diagram shown is of the Doppler frequency shift generator circuit.

[0015] Figure 7 This is a schematic diagram of the implementation of the numerically controlled oscillator circuit and index generator used in the Doppler frequency shift generator circuit of an embodiment of the present invention.

[0016] Figure 8 This is an embodiment of the present invention. Figure 1 Another implementation block diagram of the Doppler frequency shift generator circuit is shown.

[0017] Figure 9 This is an embodiment of the present invention. Figure 1 The diagram shows a multiplier circuit.

[0018] [Symbol Explanation]

[0019] 100: Local copy generator circuit

[0020] 102: Code Generator Circuit

[0021] 104: Doppler frequency shift generator circuit

[0022] 106: Multiplier Circuit

[0023] 112, 122: Control circuit

[0024] 114: Code sequence processing circuit

[0025] 124: Doppler frequency shift processing circuit

[0026] 202, 504: Code Index Difference Generator Circuit

[0027] 204, 502, 601, 601': NCO-based index generator circuits

[0028] 206, 506: Adaptive code table generator circuit

[0029] 208: Mapping Circuit

[0030] 302, 508, 602, 602': NCO

[0031] '304, 510, 604, 604': Index generator

[0032] 306, 516: PRN code generator

[0033] '308, 606, 606': Lookup table

[0034] 312, 410, 512: Subtractors

[0035] 314, 404, 514, 704: Buffers

[0036] 402, 406, 702, 706: Adders

[0037] 408, 708: Floor function operators

[0038] 412, 608, 608', 802: Multiplexers

[0039] 607, 607': Post-processing circuit

[0040] 610, 610': Conjugate operators

[0041] 804: Negative Operator

[0042] CTRL_1, CTRL_2: Control output

[0043] C_OUT: Code generator output

[0044] DS_OUT: Output of the Doppler frequency shift generator

[0045] Doppler_shift: Doppler frequency shift

[0046] Local_replica_out: Local replica output

[0047] LUT: Lookup Table

[0048] BS: Block Size

[0049] Local copy output sampling rate

[0050] c7, c6, c1, c0: Code index

[0051] out7, out6, out1, out0: Code bits

[0052] nco_acc, phase_acc: Accumulated value

[0053] , , , Increasing value

[0054] Offset0, Offset1, Offset6, Offset7: Offset values

[0055] Index_diff: Code index difference

[0056] p7, p6, p1, p0: Phase index

[0057] out7, out6, out1, out0: Complex number output

[0058] CV7, CV6, CV1, CV0: Complex values

[0059] Polarity of Doppler frequency shift Detailed Implementation

[0060] Certain terms are used in the specification and claims to refer to specific elements. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same element. This specification and claims do not distinguish elements based on differences in name, but rather on differences in function. The terms "comprising" and "including" used throughout the specification and claims are open-ended and should be interpreted as "comprising but not limited to." Furthermore, the terms "coupled" or "coupled" herein include any direct and indirect electrical connection means. Therefore, if a first device is described as coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices and connection means.

[0061] Figure 1This is a block diagram of a local replica generator circuit according to an embodiment of the present invention. For example (but the invention is not limited thereto), the local replica generator circuit 100 may be a GNSS local replica generator, used to generate a local replica (Local_replica_out, e.g., a PRN code sequence) and output it to a GNSS correlator, wherein the GNSS correlator also receives a GNSS baseband received signal and performs correlation operations based on the local replica (Local_replica_out) and the GNSS baseband received signal. However, this is only an illustrative example and is not intended to limit the invention. In fact, any application using the local replica generator design and / or the code generator design proposed in this invention falls within the scope of this invention.

[0062] In some embodiments of the present invention, the GNSS correlator can perform correlation operations in the frequency domain; therefore, the sampling rate of the local replica_replica_out needs to be the same as the up-sampling rate of the GNSS baseband received signal. For example, the PRN code used by Galileo E5 has 10230 code bits per millisecond (ms) (also referred to as a chip, mainly because it does not carry any useful data information). If a 32768-point Fast Fourier Transform (FFT) is used for correlation operations in the frequency domain, the GNSS baseband received signal should be upsampled to 32768 samples / millisecond, and the sampling rate of the local replica (Local_replica_out) should also be 32768 samples / millisecond, which is higher than the chip rate of 10230 chips / millisecond for the PRN code specified by Galileo E5. However, applying traditional upsampling methods (e.g., zero-padding or interpolation) to the local replica may require additional hardware or more complex calculations.

[0063] In some embodiments of the present invention, the GNSS correlator can perform correlation operations in the frequency domain using block-wide processing. For example, a 32768-point FFT can be decomposed into eight 4096-point FFTs, and the GNSS correlator can be equipped with eight FFT engines for block-wide processing. The local replica (Local_replica_out) needs to provide a block containing eight samples per clock cycle (i.e., block size = 8 samples / block), where these eight samples are provided to eight FFT engines respectively. However, using conventional methods to temporarily store the local replica and rearrange the stored local replica to provide the blocks of samples required for block-wide processing may require additional hardware and more control.

[0064] As mentioned above, GNSS baseband received signals are affected by the Doppler effect (including code Doppler and carrier Doppler). To improve extraction performance, GNSS receivers need to handle the Doppler effect. If the GNSS receiver handles code Doppler and carrier Doppler separately, a complex circuit structure is required. If code Doppler compensation is performed in the time domain, more software control is needed. If code Doppler compensation is performed in the frequency domain, the compensation accuracy is limited by the FFT size.

[0065] To address the aforementioned problems, this invention proposes a local replica generator design capable of simultaneously performing code Doppler compensation (with compensation accuracy not limited by the FFT size) and carrier Doppler compensation, upsampling the local replica to an arbitrary sampling rate, and / or outputting all samples of a block per clock cycle for subsequent block-wise correlation processing. More specifically, the proposed local replica generator design employs a code generator design capable of performing code Doppler compensation (with compensation accuracy not limited by the FFT size), upsampling the local replica to an arbitrary sampling rate, and / or outputting all samples of a block per clock cycle. Further details of the proposed local replica generator design and code generator design will be described below with reference to the accompanying drawings.

[0066] like Figure 1As shown, the local copy generator circuit 100 includes a code generator circuit 102, a Doppler-shift generator circuit 104, and a multiplier circuit 106. The code generator circuit 102 includes a control circuit 112 and a code sequence processing circuit 114. The control circuit 112 generates a control output CTRL_1, which contains control information used by the code sequence processing circuit 114. The code sequence processing circuit 114 generates a code generator output C_OUT based on the control output CTRL_1 of the control circuit 112. The Doppler shift (Hz) is provided to the code generator circuit 102, and the code generator output C_OUT provided to the multiplier circuit 106 is itself code Doppler-compensated, provided that the control output CTRL_1 is appropriately set according to the Doppler shift.

[0067] The Doppler frequency shift generator circuit 104 includes a control circuit 122 and a Doppler frequency shift processing circuit 124. The control circuit 122 generates a control output CTRL_2, which contains control information used by the Doppler frequency shift processing circuit 124. The Doppler frequency shift processing circuit 124 generates a Doppler frequency shift generator output DS_OUT based on the control output CTRL_2 of the control circuit 122. The Doppler frequency shift (Hz) is also provided to the Doppler frequency shift generator circuit 104. With the control output CTRL_2 appropriately set according to the Doppler frequency shift (Hz), the Doppler frequency shift generator output DS_OUT provided to the multiplier circuit 106 is used for carrier Doppler compensation.

[0068] Multiplier circuit 106 generates a local replica output, Local_replica_out, by performing a multiplication operation on the code generator output C_OUT and the Doppler shift generator output DS_OUT. As described above, the code generator output C_OUT generated in response to the Doppler shift (Hz) is already code Doppler compensated, while the Doppler shift generator output DS_OUT generated in response to the same Doppler shift (Hz) is used for carrier Doppler compensation. Therefore, code Doppler compensation and carrier Doppler compensation can be jointly implemented through the local replica output, Local_replica_out. Compared to conventional GNSS receiver designs that require complex circuit structures to process code Doppler and carrier Doppler separately, the GNSS receiver using the local replica generator circuit 100 proposed in this invention to jointly process code Doppler and carrier Doppler will have lower hardware complexity.

[0069] In addition to code Doppler compensation, the code generator circuit 102 is also capable of upsampling the local copy to any sampling rate and / or outputting all samples of a block in each clock cycle for block correlation processing in the frequency domain. Figure 2 This is an embodiment of the present invention. Figure 1 The block diagram of code generator circuit 102 is shown. The control circuit 112 of code generator circuit 102 may include a code index difference generator circuit (labeled "code index difference generator") 202 and an index generator circuit based on a numerically controlled oscillator (hereinafter referred to as "NCO") (labeled "NCO-based index generator") 204. Code sequence processing circuit 114 may include an adaptive code table generator circuit (labeled "adaptive code table generator") 206 and a mapping circuit (labeled "mapping") 208. When the correlation operation performed by the GNSS correlator in the frequency domain is block-based, the code generator output C_OUT of code generator circuit 102 contains multiple code bits (multiple samples) of a block output per clock cycle. Figure 1The control output CTRL_1 shown can contain multiple code indices and a control signal, which is provided to the adaptive code table generator circuit 206, and the multiple code indices are provided to the mapping circuit 208. The NCO-based index generator circuit 204 generates the multiple code indices, and the mapping circuit 208 outputs multiple code bits (multiple samples) of a block based on a look-up table (LUT) and the multiple code indices. The code index difference generator circuit 202 generates a code index difference as a control signal for the adaptive code table generator circuit 206. The code index difference generated in each clock cycle is used to instruct the adaptive code table generator circuit 206 to adaptively update the look-up table used by the mapping circuit 208.

[0070] Regarding the generation of code indices (especially "code Doppler compensated" code indices), the NCO-based index generator circuit 204 may consider some or all of several factors, including Doppler shift (Hz), block size (BS) (samples / block), and local copy output sampling rate. (samples / second), where the local copy output sampling rate (Samples per second) can differ from (for example, be higher than) the local copy chip rate. (chips per second), such as the 10.23M chips per second (i.e., 10230 chips per millisecond) specified by Galileo E5 / BeiDou B2 / Global Positioning System (GPS) L5. Figure 3 This is an embodiment of the present invention. Figure 1 The block diagram shows an implementation of the code generator circuit 102. The NCO-based index generator circuit (labeled "NCO-based index generator") 204 may include an NCO circuit (labeled "NCO") 302 and multiple index generators (labeled "index generator 7", "index generator 6", ..., "index generator 1", "index generator 0") 304. The code index difference generator 202 may include a subtractor 312 and a buffer (labeled "D") 314, for example, the buffer 314 may be implemented using a D-type flip-flop or other storage element. The adaptive code table generator circuit (labeled "adaptive code table generator") 206 may include a PRN code generator circuit (labeled "PRN code generator") 306 and a lookup table 308. The mapping circuit (labeled "mapping") 208 may include multiple subtractors 312 and multiple multiplexers 310.

[0071] To better understand the technical features of this invention, it is assumed below that the block size is 8 (i.e., BS=8). Figure 3 The NCO-based index generator circuit 204 shown has eight index generators 304 to output eight code indices c7, c6, ..., c1, c0 respectively; and the mapping circuit 208 has eight multiplexers 310 to output eight code bits out7, out6, ..., out1, out0 respectively. However, this is only an example and is not intended to limit the invention. In fact, the code generator design proposed in this invention can support any block size and / or generate any number of samples in each clock cycle to meet the requirements of block correlation processing performed in the frequency domain.

[0072] The NCO circuit 302 in the NCO-based index generator circuit 204 is used to accumulate an increment value once per clock cycle. (For example, in this embodiment, BS=8) to update the accumulated value nco_acc, which can be calculated using the following formula.

[0073] (1)

[0074] For example, NCO circuit 302 may include adder 402 and buffer (labeled "D") 404, such as Figure 4 As shown, for example, buffer 404 can be implemented using a D-type flip-flop or other storage elements. According to the code generator design proposed in this invention, an incrementing value is accumulated once per clock cycle. (For example, in this embodiment, BS=8) is set depending on the Doppler frequency shift. (Hz), Block size BS (samples / block), Local copy output sampling rate (samples / second) or any combination thereof. The value can be calculated using the following formula.

[0075] (2)

[0076] (3)

[0077] In the above formulas (2) and (3), The local copy chip rate (chips per second) For local copy chip rate The code length per millisecond below, Output sampling rate for local copy Code length per millisecond below (samples / second). For code-Doppler compensation, For Doppler frequency shift (Hz), and This refers to the carrier frequency. For example, for frequency domain correlation operations using a 32768-point FFT, Regarding Galileo E5, ; and for Galileo E5, the frequency ratio / .

[0078] Since the block size BS in this embodiment is 8, the NCO circuit 302 must accumulate once in each clock cycle. For example, when the Doppler frequency shift (Hz) is zero, in , and / In the case of increasing value It will equal 2.49755859375. There are a total of 8 values ​​less than the increment value. And the uniformly distributed offset values ​​Offset0=0, Offset1= Offset6 = ... Offset7= These are used by index generator circuits (labeled "index generator 0", "index generator 1", ..., "index generator 6", "index generator 7") 302 to generate eight indices c0, c1, ..., c6, c7 respectively. Each index generator circuit 304 receives the same accumulated value nco_acc and generates a code index by performing an arithmetic operation on the sum of an offset value and the accumulated value nco_acc. For example, each index generator circuit 304 can be... Figure 4 The adder 406, floor function operator 408, subtractor 410, and multiplexer 412 shown are used to implement this. (Code index) The calculation can be expressed by the following formula.

[0079] (4)

[0080] In the above formula (4), This is the cumulative value. This is the offset value. For local copy chip rate Code length per millisecond (chips / second), This is the floor function. This is the modulo operation. For example, for Galileo E5, =10230.

[0081] like Figure 3 As shown, the code index difference generator 202 includes a subtractor 312 and a buffer (labeled "D") 314. For example, the buffer 314 can be implemented using a D-type flip-flop or other storage element. Therefore, the code index difference generator 202 temporarily stores a specific code index (e.g., c7) generated in the previous clock cycle and subtracts the specific code index (e.g., c7) generated in the current clock cycle from the specific code index (e.g., c7) generated in the previous clock cycle to generate the code index difference Index_diff. The code index difference Index_diff serves as a control signal for the adaptive code table generator circuit 206 (especially the PRN code generator circuit 306 within the adaptive code table generator circuit 206). Specifically, the PRN code generator circuit 306 adaptively updates the lookup table 308 based on the code index difference Index_diff generated in each clock cycle. For example, the PRN code generator circuit 306 can be implemented using a linear-feedback shift register (LFSR). Under the control of the code index difference Index_diff, the PRN code generator circuit 306 generates and outputs k code chips (code bits) {a0, …, a k},in For the lookup table size (LUT size), and and It depends on the GNSS system specifications. Regarding... Figure 3 The embodiment shown, and Due to the increasing value The value is 2.49755859375, which means that the PRN code generator circuit 306 expects to generate and output 2.49755859375 chips in each clock cycle. Since 2.49755859375 is not an integer, the code index difference Index_diff will be selected from {2, 3} in different clock cycles so that the PRN code generator circuit 306 generates 2 (k=2) chips and 3 (k=3) chips in an interleaving manner. In this way, the average number of chips generated by the PRN code generator circuit 306 in each clock cycle can be equal to 2.49755859375. When Index_diff = 2, the PRN code generator circuit 306 generates two more chips (bits) to update the lookup table 308. The current lookup table entries a0 and a1 are updated by the two most recently generated chips (bits) from the PRN code generator circuit 306, and a2 is set by a0 from the previous lookup table. When Index_diff = 3, the PRN code generator circuit 306 generates three more chips (bits) to update the lookup table 308. The current lookup table entries a0, a1, and a2 are set by the three most recently generated chips (bits) from the PRN code generator circuit 306.

[0082] Figure 3 The mapping circuit 208 shown is used to output the code bits out0, out1, ..., out6, out7 of a block in each clock cycle according to the lookup table 308 and code indices c0, c1, ..., c6, c7. In this embodiment, the mapping circuit 208 will output the code bits out0, out1, ..., out6, out7 of a block according to a corresponding code index ci and a specific code index c7 (which is the maximum offset value received). The difference (c7-ci) between the outputs of the index generator circuit and the lookup table 308 (which contains 3 code bits {a0, a1, a2}) is used to search for code bit outi, such as Figure 3 As shown, one of the multiplexers 310 will output a0 as code bit out7 in response to 0 (i.e., c7-c7=0), one of the multiplexers 310 will output one of {a0, a1, a2} as code bit out6 in response to (c7-c6), one of the multiplexers 310 will output one of {a0, a1, a2} as code bit out1 in response to (c7-c1), and one of the multiplexers 310 will output one of {a0, a1, a2} as code bit out0 in response to (c7-c0).

[0083] Figure 3The code generator design proposed in this invention is used to generate multiple samples of a block in each clock cycle to meet the requirements of subsequent frequency domain block correlation processing. However, this is only an example and is not intended to limit the invention. The same design concept is also applicable to situations where frequency domain correlation operations do not use block processing (i.e., the block size is equal to 1).

[0084] Figure 5 This is an embodiment of the present invention. Figure 1 A block diagram of another implementation of the code generator circuit 102 shown. In this embodiment, the control circuit 112 includes an NCO-based index generator circuit (labeled "NCO-based index generator") 502 and a code index difference generator circuit 504, while the code sequence processing circuit 114 includes an adaptive code table generator circuit (labeled "adaptive code table generator") 506. Figure 5 The circuit design of the code generator circuit 102 shown is as follows: Figure 3 The circuit design shown is a simplified version of the code generator circuit 102. Since the block size is equal to 1 (i.e., BS=1), the code generator output C_OUT outputs only a single code bit out per clock cycle. The NCO-based index generator 502 requires only one index generator circuit (labeled "Index Generator 0") 510. Since the block size is equal to 1 (i.e., BS=1), the increment to be accumulated by the NCO circuit 508 is set to... The operation of the index generator circuit 510 and Figure 3 The operation of the index generator circuit shown (labeled "index generator 0") 304 is the same; for example, index generator circuit 510 can be generated by... Figure 4 The adder 406, the floor function operator 408, the subtractor 410, and the multiplexer 412 shown are used to implement this.

[0085] The code index difference generator circuit 504 includes a subtractor 512 and a buffer (labeled "D") 514. For example, the buffer 514 can be implemented using a D-type flip-flop or other storage element. Therefore, the code index difference generator 502 is used to temporarily store the single code index c0 generated in the previous clock cycle and subtract the single code index c0 generated in the previous clock cycle from the single code index c0 generated in the current clock cycle to generate the code index difference value Index_diff. As... Figure 3The code index difference generator circuit 202 and code index difference generator circuit 504 shown also output the code index difference Index_diff as a control signal for the adaptive code table generator circuit 506 (especially the PRN code generator circuit 516 of the adaptive code table generator circuit 506). Since the output of the PRN code generator circuit 516 is directly used as the output of the code generator circuit 102, the adaptive code table generator circuit 506 can be omitted. Figure 3 The mapping circuit 208 is shown. In this embodiment, the code index difference Index_diff in different clock cycles is selected from {0, 1}. When Index_diff=1, the PRN code generator circuit 516 generates the next chip (code bit) as the code bit output of the code generator circuit 102, while when Index_diff=0, the PRN code generator circuit 516 repeats the generation of the current chip (code bit) as the code bit output of the code generator circuit 102. Consider... In this case, the output of index generator circuit 510 is: co=0, 0, 1, 1, 2, 2, 3, 3, …, the output of code index difference generator circuit 504 is: Index_diff=1, 0, 1, 0, 1, 0, 1, 0, …, and the output of PRN code generator circuit 516 is: out=chip0, chip0, chip1, chip1, chip2, chip2, ….

[0086] Figure 6 This is an embodiment of the present invention. Figure 1 The block diagram shown is of the Doppler frequency shift generator circuit 104. The control circuit 122 of the Doppler frequency shift generator circuit 104 may include an NCO-based index generator circuit (labeled "NCO-based index generator") 601. The Doppler frequency shift processing circuit 124 may include a lookup table (labeled "SIN & COS LUT") 606 and post-processing circuitry 607. When the correlation operation performed by the GNSS correlator in the frequency domain is performed in a block manner, the Doppler frequency shift generator output DS_OUT of the Doppler frequency shift generator circuit 104 contains multiple complex outputs for each clock cycle. Figure 1 The control output CTRL_2 shown can contain multiple phase indices provided to lookup table 606. An NCO-based index generator circuit 601 generates these multiple phase indices. Lookup table 606 outputs multiple complex values ​​based on these phase indices. Post-processing circuit 607 generates these multiple complex outputs based on the multiple complex values ​​and the polarity of the Doppler shift. A complex output generated by Doppler shift generator circuit 104 can be used... To indicate, among which It is the Doppler frequency shift (Hz).

[0087] Regarding the generation of the phase index, the NCO-based index generator circuit 601 can consider some or all of a number of factors, including Doppler frequency shift. (Hz), block size BS (samples / block), and local copy output sampling rate (samples / second), where the local copy output sampling rate (samples / second) may differ from (e.g., higher than) the local copy chip rate. (chips per second), such as the 10.23M chips per second (i.e., 10230 chips per millisecond) specified by Galileo E5 / BeiDou B2 / Global Positioning System L5. Figure 6 As shown, the NCO-based index generator circuit 601 includes an NCO circuit (labeled "NCO") 602 and multiple index generators (labeled "index generator 7", "index generator 6", ..., "index generator 1", "index generator 0") 604. For better understanding of the technical features of this invention, it is assumed below that the block size is 8 (i.e., BS = 8 samples / block). Therefore, the NCO-based index generator circuit 601 has eight index generators 604 for outputting eight phase indices p7, p6, ..., p1, p0 respectively; and a post-processing circuit 607 outputting eight complex outputs out7, out6, ..., out1, out0 in each clock cycle. However, this is merely illustrative and not intended to limit the invention.

[0088] The NCO circuit 602, based on the NCO-based index generator circuit 601, is used to accumulate an increment value once per clock cycle. (For example, in this embodiment, BS=8) to update the accumulated value phase_acc. The calculation of the accumulated value phase_acc can be expressed by the following formula.

[0089] (5)

[0090] For example, NCO circuit 602 may include adder 702 and D-type flip-flop (labeled "D") 704, such as Figure 7 As shown. According to the Doppler frequency shift generator design proposed in this invention, an incremental value is accumulated in each clock cycle. (For example, in this embodiment, BS=8) is set depending on the Doppler frequency shift. (Hz), Block size BS (samples / block), Local copy output sampling rate (samples / second) or any combination thereof. The value can be calculated using the following formula.

[0091] (6)

[0092] In the above formula (6), It is an absolute value function. For Doppler frequency shift, and Output sampling rate for the local copy.

[0093] Since the block size BS in this embodiment is 8, the NCO circuit 602 must accumulate once in each clock cycle. There are a total of 8 values ​​smaller than the increment value. And the uniformly distributed offset values ​​dophase_offset=0, dophase_offset= ..., dophase_offset= dophase_offset= Each of these is used by index generator circuits (labeled "Index Generator 0", "Index Generator 1", ..., "Index Generator 6", "Index Generator 7") 604 to generate eight phase values ​​p0, p1, ..., p6, p7 respectively. Each index generator circuit 604 receives the same accumulated value phase_acc and generates a phase index by performing an arithmetic operation on the sum of the offset value dophase_offset and the accumulated value phase_acc. For example, each index generator circuit 604 can be... Figure 7 The adder 706 and the floor function operator 708 shown are used to implement this. The phase index phase_Index can be calculated using the following formula.

[0094] (7)

[0095] In the above formula (7), This is the floor function.

[0096] Lookup table 606 records multiple pre-calculated sine and cosine values ​​indexed by different phase indices, and outputs complex values ​​CV7, CV6, ..., CV1, CV0 respectively based on phase indices p7, p6, ..., p1, p0. Post-processing circuit 607 contains multiple conjugate operators (labeled as "..."). ” 610 and a multiplexer 608, wherein the multiplexer 608 is determined by the polarity of the Doppler frequency shift (i.e., ,in It is controlled by the sign function. When the multiplexer 608 selects complex values ​​CV7, CV6, ..., CV1, CV0 as complex outputs out7, out6, ..., out1, out0 respectively. At that time, the multiplexer 608 selects the conjugates of the complex values ​​CV7, CV6, ..., CV1, CV0 as the complex outputs out7, out6, ..., out1, out0 respectively.

[0097] Figure 6 The Doppler frequency shift generator design proposed in this invention is used to generate multiple samples in each clock cycle to meet the requirements of subsequent frequency domain block correlation processing. However, this is only an example and is not intended to limit the invention. The same design concept is also applicable to situations where frequency domain correlation operations do not use block processing (i.e., the block size is equal to 1).

[0098] Figure 8 This is an embodiment of the present invention. Figure 1 A block diagram of another implementation of the Doppler frequency shift generator circuit 104 is shown. In this embodiment, the control circuit 122 includes an NCO-based index generator circuit (labeled "NCO-based index generator") 601', and the Doppler frequency shift processing circuit 124 includes a lookup table (labeled "SIN & COS LUT") 606' and a post-processing circuit 607'. Figure 8 The circuit design of the Doppler frequency shift generator circuit 104 shown is Figure 7 The circuit design shown is a simplified version of the Doppler frequency shift generator circuit 104. Since the block size is equal to 1 (i.e., BS = 1), therefore... Figure 8 The Doppler frequency shift generator design shown uses an increment value set as... Each clock cycle generates only one phase index p0, only one complex value CV0, and only one complex output out0. For example, the NCO circuit 602' accumulates an increment value once per clock cycle. The index generator (labeled "index generator 0") 604' generates a phase index p0 based on the accumulated value phase_acc. The lookup table 606' receives only a single phase index p0 in each clock cycle, and the post-processing circuit 607 (containing a conjugate operator 610' and a multiplier 608') outputs only a single complex output out0 in each clock cycle, referencing the complex value CV0 and the polarity of the Doppler shift.

[0099] Figure 1The multiplier circuit 106 shown is used to generate a local replica output, Local_replica_out, by multiplying the code generator output C_OUT and the Doppler shift generator output DS_OUT. In some embodiments of the invention, the multiplication operation can be simply implemented using a multiplexer. Figure 9 This is an embodiment of the present invention. Figure 1 The diagram shows a schematic of the multiplier circuit 106. Satellite data is transmitted using a binary phase shift keying (BPSK) modulation scheme. Therefore, for BPSK modulation, the logic value 0 of the PRN code sequence is transformed to +1, and the logic value 1 of the PRN code sequence is transformed to -1. For a GNSS receiver using the local copy generator circuit 100, the logic value "0" of the code generator output C_OUT is transformed to "+1" for correlation operations, and the logic value "1" of the code generator output C_OUT is transformed to "-1" for correlation operations. The complex output generated by the Doppler frequency shift generator circuit 104 is... The logic values ​​{0, 1} of the code generator output C_OUT are transformed into {+1, -1} for correlation operations. Therefore, a multiplexer can be used to implement the multiplication operation between the code generator output C_OUT and the Doppler shift generator output DS_OUT. For example... Figure 9 As shown, the multiplier circuit 106 includes a negative operator (labeled "-z") 804 and a multiplexer (labeled "MUX") 802. The negative operator 804 is used to generate a complex output of the Doppler frequency shift generator output DS_OUT. negative version When a bit of the code generator output C_OUT has a logic value of "0", the multiplexer 820 selects the complex output. This is used as a sample of the local replica_replica_out used in subsequent frequency domain correlation operations (which is a complex value). When a bit of the code generator output C_OUT has a logic value of "1", the multiplexer 820 selects the negative version. The sample (which is a complex value) is used as the local replica_replica_out for subsequent frequency domain correlation operations.

[0100] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be within the scope of the present invention.

Claims

1. A code generator circuit, comprising: A control circuit is configured to update an accumulated value by adding an increment value each clock cycle, and to generate a control output each clock cycle with reference to the accumulated value, wherein the increment value is set based on one of Doppler shift, block size, and local copy output sampling rate; and A code sequence processing circuit is used to generate a code generator output based on the control output of the control circuit.

2. The code generator circuit as claimed in claim 1, wherein the increment value is set to... It is the size of the block, and The calculation is as follows: as well as , Where f c It is the local copy chip rate. It is the code length per millisecond at this local replica chip rate. It is the code length per millisecond at the local copy output sampling rate. It is code-Doppler compensation. It is the Doppler frequency shift, and It is the carrier frequency.

3. The code generator circuit as claimed in claim 1, wherein the code generator output includes a plurality of code bits output in each clock cycle.

4. The code generator circuit as claimed in claim 3, wherein the control output includes a plurality of code indices; the control circuit includes: An index generator circuit based on a numerically controlled oscillator is used to generate the multiple code indices; and The code sequence processing circuit includes: A mapping circuit is used to output the multiple code bits based on a lookup table and the multiple code indices.

5. The code generator circuit of claim 4, wherein the index generator circuit based on the numerically controlled oscillator comprises: A numerically controlled oscillator circuit is used to generate the accumulated value based on the increment value; and Multiple index generator circuits, each receiving the accumulated value and generating a code index by performing an arithmetic operation on the sum of the offset value and the accumulated value, wherein multiple different offset values ​​used by the multiple index generator circuits are all less than the increment value.

6. The code generator circuit as described in claim 5, wherein the code index is calculated as follows: ,in This is the index of the code. This is the accumulated value. It is this offset value. It is the code length per millisecond at the local replica chip rate. It is the floor function, and It is a modulo operation.

7. The code generator circuit of claim 4, wherein the mapping circuit is used to search for code bits from the plurality of code bits in the lookup table based on the difference between a specific code index in the plurality of code indices and a code index in the plurality of code indices.

8. The code generator circuit as claimed in claim 4, wherein the control output further includes a code index difference; the control circuit further includes: A code index difference generator circuit is used to temporarily store a specific code index generated in the previous clock cycle, and to generate the code index difference by subtracting the specific code index generated in the previous clock cycle from the specific code index generated in the current clock cycle; and The code sequence processing circuit also includes: A pseudo-random noise code generator circuit is used to adaptively update the lookup table in response to the code index difference.

9. The code generator circuit of claim 1, wherein the code generator outputs only a single code bit in each clock cycle.

10. The code generator circuit of claim 9, wherein the control output includes a code index difference and a single code index; the control circuit comprises: An index generator circuit based on a numerically controlled oscillator is used to generate this single-code index; and A code index difference generator circuit is used to temporarily store the single code index generated in the previous clock cycle, and subtract the single code index generated in the previous clock cycle from the single code index generated in the current clock cycle to generate the code index difference; and The code sequence processing circuit includes: A pseudo-random noise code generator circuit is used to output the single code bit in response to the code index difference.

11. The code generator circuit of claim 10, wherein the index generator circuit based on a numerically controlled oscillator comprises: A numerically controlled oscillator circuit is used to generate the accumulated value based on the increment value; and An index generator circuit is used to receive the accumulated value and generate the single-code index by performing arithmetic operations on the accumulated value.

12. The code generator circuit of claim 11, wherein the single code index is calculated as follows: ,in It is the single-code index. This is the accumulated value. It is a single offset value. It is the code length per millisecond at the local replica chip rate. It is the floor function, and It is a modulo operation.

13. A local copy generator circuit, comprising: Code generator circuit, including: A first control circuit is configured to update a first accumulated value by accumulating a first increment value in each clock cycle, and to generate a first control output in each clock cycle with reference to the first accumulated value, wherein the setting of the first increment value depends on one of Doppler frequency shift, block size, and local copy output sampling rate; as well as A code sequence processing circuit is used to generate a code generator output based on the first control output of the first control circuit. Doppler frequency shift generator circuit, including: The second control circuit is configured to update the second accumulated value by accumulating a second increment value in each clock cycle, and to generate a second control output in each clock cycle with reference to the second accumulated value, wherein the setting of the second increment value depends on one of the Doppler frequency shift, the block size, and the local copy output sampling rate; as well as The Doppler frequency shift processing circuit is used to generate the Doppler frequency shift generator output based on the second control output of the second control circuit; as well as A multiplier circuit is used to generate a local copy output of the local copy generator circuit by performing a multiplication operation between the code generator output and the Doppler frequency shift generator output.

14. The local copy generator circuit of claim 13, wherein the second increment value is set to It is the size of the block, and The calculation is as follows: ,in It is an absolute value function. It is the Doppler frequency shift, and This is the local copy's output sampling rate.

15. The local copy generator circuit of claim 13, wherein the Doppler shift generator output comprises a plurality of complex outputs in each clock cycle.

16. The local copy generator circuit of claim 15, wherein the second control output includes a plurality of phase indices; the second control circuit includes: An index generator circuit based on a numerically controlled oscillator is used to generate the multiple phase indices; and The Doppler frequency shift processing circuit includes: A lookup table is used to output multiple complex values ​​based on these multiple phase indices; and The post-processing circuit is used to generate the multiple complex outputs based on the polarity of the Doppler frequency shift and the multiple complex values.

17. The local copy generator circuit of claim 16, wherein the index generator circuit based on a numerically controlled oscillator comprises: A numerically controlled oscillator circuit is used to generate the second accumulated value based on the second increment value; and Multiple index generator circuits, each index generator circuit receiving the second accumulated value and generating a phase index by performing an arithmetic operation on the sum of the offset value and the second accumulated value, wherein multiple different offset values ​​used by the multiple index generator circuits are all less than the second increment value.

18. The local copy generator circuit of claim 17, wherein the phase index is calculated as follows: ， in It is the phase index. This is the second accumulated value. It is the offset value, and It is a floor function.

19. The local copy generator circuit of claim 13, wherein the Doppler shift generator output outputs only a single complex output in each clock cycle.

20. The local copy generator circuit of claim 19, wherein the second control output has only a single phase index; the second control circuit comprises: An index generator circuit based on a numerically controlled oscillator is used to generate this single-phase index; and The Doppler frequency shift processing circuit includes: A lookup table is used to output a single complex value based on this single phase index; and The post-processing circuitry is used to generate the single complex output based on the polarity of the Doppler frequency shift and the single complex value.

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