Multi-stage output low voltage suppression LDO power supply circuit

Abstract

A multi-stage output low voltage restraint LDO (low dropout regulator) power circuit relates to the technical field of integrated circuits and comprises a standard reference voltage, an error amplifier, a voltage division sampling circuit and an adjusting transistor, the voltage division sampling circuit is a multi-stage voltage division sampling circuit, and the specific structure of the multi-stage voltage division sampling circuit is as follows: a plurality of voltage division sampling resistors are connected in series; voltage sampling points are arranged between the adjacent voltage division sampling resistors, each voltage sampling point is connected to a sampling voltage output end through a respective sampling point switch, and under the control of an external logic signal, the divided voltage of one voltage sampling point is selected to serve as sampling voltage to be input to one input end of the error amplifier; the output voltage of the error amplifier serves as the grid voltage of the adjusting transistor, and the on-off of the source and drain of the adjusting transistor is controlled through the grid voltage. The problem that LDO output voltage parameters are single is solved, and the problem of thermal power loss caused by too large range of feedback input voltage and reference voltage due to too low output voltage is solved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a multi-stage output low-voltage suppression LDO power supply circuit. Background Technology

[0002] LDO (Low Dropout Regulator) is a type of voltage source widely used in various analog circuit modules. It has advantages such as simple structure, few external components required, and low cost. However, its initial structure also has disadvantages such as a single output voltage parameter, a narrow adjustable voltage range, high overall heat loss and power consumption, and applicability only to buck circuits.

[0003] LDOs, as linear power supplies, are generally used in step-down output circuits, meaning the output voltage must be lower than the input voltage. The core component controlling the output voltage is the regulating transistor (typically a bipolar junction transistor / MOSFET) operating in its linear range. Low dropout voltage refers to a low input-output voltage difference; for example, an input of 3.3V can result in an output of 3.2V. Linearity refers to the linear operating range of the MOSFET inside the LDO, which can be equivalently considered as a variable resistor controlled by its gate voltage. This section explains the purpose of LDOs for power supply voltage regulation.

[0004] like Figure 1 As shown, a traditional LDO basically consists of four main parts: a reference voltage (VREF), an error amplifier circuit (operational amplifier), a voltage divider sampling circuit (sampling resistors), and a transistor adjustment circuit. The reference voltage is typically an externally supplied bandgap reference voltage, a stable power supply voltage unaffected by ambient temperature, providing the reference voltage source for the entire LDO structure. The voltage divider sampling circuit samples the output voltage using a proportional combination of voltage divider resistors and feeds the sampled voltage back to the error amplifier circuit. The error amplifier circuit compares the reference voltage with the sampled voltage fed back from the voltage divider sampling circuit and then amplifies the comparison result. The transistor adjustment circuit uses the output voltage of the error amplifier circuit (i.e., the op-amp comparison result) as the gate voltage of the transistor, controlling the source-drain switching of the transistor through the gate voltage.

[0005] LDO working principle: First, the voltage divider sampling circuit uses its voltage divider resistors to sample the output voltage, which is then input to the error amplifier circuit. The error amplifier circuit compares the sampled voltage with the reference voltage and amplifies the comparison result. The amplified signal is input to the gate of the transistor adjustment circuit. The transistor is in the linear amplification operating region, and its overall value can be regarded as a voltage-controlled resistor whose resistance is controlled by the gate-source voltage. Therefore, the input gate signal controls the overall conduction of the transistor, thereby controlling the current in the output circuit. The final output voltage is determined by the voltage divider sampling resistors.

[0006] As described above, the various parts of the LDO form a negative feedback regulation loop. The specific regulation mechanism is as follows: Assume the transistor in the regulation circuit is a P-type MOSFET. The voltage sampled by the voltage divider sampling circuit is connected to the non-inverting input of the operational amplifier in the amplifier circuit, and the reference voltage is connected to the inverting input of the operational amplifier in the amplifier circuit. If the output voltage increases, the feedback sampling voltage increases, the non-inverting input voltage of the operational amplifier in the amplifier circuit increases, the output comparison difference of the operational amplifier increases, the gate voltage of the P-type MOSFET in the transistor regulation circuit increases, VGS decreases, the equivalent resistance of the P-type MOSFET in the linear operating region increases, the output voltage decreases, and the negative feedback regulation is achieved.

[0007] Advantages and disadvantages of LDO structure: Compared with other power supply regulator circuits, LDO circuit structure is simple, requires fewer external components, and is easier to optimize in terms of area and cost. However, the circuit has poor efficiency and the maximum output voltage is limited. Due to the inherent voltage difference between different parts and the presence of voltage divider resistors, the overall heat generation of the circuit is quite serious.

[0008] For example, in Chinese patent CN202410940975.6 "An LDO Circuit", the output voltage cannot be adjusted. CN202411128125.2 "An LDO Power Generation Circuit and Method with Adjustable Output without Compensation" also proposes an adjustable output, but it requires simultaneous adjustment of the reference voltage Verf, the ratio of the adjustable resistor to the resistor R0, and the current ratio of the power transistor M3 and the power transistor M2. The circuit implementation and adjustment methods are complicated, and neither of them takes into account the serious problem of power waste (heat generation) in LDO circuits.

[0009] From the above analysis of the principles of existing LDO technology, it can be seen that LDOs, as power supply regulator circuits, are widely used due to their simple structure, low cost, and practical application. However, LDO circuits also have structural disadvantages. Because they rely on resistor voltage division sampling to generate the output voltage, the maximum threshold of the output voltage is always clamped by the input voltage. At the same time, LDO circuits suffer from significant power waste (heat generation), specifically due to the following reasons: the error amplification structure always maintains a difference output, and the operational amplifier always has heat dissipation; the adjustment transistor, as the core of the adjustment circuit, is always in the linear region, and a voltage division exists between it and the voltage division sampling resistor, which also has a certain amount of heat dissipation. Furthermore, as... Figure 1 As shown, the fixed voltage divider sampling circuit determines the constant input voltage, which cannot meet the requirement of achieving multi-stage output voltage. Summary of the Invention

[0010] The purpose of this invention is to propose a new LDO circuit structure to solve the problem of the single output voltage parameter of LDO, and to further optimize the problem of heat power loss caused by the large difference between the feedback input voltage and the reference voltage due to the low output voltage.

[0011] To achieve the above objectives, the technical solution adopted by this invention is as follows: a multi-stage output low-voltage suppression LDO power supply circuit, comprising a reference voltage, an error amplifier, a voltage divider sampling circuit, and an adjustment transistor. The voltage divider sampling circuit is a multi-stage voltage divider sampling circuit. Specifically, multiple voltage divider sampling resistors are connected in series, with adjacent voltage divider sampling resistors serving as voltage sampling points. Each voltage sampling point is connected to the sampling voltage output terminal through its own sampling point switch. The sampling point switch is used to selectively conduct under the control of an external logic signal, thereby selectively selecting the voltage divider of one of the voltage sampling points as the sampling voltage input to one input terminal of the error amplifier. The reference voltage is input to the other input terminal of the error amplifier. The output terminal of the LDO power supply circuit is grounded through the voltage divider sampling circuit. The error amplifier is an operational amplifier. The output voltage of the error amplifier, i.e., the operational amplifier comparison result, serves as the gate voltage of the adjustment transistor, and the source-drain switching of the adjustment transistor is controlled by the gate voltage.

[0012] Furthermore, the adjustment transistor is a PMOS adjustment transistor. The inverting input terminal of the error amplifier is connected to the reference voltage, and the non-inverting input terminal is connected to the sampling voltage output terminal of the multi-stage voltage divider sampling circuit. The gate of the PMOS adjustment transistor is connected to the output terminal of the error amplifier, the source is connected to the input voltage of the LDO power supply circuit, and the drain is grounded through the multi-stage voltage divider sampling circuit. The drain of the PMOS adjustment transistor serves as the output terminal of the LDO power supply circuit.

[0013] Furthermore, the specific structure of the sampling point switch is as follows: it consists of an NMOS transistor and a PMOS transistor. The drain of the NMOS transistor is connected to the source of the PMOS transistor and then connected to the voltage sampling point. The source of the NMOS transistor is connected to the drain of the PMOS transistor and then connected to the sampling voltage output terminal. The external logic signals ADJ and ADJN are connected to the gate of the NMOS transistor and the gate of the PMOS transistor, respectively.

[0014] Furthermore, it also has a simple comparator, with the non-inverting input connected to the output of the LDO power supply circuit, the inverting input connected to the second reference voltage, and the output connected to the power input of the error amplifier.

[0015] Furthermore, the second reference voltage is a voltage divider sampling voltage of the reference voltage, that is, the second reference voltage is obtained by voltage divider sampling of the reference voltage.

[0016] Furthermore, the positive terminal of the reference voltage is grounded through resistors r1 and r2 connected in series, and the inverting input of the simple comparator is connected to the junction between resistors r1 and r2. That is, the sampling point of the second reference voltage is located at resistor r2.

[0017] The beneficial effects of this invention are:

[0018] (i) Multiple voltage sampling points are set in the voltage divider sampling resistor structure, and an external logic control signal ADJ is introduced to sample different output voltages VOUT in segments. The ADJ signal controls the gate voltage of the switching MOS transistor, thus solving the problem of the single output voltage parameter of LDO without changing the main feedback mechanism of LDO.

[0019] (ii) Introduce a simple comparator into the error amplifier circuit. The output of the simple comparator enables and controls the error amplifier, thereby clamping the output voltage of the output circuit and optimizing the heat power loss caused by the large difference between the feedback input voltage and the reference voltage due to the low output voltage. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of a traditional LDO circuit structure;

[0021] Figure 2 This is a schematic diagram of the LDO circuit structure according to an embodiment of the present invention;

[0022] Figure 3 This is a schematic diagram of the multi-stage voltage divider sampling circuit ADJR in an embodiment of the present invention. Detailed Implementation

[0023] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0024] Figures 2-3 One specific embodiment of the present invention is a multi-stage output low-voltage suppression LDO power supply circuit, including a reference voltage VREF, an error amplifier OP, a voltage divider sampling circuit, an adjustment transistor, and a simple comparator COMP, wherein the voltage divider sampling circuit is a multi-stage voltage divider sampling circuit ADJR;

[0025] like Figure 2 As shown, this embodiment uses a PMOS transistor as the adjustment transistor. The inverting input of the error amplifier OP is connected to the reference voltage VREF, and the non-inverting input is connected to the sampling voltage output of the multi-stage voltage divider sampling circuit ADJR. The gate of the adjustment transistor PMOS is connected to the output of the error amplifier OP, the source is connected to the input voltage VIN of the LDO power supply circuit, and the drain is grounded through the multi-stage voltage divider sampling circuit ADJR. The drain of the adjustment transistor PMOS serves as the output of the LDO power supply circuit. The error amplifier OP is an operational amplifier, and its output voltage, i.e., the operational amplifier comparison result, serves as the gate voltage of the adjustment transistor PMOS. The gate voltage controls the on / off state of the source and drain of the adjustment transistor PMOS.

[0026] The specific structure of the multi-stage voltage divider sampling circuit ADJR is as follows: five voltage divider sampling resistors R1, R03, R02, R01, and R00 are connected in series, where R1 is connected to the output voltage VOUT of the LDO power supply circuit and R00 is grounded; adjacent voltage divider sampling resistors serve as voltage sampling points, for a total of four voltage sampling points. Each voltage sampling point is connected to the sampling voltage output terminal through its own sampling point switch. The sampling point switch is used to selectively conduct under the control of an external logic signal, thereby selectively selecting the voltage divider of one of the voltage sampling points as the sampling voltage input to the non-inverting input terminal of the error amplifier OP.

[0027] like Figure 3 As shown, the specific structure of each sampling point switch in this embodiment is as follows: it consists of an NMOS transistor N and a PMOS transistor P. The drain of the NMOS transistor is connected to the source of the PMOS transistor and then connected to the voltage sampling point. The source of the NMOS transistor is connected to the drain of the PMOS transistor and then connected to the sampling voltage output terminal. The external logic signals ADJ<3:0> and ADJN<3:0> are connected to the gate of the NMOS transistor and the gate of the PMOS transistor, respectively.

[0028] In this embodiment, the non-inverting input of the simple comparator COMP is connected to the output of the LDO power supply circuit, the inverting input is connected to the second reference voltage VREF2, and the output of the simple comparator COMP is connected to the power input of the error amplifier OP.

[0029] The second reference voltage VREF2 is obtained by voltage division and sampling of the reference voltage VREF. Specifically, the positive terminal of the reference voltage VREF is grounded through resistors r1 and r2 connected in series, and the inverting input of the simple comparator COMP is connected to the connection point between resistors r1 and r2. That is, the sampling point of the second reference voltage VREF2 is located at resistor r2.

[0030] Combination Figures 2-3 The working principle of the circuit in this embodiment is explained as follows:

[0031] First, such as Figure 3 As shown, to solve the problem of single-stage output voltage, multiple voltage sampling points are set on the voltage divider sampling resistor string. The on / off state of the sampling point switching MOS transistor is controlled by the external logic signals ADJ<3:0> and ADJN<3:0>, thereby selecting different voltage divisions of the voltage divider sampling resistor as the sampling voltage feedback input to the error amplifier OP. Correspondingly, the final output voltage is adjusted to different values ​​by the negative feedback regulation mechanism.

[0032] The specific circuit feedback principle is as follows: Assume the ADJ<3:0> value is 1000, representing ADJ signals of 1, 0, 0, and 0 respectively for the sampling point switches at R03, R02, R01, and R00 (at this time, the ADJN<3:0> value is 0111). Both the N-transistor and P-transistor of the sampling point switch at R03 are turned on, so the sampling voltage sampling point is located at R03, the sampling voltage is maximum, the non-inverting input of the error amplifier OP is maximum, the amplified output difference is maximum, the gate voltage of the adjustment transistor PMOS is highest, its equivalent resistance is maximum, the current flowing through the adjustment transistor PMOS is minimum, and the output voltage VOUT is minimum. The output voltage values ​​corresponding to other ADJ values ​​are deduced similarly. By inputting different ADJ and ADJN signals from the outside, the multi-stage voltage divider sampling circuit ADJR is controlled to sample and select different voltage feedbacks. Through the negative feedback adjustment mechanism, different voltage values ​​can ultimately be output.

[0033] Second, to optimize the power waste problem in the LDO circuit, the enable control function of the error amplifier OP is added. The power supply current of the error amplifier OP is controlled by an external signal, thereby controlling the generation of the amplified signal output by the error amplifier OP, controlling the gate voltage of the PMOS transistor and the final output voltage, and regulating the heat generation power of the entire LDO circuit.

[0034] like Figure 2 As shown, as a low-dropout power supply stabilizer, the lower the LDO output voltage, the larger the input / output voltage difference, the worse the circuit efficiency, and the more serious the overall power waste problem. Therefore, to prevent the aforementioned adjustable output voltage structure from causing the final output voltage VOUT to be too low, an additional simple comparator COMP is set. Its non-inverting input is connected to the LDO output voltage, and its inverting input is directly obtained by sampling the reference voltage VREF through voltage division. The output value of the simple comparator COMP enables the switching of the supply current of the error amplifier OP. When the LDO output voltage VOUT is too low (below the second reference voltage VREF2), and the overall circuit efficiency is too poor, the comparison output result of the simple comparator COMP is 0, enabling the switching of the supply current of the error amplifier OP. The error amplifier OP is turned off, the gate voltage of the adjusting transistor PMOS is set to 0, the PMOS is turned on, its equivalent resistance decreases, the current flowing through the adjusting transistor PMOS increases, and the output voltage VOUT is pulled high, thus achieving a new negative feedback regulation.

[0035] It is evident that, in order to solve the problems of poor circuit efficiency and serious power waste when the LDO output voltage is too low, a new negative feedback regulation structure is introduced in addition to the original circuit structure. The new structure itself is simple and effective, with no additional power consumption, and can better optimize the problems in the traditional LDO structure design.

[0036] In summary, the novel structure provided by this invention aims to solve the problems of single-polarization of the output voltage and overall circuit heat and power consumption in traditional LDO circuits. By changing the structure of the voltage divider sampling circuit in the traditional circuit and introducing an external logic control signal, it achieves both multi-polarization of the output voltage and external adjustment capabilities. Furthermore, by adding a new, simple negative feedback adjustment structure, the low efficiency and high heat generation of traditional LDO circuits are optimized.

Claims

1. A multi-stage output low-voltage suppression LDO power supply circuit, comprising a reference voltage (VREF), an error amplifier (OP), a voltage divider sampling circuit, and an adjustment transistor, characterized in that: The voltage divider sampling circuit is a multi-stage voltage divider sampling circuit (ADJR). The specific structure of the multi-stage voltage divider sampling circuit (ADJR) is as follows: multiple voltage divider sampling resistors are connected in series, and adjacent voltage divider sampling resistors are used as voltage sampling points. Each voltage sampling point is connected to the sampling voltage output terminal through its own sampling point switch. The sampling point switch is used to selectively conduct under the control of an external logic signal.

2. The multi-stage output low-voltage suppression LDO power supply circuit according to claim 1, characterized in that: The adjustment transistor is a PMOS adjustment transistor. The inverting input of the error amplifier (OP) is connected to the reference voltage (VREF), and the non-inverting input is connected to the sampling voltage output of the multi-stage voltage divider sampling circuit (ADJR). The gate of the PMOS adjustment transistor is connected to the output of the error amplifier (OP), the source is connected to the input voltage (VIN) of the LDO power supply circuit, and the drain is grounded through the multi-stage voltage divider sampling circuit (ADJR). The drain of the PMOS adjustment transistor serves as the output of the LDO power supply circuit.

3. The multi-stage output low-voltage suppression LDO power supply circuit according to claim 1, characterized in that, The specific structure of the sampling point switch is as follows: it consists of an NMOS transistor and a PMOS transistor. The drain of the NMOS transistor is connected to the source of the PMOS transistor and then connected to the voltage sampling point. The source of the NMOS transistor is connected to the drain of the PMOS transistor and then connected to the sampling voltage output terminal. The external logic signals ADJ and ADJN are connected to the gate of the NMOS transistor and the gate of the PMOS transistor, respectively.

4. The multi-stage output low-voltage suppression LDO power supply circuit according to claim 1, characterized in that: It also features a simple comparator (COMP), with its non-inverting input connected to the output of the LDO power supply circuit and its inverting input connected to the second reference voltage (VREF2). The output of the simple comparator (COMP) is connected to the power input of the error amplifier (OP).

5. A multi-stage output low-voltage suppression LDO power supply circuit according to claim 4, characterized in that: The second reference voltage (VREF2) is the voltage sampled by the voltage divider of the reference voltage (VREF).

6. The multi-stage output low-voltage suppression LDO power supply circuit according to claim 5, characterized in that: The positive terminal of the reference voltage (VREF) is grounded through resistors r1 and r2 connected in series, and the inverting input of the simple comparator (COMP) is connected to the junction between resistors r1 and r2.

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