Processor chip supporting adaptive power consumption adjustment

Abstract

The invention provides a processor chip supporting self-adaptive power consumption adjustment, a plurality of functional cores and a plurality of routers are integrated on the chip, each router is used for receiving and transmitting data packets generated by the functional cores, each router comprises a plurality of input ports, each input port corresponds to an input buffer area, and each input buffer area corresponds to an output buffer area. Each input buffer area is used for providing a temporary storage space for a data packet, each input buffer area is provided with a corresponding input clock gating unit, and each input clock gating unit is used for receiving the data packet based on the storage state of the corresponding input buffer area and the receiving state of the input buffer area; whether a gated clock signal is input to the corresponding input buffer area is determined so as to control the working state of the input buffer area. Wherein when a data packet is stored in the input buffer area and / or the input buffer area effectively receives the data packet, the input clock gating unit inputs a gating clock signal to the input buffer area so as to control the input buffer area to work.

Description

Technical Field

[0001] This invention relates to integrated chips, more specifically to low-power integrated chips, and more particularly to a processor chip that supports adaptive power consumption adjustment. Background Technology

[0002] With advancements in integrated circuit technology, a single chip can integrate multiple functional cores (CPU, GPU, I / O, PICE, etc.) to form a large-scale System-on-Chip (SoC). In such multi-core systems, the Network-on-Chip (NoC) is a key device providing interconnectivity and meeting communication requirements. Functional cores are mounted on the NoC as master / slave devices, directly sending data packets to routers within the NoC for transmission to the target device. The NoC includes multiple routers and links, and can flexibly adopt different network topologies.

[0003] However, current on-chip networks (SoCs) face significant power consumption challenges. Specifically, the large scale, high operating frequency, and extensive cache resources of on-chip SoCs collectively lead to substantial power consumption. This high power consumption has multiple negative impacts on the chip: firstly, it restricts the overall performance of the chip; secondly, and more seriously, high power consumption can cause overheating, which not only reduces the stability of chip operation but also shortens its lifespan in the long run. Furthermore, power consumption is of widespread importance at the application level: for mobile devices, reducing power consumption directly relates to extending battery life, which is crucial for meeting users' portability and long-term usage needs; for scenarios such as cloud computing and data centers, reducing power consumption helps improve overall energy efficiency, thereby effectively reducing operating costs. Therefore, solving the high power consumption problem of on-chip networks has become an urgent need to improve chip performance and reliability.

[0004] To reduce the power consumption of on-chip networks, researchers have proposed two approaches. One approach is global information collection and power management, which manages power consumption by collecting information from all devices and NoC components within the chip, thereby reducing the power consumption of the on-chip network. The other approach is operating frequency adjustment, which reduces power consumption by adjusting the operating frequency of the on-chip network.

[0005] While both approaches can reduce the power consumption of on-chip networks (NoCs), they both have significant drawbacks. The core flaw of the global information collection and power management approach lies in the fact that collecting global information from all devices and NoC components for power management leads to extremely complex control logic and introduces excessive management overhead. The main drawback of the operating frequency adjustment approach is that achieving effective power reduction often requires overly fine-grained frequency adjustments, which makes clock switching control exceptionally complex and also results in high control overhead.

[0006] In summary, while existing technologies can reduce the power consumption of on-chip networks, they are difficult to implement efficiently due to control complexity and high overhead.

[0007] It should be noted that the background information presented here is only for illustrating relevant information about the present invention to aid in understanding the technical solutions of the present invention, and does not imply that the relevant information is necessarily prior art. In the absence of evidence indicating that the relevant information was disclosed before the filing date of this invention, the relevant information should not be considered prior art. Summary of the Invention

[0008] Therefore, the purpose of this invention is to overcome the shortcomings of the prior art and provide a processor chip that supports adaptive power consumption adjustment.

[0009] The objective of this invention is achieved through the following technical solutions.

[0010] This invention provides a processor chip that supports adaptive power consumption adjustment. The processor chip integrates multiple functional cores and multiple routers. All routers are interconnected to form an on-chip network. All functional cores are mounted on the on-chip network to achieve mutual communication. Each router is used to receive and transmit data packets generated by each functional core. Each router includes multiple input ports, each input port corresponding to an input buffer. Each input buffer provides temporary storage space for received data packets. Each input buffer is equipped with a corresponding input clock gating unit. Each input clock gating unit is used to determine whether to input a gating clock signal to the corresponding input buffer to control its working state based on the storage state and reception state of the corresponding input buffer. Specifically, when the input buffer stores data packets and / or the input buffer effectively receives data packets, the input clock gating unit inputs a gating clock signal to the input buffer to control its operation.

[0011] In some embodiments of the present invention, each router includes multiple output ports, each output port corresponds to an output buffer, each output buffer is used to provide temporary storage space for data packets transmitted from its own router to other routers, each output buffer is provided with a corresponding output clock gating unit, each output clock gating unit is used to determine whether to input a gating clock signal to the corresponding output buffer to control the working state of the output buffer based on the storage state and the receiving state of the corresponding output buffer; wherein, when the output buffer stores data packets and / or the output buffer effectively receives data packets, the output clock gating unit inputs a gating clock signal to the output buffer to control the operation of the output buffer.

[0012] In some embodiments of the present invention, the input clock gating unit includes an input gating unit and a logic OR gate, wherein the input gating unit is connected to the logic OR gate, and the logic OR gate is used to obtain the storage status signal and the reception status signal of the corresponding input buffer, and outputs a control signal to the input gating unit when the storage status signal indicates that the input buffer stores a data packet and / or the reception status signal indicates that the input buffer has effectively received a data packet; the input gating unit is used to input a gating clock signal to the corresponding input buffer based on the received control signal to control the operation of the input buffer.

[0013] In some embodiments of the present invention, the output clock gating unit includes an output gating unit and a logic OR gate, wherein the output gating unit is connected to the logic OR gate, and the logic OR gate is used to obtain the storage status signal and the reception status signal of the corresponding output buffer, and outputs a control signal to the output gating unit when the storage status signal indicates that the output buffer stores a data packet and / or the reception status signal indicates that the output buffer has effectively received a data packet; the output gating unit is used to input a gating clock signal to the corresponding output buffer based on the received control signal to control the operation of the output buffer.

[0014] In some embodiments of the present invention, the router further includes a routing calculation module for determining the output port corresponding to each data packet in the input buffer corresponding to each input port, so that each data packet in the input buffer corresponding to each input port is transmitted to other routers through the corresponding output port.

[0015] In some embodiments of the present invention, the router further includes a virtual channel allocation module, which is used to allocate a usable virtual channel between the corresponding input port and output port of each data packet in each input buffer based on the input port and output port corresponding to each data packet in each input buffer, so that each data packet is transmitted to the corresponding output port through the allocated virtual channel.

[0016] In some embodiments of the present invention, the router further includes a crossbar switch module, which is used to respond to access requests for each data packet in the input buffer corresponding to each input port, and to establish an allocated virtual channel between the input port and the output port corresponding to each data packet to transmit the data packet from the corresponding input buffer to the corresponding output port.

[0017] In some embodiments of the present invention, the router further includes a switch allocation module, which is used to adjudicate access requests from multiple data packets in the input buffers corresponding to multiple input ports to the cross switch module, so that the cross switch module sequentially establishes allocated virtual channels between the corresponding input ports and output ports according to the adjudication results, so as to transmit each data packet from the corresponding input buffer to the corresponding output port.

[0018] In some embodiments of the present invention, the network topology of the on-chip network is a Mesh network topology, a Ring network topology, or a Torus network topology.

[0019] Compared with the prior art, the advantages of the present invention are: by configuring an input clock gating unit for each input buffer and an output clock gating unit for each output buffer, fine-grained control of the input buffer and the output buffer can be achieved, thereby ensuring that the on-chip network power consumption is reduced without generating excessive management overhead. Attached Figure Description

[0020] The embodiments of the present invention will be further described below with reference to the accompanying drawings, wherein:

[0021] Figure 1 This is a schematic diagram of the composition of a processor chip according to an embodiment of the present invention;

[0022] Figure 2 A schematic diagram of the input buffer without an input clock gating unit configured;

[0023] Figure 3 This is a schematic diagram of an input buffer configured with an input clock gating unit according to an embodiment of the present invention;

[0024] Figure 4 A schematic diagram of the output buffer without an output clock gating unit configured;

[0025] Figure 5 This is a schematic diagram of an output buffer configured with an output clock gating unit according to an embodiment of the present invention. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the invention.

[0027] Before describing the present invention, let me first introduce some existing methods for reducing the power consumption overhead of on-chip networks.

[0028] Chinese patent application CN202011135266.9 proposes a method, apparatus, CPU chip, and server for reducing on-chip network (NoC) power consumption. The method involves acquiring the operating status data of the NoC, including one or more of the following: the number of unresponsive requests initiated by the NIU within a time window, the number of requests and responses cached in the RU within a time window, and historical bandwidth statistics of the NoC. Based on this data, the method calculates the expected operating frequency of the NoC and adjusts its operating frequency accordingly, ultimately reducing the power consumption overhead of the NoC. While this method can reduce the power consumption overhead of the NoC, it requires overly fine-grained frequency adjustments, which makes clock switching control exceptionally complex and introduces high control overhead.

[0029] Chinese patent application CN202011135779.X discloses a method, apparatus, CPU chip, and server for reducing the power consumption of an on-chip network (NoC). The method includes: acquiring the operating status data of the NoC, which includes one or more of the following: the maximum number of caches used by the NIU and the maximum number of caches used by the RU in a recent period; calculating the number of caches that need to be enabled in the NIU and RU respectively based on the operating status data; and disabling the remaining caches in the NIU and RU based on the number of caches that need to be enabled. While this method can reduce the power consumption of the NoC, collecting global information from all devices and all NoC components for power management leads to extremely complex control logic and introduces excessive management overhead.

[0030] Chinese patent application CN202011135270.5 discloses a method, apparatus, CPU chip, and server for reducing the power consumption of an on-chip network (NoC). The method includes: acquiring operating status data of the on-chip NoC's mounted devices within a time window, the operating status data including one or more of the following: the frequency of bandwidth-sensitive events occurring in the device, cache utilization in the device, and the bandwidth of the device's interface bus; calculating the expected operating frequency of the NoC based on the operating status data; and adjusting the operating frequency of the NoC based on the expected operating frequency. While this method can reduce the power consumption of the on-chip network, it requires overly fine-grained frequency adjustments, which makes clock switching control exceptionally complex and introduces high control overhead.

[0031] Chinese patent application CN202011284050.9 discloses a method, apparatus, CPU chip, and server for reducing the power consumption of an on-chip network (NoC). The method includes: dividing the NoC into two or more non-overlapping regions, each region using its own independent operating clock; acquiring the operating status data of the routing units (RUs) of the NoC; calculating the expected operating frequency of each region of the NoC based on the operating status data; and adjusting the operating frequency of each region of the NoC to the expected operating frequency. While this method can reduce the power consumption of the NoC, it requires overly fine-grained frequency adjustments, which makes clock switching control exceptionally complex and introduces high control overhead.

[0032] As can be seen from the background technology and the above-mentioned methods for reducing the power consumption of on-chip networks, although existing technologies can reduce the power consumption of on-chip networks, they are difficult to be efficient and practical due to control complexity and high management overhead.

[0033] To address the aforementioned issues, the inventors analyzed on-chip networks and discovered that a significant portion of the on-chip network's power consumption originates from the buffers within the router. This power consumption arises from the periodic updates of these buffers. Periodic updates mean that in each clock cycle, the buffer performs data shift-in (writing new data) and / or shift-out (reading old data) operations (periodic updates can be understood as keeping the buffer constantly active). In reality, buffers do not need periodic updates. When a buffer is neither written to nor read from in a given cycle, it does not need to be updated (in this case, the buffer should remain in an inactive state for that cycle). Based on this, the inventors proposed a low-power chip that uses clock gating within the router to control buffer updates, thereby avoiding the substantial power overhead caused by meaningless updates, ultimately reducing on-chip network power consumption and improving chip performance and reliability.

[0034] In summary, such as Figure 1 As shown, this invention proposes a processor chip that supports adaptive power consumption adjustment. The processor chip integrates multiple functional cores and multiple routers. All routers are interconnected to form an on-chip network. All functional cores are mounted on the on-chip network to achieve mutual communication. Each router is used to receive and transmit data packets generated by each functional core. Each router includes multiple input ports, each input port corresponding to an input buffer. Each input buffer provides temporary storage space for received data packets. Each input buffer is equipped with a corresponding input clock gating unit. Each input clock gating unit is used to determine whether to input a gating clock signal to the corresponding input buffer to control its working state based on the storage state and reception state of the corresponding input buffer. Specifically, when the input buffer stores data packets and / or the input buffer effectively receives data packets, the input clock gating unit inputs a gating clock signal to the input buffer to control its operation.

[0035] It should be noted that, for ease of understanding, Figure 1 Each input buffer has a corresponding input clock gating unit above it, and each output buffer also has a corresponding output clock gating unit above it, but... Figure 1 What is shown is only the one-to-one correspondence between the input buffer and the input clock gating unit, and the one-to-one correspondence between the output buffer and the output clock gating unit. The actual connection relationship between the input clock gating unit and the corresponding input buffer, and between the output buffer and the corresponding output clock gating unit, is not as shown. Figure 1 As shown (see other attached figures).

[0036] To better understand the present invention, the following detailed description is provided with reference to specific embodiments of the router in the processor chip proposed in the present invention.

[0037] Depend on Figure 1 It is known that each router in the processor chip includes multiple input ports, each input port corresponds to an input buffer, each input buffer is used to provide temporary storage space for received data packets, each input buffer is equipped with a corresponding input clock gating unit, each input clock gating unit is used to determine whether to input a gating clock signal to the corresponding input buffer to control the working state of the input buffer based on the storage state and the receiving state of the corresponding input buffer.

[0038] According to one embodiment of the present invention, the input clock gating unit includes an input gating unit and a logic OR gate, wherein the input gating unit is connected to the logic OR gate, and the logic OR gate is used to obtain the storage status signal and the reception status signal of the corresponding input buffer, and outputs a control signal to the input gating unit when the storage status signal indicates that the input buffer stores a data packet and / or the reception status signal indicates that the input buffer has effectively received a data packet; the input gating unit is used to input a gating clock signal to the corresponding input buffer based on the received control signal to control the operation of the input buffer.

[0039] To better understand this invention, the following is combined with... Figure 2 and Figure 3 This section details how the gating unit controls the operating state of the corresponding input buffer based on the input clock. Figure 2 This indicates an input buffer without an configured input clock gating unit. Figure 3 This indicates an input buffer configured with an input clock gating unit.

[0040] Depend on Figure 2 It is known that an input buffer without an input clock gating unit will continuously receive clock signals to keep the input buffer in a working state, which will generate a lot of unnecessary power consumption.

[0041] Depend on Figure 3 As can be seen, the input clock gating unit includes an input gating unit and a logic OR gate, with the input gating unit connected to the logic OR gate. The logic OR gate receives the storage status signal and the receive status signal of the corresponding input buffer. When the storage status signal indicates that the input buffer stores a data packet (the storage status signal value is 1), or when the receive status signal indicates that the input buffer has effectively received a data packet (the receive status signal value is 1), or when both the storage status signal and the receive status signal indicate that the input buffer has effectively received a data packet (both storage and receive status signal values ​​are 1), the gate outputs a control signal (control signal value is 1) to the input gating unit. The input gating unit is used to input a gating clock signal to the corresponding input buffer based on the received control signal to control the operation of that input buffer. It should be noted that when the input buffer does not store a data packet, the storage status signal value of the input buffer is 0; when the input buffer has not received a data packet, the receive status signal of the input buffer is 0.

[0042] In simple terms, the working principle of the input clock gating unit can be summarized as follows: when the OR gate receives a storage status signal value and / or a receive status signal value of 1 from the input buffer, it outputs a control signal of value 1 to the input gating unit, so that the input gating unit inputs a gating clock signal to the corresponding input buffer to control the operation of the input buffer; when the OR gate receives a storage status signal value and a receive status signal value of 0 from the input buffer, it outputs a control signal of value 0 to the input gating unit, so that the input gating unit does not input a gating clock signal to the corresponding input buffer, making the input buffer in a non-working state.

[0043] As described in the foregoing embodiments, each input buffer is configured with a corresponding input clock gating unit to control its own operating state. This ensures that the input buffer is in a non-operating state when it has neither received nor stored data, avoiding unnecessary power consumption and effectively reducing the power consumption of the on-chip network to improve chip performance and reliability. Furthermore, each input buffer independently controls its own operating state through its configured input clock gating unit. This control method achieves fine-grained control of the input buffer without incurring high management overhead.

[0044] According to one embodiment of the present invention, each router includes multiple output ports, each output port corresponds to an output buffer, each output buffer is used to provide temporary storage space for data packets transmitted from its own router to other routers, each output buffer is provided with a corresponding output clock gating unit, each output clock gating unit is used to determine whether to input a gating clock signal to the corresponding output buffer to control the working state of the output buffer based on the storage state and the receiving state of the corresponding output buffer; wherein, when the output buffer stores data packets and / or the output buffer effectively receives data packets, the output clock gating unit inputs a gating clock signal to the output buffer to control the operation of the output buffer.

[0045] According to one embodiment of the present invention, the output clock gating unit includes an output gating unit and a logic OR gate, wherein the output gating unit is connected to the logic OR gate, and the logic OR gate is used to acquire the storage status signal and the reception status signal of the corresponding output buffer, and outputs a control signal to the output gating unit when the storage status signal indicates that the output buffer stores a data packet and / or the reception status signal indicates that the output buffer has effectively received a data packet; the output gating unit is used to input a gating clock signal to the corresponding output buffer based on the received control signal to control the operation of the output buffer.

[0046] To better understand this invention, the following is combined with... Figure 4 and Figure 5This section details how the output clock gating unit controls the operating state of the corresponding output buffer. Figure 4 This indicates that the output buffer of the output clock gating unit is not configured. Figure 5 This indicates an input buffer configured with an output clock gating unit.

[0047] Depend on Figure 4 It is known that the output buffer without an output clock gating unit will continuously receive clock signals to keep the output buffer in a working state, which will generate a lot of unnecessary power consumption.

[0048] Depend on Figure 5 As can be seen, the output clock gating unit includes an output gating unit and a logic OR gate, with the output gating unit connected to the logic OR gate. The logic OR gate receives the storage status signal and the receive status signal of the corresponding output buffer. When the storage status signal indicates that the output buffer stores a data packet (the storage status signal value is 1), or when the receive status signal indicates that the output buffer has effectively received a data packet (the receive status signal value is 1), or when both the storage status signal and the receive status signal indicate that the output buffer has effectively received a data packet (both storage and receive status signal values ​​are 1), the gate outputs a control signal (control signal value is 1) to the output gating unit. The output gating unit is used to input a gating clock signal to the corresponding output buffer based on the received control signal to control the operation of that output buffer. It should be noted that when the output buffer does not store a data packet, the storage status signal value of the output buffer is 0; when the output buffer has not received a data packet, the receive status signal of the output buffer is 0.

[0049] In simple terms, the working principle of the output clock gating unit can be summarized as follows: When the logic OR gate receives the storage status signal value and / or the receive status signal value of the output clock gating unit as 1, it outputs a control signal of value 1 to the output gating unit, so that the output gating unit inputs a gating clock signal to the corresponding output buffer to control the operation of the input buffer; when the logic OR gate receives the storage status signal value and the receive status signal value of the output clock gating unit as 0, it outputs a control signal of value 0 to the output gating unit, so that the output gating unit does not input a gating clock signal to the corresponding output buffer, making the output buffer in a non-working state.

[0050] As described in the foregoing embodiments, each output buffer is configured with a corresponding output clock gating unit to control its own operating state. This ensures that the output buffer is in a non-operating state when no data is received or stored, avoiding unnecessary power consumption and effectively reducing the power consumption of the on-chip network to improve chip performance and reliability. Furthermore, each output buffer independently controls its own operating state through its configured output clock gating unit. This control method achieves fine-grained control of the output buffer without incurring high management overhead.

[0051] According to one embodiment of the present invention, such as Figure 1 As shown, the router also includes a routing calculation module, which is used to determine the output port corresponding to each data packet in the input buffer of each input port, so that each data packet in the input buffer of each input port is transmitted to other routers through the corresponding output port.

[0052] According to one embodiment of the present invention, such as Figure 1 As shown, the router also includes a virtual channel allocation module, which is used to allocate a usable virtual channel between the corresponding input port and output port of each data packet in each input buffer based on the input port and output port corresponding to each data packet in each input buffer, so that each data packet can be transmitted to the corresponding output port through the allocated virtual channel.

[0053] According to one embodiment of the present invention, such as Figure 1 As shown, the router also includes a crossbar switch module, which is used to respond to the access request of each data packet in the input buffer corresponding to each input port, and to establish an allocated virtual channel between the input port and the output port corresponding to each data packet to transmit the data packet from the corresponding input buffer to the corresponding output port.

[0054] According to one embodiment of the present invention, such as Figure 1 As shown, the router also includes a switch allocation module, which is used to adjudicate access requests from multiple data packets in the input buffers of multiple input ports to the cross switch module, so that the cross switch module establishes allocated virtual channels between the corresponding input ports and output ports in sequence according to the adjudication results, so as to transmit each data packet from the corresponding input buffer to the corresponding output port.

[0055] According to one embodiment of the present invention, the network topology of the on-chip network is a Mesh network topology, a Ring network topology, or a Torus network topology.

[0056] As can be seen from the foregoing embodiments, unlike the prior art, the present invention focuses on reducing the power consumption of input buffers and output buffers in routers. By configuring an input clock gating unit for each input buffer and an output clock gating unit for each output buffer, fine-grained control of input buffers and output buffers is achieved, thereby ensuring that on-chip network power consumption is reduced without generating excessive management overhead.

[0057] The beneficial effects of this invention are as follows: by configuring an input clock gating unit for each input buffer and an output clock gating unit for each output buffer, fine-grained control of the input and output buffers can be achieved, thereby ensuring that the on-chip network power consumption is reduced without generating excessive management overhead.

[0058] It should be noted that although the steps are described in a specific order above, it does not mean that the steps must be executed in the above specific order. In fact, some of these steps can be executed concurrently or even in a different order, as long as the required function can be achieved.

[0059] This invention can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of the invention.

[0060] Computer-readable storage media can be tangible devices that hold and store instructions for use by an instruction execution device. Computer-readable storage media can include, for example, but not limited to, electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination thereof.

[0061] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A processor chip supporting adaptive power consumption adjustment, wherein the processor chip integrates multiple functional cores and multiple routers, all routers are interconnected to form an on-chip network, and all functional cores are mounted on the on-chip network to achieve mutual communication, wherein... Each router is used to receive and transmit data packets generated by various functional cores. Each router includes multiple input ports, each input port corresponds to an input buffer, and each input buffer is used to provide temporary storage space for received data packets. Its features include: Each input buffer is equipped with a corresponding input clock gating unit. Each input clock gating unit is used to determine whether to input a gating clock signal to the corresponding input buffer to control the working state of the input buffer based on the storage state and reception state of the corresponding input buffer. Specifically, when the input buffer stores data packets and / or the input buffer effectively receives data packets, the input clock gating unit inputs a gating clock signal to the input buffer to control the operation of the input buffer.

2. The processor chip according to claim 1, wherein each router includes multiple output ports, each output port corresponds to an output buffer, and each output buffer is used to provide temporary storage space for data packets transmitted from its own router to other routers, characterized in that: Each output buffer is equipped with a corresponding output clock gating unit. Each output clock gating unit is used to determine whether to input a gating clock signal to the corresponding output buffer to control the working state of the output buffer based on the storage state and the receiving state of the corresponding output buffer. Specifically, when the output buffer stores data packets and / or the output buffer effectively receives data packets, the output clock gating unit inputs a gating clock signal to the output buffer to control the operation of the output buffer.

3. The processor chip according to claim 2, characterized in that, The input clock gating unit includes an input gating unit and a logic OR gate, wherein the input gating unit is connected to the logic OR gate, and: The logic OR gate is used to obtain the storage status signal and the reception status signal of the corresponding input buffer, and outputs a control signal to the input gating unit when the storage status signal indicates that the input buffer stores a data packet and / or the reception status signal indicates that the input buffer has effectively received a data packet; The input gating unit is used to input a gating clock signal to the corresponding input buffer based on the received control signal in order to control the operation of the input buffer.

4. The processor chip according to claim 3, characterized in that, The output clock gating unit includes an output gating unit and a logic OR gate, wherein the output gating unit is connected to the logic OR gate, and: The logic OR gate is used to obtain the storage status signal and the reception status signal of the corresponding output buffer, and outputs a control signal to the output gating unit when the storage status signal indicates that the output buffer stores a data packet and / or the reception status signal indicates that the output buffer has effectively received a data packet; The output gating unit is used to input a gating clock signal to the corresponding output buffer based on the received control signal in order to control the operation of the output buffer.

5. The processor chip according to claim 4, characterized in that, The router also includes a routing calculation module, which is used to determine the output port corresponding to each data packet in the input buffer of each input port, so that each data packet in the input buffer of each input port is transmitted to other routers through the corresponding output port.

6. The processor chip according to claim 5, characterized in that, The router also includes a virtual channel allocation module, which allocates a usable virtual channel between the corresponding input port and output port of each data packet in each input buffer based on the input port and output port corresponding to each data packet in each input buffer, so that each data packet can be transmitted to the corresponding output port through the allocated virtual channel.

7. The processor chip according to claim 6, characterized in that, The router also includes a crossbar switch module, which is used to respond to access requests for each data packet in the input buffer corresponding to each input port, and to establish an allocated virtual channel between the input port and the output port corresponding to each data packet to transmit the data packet from the corresponding input buffer to the corresponding output port.

8. The processor chip according to claim 7, characterized in that, The router also includes a switch allocation module, which is used to adjudicate access requests from multiple data packets in the input buffers of multiple input ports to the cross switch module. This allows the cross switch module to establish allocated virtual channels between the corresponding input ports and output ports in sequence according to the adjudication results, so as to transmit each data packet from the corresponding input buffer to the corresponding output port.

9. The processor chip according to claim 8, characterized in that, The network topology of the on-chip network is a Mesh network topology, a Ring network topology, or a Torus network topology.

10. An electronic device, characterized in that, include: One or more processor chips as described in any one of claims 1-9, and a memory.

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