Floating point number processing device and method

Abstract

The embodiment of the invention discloses a floating-point number processing device and method, and the device comprises an index adjustment module and a floating-point number calculation module. The index adjustment module is used for performing additive operation on the index of the first floating-point number and the index of the second floating-point number to obtain a first addition index, and unifying the data formats of the first addition index and the index of the third floating-point number; and the floating-point number calculation module is used for determining a target floating-point number after multiplication and addition operation is performed on the first floating-point number, the second floating-point number and the third floating-point number based on the unified first addition index and the unified index of the third floating-point number. Therefore, index addition and data format unification can be realized in one step, a format converter does not need to be additionally arranged, and the calculation rate is improved while the hardware cost is reduced.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of computer technology, and particularly to a floating-point number processing apparatus and method. Background Technology

[0002] Fused Multiply-Add (FFMA) is a highly efficient floating-point arithmetic method that optimizes performance by combining multiplication and addition into a single operation step. In traditional floating-point arithmetic, multiplication and addition are performed separately, which reduces computation speed and increases latency. FFMA, however, allows multiplication and addition to be completed within a single instruction cycle, thereby improving overall computation speed.

[0003] However, in related technologies, floating-point numbers need to be formatted before multiplication and addition operations, which reduces the calculation speed. Summary of the Invention

[0004] In view of this, the present disclosure provides at least one floating-point number processing apparatus and method.

[0005] The technical solution of this disclosure embodiment is implemented as follows: On one hand, this disclosure provides a floating-point number processing device, which includes: an exponent adjustment module and a floating-point number calculation module; the exponent adjustment module is used to perform an addition operation on the exponent of a first floating-point number and the exponent of a second floating-point number to obtain a first addition exponent, and to unify the data format of the first addition exponent and the exponent of a third floating-point number; the floating-point number calculation module is used to determine the target floating-point number after performing multiplication and addition operations on the first floating-point number, the second floating-point number and the third floating-point number based on the unified first addition exponent and the unified exponent of the third floating-point number.

[0006] In some embodiments, the exponent adjustment module is specifically used to determine the exponent offset of the first floating-point number, the exponent offset of the second floating-point number, the exponent offset of the third floating-point number, and the exponent offset of the intermediate format; perform addition on the exponents of the first and second floating-point numbers to obtain a first additive exponent; unify the data format of the first additive exponent based on the exponent offsets of the first, second, and intermediate formats to obtain a unified first additive exponent; unify the data format of the third floating-point exponent based on the exponent offsets of the third and intermediate formats to obtain a unified third floating-point exponent; the exponent offset of the intermediate format is determined based on the maximum value of the exponent bit width among the first, second, and third floating-point numbers.

[0007] In some embodiments, the floating-point calculation module includes: a mantissa adjustment module, a mantissa multiplication module, and a floating-point addition module; the mantissa adjustment module is used to adjust the mantissa of the third floating-point number based on the unified first addition exponent and the unified exponent of the third floating-point number to obtain the adjusted mantissa of the third floating-point number; the mantissa multiplication module is used to perform multiplication on the mantissa of the first floating-point number and the mantissa of the second floating-point number to obtain the multiplication mantissa; the floating-point addition module is used to determine the target floating-point number based on the adjusted mantissa of the third floating-point number and the multiplication mantissa.

[0008] In some embodiments, the mantissa adjustment module includes: an exponent subtraction module and a mantissa shift module; the exponent subtraction module is used to determine the exponent difference between the unified first addition exponent and the unified third floating-point number exponent; the mantissa shift module is used to shift the mantissa of the third floating-point number based on the exponent difference to obtain the mantissa of the adjusted third floating-point number.

[0009] In some embodiments, the exponent subtraction module is specifically used to determine a temporary exponent difference based on the unified first addition exponent, the unified exponent of the third floating-point number, and a preset third bit threshold; when the width of the exponent of the third floating-point number is less than the exponent bit width of the intermediate format, the exponent difference is determined based on the temporary exponent difference and the number of second values ​​that the mantissa of the third floating-point number has before the first value; when the width of the exponent of the third floating-point number is greater than or equal to the exponent bit width of the intermediate format, the temporary exponent difference is used as the exponent difference.

[0010] In some embodiments, the mantissa adjustment module is specifically used to expand the mantissa of the third floating-point number based on the total bit width of the calculation window of the mantissa addition module to obtain the expanded mantissa of the third floating-point number; when the state of the multiplication-addition operation and the temporary exponent difference output by the window state detection module meet the first condition, the mantissa of the expanded third floating-point number is shifted to the left according to the number of second values ​​that the mantissa of the third floating-point number had before it was the first value, to obtain the adjusted mantissa of the third floating-point number; the first condition is that the state of the multiplication-addition operation is the second state and the temporary exponent difference is less than the second value; when the state of the multiplication-addition operation and the temporary exponent difference meet the second condition, the mantissa of the expanded third floating-point number is used as the mantissa of the adjusted third floating-point number; the second condition is that the state of the multiplication-addition operation is the first state and the temporary exponent difference is greater than or equal to the second value; when the state of the multiplication-addition operation and the temporary exponent difference do not meet the first and second conditions, the mantissa of the expanded third floating-point number is shifted to the right according to the mantissa of the expanded third floating-point number, to obtain the adjusted mantissa of the third floating-point number.

[0011] In some embodiments, the floating-point addition module includes: an addition exponent calculation module, an addition mantissa calculation module, and a floating-point adjustment module; the addition exponent calculation module is used to determine a second addition exponent based on the state of the multiplication-addition operation, the unified first addition exponent, and the unified exponent of the third floating-point number; the addition mantissa calculation module is used to determine the addition mantissa and the addition sign bit based on the mantissa of the adjusted third floating-point number and the multiplication mantissa; the floating-point adjustment module is used to determine the target floating-point number based on the second addition exponent, the addition mantissa, and the addition sign bit.

[0012] In some embodiments, the states of the multiplication-addition operation include at least one of the following: First state: the difference between the unified first addition exponent and the unified third floating-point number exponent is less than a second value; Second state: the exponent difference is greater than or equal to the second value and less than the first digit threshold; the first digit threshold indicates that the mantissa of the multiplication and the mantissa of the adjusted third floating-point number completely overlap in the position of the calculation window; Third state: the exponent difference is greater than or equal to the first digit threshold and less than the second digit threshold; the second digit threshold indicates that the mantissa of the multiplication and the mantissa of the adjusted third floating-point number do not overlap in the position of the calculation window, and the position of the mantissa of the multiplication is before the position of the mantissa of the adjusted third floating-point number; Fourth state: the exponent difference is greater than or equal to the second digit threshold.

[0013] In some embodiments, the addition exponent calculation module is specifically used to: when the multiplication-addition operation is in the first state, use the unified third floating-point number exponent as a temporary addition exponent; when the multiplication-addition operation is in the second state, determine the temporary addition exponent based on the unified first addition exponent and the third bit threshold; when the multiplication-addition operation is in the third or fourth state, use the unified first addition exponent as the temporary addition exponent; and adjust the temporary addition exponent based on the exponent offset of the temporary addition exponent and the exponent offset of the intermediate format to obtain the second addition exponent.

[0014] In some embodiments, the addition mantissa calculation module includes: a window state detection module, a window selection module, and a mantissa addition module; the window state detection module is used to detect the state of the multiplication-addition operation; the window selection module is used to place the multiplication mantissa and the adjusted third floating-point number mantissa into the calculation window of the mantissa addition module based on the state of the multiplication-addition operation; the mantissa addition module is used to perform addition operation on the multiplication mantissa and the adjusted third floating-point number mantissa in the calculation window to obtain the addition mantissa and the addition sign bit.

[0015] In some embodiments, the window selection module is specifically configured to: when the multiplication-addition operation is in the first state, assign the second value to the first addend in the calculation window, and truncate the first digit of the adjusted third floating-point number from the high-order bits downwards and assign it to the second addend in the calculation window; when the multiplication-addition operation is in the second state, truncate the second digit of the multiplication mantissa from the high-order bits downwards and assign it to the first addend in the calculation window, and truncate the first digit of the adjusted third floating-point number from the high-order bits downwards and assign it to the second addend in the calculation window; when the multiplication-addition operation is in the third state, shift the multiplication mantissa to the left by three digits and assign it to the first addend in the calculation window, and truncate the fourth digit of the adjusted third floating-point number from the high-order bits downwards and assign it to the second addend in the calculation window; when the multiplication-addition operation is in the fourth state, shift the multiplication mantissa to the left by three digits and assign it to the first addend in the calculation window, and assign the second value to the second addend in the calculation window.

[0016] In some embodiments, the addition mantissa calculation module is specifically used to determine a temporary sign based on the sign of the first floating-point number, the sign of the second floating-point number, and the sign of the third floating-point number; if the temporary sign is negative, subtract the first addend and the second addend to obtain a temporary addition mantissa; if the temporary sign is positive, add the first addend and the second addend to obtain a temporary addition mantissa; determine the addition sign based on the value of the target number of bits in the temporary addition mantissa; and determine the addition mantissa based on the addition sign and the temporary addition mantissa.

[0017] In some embodiments, the floating-point adjustment module includes a leading zero prediction module and a normalization module; the leading zero prediction module is used to determine the error of the addition mantissa; the normalization module is used to adjust the data format of the second addition exponent, the addition mantissa, and the addition sign bit based on the error of the addition mantissa to obtain the target floating-point number.

[0018] In some embodiments, the floating-point processing apparatus further includes: a leading zero detection module; the leading zero detection module is configured to detect the number of second values ​​that the mantissa of the third floating-point number has before becoming the first value, so as to assist the exponent subtraction module in determining the exponent difference.

[0019] In some embodiments, the floating-point processing apparatus further includes: a source operand extraction module; the source operand extraction module is configured to extract the floating-point number corresponding to the source operand from each input source operand according to a preset storage method.

[0020] In some embodiments, the mantissa shifting module runs in parallel with the mantissa multiplication module.

[0021] On the other hand, embodiments of this disclosure provide a method for determining floating-point numbers. The method includes: performing an addition operation on the exponents of a first floating-point number and a second floating-point number to obtain a first addition exponent, and unifying the data formats of the first addition exponent and the exponent of a third floating-point number; and determining a target floating-point number after performing multiplication and addition operations on the first floating-point number, the second floating-point number, and the third floating-point number based on the unified first addition exponent and the unified exponent of the third floating-point number.

[0022] In this embodiment of the disclosure, the exponent adjustment module can achieve the unification of exponent addition and data format in one step without the need for an additional format converter, thus reducing hardware costs. Compared with the operation in related technologies that requires format conversion through a format converter and then addition of two exponents through an exponent adder, the operation is simpler and the calculation speed is faster.

[0023] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of this disclosure. Attached Figure Description

[0024] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the specification, serve to illustrate the technical solutions of this disclosure.

[0025] Figure 1 A schematic diagram illustrating the composition structure of a floating-point number provided in an embodiment of this disclosure; Figure 2 A schematic diagram of the composition structure of a floating-point multiply-accumulate arithmetic device in a related art provided in this disclosure embodiment; Figure 3 A schematic diagram of the composition structure of a floating-point processing device provided in this embodiment of the present disclosure. Figure 1 ; Figure 4 A schematic diagram of the composition structure of a floating-point processing device provided in this embodiment of the present disclosure. Figure 2 ; Figure 5 A schematic diagram of the composition structure of a floating-point processing device provided in this embodiment of the present disclosure. Figure 3 ; Figure 6 A schematic diagram illustrating the implementation of a calculation window in a floating-point processing device provided in this embodiment of the present disclosure; Figure 7 A schematic diagram of the implementation process of a floating-point number processing method provided in this embodiment of the present disclosure. Figure 1 ; Figure 8 A schematic diagram of the implementation process of a floating-point number processing method provided in this embodiment of the present disclosure. Figure 2 ; Figure 9 A schematic diagram of the composition structure of a floating-point processing device provided in this embodiment of the present disclosure. Figure 4 ; Figure 10 This is a schematic diagram of the hardware entity of a computer device provided in an embodiment of this disclosure. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this disclosure clearer, the technical solutions of this disclosure are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0027] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0028] The terms “first / second / third” are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that “first / second / third” may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. The terminology used herein is for descriptive purposes only and is not intended to limit the scope of this disclosure.

[0030] To better understand the floating-point processing apparatus provided in the embodiments of this disclosure, the solutions in the related technologies will be described below.

[0031] A floating-point number consists of 1 sign bit, n exponent bits, and m mantissa bits. The sign bit indicates whether the floating-point number is positive or negative (e.g., 0 for positive, 1 for negative). The exponent bits represent the range of the value. The mantissa bits represent the precision of the value, that is, the decimal part. n and m are both positive integers greater than or equal to 1. Figure 1 As shown, taking a 32-bit floating point (FP32) as an example, the 32-bit width includes 23 mantissa bits (bits 0-23), 8 exponent bits (bits 24-30), and 1 sign bit (bit 31).

[0032] Floating-point multiplication and addition is one of the most frequently used instructions in computers. It multiplies two floating-point numbers and then adds a third floating-point number to the result. The key feature of this instruction is that it performs both floating-point multiplication and addition in a single instruction. Furthermore, it does not normalize the multiplication result when adding it to the third floating-point number, preserving more relevant information. Therefore, the final result is more accurate than calculating using floating-point multiplication and addition separately.

[0033] The mixed-precision floating-point multiplication and addition method in related technologies can be divided into the following steps 1 to 7: 1. Convert the three floating-point numbers used for calculation into a unified floating-point format.

[0034] 2. Multiply the last digits of the two numbers to be multiplied (floating-point number one and floating-point number two) to get the last digit of the multiplication result.

[0035] 3. Add the exponents of the two numbers to be multiplied to get the exponent of the multiplication result.

[0036] 4. Subtract the exponent of the multiplication result from the exponent of the floating-point number 3 to obtain the difference in exponents.

[0037] 5. Adjust the relative positions of the mantissas of the multiplication result and the mantissas of the floating-point number three according to the difference in exponents, so that their exponents are the same, thus achieving exponent alignment.

[0038] 6. Add (or subtract) the two mantissas after exponent alignment to obtain the mantissa and sign bit of the addition result, and use the aligned exponent as the exponent of the addition result.

[0039] 7. Normalize the exponent and mantissa of the addition result to meet the format requirements of floating-point numbers.

[0040] In related technologies, step 4 can be implemented as follows: Choose the smaller exponent between the multiplication result and the floating-point number 3, and right-shift its mantissa. For each bit shifted to the right, the corresponding exponent is incremented by 1, until the two exponents are the same. Related technologies typically use... Figure 2 The hardware structure shown is used to perform similar calculations: like Figure 2As shown in Figure 2, assume the multiplication operation involves multiplying floating-point number 1 by floating-point number 2, and then adding the result to floating-point number 3. Correspondingly, floating-point number 1 is split into sign bit 1, exponent 1, and mantissa bit 1; floating-point number 2 is split into sign bit 2, exponent 2, and mantissa bit 2; and floating-point number 3 is split into sign bit 3, exponent 3, and mantissa bit 3. As can be seen from Figure 2, a format converter must perform a pre-format conversion operation before the multiplication and addition operations. After the format conversion, the calculation of mantissa bit multiplied by mantissa bit 2 must be completed before other calculations targeting the mantissa can begin. During the multiplication calculation, mantissa bit 3 must wait. In practical circuits, time is mainly consumed in mantissa calculations, so it is best to utilize the multiplication time to perform more processing on mantissa bit 3.

[0041] In related technologies, because the multiplication and addition operations must first undergo format conversion and the calculation of mantissa one multiplied by mantissa two, other operations on the mantissa can only wait for the processing results of these two features, resulting in low processing efficiency.

[0042] Therefore, embodiments of this disclosure provide a floating-point processing apparatus, such as... Figure 3 As shown, the floating-point processing device 30 includes: an exponent adjustment module 31 and a floating-point calculation module 32; The exponent adjustment module 31 is used to perform an addition operation on the exponent of the first floating-point number and the exponent of the second floating-point number to obtain a first additive exponent, and to unify the data format of the first additive exponent and the exponent of the third floating-point number. The floating-point calculation module 32 is used to determine the target floating-point number after performing multiplication and addition operations on the first floating-point number, the second floating-point number, and the third floating-point number based on the unified first addition exponent and the unified exponent of the third floating-point number.

[0043] If the floating-point processing device provided in this embodiment is used to calculate the multiplication and addition of three floating-point numbers—a first floating-point number, a second floating-point number, and a third floating-point number—and the calculation method is first floating-point number * second floating-point number + third floating-point number, then the first floating-point number, second floating-point number, and third floating-point number can be represented by characters for easier calculation.

[0044] Specifically, the first floating-point number can be represented as src0, the second floating-point number as src1, and the third floating-point number as src2. For the first floating-point number, the sign can be represented as sgn0, the exponent as exp0, and the mantissa as mat0; the bit width can be represented as num0_width, the exponent bit width as exp0_width, and the mantissa bit width as mat0_width.

[0045] Similarly, for the second floating-point number, the sign of the second floating-point number can be represented as sgn1, the exponent of the second floating-point number as exp1, and the mantissa of the second floating-point number as mat1; the bit width of the second floating-point number can be represented as num1_width, the bit width of the exponent of the second floating-point number as exp1_width, and the bit width of the mantissa of the second floating-point number as mat1_width.

[0046] Similarly, for a third floating-point number, the bit width of the third floating-point number can be represented as num2_width, the sign of the third floating-point number as sgn2, the exponent of the third floating-point number as exp2, and the mantissa of the third floating-point number as mat2; the bit width of the third floating-point number can be represented as num2_width, the bit width of the exponent of the third floating-point number as exp2_width, and the bit width of the mantissa of the third floating-point number as mat2_width.

[0047] It should be noted that the floating-point processing device 30 provided in this embodiment can support mixed operations of floating-point numbers with x different precisions. Therefore, the precisions of the first, second, and third floating-point numbers may be different. Thus, during multiplication and addition operations, it is necessary to unify the data format of the floating-point numbers to facilitate multiplication and addition operations.

[0048] This embodiment selects an intermediate format to unify the data formats of the three floating-point numbers, thereby achieving exponent alignment. In one feasible implementation, the intermediate format can be the format with the largest bit width among the floating-point types supported by the floating-point processing device 30. For example, if the floating-point processing device 30 supports mixed operations of floating-point numbers with two precisions, FP32 and FP16, then the intermediate format can be the data format of the FP32 floating-point type.

[0049] For example, regarding the first floating-point number src0, the second floating-point number src1, and the third floating-point number src2, the maximum value among the exponent widths exp0_width, exp1_width, and exp2_width is selected as the exponent width of the intermediate format, which can be represented as exp_width_tmp; the maximum value among the mantissa widths mat0_width, mat1_width, and mat2_width is selected as the mantissa width of the intermediate format, which can be represented as mat_width_tmp.

[0050] The exponent adjustment module 31 is used to determine the exponent of the first floating-point number and the sum of the exponents of the second floating-point number, and to obtain the exponent sum with a unified data format and the exponent of the third floating-point number. The exponent of the first floating-point number and the sum of the exponents of the second floating-point number can be called the first additive exponent, which can be represented as exp01.

[0051] The exponent adjustment module 31 is used to determine the first addition exponent based on the exponent of the first floating-point number, the exponent of the second floating-point number, the exponent offset of the first floating-point number, the exponent offset of the second floating-point number, and the exponent offset of the intermediate format.

[0052] In some implementations, the exponent adjustment module 31 is specifically used to determine the exponent offset of the first floating-point number, the exponent offset of the second floating-point number, the exponent offset of the third floating-point number, and the exponent offset of the intermediate format; and to perform an addition operation on the exponent of the first floating-point number and the exponent of the second floating-point number to obtain a first additive exponent.

[0053] In some implementations, the exponent adjustment module 31 is specifically used to unify the data format of the first addition exponent based on the exponent offset of the first floating-point number, the exponent offset of the second floating-point number, and the exponent offset of the intermediate format, to obtain the unified first addition exponent; and to unify the data format of the third floating-point exponent based on the exponent offset of the third floating-point number and the exponent offset of the intermediate format, to obtain the unified exponent of the third floating-point number; wherein the exponent offset of the intermediate format is determined based on the maximum value of the exponent bit width among the first floating-point number, the second floating-point number, and the third floating-point number.

[0054] For example, the exponent adjustment module 31 determines that the calculation formula for the first additive exponent exp01 can be: exp01 = exp0 + exp1 - bias0 - bias1 + bias_tmp. Here, exp0 represents the exponent of the first floating-point number, exp1 represents the exponent of the second floating-point number, bias0 represents the exponent offset of the first floating-point number, bias1 represents the exponent offset of the second floating-point number, and bias_tmp represents the exponent offset in intermediate format. "-bias0 - bias1 + bias_tmp" can be considered as a format unification of "exp0 + exp1".

[0055] The exponential offset can be calculated as 2 raised to the power of the width minus 1. For example, the formula for calculating the exponential offset in intermediate format is: bias_tmp= -1; The formula for calculating the exponent offset of the first floating-point number is: bias0 = The formula for calculating the exponent offset of the second floating-point number is: bias1 = -1; The formula for calculating the exponent offset of the third floating-point number is: bias2 = -1.

[0056] For example, the formula for unifying the data format of the exponent of the third floating-point number by the exponent adjustment module 31 can be: exp2' = exp2 - bias2 + bias_tmp. Here, exp2' represents the unified exponent of the third floating-point number, exp2 represents the exponent of the third floating-point number, bias2 represents the exponent offset of the third floating-point number, and bias_tmp represents the exponent offset of the intermediate format.

[0057] When the data formats of the first, second, and third floating-point numbers are the same, the exponent adjustment module 31 only needs to obtain the first additive exponent exp01 through the formula exp0+exp1. At this time, the data formats of the first additive exponent and the exponent of the third floating-point number are unified, and there is no need to unify the data format through the exponent offset. Therefore, exp2 is used to represent the unified exponent of the third floating-point number, and exp01 is used to represent the unified first additive exponent.

[0058] It should be noted that, in order to improve the calculation speed, this embodiment combines the unification of data format and the exponential addition operation into a single step. That is, unlike related technologies that require format conversion via a format converter followed by addition of the two exponents via an exponential adder, this embodiment, through the calculation formulas of exp01 and exp2 in the exponential adjustment module 31, can achieve exponential addition and data format unification in one step, without the need for an additional format converter, resulting in a faster calculation speed.

[0059] The floating-point calculation module 32 is used to determine the target floating-point number after performing multiplication and addition operations on the first, second, and third floating-point numbers, based on the unified first addition exponent and the unified exponent of the third floating-point number. The target floating-point number is the floating-point number obtained after performing multiplication and addition operations on the first, second, and third floating-point numbers.

[0060] In some implementations, the floating-point calculation module 32 can be a multiply-accumulate operator in the related art, which determines the target floating-point number after multiplying and accumulating the first floating-point number, the second floating-point number, and the third floating-point number based on the unified first addition exponent and the unified exponent of the third floating-point number.

[0061] In some embodiments, the first floating-point number, the second floating-point number, and the third floating-point number can be input according to a certain storage format. In this case, the floating-point number processing device 30 further includes a source operand extraction module. The source operand extraction module is used to extract the floating-point number corresponding to each input source operand according to a preset storage method.

[0062] The source operand extraction module is used to extract a floating-point number in a specified format from each input source operand according to a predefined storage method. For example, if each source operand is 32 bits wide, then an FP32 type source operand is stored within all 32 bits, while the significant bits of an FP16 type source operand are stored in the lower 16 bits, the higher 16 bits, or distributed across the 32 bits. The only requirement is to ensure that the corresponding floating-point number can be extracted subsequently according to the predefined storage method.

[0063] Based on the above technical means, the source operand extraction module can extract the effective floating-point part according to different storage formats, thereby adapting to multiple input formats and enhancing the versatility and flexibility of the device.

[0064] Based on the foregoing embodiments, this disclosure provides a new floating-point number calculation module. Specifically, as shown in... Figure 4 As shown, the floating-point calculation module 32 includes: a mantissa adjustment module 321, a mantissa multiplication module 322, and a floating-point addition module 323; the mantissa adjustment module 321 is used to adjust the mantissa of the third floating-point number based on the unified first addition exponent and the unified exponent of the third floating-point number to obtain the adjusted mantissa of the third floating-point number; the mantissa multiplication module 322 is used to perform multiplication on the mantissa of the first floating-point number and the mantissa of the second floating-point number to obtain the multiplication mantissa; the floating-point addition module 323 is used to determine the target floating-point number based on the adjusted mantissa of the third floating-point number, the multiplication mantissa, the unified first addition exponent, and the unified exponent of the third floating-point number.

[0065] Based on the above technical means, the mantissa adjustment module shifts and adjusts the mantissa of the third floating-point number to align it with the exponent of the multiplication result. The mantissa multiplication module performs the multiplication operation, and the floating-point addition module adds the multiplication mantissa to the adjusted mantissa, thus achieving efficient and accurate multiplication and addition operations.

[0066] The following is a detailed explanation of the tail number adjustment module 321.

[0067] The mantissa adjustment module 321 is used to adjust the mantissa of the third floating-point number based on the exponent difference between the unified first addition exponent and the unified third floating-point number exponent, to obtain the adjusted mantissa of the third floating-point number. The adjusted mantissa of the third floating-point number can be represented as shf_mat2.

[0068] In some implementations, such as Figure 5As shown, the mantissa adjustment module 321 includes: an exponent subtraction module 3211 and a mantissa shift module 3212; the exponent subtraction module 3211 is used to determine the exponent difference between the unified first addition exponent and the unified third floating-point number; the mantissa shift module 3212 is used to shift the mantissa of the third floating-point number based on the exponent difference to obtain the mantissa of the adjusted third floating-point number.

[0069] The exponent subtraction module 3211 is used to calculate the exponent difference between the unified first additive exponent exp01 and the unified third floating-point exponent exp2. The exponent difference can be represented as exp_diff.

[0070] Further, the exponent subtraction module 3211 is specifically used to: determine a temporary exponent difference based on the unified first addition exponent, the unified exponent of the third floating-point number, and a preset third bit threshold; when the width of the exponent of the third floating-point number is less than the exponent bit width of the intermediate format, determine the exponent difference based on the temporary exponent difference and the number of second values ​​that the mantissa of the third floating-point number has before the first value; when the width of the exponent of the third floating-point number is greater than or equal to the exponent bit width of the intermediate format, use the temporary exponent difference as the exponent difference.

[0071] The third-digit threshold can be represented as exp_constant. In one feasible implementation, the third-digit threshold can be determined based on the mantissa width of the intermediate format. For example, the formula for calculating the third-digit threshold can be: exp_constant = mat_width_tmp + 4; where mat_width_tmp represents the mantissa width of the intermediate format. It should be noted that the specific values ​​involved in the embodiments of this disclosure can be adjusted according to actual needs and are not limited to unique values.

[0072] In one feasible implementation, the specific implementation of "determining the temporary exponent difference based on the unified first addition exponent, the unified third floating-point exponent, and the preset third bit threshold" can be as follows: first, perform a subtraction operation on the unified first addition exponent and the unified third floating-point exponent, and then add the result of the operation to the third bit threshold to obtain the temporary exponent difference.

[0073] For example, the formula for calculating the temporary exponential difference can be: exp_diff_tmp = exp01 + exp_constant – exp2; where exp_diff_tmp represents the temporary exponential difference, exp01 represents the unified first additive exponent, exp_constant represents the third bit threshold, and exp2 represents the unified third floating-point exponent.

[0074] The number of second values ​​that the mantissa of a third floating-point number has before the first value refers to the number of zeros in the highest bit of the mantissa of the third floating-point number. In this case, the first value refers to 1 and the second value refers to 0. The number of zeros in the highest bit of the mantissa of the third floating-point number can be represented as src2_lzd.

[0075] Based on the above technical means, the exponent subtraction module calculates the exponent difference to provide a basis for subsequent mantissa adjustment; the mantissa shift module shifts the mantissa accordingly based on the exponent difference to ensure that the multiplication result and the third floating-point number are consistent in terms of exponent, thereby improving the accuracy of multiplication and addition operations.

[0076] In some implementations, the number of second values ​​that the mantissa of the third floating-point number has before the first value can be detected by a leading zero detection module in the floating-point processing device 30.

[0077] Specifically, the leading zero detection module is used to detect the number of second values ​​that the mantissa of the third floating-point number has before it becomes the first value, so as to assist the exponent subtraction module 3211 in determining the exponent difference.

[0078] For example, the leading zero detection module is used to detect the number of zeros in the most significant bit of mat2 (the mantissa of the third floating-point number). The output of this module is src2_lzd. If there are src2_lzd_tmp zeros in the most significant bit of mat2 and src2 (the third floating-point number) is a denormalized number, then src2_lzd = src2_lzd_tmp + 1; if src2 is not a denormalized number, then src2_lzd = 0; if mat2 is all zeros, then any value can be output.

[0079] It should be noted that since the mantissa of a normalized number implicitly contains a leading 1 (for example, the mantissa of a single-precision normalized number is actually 1.M, but the leading 1 is omitted during storage to save bit width), while the mantissa of a denormalized number does not have an implicit leading 1 (it is directly 0.M), in order to unify denormalized and normalized numbers, when the third floating-point number is a denormalized number, it is necessary to add 1 to src2_lzd_tmp.

[0080] Based on the aforementioned technical means, the leading zero detection module can identify the number of leading zeros in denormalized numbers to assist in the calculation of exponent difference, thereby improving the accuracy of exponent adjustment, especially when processing low-precision floating-point numbers.

[0081] The specific implementation of the exponent subtraction module 3211, which determines the exponent difference based on the temporary exponent difference, can be as follows: When the exponent width of the third floating-point number is less than the exponent bit width of the intermediate format, the temporary exponent difference and the second value that the mantissa of the third floating-point number has before reaching the first value are subtracted to obtain the exponent difference; in this case, the formula for calculating the exponent difference can be expressed as: exp_diff = exp_diff_tmp - src2_lzd. When the exponent width of the third floating-point number is greater than or equal to the exponent bit width of the intermediate format, the temporary exponent difference is used as the exponent difference; in this case, the formula for calculating the exponent difference can be expressed as: exp_diff = exp_diff_tmp.

[0082] In some embodiments, the mantissa shifting module 3212 needs to use the multiplication-addition operation state when shifting the mantissa of the third floating-point number. Therefore, before describing the mantissa shifting module 3212, the state of the multiplication-addition operation will be introduced first.

[0083] Specifically, the state of the multiplication-addition operation can be divided into four states based on the exponent difference exp_diff determined by the exponent subtraction module 3211 and the difference in the number of bits between the mantissa of the multiplication and the mantissa of the adjusted third floating-point number.

[0084] The state of the multiply-add operation includes at least one of the following: First state: The difference between the unified first additive exponent and the unified third floating-point exponent is less than the second value; Second state: The exponent difference is greater than or equal to the second value and less than the first digit threshold; the first digit threshold indicates that the mantissa of the multiplication and the mantissa of the adjusted third floating-point number completely overlap in the position of the calculation window; Third state: The exponent difference is greater than or equal to the first bit threshold and less than the second bit threshold; the second bit threshold indicates that the mantissa of the multiplication and the mantissa of the adjusted third floating-point number do not overlap in the position of the calculation window, and the position of the mantissa of the multiplication is before the position of the mantissa of the adjusted third floating-point number; Fourth state: The exponential difference is greater than or equal to the second bit threshold.

[0085] The mantissa addition module performs addition operations through a calculation window. The calculation window refers to the bit width range of data that can be processed at one time, i.e., the granularity of the operation. In some implementations, the total bit width of the calculation window can be determined based on the mantissa bit width of the intermediate format, such as... Figure 6 As shown, the total bit width of the calculation window can be mat_width_tmp*4+7 bits.

[0086] Regarding the first state, the exponent difference between the unified first additive exponent and the unified third floating-point exponent is represented as exp_diff, and the second value is 0; at this time, the first state is: 0>exp_diff.

[0087] When the mantissa of the multiplication (mat01) and the mantissa of the adjusted third floating-point number (shf_mat2) completely overlap in the position of the calculation window, the threshold for the first digit is mat_width_tmp+3. At this time, the second state is: (mat_width_tmp+3)>exp_diff>=0.

[0088] When the mantissa of the multiplication and the mantissa of the adjusted third floating-point number do not overlap in the calculation window of the mantissa addition module, and the position of the mantissa of the multiplication is before the position of the mantissa of the adjusted third floating-point number, the second bit threshold can be mat_width_tmp*3+7. In this case, the third state can be represented as: (mat_width_tmp*3+7)>exp_diff>=(mat_width_tmp+3), and the fourth state can be represented as: exp_diff>=(mat_width_tmp*3+7).

[0089] It should be noted that, based on the relationship between the exponent difference and the bit threshold, the multiplication-addition operation is divided into four states, which fully considers all possible scenarios of the exponent difference, so as to more finely control the placement of the mantissa during the multiplication-addition operation, thereby optimizing the efficiency of the adder, reducing unnecessary hardware resource overhead, and improving the operation speed.

[0090] The following is a detailed explanation of the tail displacement module 3212 in the tail adjustment module 321.

[0091] The mantissa shifting module 3212 is used to shift the mantissa of the third floating-point number based on the exponent difference to obtain the adjusted mantissa of the third floating-point number. The adjusted mantissa of the third floating-point number can be represented as shf_mat2.

[0092] The mantissa shift module 3212 is specifically used for: expanding the mantissa of the third floating-point number based on the total bit width of the calculation window of the mantissa addition module to obtain the mantissa of the expanded third floating-point number; when the state of the multiplication-addition operation output by the window state detection module and the temporary exponent difference satisfy a first condition, shifting the mantissa of the expanded third floating-point number to the left according to the number of second values ​​that the mantissa of the third floating-point number had before being a first value, to obtain the mantissa of the adjusted third floating-point number; the first condition is that the state of the multiplication-addition operation is the second state and the temporary exponent difference is... If the difference is less than the second value; if the state of the multiplication-addition operation and the temporary exponent difference satisfy the second condition, the mantissa of the extended third floating-point number is taken as the mantissa of the adjusted third floating-point number; the second condition is that the state of the multiplication-addition operation is the first state and the temporary exponent difference is greater than or equal to the second value; if the state of the multiplication-addition operation and the temporary exponent difference do not satisfy the first condition and the second condition, the mantissa of the extended third floating-point number is right-shifted according to the mantissa of the extended third floating-point number to obtain the mantissa of the adjusted third floating-point number.

[0093] The total bit width of the calculation window for the mantissa addition module can be mat_width_tmp*4+7 bits.

[0094] In one feasible implementation, the specific implementation of "extending the mantissa of the third floating-point number based on the total bit width of the calculation window of the mantissa addition module to obtain the extended mantissa of the third floating-point number" can be as follows: extend the mantissa of the third floating-point number upward by one bit to obtain the extended mantissa of the third floating-point number by one bit; extend the extended mantissa of the third floating-point number by one bit downward to the total bit width to obtain the extended mantissa of the third floating-point number.

[0095] Specifically, the implementation of "extending the mantissa of the third floating-point number up by one bit to obtain the mantissa of the extended third floating-point number" can be as follows: if the third floating-point number is denormalized, the highest bit of the extended number is set to 1; if the third floating-point number is not denormalized, the highest bit of the extended number is set to 0. In this case, the mantissa of the extended third floating-point number can be represented as ext_mat2_tmp.

[0096] Specifically, the implementation of "extending the mantissa of the extended third floating-point number by one bit down to the total bit width to obtain the mantissa of the extended third floating-point number" can be as follows: extend the mantissa (ext_mat2_tmp) of the extended third floating-point number by one bit down to the total bit width (mat_width_tmp*4+7 bits) to obtain the mantissa of the extended third floating-point number. In this case, the mantissa of the extended third floating-point number can be represented as ext_mat2.

[0097] For example, when expanding ext_mat2_tmp downward to obtain ext_mat2, it needs to be expanded by mat_width_tmp * 3 + 6 bits. All the positions expanded downward are set to 0. After expansion, the total bit width is mat_width_tmp * 4 + 7 bits.

[0098] The state of the multiply-add operation is the second state, which means that the state of the multiply-add operation is: (mat_width_tmp + 3) > exp_diff >= 0; the temporary exponent difference is less than the second value, which means that exp_diff_tmp < 0. At this time, the first condition is: exp_diff_tmp < 0, and the state of the multiply-add operation is: (mat_width_tmp + 3) > exp_diff >= 0.

[0099] The state of the multiply-add operation is the first state, which means that the state of the multiply-add operation is: 0 > exp_diff; the temporary exponent difference is greater than or equal to the second value, which means that exp_diff_tmp ≥ 0. At this time, the second condition is: exp_diff_tmp ≥ 0 and 0 > exp_diff.

[0100] In a feasible implementation, when the first condition is satisfied, the calculation formula for the mantissa of the adjusted third floating-point number can be: shf_mat2 = ext_mat2 << src2_lzd. Here, shf_mat2 represents the mantissa of the adjusted third floating-point number, ext_mat2 represents the mantissa of the expanded third floating-point number, and src2_lzd represents the second value that the mantissa of the third floating-point number has before being the first value.

[0101] In a feasible implementation, when the second condition is satisfied, the calculation formula for the mantissa of the adjusted third floating-point number can be: shf_mat2 = ext_mat2.

[0102] In a feasible implementation, when the first condition and the second condition are not satisfied, the calculation formula for the mantissa of the adjusted third floating-point number can be: shf_mat2 = ext_mat2 >> ext_mat2.

[0103] The mantissa multiplication module 322 will be specifically described below.

[0104] The mantissa multiplication module 322 is used to perform a multiplication operation on the mantissa (mat0) of the first floating-point number and the mantissa (mat1) of the second floating-point number to obtain a multiplication mantissa. The multiplication mantissa can be represented as mat01.

[0105] In some implementations, the mantissa multiplication module 322 is specifically used to: extend the mantissa of the first floating-point number and the mantissa of the second floating-point number to the maximum value of the mantissa width (mat_width_tmp); and multiply the extended mantissa of the first floating-point number and the extended mantissa of the second floating-point number to obtain the multiplication mantissa.

[0106] In one feasible implementation, "extending the mantissa of the first floating-point number and the mantissa of the second floating-point number to the maximum value of the mantissa bit width" can be achieved by padding the lower bits of the mantissa with 0, and then extending the mantissas of the extended src0 and src1 by 1 bit upwards. Specifically, if src0 (or src1) is a denormalized number, the highest bit of the extension is set to 1; otherwise, it is set to 0.

[0107] The following is a detailed explanation of the floating-point addition module 323.

[0108] In some embodiments, the floating-point addition module 323 may include an exponent adder, a mantissa adder, and a normalization module, as described in the related art.

[0109] In the embodiments disclosed herein, such as Figure 5 As shown, the floating-point addition module 323 includes: an addition exponent calculation module 3231, an addition mantissa calculation module 3232, and a floating-point adjustment module 3233; The addition exponent calculation module 3231 is used to determine the second addition exponent based on the state of the multiplication-addition operation, the unified first addition exponent, and the unified third floating-point exponent. The addition mantissa calculation module 3232 is used to determine the addition mantissa and the addition sign bit based on the mantissa of the adjusted third floating-point number, the multiplication mantissa, and the exponent difference between the unified first addition exponent and the unified third floating-point number. The floating-point adjustment module 3233 is used to determine the target floating-point number based on the second addition exponent, the addition mantissa, and the addition sign bit.

[0110] The addition exponent calculation module 3231 is used to determine the second addition exponent based on the state of the multiplication-addition operation. The second addition exponent can be represented as exp_add.

[0111] The addition exponent calculation module 3231 is specifically used for: when the multiplication-addition operation is in the first state, using the unified third floating-point number exponent as a temporary addition exponent; when the multiplication-addition operation is in the second state, determining a temporary addition exponent based on the unified first addition exponent and the third bit threshold; when the multiplication-addition operation is in the third or fourth state, using the unified first addition exponent as a temporary addition exponent; and adjusting the temporary addition exponent based on the exponent offset of the temporary addition exponent and the exponent offset of the intermediate format to obtain the second addition exponent.

[0112] For example, a temporary additive exponent can be represented as exp_add_tmp. The temporary additive exponent can be determined in three ways: In the first case, if the multiplication-addition operation is in the first state, then set exp_add_tmp=exp2; where exp2 represents the exponent of the unified third floating-point number.

[0113] In the second case, if the multiplication-addition operation is in the second state, then set the temporary addition exponent exp_add_tmp = exp01 + mat_width_tmp + 4, where exp01 represents the first addition exponent, mat_width_tmp represents the mantissa width of the intermediate format, and mat_width_tmp + 4 is the third bit threshold.

[0114] In the third case, if the multiplication-addition operation is in the third or fourth state, then set exp_add_tmp=exp01.

[0115] In one feasible implementation, the specific implementation of "adjusting the temporary additive exponent based on the exponent offset of the temporary additive exponent and the exponent offset of the intermediate format to obtain the second additive exponent" can be as follows: determine the exponent width expd_width of the temporary additive exponent; determine the second additive exponent based on the temporary additive exponent, the exponent offset of the temporary additive exponent, and the exponent offset of the intermediate format.

[0116] For example, the formula for calculating the exponential bias of a temporary additive exponent can be: exp_add_bias= -1. The formula for calculating the second additive exponent is: exp_add = exp_add_tmp - bias_tmp + exp_add_bias.

[0117] The addition mantissa calculation module 3232 is used to place the multiplication mantissa and the adjusted third floating-point number mantissa into the calculation window of the mantissa addition module based on the state of the multiplication-addition operation; and to perform addition operation on the multiplication mantissa and the adjusted third floating-point number mantissa in the calculation window to obtain the addition mantissa and the addition sign bit.

[0118] In some embodiments, the addition mantissa calculation module 3232 includes: a window state detection module 32321, a window selection module 32322, and a mantissa addition module 32323; The window state detection module 32321 is used to detect the state of the multiplication-addition operation; The window selection module 32322 is used to place the mantissa of the multiplication and the mantissa of the adjusted third floating-point number into the calculation window of the mantissa addition module based on the state of the multiplication-addition operation. The mantissa addition module 32323 is used to perform addition operations on the mantissa of the multiplication and the mantissa of the adjusted third floating-point number in the calculation window to obtain the addition mantissa and the addition sign bit.

[0119] The window selection module 32322 is specifically used for: when the multiplication-addition operation is in the first state, assigning the second value to the first addend in the calculation window, and truncating the first digit of the mantissa of the adjusted third floating-point number from the high digit downwards and assigning it to the second addend in the calculation window; when the multiplication-addition operation is in the second state, truncating the second digit of the mantissa of the multiplication from the high digit downwards and assigning it to the first addend in the calculation window, and truncating the first digit of the mantissa of the adjusted third floating-point number from the high digit downwards and assigning it to the second addend in the calculation window; when the multiplication-addition operation is in the third state, shifting the mantissa of the multiplication to the left by three digits and assigning it to the first addend in the calculation window, and truncating the fourth digit of the mantissa of the adjusted third floating-point number from the high digit downwards and assigning it to the second addend in the calculation window; when the multiplication-addition operation is in the fourth state, shifting the mantissa of the multiplication to the left by three digits and assigning it to the first addend in the calculation window, and assigning the second value to the second addend in the calculation window.

[0120] In one feasible implementation, the first addend is represented as addin0, the second addend as addin1, and the mantissa of the adjusted third floating-point number is represented as shf_mat2. If the multiplication-addition operation is in the first state, addin0 is set to 0, and shf_mat2 is truncated from the most significant bit downwards by mat_width_tmp*2+5 bits and assigned to addin1, i.e., addin1=shf_mat2[mat_width_tmp*4+6: mat_width_tmp*2+2]; and if mat01 is not equal to 0, sticky is set to 1, otherwise sticky is set to 0.

[0121] If the multiplication-addition operation is in the second state, then truncate mat01 from high to low by taking the value of mat_width_tmp+2 bits and assign it to addin0, i.e., addin0=mat01[mat_width_tmp*2+1: mat_width_tmp]. Then shf_mat2 truncates mat_width_tmp*2+5 bits from the highest bit and assigns it to addin1, i.e., addin1=shf_mat2[mat_width_tmp*4+6: mat_width_tmp*2+2]. Furthermore, if mat01[mat_width_tmp-1:0] is not equal to 0, then sticky=1 is set; otherwise, sticky=0 is set.

[0122] If the multiplication-addition operation is in the third state, then set addin0 = mat01 << 2, and truncate mat_width_tmp * 2 + 4 bits from the highest bit downwards, assigning them to addin1. addin1=shf_mat2[mat_width_tmp*3+3:mat_width_tmp]; and if shf_mat2[mat_width_tmp-1:0] is not equal to 0, then set sticky=1, otherwise set sticky=0.

[0123] If the multiplication-addition operation is in the fourth state, then set addin0=mat01<<2 and addin1=0; and if ext_mat2_tmp is not equal to 0, then set sticky=1, otherwise set sticky=0.

[0124] like Figure 6As shown, the total bit width of the calculation window is mat_width_tmp*4+7 bits. The bit width of the calculation window is mat_width_tmp*2+6 when the multiplication-addition operation is in the first and second states, and mat_width_tmp*2+6 when the multiplication-addition operation is in the third and fourth states. When the multiplication-addition operation is in the first state, ext_mat2_tmp (the mantissa of the third floating-point number after being extended by one bit) and mat01 (the mantissa of the multiplication) do not overlap. At this time, addin0=0, and addin1=shf_mat2 [mat_width_tmp*4+6: mat_width_tmp*2+2]. When the multiply-add operation is in the second state, ext_mat2_tmp and mat01 partially overlap, but ext_mat2_tmp comes first and mat01 comes second. In this case, addin0 = mat01[mat_width_tmp*2+1:mat_width_tmp], and addin1 = shf_mat2[mat_width_tmp*4+6: mat_width_tmp*2+2]. When the multiply-add operation is in the third state, ext_mat2_tmp and mat01 partially overlap, but ext_mat2_tmp comes second and mat01 comes first. In this case, addin0 = mat01<<2, and addin1 = shf_mat2[mat_width_tmp*3+3:mat_width_tmp]. When the multiply-add operation is in the fourth state, ext_mat2_tmp and mat01 do not overlap, but ext_mat2_tmp comes second and mat01 comes first. In this case, addin0 = mat01<<2, and addin1 = 0.

[0125] It should be noted that different truncation operations are performed under different states of multiplication and addition to obtain the significant bits of the floating-point number, facilitating subsequent addition of the mantissa. Furthermore, Figure 6 The reason for setting the first front extension bit to 61 is that when performing addition operations, there may be situations where it is necessary to carry over one bit. Figure 6 The reason for setting the second pre-extension bit 62 is to add a sign bit so as to know the sign after the subtraction operation. Figure 6 The reason for setting the first extension bit 63 is to provide a rounding bit for easier rounding operations. Figure 6 The reason for setting a second extension bit of 64 is to set a sticky bit.

[0126] The mantissa addition module 32323 is used to process the addition or subtraction operation of two addends in the calculation window, thereby obtaining the mantissa and the sign bit of the addition.

[0127] The mantissa addition module 32323 is specifically used for: determining a temporary sign based on the sign of the first floating-point number, the sign of the second floating-point number, and the sign of the third floating-point number; performing subtraction on the first addend and the second addend when the temporary sign is negative to obtain the temporary addition mantissa; performing addition on the first addend and the second addend when the temporary sign is positive to obtain the temporary addition mantissa; determining the addition sign based on the value of the target number of bits in the temporary addition mantissa; and determining the addition mantissa based on the addition sign and the temporary addition mantissa.

[0128] In one feasible implementation, the specific method for "determining a temporary symbol based on the sign of the first floating-point number, the sign of the second floating-point number, and the sign of the third floating-point number" can be: Perform an exponentiation operation on the sign of the first and second floating-point numbers, and then perform an exponentiation operation on the result of the exponentiation and the sign of the third floating-point number to obtain the temporary symbol. For example, sgn01 = sgn0^sgn1, sub = sgn01^sgn2; where sgn0 represents the sign of the first floating-point number, sgn1 represents the sign of the second floating-point number, sgn2 represents the sign of the third floating-point number, sgn01 represents the result of the exponentiation operation, and sub represents the temporary symbol.

[0129] In one feasible implementation, if the temporary sign is negative, determine whether the result of the exponentiation is negative. If the result is negative, subtract the second addend, the first addend, and the sticky bit in sequence to obtain the temporary addition mantissa. If the result is not negative, subtract the first addend, the second addend, and the sticky bit in sequence to obtain the temporary addition mantissa.

[0130] For example, if `sub` is negative (a negative number can be represented as 1), subtraction is performed; if `sub` is positive (a positive number can be represented as 0), addition is performed. If subtraction is performed, it is checked whether `sgn01` is negative. If `sgn01` is negative, the formula for calculating the temporary addition mantissa is: `mat_add_tmp = addin1 – addin0 – sticky`. If `sgn01` is not negative, the formula for calculating the temporary addition mantissa is: `mat_add_tmp = addin0 – addin1 – sticky`. In summary, the formula for calculating the temporary addition mantissa can be expressed as: `mat_add_tmp = sgn01 ? addin1 – addin0 – sticky : addin0 – addin1 – sticky`. If addition is performed, the formula for calculating the temporary addition mantissa is: `mat_add_tmp = addin1 + addin0`.

[0131] In one feasible implementation, the specific method for "determining the addition sign based on the target number of bits in the temporary addition mantissa" can be as follows: the value of mat_width_tmp*2+6-1 bits in the temporary addition mantissa is used as the addition sign. The formula for calculating the addition sign can be expressed as: sgn_add = mat_add_tmp[mat_width_tmp*2+6-1]; where sgn_add represents the addition sign, mat_add_tmp represents the temporary addition mantissa, and mat_width_tmp*2+6-1 is the target number of bits.

[0132] In one feasible implementation, the specific method for "determining the mantissa based on the addition sign and the temporary addition mantissa" can be as follows: when the addition sign is negative, subtract the temporary addition mantissa and the sticky bit to obtain the addition mantissa. When the addition sign is positive, use the temporary addition mantissa as the addition mantissa.

[0133] Based on the above technical means, the window state detection module divides different operation states according to the exponent difference, and the window selection module places the multiplication mantissa and the adjusted mantissa in different positions of the adder accordingly. The mantissa addition module then performs the corresponding addition or subtraction operation. This method can control the calculation window more precisely and improve the accuracy and efficiency of the operation.

[0134] In some embodiments, such as Figure 5 As shown, the floating-point adjustment module 3233 includes a leading zero prediction module 32331 and a normalization module 32332; the leading zero prediction module 32331 is used to determine the error of the mantissa of the addition; the normalization module 32332 is used to adjust the data format of the second addition exponent, the addition mantissa and the addition sign bit based on the error of the addition mantissa to obtain the target floating-point number.

[0135] The leading zero prediction module 32331 runs in parallel with the mantissa addition module and is used to calculate the number of leading zeros in the mantissa of the addition. The number of leading zeros refers to the number of consecutive zeros before the most significant bit. The number of leading zeros in the mantissa of the addition can be represented as lzc, which may have a 1-bit error and needs to be corrected in the normalization module. Specifically, the leading zero prediction module 32331 determines the most significant bit by judging the bit size of the two addends.

[0136] The normalization module 32332 is used to adjust the format of the calculated mantissa, second exponent, and sign bit to output a floating-point number according to the required format; it is also used to correct errors detected by the leading zero prediction module 32331. In some embodiments, the correction can be implemented by comparing the actual number of detected leading zeros with the output value to determine the error value; and then correcting the mantissa based on the error value. This application does not limit the specific format adjustment and error detection methods.

[0137] Based on the above technical means, the leading zero prediction module is used to quickly estimate the number of leading zeros in the mantissa of the addition, and the normalization module is used to adjust the exponent and mantissa according to the prediction result to meet the format requirements of the target floating-point number. This method can speed up the normalization process and reduce the calculation delay.

[0138] This disclosure provides a floating-point number processing method, which can be applied, for example, to a computer device equipped with a floating-point number processing unit. The structure and exemplary implementation of the floating-point number processing unit can be found in [reference needed]. Figures 3 to 6 The example shown. Figure 7 This is a schematic diagram illustrating the implementation flow of a floating-point number processing method provided in an embodiment of this disclosure, as shown below. Figure 7 As shown, the method includes the following steps 701 to 702: Step 701: Perform an addition operation on the exponents of the first floating-point number and the second floating-point number to obtain the first additive exponent, and unify the data format of the first additive exponent and the exponent of the third floating-point number.

[0139] In some implementations, the specific way to obtain the first floating-point number, the second floating-point number, and the third floating-point number can be: by using the source operand extraction module, the first floating-point number, the second floating-point number, and the third floating-point number are extracted sequentially from the first source operand, the second source operand, and the third source operand according to the agreed storage method.

[0140] For example, if the floating-point processing device supports mixed operations of floating-point numbers with FP32 and FP16 precisions, the bit widths corresponding to each precision are num0_width=32 and num1_width=16, the exponent bit widths are exp0_width=8 and exp1_width=5, and the mantissa bit widths are mat0_width=23 and mat1_width=10. The exponent width for intermediate floating-point formats is exp_width_tmp=8, and the mantissa width is mat_width_tmp=23. It is agreed that each source operand has a bit width of 32 bits, with FP32 type source operands stored in all 32 bits, and FP16 type source operands having their significant bits stored in the lower 16 bits of the 32 bits.

[0141] In implementation, each source operand corresponds to a source operand extraction module. Through the source operand extraction module corresponding to each source operand, the valid part is extracted from each input source operand according to the agreed storage method to obtain the floating-point number to be processed.

[0142] In some implementations, step 701 can be specifically implemented as follows: The exponent adjustment module determines the first floating-point number's exponent offset, the second floating-point number's exponent offset, the third floating-point number's exponent offset, and the intermediate format exponent offset; it performs addition on the first floating-point number's exponent and the second floating-point number's exponent to obtain a first additive exponent; it unifies the data format of the first additive exponent based on the first floating-point number's exponent offset, the second floating-point number's exponent offset, and the intermediate format exponent offset to obtain the unified first additive exponent; it unifies the data format of the third floating-point number's exponent based on the third floating-point number's exponent offset and the intermediate format exponent offset to obtain the unified third floating-point number's exponent; the intermediate format exponent offset is determined based on the maximum value of the exponent bit width among the first, second, and third floating-point numbers.

[0143] In one feasible implementation, the unified first additive exponent exp01 and the unified third floating-point exponent exp2 can be calculated through the above description of the exponent adjustment module 31.

[0144] Specifically, calculate the exponent offsets bias0, bias1, and bias2 for the three floating-point numbers. If a floating-point number is in FP32 format, the exponent offset is equal to 127 (2... 7 -1); if a floating-point number is in FP16 format, then the exponent offset is equal to 15 (2 4 -1). At this point, the exponent offset of the intermediate format is equal to 127. According to the formula exp01=exp0+exp1-bias0-bias1+127, the unified first additive exponent exp01 is obtained; according to the formula exp2=exp2-bias2+127, the unified third floating-point exponent exp2 is obtained.

[0145] It should be noted that by adding an offset to the actual exponent (such as an offset of 127 for single-precision floating-point numbers), all signed exponents can be converted to unsigned integers to remove the sign of the exponent, thereby achieving the purpose of unifying the data format and improving the efficiency of subsequent calculations.

[0146] Step 702: Based on the unified first addition exponent and the unified third floating-point exponent, determine the target floating-point number after performing multiplication and addition operations on the first floating-point number, the second floating-point number, and the third floating-point number.

[0147] In some implementations, step 702 can be specifically implemented as follows: using a multiply-accumulate operator in related technologies, based on the unified first addition exponent and the unified exponent of the third floating-point number, the target floating-point number after multiplying and accumulating the first floating-point number, the second floating-point number, and the third floating-point number is determined.

[0148] In some implementations, step 702 can be specifically implemented as follows: (The sentence is incomplete and requires more context to translate accurately.) Figure 5 The floating-point calculation module shown determines the target floating-point number after multiplying and adding the first, second, and third floating-point numbers, based on the unified first addition exponent and the unified third floating-point exponent.

[0149] In this embodiment of the disclosure, the exponent adjustment module can achieve the unification of exponent addition and data format in one step without the need for an additional format converter, thus reducing hardware costs. Compared with the operation in related technologies that requires format conversion through a format converter and then addition of two exponents through an exponent adder, the operation is simpler and the calculation speed is faster.

[0150] This disclosure provides a floating-point number processing method, applied to a computer device including a floating-point number processing apparatus. For example... Figure 8 As shown, the method includes the following steps 801 to 805: Step 801: Perform an addition operation on the exponents of the first floating-point number and the second floating-point number to obtain the first additive exponent, and unify the data format of the first additive exponent and the exponent of the third floating-point number.

[0151] Here, step 801 corresponds to step 701 mentioned above, and the specific implementation of step 701 can be referred to during implementation.

[0152] Step 802: Determine the exponent difference between the unified first addition exponent and the unified third floating-point exponent.

[0153] In one feasible implementation, the temporary exponent difference between the unified first addition exponent and the unified third floating-point exponent can be determined through the exponent subtraction module; the temporary exponent difference is then adjusted based on the number of zeros in the highest bit of the third floating-point number to obtain the exponent difference.

[0154] In some implementations, step 802 can be specifically implemented as follows: using the exponent subtraction module, a temporary exponent difference is determined based on the unified first addition exponent, the unified exponent of the third floating-point number, and a preset third bit threshold; if the width of the exponent of the third floating-point number is less than the exponent bit width of the intermediate format, the exponent difference is determined based on the temporary exponent difference and the number of second values ​​that the mantissa of the third floating-point number has before the first value; if the width of the exponent of the third floating-point number is greater than or equal to the exponent bit width of the intermediate format, the temporary exponent difference is used as the exponent difference.

[0155] In one feasible implementation, the specific method for "determining the temporary exponent difference based on the unified first additive exponent, the unified third floating-point exponent, and a preset third-digit threshold" can be as follows: First, subtract the unified first additive exponent from the unified third floating-point exponent, then add the result to the third-digit threshold to obtain the temporary exponent. The formula for calculating the temporary exponent difference can be: exp_diff_tmp = exp01 + exp_constant – exp2; where exp01 represents the first additive exponent, exp_constant represents the third-digit threshold, and exp2 represents the unified third floating-point exponent.

[0156] For example, the formula for calculating the third-digit threshold is: exp_constant = mat_width_tmp + 4. When the floating-point processing device supports mixed operations of FP32 and FP16 precision floating-point numbers, mat_width_tmp = 23, then the third-digit threshold is 27. In this case, the formula for calculating the temporary exponent difference can be: exp_diff_tmp = exp01 + 27 – exp2.

[0157] In one feasible implementation, the specific method for "determining the temporary exponent difference based on the unified first addition exponent, the unified third floating-point number exponent, and a preset third bit threshold" can be as follows: When the width of the third floating-point number exponent is less than the exponent width of the intermediate format, the temporary exponent difference is obtained by subtracting the number of second values ​​that the mantissa of the third floating-point number has before reaching the first value. In this case, the formula for calculating the exponent difference can be expressed as: exp_diff = exp_diff_tmp - src2_lzd. When the width of the third floating-point number exponent is greater than or equal to the exponent width of the intermediate format, the temporary exponent difference is used as the exponent difference. In this case, the formula for calculating the exponent difference can be expressed as: exp_diff = exp_diff_tmp. The number of second values ​​that the mantissa of the third floating-point number has before reaching the first value is detected by a leading zero detection module.

[0158] Step 803: Shift the mantissa of the third floating-point number based on the exponent difference to obtain the adjusted mantissa of the third floating-point number.

[0159] In one feasible implementation, the mantissa of the third floating-point number is expanded based on the total bit width of the calculation window of the mantissa addition module to obtain the expanded mantissa of the third floating-point number; the mantissa of the expanded third floating-point number is shifted based on the state of the multiplication-addition operation and the temporary exponent difference to obtain the adjusted mantissa of the third floating-point number.

[0160] In some implementations, the specific method of "expanding the mantissa of the third floating-point number based on the total bit width of the calculation window of the mantissa addition module to obtain the extended mantissa of the third floating-point number" can be: through the mantissa shift module, the mantissa of the third floating-point number is expanded based on the total bit width of the calculation window of the mantissa addition module to obtain the extended mantissa of the third floating-point number.

[0161] In one feasible implementation, the specific implementation of "extending the mantissa of the third floating-point number based on the total bit width of the calculation window of the mantissa addition module to obtain the extended mantissa of the third floating-point number" can be as follows: extend the mantissa of the third floating-point number upward by one bit to obtain the extended mantissa of the third floating-point number by one bit; extend the extended mantissa of the third floating-point number by one bit downward to the total bit width to obtain the extended mantissa of the third floating-point number.

[0162] In some implementations, the specific method for "shifting the mantissa of the extended third floating-point number based on the state of the multiplication-addition operation and the temporary exponent difference to obtain the mantissa of the adjusted third floating-point number" can be as follows: when the state of the multiplication-addition operation and the temporary exponent difference output by the window state detection module satisfy a first condition, the mantissa of the extended third floating-point number is shifted to the left according to the number of second values ​​that the mantissa of the third floating-point number has before it becomes a first value, to obtain the mantissa of the adjusted third floating-point number; the first condition is that the state of the multiplication-addition operation is a second state and the... If the temporary exponent difference is less than the second value; if the state of the multiplication-addition operation and the temporary exponent difference satisfy the second condition, the mantissa of the extended third floating-point number is taken as the mantissa of the adjusted third floating-point number; the second condition is that the state of the multiplication-addition operation is the first state and the temporary exponent difference is greater than or equal to the second value; if the state of the multiplication-addition operation and the temporary exponent difference do not satisfy the first condition and the second condition, the mantissa of the extended third floating-point number is right-shifted according to the mantissa of the extended third floating-point number to obtain the mantissa of the adjusted third floating-point number.

[0163] When the floating - point processing unit supports mixed operations of floating - point numbers with two precisions, FP32 and FP16, and mat_width_tmp = 23, then according to the formula for the total bit width mat_width_tmp * 4+7, the total bit width of the calculation window of the mantissa addition module is 99; according to the formula for the first - digit threshold mat_width_tmp + 3, the first - digit threshold is 26; according to the formula for the second - digit threshold mat_width_tmp * 3+7, the second - digit threshold is 76. In this case, the state of the multiply - add operation is as follows: State 1: 0>exp_diff; State 2: 26>exp_diff>=0; State 3: 76>exp_diff>=26; State 4: exp_diff>=76; where exp_diff represents the temporary exponent difference.

[0164] In a feasible implementation, when the state of the multiply - add operation is 26>exp_diff>=0 (the second state) and exp_diff_tmp (temporary exponent difference) is less than 0, shift ext_mat2 (the mantissa of the extended third floating - point number) to the left according to src2_lzd (the number of the second value before the mantissa of the third floating - point number becomes the first value) to obtain shf_mat2 (the adjusted mantissa of the third floating - point number); at this time, the calculation formula for shf_mat2 can be: shf_mat2 = ext_mat2<<src2_lzd. When the state of the multiply - add operation is 0>exp_diff (the first state) and exp_diff_tmp≥0, use ext_mat2 as shf_mat2; at this time, the calculation formula for shf_mat2 can be: shf_mat2 = ext_mat2. When the state of the multiply - add operation and the temporary exponent difference do not meet the above conditions, shift ext_mat2 to the right according to ext_mat2 to obtain shf_mat2; at this time, the calculation formula for shf_mat2 can be: shf_mat2 = ext_mat2>>ext_mat2.

[0165] Example, when the floating-point processing unit supports mixed operations of floating-point numbers with two precisions, FP32 and FP16, pad 75 (mat_width_tmp * 3 + 6) zeros at the lower bits of the 24-bit mat2 to obtain the 99-bit (mat_width_tmp * 4 + 7) ext_mat2; if exp_diff_tmp < 0 and the window state is state two, shf_mat2 = ext_mat2 << src2_lzd; if exp_diff_tmp ≥ 0 and the window state is state one, shf_mat2 = ext_mat2; otherwise, shf_mat2 = ext_mat2 >> ext_mat2.

[0166] Step 804: Perform a multiplication operation on the mantissa of the first floating-point number and the mantissa of the second floating-point number to obtain a multiplication mantissa.

[0167] In a feasible implementation manner, the specific implementation manner of step 804 can be: through the mantissa multiplication module, expand the mantissa of the first floating-point number and the mantissa of the second floating-point number according to the mantissa bit width of the intermediate format; perform a multiplication operation on the expanded mantissa of the first floating-point number and the expanded mantissa of the second floating-point number to obtain a multiplication mantissa.

[0168] When the floating-point processing unit supports mixed operations of floating-point numbers with two precisions, FP32 and FP16, mat_width_tmp = 23; then expand the mantissa of the first floating-point number and the mantissa of the second floating-point number according to the mantissa bit width of the intermediate format; that is, pad 13 zeros at the lower bits of the mantissa of the FP16 format floating-point number to make the mantissa up to 23 bits; if the exponent of the floating-point number is not 0, then execute mat = mat | (1 << 23) to expand the sign bit of the floating-point number; then, at this time, both the expanded first floating-point number and the expanded second floating-point number are 24 bits, and the multiplication mantissa after multiplication is 48 bits. In addition, the leading zero detection module can perform a leading zero detection on mat2 and output src2_lzd.

[0169] Step 805: Determine the target floating-point number based on the adjusted mantissa of the third floating-point number, the multiplication mantissa, the unified first addition exponent, and the exponent of the unified third floating-point number.

[0170] In a feasible implementation manner, the specific implementation manner of step 805 can be: based on the state of the multiply-add operation, select a second addition exponent from the unified first addition exponent and the exponent of the unified third floating-point number; perform an addition operation on the multiplication mantissa and the second addition exponent to obtain an addition mantissa and an addition sign; determine the target floating-point number based on the second addition exponent, the addition mantissa, and the addition sign.

[0171] In some implementations, step 805 can be achieved by the following steps 8051 to 8055: Step 8051: Detect the state of the multiplication-addition operation.

[0172] Step 8052: Determine the second addition exponent based on the state of the multiplication-addition operation, the unified first addition exponent, and the unified third floating-point exponent.

[0173] In some implementations, step 8052 can be specifically implemented as follows: when the multiplication-addition operation is in the first state, the exponent of the unified third floating-point number is used as a temporary addition exponent; when the multiplication-addition operation is in the second state, a temporary addition exponent is determined based on the unified first addition exponent and the third bit threshold; when the multiplication-addition operation is in the third or fourth state, the unified first addition exponent is used as a temporary addition exponent; the temporary addition exponent is adjusted based on the exponent offset of the temporary addition exponent and the exponent offset of the intermediate format to obtain the second addition exponent.

[0174] For example, if the window state is the first state, then set exp_add_tmp (temporary addition exponent) = exp2; if the multiplication-addition operation state is the second state, then set exp_add_tmp = exp01 (first addition exponent) + mat_width_tmp (mantissa width of intermediate format) + 4; if the window state is the third or fourth state, then set exp_add_tmp = exp01. If the output floating-point format is FP16, then exp_add (second addition exponent) = exp_add_tmp - 112 (2 7- 2 4 Otherwise, exp_add = exp_add_tmp.

[0175] Step 8053: Based on the state of the multiplication-addition operation, place the mantissa of the multiplication and the mantissa of the adjusted third floating-point number into the calculation window of the mantissa addition module.

[0176] In one feasible implementation, step 8053 can be implemented as follows: by selecting the window module, the mantissa of the multiplication is assigned to the first addend in the calculation window based on the state of the multiplication-addition operation, and the mantissa of the adjusted third floating-point number is assigned to the second addend in the calculation window based on the state of the multiplication operation, so as to place the mantissa of the multiplication and the mantissa of the adjusted third floating-point number in the calculation window of the mantissa addition module.

[0177] In some implementations, step 8053 can be specifically implemented as follows: when the multiplication-addition operation is in the first state, the second value is assigned to the first addend in the calculation window, and the first digit of the mantissa of the adjusted third floating-point number is truncated from the high digit and assigned to the second addend in the calculation window; when the multiplication-addition operation is in the second state, the second digit of the mantissa of the multiplication is truncated from the high digit and assigned to the first addend in the calculation window, and the first digit of the mantissa of the adjusted third floating-point number is truncated from the high digit and assigned to the second addend in the calculation window; when the multiplication-addition operation is in the third state, the mantissa of the multiplication is shifted left by three digits, and the fourth digit of the mantissa of the adjusted third floating-point number is truncated from the high digit and assigned to the second addend in the calculation window; when the multiplication-addition operation is in the fourth state, the mantissa of the multiplication is shifted left by three digits, and the second value is assigned to the second addend in the calculation window.

[0178] For example, when the floating-point processing device supports mixed operations of floating-point numbers with both FP32 and FP16 precision, the width of the adder can be calculated as 52 according to the formula mat_width_tmp*2+6. If the multiplication-addition operation is in the first state, then addin0=0, addin1=shf_mat2[98:48], and sticky=|mat01; if the multiplication-addition operation is in the second state, then ddin=mat01[47:23], addin1=shf_mat2[98:48], and sticky=|mat01[22:0]; if the multiplication-addition operation is in the third state, then addin0=mat01<<2, addin1=shf_mat2[72:23], and sticky=|shf_mat2[22:0]; if the multiplication-addition operation is in the fourth state, then addin0=mat01<<2, addin1=0, and if src2 is not equal to 0, then sticky=1, otherwise sticky=0. addin0 represents the first addend, addin1 represents the second addend, shf_mat2 represents the mantissa of the adjusted third floating-point number, and sticky represents the sticky bit.

[0179] Step 8054: Perform an addition operation on the mantissa of the multiplication and the mantissa of the adjusted third floating-point number in the calculation window to obtain the mantissa of the addition and the addition sign.

[0180] In some implementations, step 8054 can be specifically implemented as follows: determining a temporary sign based on the sign of the first floating-point number, the sign of the second floating-point number, and the sign of the third floating-point number; if the temporary sign is negative, performing subtraction on the first addend and the second addend to obtain the temporary addition mantissa; if the temporary sign is positive, performing addition on the first addend and the second addend to obtain the temporary addition mantissa; determining the addition sign based on the value of the target number of bits in the temporary addition mantissa; and determining the addition mantissa based on the addition sign and the temporary addition mantissa.

[0181] In one feasible implementation, the specific method for "determining a temporary symbol based on the sign of the first floating-point number, the sign of the second floating-point number, and the sign of the third floating-point number" can be: Perform an exponentiation operation on the sign of the first and second floating-point numbers, and then perform an exponentiation operation on the result of the exponentiation and the sign of the third floating-point number to obtain the temporary symbol. For example, sgn01 = sgn0^sgn1, sub = sgn01^sgn2; where sgn0 represents the sign of the first floating-point number, sgn1 represents the sign of the second floating-point number, sgn01 represents the result of the exponentiation operation, and sub represents the temporary symbol.

[0182] In one feasible implementation, if the temporary sign is negative, determine whether the result of the exponentiation is negative. If the result is negative, subtract the second addend, the first addend, and the sticky bit in sequence to obtain the temporary addition mantissa. If the result is not negative, subtract the first addend, the second addend, and the sticky bit in sequence to obtain the temporary addition mantissa.

[0183] For example, if `sub` is negative (a negative number can be represented as 1), subtraction is performed; if `sub` is 0, addition is performed. If subtraction is performed, it is checked whether `sgn01` is negative. If `sgn01` is negative, the formula for calculating the temporary addition mantissa is: `mat_add_tmp = addin1 – addin0 – sticky`. If `sgn01` is not negative, the formula for calculating the temporary addition mantissa is: `mat_add_tmp = addin0 – addin1 – sticky`. In summary, the formula for calculating the temporary addition mantissa can be expressed as: `mat_add_tmp = sgn01 ? addin1 – addin0 – sticky : addin0 – addin1 – sticky`.

[0184] In one feasible implementation, the specific method for "determining the addition sign based on the target number of bits in the temporary addition mantissa" can be as follows: the value of mat_width_tmp*2+6-1 bits in the temporary addition mantissa is used as the addition sign. The formula for calculating the addition sign can be expressed as: sgn_add = mat_add_tmp[mat_width_tmp*2+6-1]; where sgn_add represents the addition sign, mat_add_tmp represents the temporary addition mantissa, and mat_width_tmp*2+6-1 is the target number of bits.

[0185] In one feasible implementation, the specific method for "determining the mantissa based on the addition sign and the temporary addition mantissa" can be as follows: when the addition sign is negative, subtract the temporary addition mantissa and the sticky bit to obtain the addition mantissa. When the addition sign is an integer, use the temporary addition mantissa as the addition mantissa.

[0186] For example, the specific implementation of adding or subtracting addin0 (the first addend) and addin1 (the second addend) based on the sign bit using the mantissa addition module is as follows: 1. Calculate sgn01 = sgn0^sgn1; 2. Calculate sub = sgn01^sgn2. If sub = 1, perform subtraction; otherwise, perform addition. 3. If subtraction is performed, then mat_add_tmp = sgn01?addin1–addin0-sticky:addin0–addin1-sticky; 4. If addition is performed, the temporary addition mantissa is mat_add_tmp = addin1 + addin0; 5. Set the addition symbol to sgn_add=mat_add_tmp

[51] ; 6. Set the addition mantissa to mat_add=sgn_add?mat_add_tmp-sticky:mat_add_tmp.

[0187] Step 8055: Determine the target floating-point number based on the second addition exponent, the addition mantissa, and the addition sign.

[0188] In some implementations, the floating-point adjustment module includes a leading zero prediction module and a normalization module. Step 8055 can be specifically implemented as follows: the leading zero prediction module determines the error of the mantissa; the normalization module adjusts the data format of the second addition exponent, the mantissa, and the sign bit based on the error of the mantissa to obtain the target floating-point number. The final target floating-point number has the second addition exponent as its exponent, the mantissa as the number of addition bits, and the sign bit as the addition sign bit.

[0189] In one feasible implementation, while the mantissa addition module determines the mantissa based on the first and second addends, the leading zero prediction module sequentially judges the bit size of the first and second addends to determine the most significant bit, so as to determine whether there is an error in the mantissa addition.

[0190] In this embodiment of the disclosure, the exponent adjustment module can achieve the unification of exponent addition and data format in one step without the need for an additional format converter, thus reducing hardware costs. Compared with the operation in related technologies that requires format conversion through a format converter and then addition of two exponents through an exponent adder, the operation is simpler and the calculation speed is faster.

[0191] The following describes the application of the floating-point number processing method provided in the embodiments of this disclosure in real-world scenarios.

[0192] This disclosure proposes a novel mixed-precision floating-point multiply-accumulate module design, which improves circuit time utilization efficiency and reduces algorithm execution time. For example... Figure 9 As shown, the hardware structure of the mixed-precision floating-point multiply-add module includes a source operand extraction module, a leading zero detection module, an exponent adjustment module, an addition exponent calculation module, an exponent subtraction module, a window state detection module, a mantissa multiplication module, a mantissa shift module, a window selection module, a mantissa addition module, a leading zero prediction module, and a normalization module.

[0193] The functions of each module will be introduced below in the context of floating-point mixed arithmetic: Suppose that the multiply-accumulate module to be designed supports mixed operations on floating-point numbers of x precisions. The bit widths corresponding to each precision of the floating-point number are num0_width, num1_width, ..., numx_width; the exponent bit widths corresponding to each precision of the floating-point number are exp0_width, exp1_width, ..., expx_width; and the mantissa bit widths corresponding to each precision of the floating-point number are mat0_width, mat1_width, ..., matx_width.

[0194] The maximum value among the exponent widths exp0_width, exp1_width, ..., expx_width is selected as the exponent width for the intermediate format. Assume the exponent width for the intermediate format is exp_width_tmp. Similarly, the maximum value among the mantissa widths mat0_width, mat1_width, ..., matx_width is selected as the exponent width for the intermediate format. Assume the exponent width for the intermediate format is mat_width_tmp.

[0195] Suppose the multiply-accumulate module to be designed is used to calculate the multiplication and addition of three floating-point numbers. These three floating-point numbers are src0, src1, and src2, and the calculation method is defined as src0 * src1 + src2. Correspondingly, the sign bits of these three floating-point numbers are named sgn0, sgn1, and sgn2, the exponents are named exp0, exp1, and exp2, and the mantissas are named mat0, mat1, and mat2.

[0196] Figure 9 The three source operand extraction modules are used to extract floating-point numbers in a specified format from each input source operand according to a pre-defined storage method. To ensure a consistent floating-point data format, floating-point numbers are input according to a pre-defined storage method. Therefore, before computation, the original floating-point numbers need to be obtained according to this pre-defined storage method. This pre-defined storage method is based on the maximum floating-point bit width, storing the lower-bit floating-point numbers in the high-order bits, low-order bits, or a distributed storage method. For example, if the pre-defined storage method stores the source operands in the low-order bits, then the floating-point bit width of each source operand is 32 bits. In this case, FP32 type source operands are stored in all 32 bits, and FP16 type source operands are stored in the lower 16 bits of the 32 bits according to the pre-defined storage method.

[0197] Figure 9 The exponent adjustment module is used to adjust exp0 and exp1 into an intermediate format, add the two adjusted exponents to obtain exp01, and adjust the exponent offset of exp2. Since the exponent formats of the three floating-point numbers are different, an intermediate exponent format is selected to unify the exponent formats of the three floating-point numbers, facilitating subsequent calculations. The intermediate exponent format is the format of the maximum value of the exponent bit width.

[0198] The specific implementation method of the index adjustment module is as follows: 1. Calculate the exponents exp0, exp1, exp2, and the exponent offset for the intermediate format, and name them bias0, bias1, bias2, and bias_tmp, respectively. The method for calculating the exponent offset is: 2 raised to the power of the exponent width minus 1. For example, taking the intermediate exponent format, bias0 = 2. exp0_width -1, bias1=2 exp1_width -1, bias_tmp = 2 exp_width_tmp -1.

[0199] 2. Calculate exp01.

[0200] The formula for calculating exp01 is: exp01 = exp0 + exp1 - bias0 - bias1 + bias_tmp.

[0201] 3. Adjust the value of exp2. The formula for adjusting exp2 is: exp2 = exp2 - bias2 + bias_tmp.

[0202] It should be noted that the calculation formulas for exp01 and exp2 are primarily used to unify exp01 and exp2 into a unified format, achieving exponent alignment. If the exponents are already the same, then exponent offset is not necessary.

[0203] Furthermore, related technologies require format conversion before addition, but this application can directly obtain the result of exponent addition through the calculation formula of exp01 without separate format conversion, resulting in a faster calculation speed.

[0204] Figure 9 The mantissa multiplication module is used to calculate the result mat01, which is the result of multiplying the mantissas of src0 and src1.

[0205] Specifically, the mantissa lengths of src0 and src1 are extended to the maximum mantissa width, mat_width_tmp. The extension method involves padding the lower bits of the mantissa with 0s, and then extending the extended mantissas of src0 and src1 by one bit upwards. If the floating-point number is denormalized, the highest extended bit is set to 1; otherwise, it is set to 0. The two extended mantissas are then multiplied to obtain the mantissa multiplication result, mat01.

[0206] The reason for extending the mantissa by one bit is that the mantissa of a floating-point number is generally displayed as 23 bits, but it hides one bit. Extending it by one bit brings this hidden bit to the surface. The rule for extending the mantissa by one bit is that if all exponents are 0, the extended value is 0; otherwise, it is 1.

[0207] Figure 9The leading zero detection module in the code is used to detect the number of 0s in the most significant bit of `mat2`. Assume the output of this module is `src2_lzd`. If there are `src2_lzd_tmp` 0s in the most significant bit of `mat2`, and if `src2` is a denormalized number, then the output of this module is `src2_lzd = src2_lzd_tmp + 1`; if `src2` is not a denormalized number, then the output is `src2_lzd = 0`. If `mat2` is all 0s, this module can output any value.

[0208] Figure 9 The exponential subtraction module in the code is used to calculate the difference between exp01 and exp2. The output of this module can be represented as exp_diff. The specific implementation of this module is as follows: 1. Set a constant exp_constant equal to mat_width_tmp + 4.

[0209] 2. Calculate a temporary intermediate result: exp_diff_tmp = exp01 + exp_constant – exp2.

[0210] 3. Calculate exp_diff. When the exponent width of src2 is less than the exponent bit width of the intermediate format, exp_diff = exp_diff_tmp - src2_lzd; otherwise, exp_diff = exp_diff_tmp.

[0211] Figure 9 The window state detection module is used to detect the state of multiplication-accumulation operations. Multiplication-accumulation operations can be divided into the following four states: 1. State 1: 0>exp_diff.

[0212] 2. State 2: (mat_width_tmp+3)>exp_diff>=0.

[0213] 3. State 3: (mat_width_tmp*3+7)>exp_diff>=(mat_width_tmp+3).

[0214] 4. State 4: exp_diff>=(mat_width_tmp*3+7).

[0215] Figure 9 The mantissa shifting module in the code is used to right-shift mat2 to obtain the result shf_mat2. The specific implementation method of this module is as follows: 1. Extend the mantissa of src2 by 1 bit. If src2 is a denormalized number, set the highest bit of the extended number to 1; otherwise, set it to 0. The extended mantissa can be represented as ext_mat2_tmp.

[0216] 2. Extend ext_mat2_tmp downwards to obtain ext_mat2, with an extension bit width of ext_width = mat_width_tmp * 3 + 6. Set all downward extension positions to 0. After extension, the total bit width is mat_width_tmp * 4 + 7 bits.

[0217] 3. If exp_diff_tmp < 0, and the multiplication-addition operation is detected as state two, then shf_mat2 = ext_mat2 < <src2_lzd。

[0218] 4. If the situation described in point 3 does not occur, and the window state is state one, then shf_mat2 = ext_mat2.

[0219] 5. If the situations described in points 3 and 4 do not occur, then shf_mat2 = ext_mat2 >> ext_mat2.

[0220] Figure 9 The window selection module is used to place mat01 and shf_mat2 into appropriate positions within the adder calculation window based on the window state. Assuming the adder width is mat_width_tmp*2+6, the specific implementation of this module is as follows: 1. If the window state is state one, set addin0 to 0, and shf_mat2 will truncate mat_width_tmp*2+5 bits from the highest bit and assign them to addin1, i.e., addin1 = shf_mat2[mat_width_tmp*4+6: mat_width_tmp*2+2]. If mat01 is not equal to 0, set sticky=1; otherwise, set sticky=0.

[0221] 2. If the window is in state two, extract mat_width_tmp+2 from mat01 from high to low and assign it to addin0, that is, addin0=mat01[mat_width_tmp*2+1:mat_width_tmp]. The assignment method of addin1 is the same as in state one. If mat01[mat_width_tmp-1:0] is not equal to 0, then set sticky=1, otherwise set sticky=0.

[0222] 3. If the window state is state three, then set addin0=mat01<<2, addin1=shf_mat2[mat_width_tmp*3+3:mat_width_tmp], and if shf_mat2[mat_width_tmp-1:0] is not equal to 0, then set sticky=1, otherwise set sticky=0.

[0223] 4. If the window state is state four, set addin0=mat01<<2 and addin1=0. If ext_mat2_tmp is not equal to 0, set sticky=1; otherwise, set sticky=0.

[0224] Figure 6 The results of right-shifting mat2, the relative positions of the two summed mantissas, the window width, and the window selection are depicted under four window states.

[0225] Figure 9 The mantissa addition module in the calculation window is used to process addition or subtraction operations between two addends, thereby obtaining the mantissa and the addition sign. There are many specific methods for handling addition and subtraction operations; the following example illustrates this.

[0226] 1. Calculate sgn01 = sgn0^sgn1.

[0227] 2. Calculate sub = sgn01^sgn2. If sub = 1, perform subtraction; otherwise, perform addition.

[0228] 3. If subtraction is performed, then mat_add_tmp = sgn01 ? addin1–addin0-sticky: addin0–addin1-sticky.

[0229] 4. If addition is performed, then mat_add_tmp = addin1 + addin0.

[0230] 5. Set the sign of the addition and subtraction results to sgn_add = mat_add_tmp[mat_width_tmp*2+6-1].

[0231] 6. Set the last digit of the addition / subtraction result to mat_add = sgn_add ? -mat_add_tmp-sticky : mat_add_tmp.

[0232] Figure 9 The addition exponent calculator in the module is used to select the addition exponent exp_add based on the window state. The specific implementation method of this module is as follows: 1. If the window state is state one, then set exp_add_tmp = exp2.

[0233] 2. If the window is in state two, then set exp_add_tmp = exp01 + mat_width_tmp + 4.

[0234] 3. If the window is in state three or state four, then set exp_add_tmp = exp01.

[0235] 4. Assuming the exponent width corresponding to the floating-point format of the output result is expd_width, set exp_add_bias = 2expd_width - 1.

[0236] 5. Set exp_add = exp_add_tmp - bias_tmp + exp_add_bias.

[0237] Figure 9 The leading zero prediction module in the middle calculates the number of leading zeros in the mantissa addition result mat_add in parallel with the mantissa addition module. It is calculated as lzc, which may have an error of 1 bit, and needs to be corrected in the normalization module. Figure 9 The normalization module is used to adjust the format of the calculated mantissa, exponent, and sign of addition, and output the result in the required floating-point format.

[0238] The floating-point number processing method provided in this embodiment will be described below using mixed operations of floating-point numbers with two precisions, FP32 and FP16.

[0239] Assume the multiply-accumulate module to be designed supports mixed operations of floating-point numbers with both FP32 and FP16 precisions. The bit widths for each precision are num0_width=32 and num1_width=16, the exponent bit widths are exp0_width=8 and exp1_width=5, and the mantissa bit widths are mat0_width=23 and mat1_width=10. The exponent width for intermediate floating-point formats is exp_width_tmp=8, and the mantissa width is mat_width_tmp=23.

[0240] Each source operand is defined as having a 32-bit width, with FP32 type source operands stored within all 32 bits, and FP16 type source operands storing the valid bits in the lower 16 bits of the 32 bits. Three source operand extraction modules extract the valid portion of each input source operand based on its data type.

[0241] The exponent adjustment module calculates exp01 and the processed exp2 according to the above scheme description. First, it calculates the exponent offsets bias0, bias1, and bias2 of the three source operands. If the input source operand is detected as FP32 format, the exponent offset equals 127 (2^7 - 1); otherwise, the exponent offset equals 15 (2^4 - 1). The exponent offset bias_tmp for intermediate format floating-point numbers is set to 127. The calculation follows: exp01=exp0+exp1-bias0-bias1+127 exp2 = exp2 - bias2 + 127 For the source operand in FP16 format, padded with 13 zeros at the least significant bit to a total of 23 bits. Then, the exponent of the source operand is checked. If the exponent is not zero, the following operations are performed: mat = mat | (1 << 23) After the mantissa multiplication module extends the mantissas of the three source operands as described above, it multiplies the extended mat0 and mat1 to obtain the 48-bit mat01. The leading zero detection module then performs leading zero detection on mat2 and outputs src2_lzd.

[0242] The exponential subtraction module calculates the difference between exp01 and exp2, exp_diff_tmp, according to the formula exp_diff_tmp = exp01–exp2+27.

[0243] If src2 is in FP32 format, then exp_diff equals exp_diff_tmp; otherwise (if the exponent width is less than that of the intermediate format), it is calculated using the formula exp_diff = exp_diff_tmp – src2_lzd.

[0244] The window state detection module classifies any multiplication-addition operation into the following four states based on the following formula: First state: 0 > exp_diff; Second state: 26>exp_diff>=0; Third state: 76>exp_diff>=26; Fourth state: exp_diff>=76.

[0245] The mantissa shift module shifts mat2 to obtain shf_mat2 according to the following method. Specifically, mat2 with 24 extended bits is padded with 75 zeros at the low bits to obtain ext_mat2 with 99 bits; if exp_diff_tmp < 0 and the window state is detected as state two, then shf_mat2 = ext_mat2 << src2_lzd; otherwise, if the window state is state one, then shf_mat2 = ext_mat2; otherwise, shf_mat2 = ext_mat2 >> ext_mat2.

[0246] It is stipulated that the width of the adder (computing window) is 52 bits, and the window selection module sets addin0, addin1, and sticky according to the following method: First state: addin0 = 0, addin1 = shf_mat2[98:48], sticky = |mat01; Second state: addin = mat01[47:23], addin1 = shf_mat2[98:48], sticky = |mat01[22:0]; Third state: addin0 = mat01 << 2, addin1 = shf_mat2[72:23], sticky = |shf_mat2[22:0] Fourth state: addin0 = mat01 << 2, addin1 = 0; if src2 is not equal to 0, then sticky = 1, otherwise sticky = 0.

[0247] The mantissa addition module adds or subtracts addin0 and addin1 according to the sign bits to obtain the addition mantissa and the addition sign. The specific method is as follows: 1. Calculate sgn01 = sgn0 ^ sgn1; 2. Calculate sub = sgn01 ^ sgn2, if sub = 1, then perform subtraction, otherwise perform addition; 3. If subtraction is performed, then mat_add_tmp = sgn01? addin1 – addin0 – sticky: addin0 – addin1 – sticky; 4. If addition is performed, then mat_add_tmp = addin1 + addin0; 5. Set the sign of the addition and subtraction result as sgn_add = mat_add_tmp

[51] ; 6. Set the last digit of the addition / subtraction result to mat_add = sgn_add ? -mat_add_tmp-sticky : mat_add_tmp.

[0248] The addition exponent calculator selects the addition exponent exp_add according to the window status using the following methods: Specifically, 1. If the window state is in the first state, then set exp_add_tmp = exp2 2. If the window state is the second state, then set exp_add_tmp = exp01 + 27 3. If the window is in the third or fourth state, then set exp_add_tmp = exp01 4. Assuming the output result is in FP16 floating-point format, then exp_add = exp_add_tmp - 112; otherwise, exp_add = exp_add_tmp. The leading zero prediction module predicts the leading zero of the mantissa of the addition based on addin0, addin1, and sub, and calculates it as lzc. There may be a 1-bit error, which needs to be corrected in the normalization module.

[0249] The calculated lzc, mat_add, syn_add, and exp_add are fed into the normalization module, and the results are adjusted to the required floating-point number format for output.

[0250] It should be noted that the floating-point processing apparatus provided in this disclosure includes at least the following innovative features: 1. This embodiment adds a leading zero detection module for counting the number of leading zeros in the mantissa of the source operand, in order to support the calculation of denormalized numbers under mixed precision; 2. The embodiments of this disclosure include a window state detection module and a window selection module, which shorten the width of the calculation window in the algorithm, saving hardware resource consumption and calculation time; 3. The addition exponent calculation module used in this embodiment of the disclosure in conjunction with the window state detection module and the window selection module; 4. Overall design of the floating-point processing device provided in the embodiments of this disclosure.

[0251] It should be noted that the floating-point processing device provided in this disclosure embodiment has at least the following technical effects: 1. This embodiment of the disclosure does not require a format conversion module for the source operands to calculate mixed-precision floating-point multiplication and addition operations; 2. The present invention changes the original serial steps of multiplication followed by exponent alignment shift to a parallel steps of multiplication and exponent alignment shift, thereby reducing the time required for mantissa multiplication and addition operations.

[0252] This disclosure provides a computer device including a memory and a processor. The memory stores a computer program that can run on the processor. When the processor executes the program, it implements some or all of the steps in the above-described method.

[0253] This disclosure provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements some or all of the steps in the above-described method. The computer-readable storage medium may be transient or non-transient.

[0254] This disclosure provides a computer program including computer-readable code, wherein when the computer-readable code is executed in a computer device, a processor in the computer device performs some or all of the steps in the above-described method.

[0255] This disclosure provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, it implements some or all of the steps in the above-described method. This computer program product can be implemented specifically through hardware, software, or a combination thereof. In some embodiments, the computer program product is specifically embodied as a computer storage medium; in other embodiments, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0256] It should be noted that the descriptions of the various embodiments above tend to emphasize the differences between them, while their similarities or commonalities can be referenced interchangeably. The descriptions of the above embodiments of the device, storage medium, computer program, and computer program product are similar to the descriptions of the above method embodiments and have similar beneficial effects. For technical details not disclosed in the embodiments of the device, storage medium, computer program, and computer program product of this disclosure, please refer to the descriptions of the method embodiments of this disclosure for understanding.

[0257] It should be noted that, Figure 10 This is a schematic diagram of a hardware entity of a computer device in an embodiment of this disclosure, such as... Figure 10 As shown, the hardware entity of the computer device 1000 includes: a processor 1001, a communication interface 1002, and a memory 1003, wherein: Processor 1001 typically controls the overall operation of computer device 1000.

[0258] The communication interface 1002 enables computer devices to communicate with other terminals or servers via a network.

[0259] The memory 1003 is configured to store instructions and applications executable by the processor 1001, and can also cache data to be processed or already processed (e.g., image data, audio data, voice communication data, and video communication data) in the processor 1001 and various modules in the computer device 1000. It can be implemented using flash memory or random access memory (RAM). Data transfer between the processor 1001, the communication interface 1002, and the memory 1003 can be performed via bus 1004.

[0260] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above embodiments of this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0261] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0262] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0263] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0264] In addition, each functional unit in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0265] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0266] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, or the part that contributes to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, magnetic disks, or optical disks.

[0267] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A floating-point number processing device, characterized in that, The floating-point processing device includes: an exponent adjustment module and a floating-point calculation module; The exponent adjustment module is used to perform an addition operation on the exponent of the first floating-point number and the exponent of the second floating-point number to obtain a first additive exponent, and to unify the data format of the first additive exponent and the exponent of the third floating-point number. The floating-point calculation module is used to determine the target floating-point number after performing multiplication and addition operations on the first floating-point number, the second floating-point number, and the third floating-point number based on the unified first addition exponent and the unified exponent of the third floating-point number.

2. The floating-point processing device according to claim 1, characterized in that, The exponent adjustment module is specifically used to determine the exponent offset of the first floating-point number, the exponent offset of the second floating-point number, the exponent offset of the third floating-point number, and the exponent offset of the intermediate format; perform addition on the exponents of the first floating-point number and the second floating-point number to obtain a first additive exponent; unify the data format of the first additive exponent based on the exponent offsets of the first floating-point number, the second floating-point number, and the intermediate format exponent offset to obtain the unified first additive exponent; unify the data format of the third floating-point number based on the exponent offset of the third floating-point number and the intermediate format exponent offset to obtain the unified third floating-point number exponent; the exponent offset of the intermediate format is determined based on the maximum value of the exponent bit width among the first floating-point number, the second floating-point number, and the third floating-point number.

3. The floating-point processing device according to claim 1, characterized in that, The floating-point calculation module includes: a mantissa adjustment module, a mantissa multiplication module, and a floating-point addition module; The mantissa adjustment module is used to adjust the mantissa of the third floating-point number based on the unified first addition exponent and the unified exponent of the third floating-point number, so as to obtain the mantissa of the adjusted third floating-point number. The mantissa multiplication module is used to perform multiplication operations on the mantissa of the first floating-point number and the mantissa of the second floating-point number to obtain the multiplication mantissa; The floating-point addition module is used to determine the target floating-point number based on the mantissa of the adjusted third floating-point number and the mantissa of the multiplication.

4. The floating-point processing device according to claim 3, characterized in that, The mantissa adjustment module includes: an exponent subtraction module and a mantissa shift module; The exponent subtraction module is used to determine the exponent difference between the unified first addition exponent and the unified third floating-point exponent. The mantissa shifting module is used to shift the mantissa of the third floating-point number based on the exponent difference to obtain the mantissa of the adjusted third floating-point number.

5. The floating-point processing device according to claim 4, characterized in that, The exponent subtraction module is specifically used to determine a temporary exponent difference based on the unified first addition exponent, the unified third floating-point exponent, and a preset third bit threshold. When the width of the exponent of the third floating-point number is less than the exponent width of the intermediate format, the exponent difference is determined based on the temporary exponent difference and the number of second values ​​that the mantissa of the third floating-point number has before becoming the first value. If the width of the exponent of the third floating-point number is greater than or equal to the exponent width of the intermediate format, the temporary exponent difference shall be used as the exponent difference.

6. The floating-point processing apparatus according to claim 3, characterized in that, The floating-point addition module includes: an addition exponent calculation module, an addition mantissa calculation module, and a floating-point adjustment module; The addition exponent calculation module is used to determine the second addition exponent based on the state of the multiplication-addition operation, the unified first addition exponent, and the unified third floating-point exponent. The addition mantissa calculation module is used to determine the addition mantissa and the addition sign bit based on the mantissa of the adjusted third floating-point number and the multiplication mantissa; The floating-point adjustment module is used to determine the target floating-point number based on the second addition exponent, the addition mantissa, and the addition sign bit.

7. The floating-point processing apparatus according to claim 6, characterized in that, The state of the multiply-add operation includes at least one of the following: First state: The difference between the unified first additive exponent and the unified third floating-point exponent is less than the second value; Second state: The exponent difference is greater than or equal to the second value and less than the first digit threshold; the first digit threshold indicates that the mantissa of the multiplication and the mantissa of the adjusted third floating-point number completely overlap in the position of the calculation window; Third state: The exponent difference is greater than or equal to the first bit threshold and less than the second bit threshold; the second bit threshold indicates that the mantissa of the multiplication and the mantissa of the adjusted third floating-point number do not overlap in the position of the calculation window, and the position of the mantissa of the multiplication is before the position of the mantissa of the adjusted third floating-point number; Fourth state: The exponential difference is greater than or equal to the second bit threshold.

8. The floating-point processing apparatus according to claim 7, characterized in that, The addition exponent calculation module is specifically used as follows: when the multiplication-addition operation is in the first state, the exponent of the unified third floating-point number is used as a temporary addition exponent; when the multiplication-addition operation is in the second state, a temporary addition exponent is determined based on the unified first addition exponent and the third bit threshold; when the multiplication-addition operation is in the third or fourth state, the unified first addition exponent is used as a temporary addition exponent; and the temporary addition exponent is adjusted based on the exponent offset of the temporary addition exponent and the exponent offset of the intermediate format to obtain the second addition exponent.

9. The floating-point processing apparatus according to claim 6, characterized in that, The addition mantissa calculation module includes: a window state detection module, a window selection module, and a mantissa addition module; The window state detection module is used to detect the state of the multiplication-accumulation operation; The window selection module is used to place the mantissa of the multiplication and the mantissa of the adjusted third floating-point number into the calculation window of the mantissa addition module based on the state of the multiplication-addition operation. The mantissa addition module is used to perform addition operations on the mantissa of the multiplication and the mantissa of the adjusted third floating-point number in the calculation window to obtain the addition mantissa and the addition sign bit.

10. The floating-point processing apparatus according to claim 9, characterized in that, The mantissa shifting module is specifically used to expand the mantissa of the third floating-point number based on the total bit width of the calculation window of the mantissa addition module to obtain the mantissa of the expanded third floating-point number; when the state of the multiplication-addition operation output by the window state detection module and the difference of the temporary exponent satisfy the first condition, the mantissa of the expanded third floating-point number is shifted to the left according to the number of second values ​​that the mantissa of the third floating-point number had before it was the first value, to obtain the mantissa of the adjusted third floating-point number; the first condition is that the state of the multiplication-addition operation is the second state and the temporary exponent... If the difference is less than the second value; if the state of the multiplication-addition operation and the temporary exponent difference satisfy the second condition, the mantissa of the extended third floating-point number is taken as the mantissa of the adjusted third floating-point number; the second condition is that the state of the multiplication-addition operation is the first state and the temporary exponent difference is greater than or equal to the second value; if the state of the multiplication-addition operation and the temporary exponent difference do not satisfy the first condition and the second condition, the mantissa of the extended third floating-point number is shifted to the right according to the mantissa of the extended third floating-point number to obtain the mantissa of the adjusted third floating-point number.

11. The floating-point processing apparatus according to claim 9, characterized in that, The window selection module is specifically used as follows: when the multiplication-addition operation is in the first state, it assigns the second value to the first addend in the calculation window, and truncates the first digit of the mantissa of the adjusted third floating-point number from the high digit downwards and assigns it to the second addend in the calculation window; when the multiplication-addition operation is in the second state, it truncates the second digit of the mantissa of the multiplication from the high digit downwards and assigns it to the first addend in the calculation window, and truncates the first digit of the mantissa of the adjusted third floating-point number from the high digit downwards and assigns it to the second addend in the calculation window; when the multiplication-addition operation is in the third state, it shifts the mantissa of the multiplication to the left by three digits and assigns it to the first addend in the calculation window, and truncates the fourth digit of the mantissa of the adjusted third floating-point number from the high digit downwards and assigns it to the second addend in the calculation window; when the multiplication-addition operation is in the fourth state, it shifts the mantissa of the multiplication to the left by three digits and assigns it to the first addend in the calculation window, and assigns the second value to the second addend in the calculation window.

12. The floating-point processing apparatus according to claim 6, characterized in that, The addition mantissa calculation module is specifically used to determine a temporary sign based on the sign of the first floating-point number, the sign of the second floating-point number, and the sign of the third floating-point number; and when the temporary sign is negative, to perform subtraction on the first addend and the second addend to obtain the temporary addition mantissa. When the temporary sign is positive, the first addend and the second addend are added to obtain the temporary addition mantissa; The addition sign is determined based on the value of the target number of digits in the temporary addition mantissa; The addition mantissa is determined based on the addition sign and the temporary addition mantissa.

13. The floating-point processing apparatus according to claim 6, characterized in that, The floating-point adjustment module includes a leading zero prediction module and a normalization module; The leading zero prediction module is used to determine the error of the addition mantissa; The normalization module is used to adjust the data format of the second addition exponent, the addition mantissa, and the addition sign bit based on the error of the addition mantissa to obtain the target floating-point number.

14. The floating-point processing apparatus according to claim 4, characterized in that, The floating-point processing device further includes: a leading zero detection module; The leading zero detection module is used to detect the number of second values ​​that the mantissa of the third floating-point number has before it becomes the first value, so as to assist the exponent subtraction module in determining the exponent difference.

15. The floating-point processing apparatus according to any one of claims 1 to 14, characterized in that, The floating-point processing device further includes: a source operand extraction module; The source operand extraction module is used to extract the floating-point number corresponding to each input source operand according to a preset storage method.

16. The floating-point processing apparatus according to claim 4, characterized in that, The mantissa shift module runs in parallel with the mantissa multiplication module.

17. A method for determining floating-point numbers, characterized in that, The method for determining floating-point numbers includes: The first additive exponent is obtained by adding the exponents of the first and second floating-point numbers, and the data formats of the first additive exponent and the exponent of the third floating-point number are unified. Based on the unified first addition exponent and the unified third floating-point exponent, the target floating-point number is determined after performing multiplication and addition operations on the first floating-point number, the second floating-point number, and the third floating-point number.

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