Branch instruction block execution method and related apparatus

Abstract

The application provides a branch instruction block execution method and related equipment, which executes an initialization branch condition instruction; executes a target jump instruction and a regular instruction flow; executes a reading branch variable instruction to write two branch variables in a target storage interval into a first source register and a second source register corresponding to a branch instruction respectively; executes a modification branch variable instruction to adjust the branch variable in the first source register or the branch variable in the second source register; and executes the branch instruction in combination with the branch variable in the first source register and the branch variable in the second source register. Before the first source register and the second source register are modified, reliable branch variables are read from the target storage interval, so that the modified branch variables and the number of cycles of the branch instruction are matched, the branch variables in the first source register and the second source register are reliable, and the controllability of the branch instruction jump is guaranteed.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of processors, in particular to a branch instruction block execution method and related device. BACKGROUND

[0002] With the rapid development of artificial intelligence and high-performance computing, processors face higher parallel computing demands. VLIW (Very Long Instruction Word) architecture is widely used in special-purpose processors due to its high parallelism and simple hardware implementation. VLIW architecture is an explicit parallel instruction computing architecture that packs multiple instructions that can be executed in parallel into a very long instruction word. Unlike traditional superscalar processors, VLIW architecture transfers the complexity of instruction scheduling from hardware to the compiler, thereby simplifying the design of the processor.

[0003] RISC-V is an open and free instruction set architecture (ISA) with strong scalability and flexibility, and has attracted the attention and participation of many companies and academia. In the RISC-V instruction set, branch instructions are important tools for changing program execution flow according to specific conditions. These instructions determine whether to jump to the target address by comparing the values of two registers, thereby implementing conditional control structures such as if-else statements, while loops, etc.

[0004] The controllability of branch instruction jumps directly affects the execution of instructions and has become one of the problems that technicians in the field are concerned about. SUMMARY

[0005] The purpose of the present application is to provide a branch instruction block execution method and related device to improve the above problems.

[0006] To achieve the above purpose, the technical solutions adopted by the embodiments of the present application are as follows:

[0007] In a first aspect, the embodiments of the present application provide a branch instruction block execution method, which comprises:

[0008] executing an initialization branch condition instruction, comprising: randomly generating two initial branch variables according to a target constraint condition, and writing the two initial branch variables into a target storage area, wherein the target constraint condition corresponds to a target loop count corresponding to the branch instruction, and the target difference between the two initial branch variables is an integer multiple of the target loop count;

[0009] execute the target jump instruction and a regular instruction stream, wherein the target jump instruction is a jump instruction corresponding to the branch instruction, and the regular instruction stream is an intermediate instruction between the target jump instruction and the branch instruction in the original instruction set;

[0010] execute a read branch variable instruction to write two branch variables in the target storage interval into a first source register and a second source register corresponding to the branch instruction respectively;

[0011] execute a modify branch variable instruction to adjust the branch variable in the first source register or the branch variable in the second source register;

[0012] execute a store branch variable instruction to update the branch variable in the first source register and the branch variable in the second source register to the target storage interval;

[0013] execute the branch instruction in combination with the branch variable in the first source register and the branch variable in the second source register.

[0014] Optionally, the two branch variables in the target storage interval are a first branch variable and a second branch variable, and the execution of the read branch variable instruction to write the two branch variables in the target storage interval into the first source register and the second source register corresponding to the branch instruction comprises:

[0015] write the first branch variable in the target storage interval into the first source register corresponding to the branch instruction;

[0016] write the second branch variable in the target storage interval into the second source register corresponding to the branch instruction.

[0017] Optionally, the execution of the modify branch variable instruction to adjust the branch variable in the first source register or the branch variable in the second source register comprises:

[0018] adjust the first branch variable in the first source register or the second branch variable in the second source register according to a preset amplitude, wherein the preset amplitude matches the target loop number and the target difference.

[0019] Optionally, the execution of the branch instruction in combination with the branch variable in the first source register and the branch variable in the second source register comprises:

[0020] determine whether a loop condition is met according to the branch variable in the first source register and the branch variable in the second source register;

[0021] if the loop condition is met, repeat the execution of the target jump instruction and the regular instruction stream;

[0022] If the loop condition is not satisfied, the branch instruction block is executed.

[0023] Optionally, the loop condition is any one of the first branch variable being greater than or equal to the second branch variable, the first branch variable being less than the second branch variable, and the first branch variable not being equal to the second branch variable.

[0024] Optionally, the process of assembling and rewriting the original instruction set to generate each branch instruction block comprises:

[0025] adding a corresponding initial instruction number to each instruction in the original instruction set;

[0026] traversing and identifying the original instruction set, and when the nth instruction is identified as a branch instruction, selecting one of the first n-1 instructions in the original instruction set as a target jump instruction of the nth instruction;

[0027] inserting a corresponding initial branch condition instruction of the nth instruction before the target jump instruction of the nth instruction;

[0028] inserting, in sequence, a corresponding read branch variable instruction, a modify branch variable instruction, and a store branch variable instruction of the nth instruction before the nth instruction, thereby generating a branch instruction block corresponding to the nth instruction.

[0029] Optionally, after selecting one of the first n-1 instructions in the original instruction set as a target jump instruction of the nth instruction, the process further comprises:

[0030] generating a jump identifier according to the target jump instruction of the nth instruction;

[0031] adding the jump identifier to the nth instruction and its corresponding target jump instruction, respectively.

[0032] Optionally, the inserted read branch variable instruction comprises a first read address of a first source register of the nth instruction and a second read address of a second source register, the first read address and the second read address belonging to the target storage interval;

[0033] the inserted modify branch variable instruction comprises a preset amplitude, a modification object, and a modification direction corresponding to the nth instruction, the modification object being the first source register or the second source register of the nth instruction;

[0034] the inserted store branch variable instruction comprises a first write address of the first source register of the nth instruction and a second write address of the second source register, the first write address and the second write address belonging to the target storage interval.

[0035] In a second aspect, an embodiment of the present application provides a random instruction generator, which implements the branch instruction block execution method described above.

[0036] In a third aspect, an embodiment of the present application provides an electronic device, which comprises the random instruction generator described above.

[0037] Compared with the prior art, the branch instruction block execution method and the related device provided by the embodiment of the present application execute an initialization branch condition instruction, including: generating two initial branch variables randomly according to a target constraint condition, and writing the two initial branch variables into a target storage interval, wherein the target constraint condition corresponds to a target loop number corresponding to a branch instruction, and a target difference between the two initial branch variables is an integer multiple of the target loop number; executing a target jump instruction and a conventional instruction flow, wherein the target jump instruction is a jump instruction corresponding to the branch instruction, and the conventional instruction flow is an intermediate instruction between the target jump instruction and the branch instruction in an original instruction set; executing a reading branch variable instruction to write the two branch variables in the target storage interval into a first source register and a second source register corresponding to the branch instruction; executing a modifying branch variable instruction to adjust the branch variable in the first source register or the branch variable in the second source register; executing a storing branch variable instruction to update the branch variable in the first source register and the branch variable in the second source register to the target storage interval; and executing the branch instruction in combination with the branch variable in the first source register and the branch variable in the second source register. Before the first source register and the second source register are modified, reliable branch variables are read from the target storage interval, so that the modified branch variables and the loop number of the branch instruction are matched, and the branch variables in the first source register and the second source register are reliable, thereby guaranteeing the controllability of the branch instruction jump.

[0038] In order to make the above objectives, features and advantages of the present application more apparent, the following will specifically describe preferred embodiments in conjunction with the accompanying drawings, and make a detailed description as follows. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments, and it should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation to the scope, and for those skilled in the art, other related drawings can also be obtained without paying creative labor on the basis of these drawings.

[0040] Figure 1 The flowchart of the branch instruction block execution method provided by the embodiment of the present application.

[0041] Figure 2The sub-step S26 provided by the embodiment of the present application is shown in the following schematic diagram.

[0042] Figure 3 The process of each branch instruction block provided by the embodiment of the present application is shown in the following schematic diagram. DETAILED DESCRIPTION

[0043] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. The components of the embodiments of the present application described and shown in the drawings can be arranged and designed in various different configurations.

[0044] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative labor are within the scope of protection of the present application.

[0045] It should be noted that: similar reference numerals and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. Meanwhile, in the description of the present application, the terms “first”, “second” and the like are only used to distinguish description, and cannot be understood as indicating or implying relative importance.

[0046] It should be noted that: similar reference numerals and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. Meanwhile, in the description of the present application, the terms “first”, “second” and the like are only used to distinguish description, and cannot be understood as indicating or implying relative importance.

[0047] In the description of the present application, it should be noted that the terms "upper", "lower", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, or the orientation or positional relationship commonly used when the product of the present application is used, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0048] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms "provided", "connected" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be connected inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0049] Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The following examples and features in the examples can be combined with each other without conflict.

[0050] The embodiment of the present application provides a branch instruction block execution method, which can be applied to the random instruction generator described below, can realize controllable forward jump of branch instruction, and operation instruction execution correctness. Please refer to Figure 1 , Figure 1 The flowchart of the branch instruction block execution method provided by the embodiment of the present application is shown. The branch instruction block execution method comprises: S21 to S26, which are specifically described as follows.

[0051] S21, execute the initialization branch condition instruction.

[0052] The initialization branch condition instruction is the first instruction in the branch instruction block.

[0053] Executing the initialization branch condition instruction comprises: randomly generating two initial branch variables (a first branch variable and a second branch variable) according to a target constraint condition, and writing the two initial branch variables into a target storage area (which can be but is not limited to a storage area in memory).

[0054] The two initial branch variables are respectively used as the first branch variable and the second branch variable, the target constraint condition corresponds to a target loop number corresponding to the branch instruction (in the branch instruction block), and the target difference between the two initial branch variables (i.e. the target difference between the initial first branch variable and the initial second branch variable) is an integer multiple of the target loop number.

[0055] S22, execute the target jump instruction and the regular instruction flow.

[0056] The target jump instruction is a jump instruction corresponding to the branch instruction, and the regular instruction flow is an intermediate instruction between the target jump instruction and the branch instruction in an original instruction set (an instruction set before assembly rewriting).

[0057] It should be understood that the target jump instruction and the regular instruction flow are executed after the initialization branch condition instruction is completed.

[0058] S23, execute the read branch variable instruction to write two branch variables in the target storage area into a first source register and a second source register corresponding to the branch instruction respectively.

[0059] The read branch variable instruction is executed after the target jump instruction and the regular instruction flow are executed.

[0060] S24, execute the modify branch variable instruction to adjust the branch variable in the first source register or the branch variable in the second source register.

[0061] The modify branch variable instruction is executed after the read branch variable instruction is executed.

[0062] S25, execute the store branch variable instruction to update the branch variable in the first source register and the branch variable in the second source register to the target storage area.

[0063] The store branch variable instruction is executed after the modify branch variable instruction is executed and the adjustment of the branch variable is completed, and at this time, the first branch variable and the second branch variable modified in the current loop process are stored in the target storage area.

[0064] Optionally, the store branch variable instruction includes: updating the first branch variable in the first source register to the target storage area as a new first branch variable; and updating the second branch variable in the second source register to the target storage area as a new second branch variable.

[0065] S26, execute the branch instruction in combination with the branch variable in the first source register and the branch variable in the second source register.

[0066] When the target jump instruction and the regular instruction flow are executed, the values in the first source register and the second source register may be modified, causing the branch variables therein to be unreliable, thereby affecting the controllability of the branch jump. In the embodiment of the application, before the first source register and the second source register are modified, reliable branch variables are read from the target storage area, so that the modified branch variables and the number of loop times of the branch instruction are matched, the branch variables in the first source register and the second source register are reliable, and the controllability of the branch instruction jump is guaranteed.

[0067] In an alternative embodiment, the two branch variables in the target storage interval are a first branch variable and a second branch variable. S23, executing the read branch variable instruction to write the two branch variables in the target storage interval into the first source register and the second source register corresponding to the branch instruction, comprises: S231 and S232, which are specified as follows.

[0068] S231, writing the first branch variable in the target storage interval into the first source register corresponding to the branch instruction.

[0069] S232, writing the second branch variable in the target storage interval into the second source register corresponding to the branch instruction.

[0070] Optionally, S24, executing the modify branch variable instruction to adjust the branch variable in the first source register or the branch variable in the second source register, comprises: adjusting the first branch variable in the first source register or the second branch variable in the second source register according to a preset amplitude, wherein the preset amplitude matches the target loop number and the target difference, and the preset amplitude is equal to the target difference divided by the target loop number.

[0071] On the basis of the foregoing, as for the content in S26, the embodiment of the application further provides an alternative embodiment, which is described with reference to Figure 2 , Figure 2 The sub-step diagram of S26 provided by the embodiment of the application is shown in FIG. 6. S26, executing the branch instruction in combination with the branch variable in the first source register and the branch variable in the second source register, comprises:

[0072] S261, determining whether the loop condition is met according to the branch variable in the first source register and the branch variable in the second source register. If the loop condition is met, repeating S22; if the loop condition is not met, executing S262.

[0073] If the loop condition is met, repeating the execution of the target jump instruction and the regular instruction stream. The branch instruction includes the identification of the target jump instruction, which can be the program count value of the target jump instruction or the prefix information added by the target jump instruction.

[0074] S262, the branch instruction block is executed completely.

[0075] After the branch instruction block is executed completely, other instructions after the branch instruction block in the original instruction set can be executed.

[0076] Optionally, the loop condition is any one of the first branch variable being greater than or equal to the second branch variable, the first branch variable being less than the second branch variable, and the first branch variable not being equal to the second branch variable.

[0077] The loop condition can be determined according to the branch instruction type, and the loop condition of beq is that the first branch variable is equal to the second branch variable, the loop condition of bge and bgeu is that the first branch variable is greater than or equal to the second branch variable, the loop condition of blt and bltu is that the first branch variable is less than the second branch variable, and the loop condition of bne is that the first branch variable is not equal to the second branch variable.

[0078] In an optional embodiment, the step length of the forward jump branch instruction cannot exceed 4kb, and the step length here is the instruction length between the target jump instruction and the branch instruction.

[0079] On the basis of the foregoing, the present embodiment further provides an optional embodiment for the process of compiling and rewriting the original instruction set to generate the branch instruction block, please refer to Figure 3 , Figure 3 The process schematic diagram of the branch instruction block provided by the present embodiment is shown in the figure. The process of compiling and rewriting the original instruction set to generate the branch instruction block includes S11 to S14, which are specifically described as follows.

[0080] S11, add the corresponding initial instruction number to each instruction in the original instruction set.

[0081] S12, traverse and identify the original instruction set, and when the nth instruction is identified as a branch instruction, select one of the first n-1 instructions in the original instruction set as the target jump instruction of the nth instruction.

[0082] The nth instruction is the instruction with the initial instruction number n in the original instruction set, and one of the first n-1 instructions in the original instruction set can be randomly selected as the target jump instruction of the nth instruction. Optionally, the instruction length between the target jump instruction of the nth instruction and the nth instruction cannot exceed 4kb.

[0083] S13, insert the corresponding initial branch condition instruction of the nth instruction before the target jump instruction of the nth instruction.

[0084] The corresponding initial branch condition instruction of the nth instruction includes the corresponding target constraint condition of the nth instruction.

[0085] S14, sequentially insert the corresponding read branch variable instruction, the modification branch variable instruction and the storage branch variable instruction of the nth instruction before the nth instruction, thereby generating the branch instruction block corresponding to the nth instruction.

[0086] Optionally, after (randomly) selecting one of the first n-1 instructions in the original instruction set as the target jump instruction of the nth instruction, further comprising: generating a jump identifier (for example, the jump identifier can be 9b, the jump identifier is also referred to as prefix information) according to the target jump instruction of the nth instruction; and adding the jump identifier to the nth instruction and the target jump instruction corresponding to the nth instruction respectively (so as to determine the jump object when subsequently executed).

[0087] Optionally, the inserted read branch variable instruction includes a first read address of the first source register of the nth instruction and a second read address of the second source register, and the first read address and the second read address belong to the target storage interval; the inserted modification branch variable instruction includes a preset amplitude corresponding to the nth instruction, a modification object, and a modification direction (increase or decrease), and the modification object is the first source register or the second source register of the nth instruction; and the inserted storage branch variable instruction includes a first write address of the first source register of the nth instruction and a second write address of the second source register, and the first write address and the second write address belong to the target storage interval.

[0088] Optionally, the first read address is equal to the first write address, and the second read address is equal to the second write address.

[0089] The embodiment of the present application further provides a random instruction generator, which implements the branch instruction block execution method described above.

[0090] The embodiment of the present application further provides an electronic device, which comprises the random instruction generator described above.

[0091] In summary, the branch instruction block execution method and related device provided by the embodiment of the present application execute the initialization branch condition instruction, including: generating two initial branch variables according to a target constraint condition, and writing the two initial branch variables into a target storage area, wherein the target constraint condition corresponds to a target loop number corresponding to the branch instruction, and a target difference between the two initial branch variables is an integer multiple of the target loop number; executing a target jump instruction and a conventional instruction stream, wherein the target jump instruction is a jump instruction corresponding to the branch instruction, and the conventional instruction stream is an intermediate instruction between the target jump instruction and the branch instruction in an original instruction set; executing a read branch variable instruction to write the two branch variables in the target storage area into a first source register and a second source register corresponding to the branch instruction; executing a modify branch variable instruction to adjust the branch variable in the first source register or the branch variable in the second source register; executing a store branch variable instruction to update the branch variable in the first source register and the branch variable in the second source register to the target storage area; and executing the branch instruction in combination with the branch variable in the first source register and the branch variable in the second source register. Before the first source register and the second source register are modified, reliable branch variables are read from the target storage area, so that the modified branch variables and the loop number of the branch instruction are matched, and the branch variables in the first source register and the second source register are reliable, thereby ensuring the controllability of the branch instruction jump.

[0092] The above only describes preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0093] It is obvious for those skilled in the art that the present application is not limited to the details of the above exemplary embodiments, and the present application can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be regarded as exemplary and non-limiting, and the scope of the present application is defined by the appended claims rather than the above description, and all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present application. Any reference signs in the claims should not be regarded as limiting the claims involved.

Claims

1. A method of branch instruction block execution, the method comprising: The branch instruction block execution method comprises: performing an initialization branch condition instruction, comprising: generating two initial branch variables according to a target constraint condition, and writing the two initial branch variables into a target storage area, wherein the target constraint condition corresponds to a target loop number corresponding to the branch instruction, and a target difference between the two initial branch variables is an integer multiple of the target loop number; performing a target jump instruction and a regular instruction stream, wherein the target jump instruction is a jump instruction corresponding to the branch instruction, and the regular instruction stream is an intermediate instruction between the target jump instruction and the branch instruction in an original instruction set; performing a read branch variable instruction to write the two branch variables in the target storage area into a first source register and a second source register corresponding to the branch instruction respectively; performing a modification branch variable instruction to adjust the branch variable in the first source register or the branch variable in the second source register; performing a storage branch variable instruction to update the branch variable in the first source register and the branch variable in the second source register to the target storage area; performing the branch instruction in combination with the branch variable in the first source register and the branch variable in the second source register.

2. The branch instruction block execution method of claim 1, wherein, The two branch variables in the target storage area are a first branch variable and a second branch variable, and the performing of the read branch variable instruction to write the two branch variables in the target storage area into the first source register and the second source register corresponding to the branch instruction respectively comprises: writing the first branch variable in the target storage area into the first source register corresponding to the branch instruction; writing the second branch variable in the target storage area into the second source register corresponding to the branch instruction.

3. The branch instruction block execution method of claim 2, wherein, The performing of the modification branch variable instruction to adjust the branch variable in the first source register or the branch variable in the second source register comprises: adjusting the first branch variable in the first source register or the second branch variable in the second source register according to a preset amplitude, wherein the preset amplitude matches the target loop number and the target difference.

4. The branch instruction block execution method of claim 3, wherein, The performing of the branch instruction in combination with the branch variable in the first source register and the branch variable in the second source register comprises: determining whether a loop condition is met according to the branch variable in the first source register and the branch variable in the second source register; if the loop condition is met, repeatedly performing the target jump instruction and the regular instruction stream; if the loop condition is not met, the branch instruction block execution is completed.

5. The branch instruction block execution method of claim 4, wherein, The loop condition is any one of the first branch variable being greater than or equal to the second branch variable, the first branch variable being less than the second branch variable, and the first branch variable not being equal to the second branch variable.

6. The branch instruction block execution method of claim 1, wherein, The process of assembling and rewriting the original instruction set to generate each branch instruction block comprises: adding a corresponding initial instruction number to each instruction in the original instruction set; traversing the original instruction set to identify, when the nth instruction is identified as a branch instruction, selecting one of the first n-1 instructions in the original instruction set as a target jump instruction of the nth instruction; inserting a corresponding initialization branch condition instruction of the nth instruction before the target jump instruction of the nth instruction; inserting, in sequence, a corresponding read branch variable instruction, a modify branch variable instruction and a store branch variable instruction of the nth instruction before the nth instruction, thereby generating a branch instruction block corresponding to the nth instruction.

7. The branch instruction block execution method of claim 6, wherein, After selecting one of the first n-1 instructions in the original instruction set as a target jump instruction of the nth instruction, further comprising: generating a jump identifier according to the target jump instruction of the nth instruction; adding the jump identifier to the nth instruction and its corresponding target jump instruction, respectively.

8. The branch instruction block execution method of claim 6, wherein, the inserted read branch variable instruction includes a first read address of a first source register of the nth instruction and a second read address of a second source register, the first read address and the second read address belonging to the target storage interval; the inserted modify branch variable instruction includes a preset amplitude, a modification object and a modification direction corresponding to the nth instruction, the modification object being the first source register or the second source register of the nth instruction; the inserted store branch variable instruction includes a first write address of the first source register of the nth instruction and a second write address of the second source register, the first write address and the second write address belonging to the target storage interval.

9. A random instruction generator, characterized by The random instruction generator executes the method of any one of claims 1-8.

10. An electronic device, comprising: The random instruction generator of claim 9. The random instruction generator of claim 9.

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