Data processing apparatus and method, processor and chip

Abstract

The present disclosure relates to a data processing device and method, a processor and a chip, and relates to the technical field of computers, the data processing device comprising a second unit and N first units, each first unit comprising an instruction transmitter, a load-store unit and a storage unit, the instruction transmitter transmitting instruction information to the load-store unit; the load-store unit analyzing the instruction information and obtaining address information carried by different thread information from the instruction information; a plurality of preset bit fields of each output data channel of the load-store unit being used to place the address information carried by different thread information, so that the load-store unit transmits the address information to the second unit at a multiple rate; the second unit receiving the address information from the load-store units in different first units and returning requested data at the address information indication to the storage unit in the corresponding first unit. The embodiment of the present disclosure can improve the instruction execution efficiency.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of computer, and particularly relates to a data processing apparatus and method, a processor and a chip. BACKGROUND

[0002] Processor chips, such as Graphics Processing Unit (GPU), play an increasingly important role in graphics and general computing scenarios due to their high parallel processing nature. The graphics processing in a GPU is usually placed in a fixed pipeline, and the general part is placed in a programmable pipeline processing. A Load Store Unit (LSU) as an access to an external storage plays a vital role in the programmable pipeline, and provides a load function or a storage function. However, the current load store unit is not efficient enough in executing a load instruction. SUMMARY

[0003] The present disclosure provides a data processing technical solution.

[0004] According to an aspect of the present disclosure, a data processing apparatus is provided, which comprises a second unit and N first units, each first unit comprising an instruction transmitter, a load store unit and a storage unit, the load store unit comprising a plurality of output data channels, N being an integer greater than 1: the instruction transmitter sends instruction information to the load store unit, the instruction information comprising a plurality of thread information; the load store unit analyzes the instruction information and obtains address information carried by different thread information from the instruction information; a plurality of preset bit fields of each output data channel of the load store unit are used to place the address information carried by the different thread information, so that the load store unit sends the address information to the second unit at a multiple rate; the second unit receives the address information from the load store unit in different first units, and returns requested data at the address information indicated to the storage unit in the corresponding first unit.

[0005] In a possible implementation, in a case where the load store unit comprises K output data channels, each output data channel comprising P preset bit fields, K and P being integers greater than 1, the load store unit is configured to: select K times P thread information from a plurality of thread information contained in the instruction information each time for analysis, to obtain address information of the K times P thread information; the P preset bit fields of each output data channel of the load store unit are used to place address information carried by P thread information, so that the load store unit sends K times P address information to the second unit at a P times rate each time.

[0006] In one possible implementation, the second unit includes a cache, a data conversion module, and N merging modules. The merging modules merge the address information from the loading storage unit and generate a merged address request to the cache. The cache responds to the merged address request by returning the request data of the merged address request to the merging module. The data conversion module obtains the request data returned by the cache from the merging module and sends it to the corresponding storage unit in the first unit.

[0007] In one possible implementation, the instruction transmitter of the i-th first unit is connected to the i-th merging module of the second unit via the load storage unit of the i-th first unit, the cache of the second unit is connected to N merging modules of the second unit respectively, and the data conversion module of the second unit is connected to N merging modules of the second unit and N storage units of the first unit respectively, where i is any integer from 1 to N.

[0008] In one possible implementation, the merging module includes an expansion unit, a merging unit, a request buffer, and an offset unit: the expansion unit performs cross-cache line judgment on multiple address information from the loading storage unit to obtain a first judgment result; the merging unit merges the multiple address information when the first judgment result indicates that multiple address information is in the same cache line to obtain a merged address request; the request buffer records the accompanying information of the merged address request and, in response to receiving the request data returned by the cache, sends the accompanying information and the request data to the offset unit; the offset unit generates a data mask signal based on the accompanying information and the request data, the data mask signal being used to indicate the byte offset of storing the request data in the storage unit.

[0009] In one possible implementation, the offset unit is further configured to: determine, based on the request data, whether the request data of the plurality of thread information included in the instruction information has been returned to the data conversion module, and obtain a second determination result; if the second determination result indicates that all request data corresponding to the plurality of thread information has been returned to the data conversion module, generate a first identification signal; wherein, in response to receiving request data of any thread information returned by the request buffer, the offset unit sends the request data to the data conversion module.

[0010] In one possible implementation, the loading storage unit, the expanding unit, and the merging unit are connected in series, the request buffer is connected to the cache, the merging unit, and the offset unit, and the offset unit is connected to the data conversion module.

[0011] In one possible implementation, the data conversion module includes an accompanying information queue, a data queue, a control module, an address calculation module, a mask processing module, and a data processing module. The accompanying information queue stores accompanying information, a first identifier signal, and a data mask signal from the merging module; the data queue stores request data from the merging module. The address calculation module, connected to the accompanying information queue, determines the destination address of different thread information based on the accompanying information stored in the accompanying information queue. The destination address indicates the location where the request data is written to the storage unit. The mask processing module, connected to the accompanying information queue, matches the data mask signal stored in the accompanying information queue with the request data to obtain a matching result. The matching result indicates the correspondence between the destination address and the request data. The control module, connected to the accompanying information queue, generates a trigger signal indicating the completion of instruction information based on the first identifier signal stored in the accompanying information queue. The trigger signal triggers the data processing device to process the next instruction information. The data processing module, connected to the data queue, converts the request data stored in the data queue, expands it according to a preset direction, and writes it to the storage unit indicated by the destination address.

[0012] According to one aspect of this disclosure, a data processing method is provided, the method being applied to a data processing apparatus, the data processing apparatus comprising a second unit and N first units, each first unit comprising an instruction transmitter, a loading storage unit, and a storage unit, the loading storage unit comprising multiple output data channels, where N is an integer greater than 1, the method comprising: the instruction transmitter sending instruction information to the loading storage unit, the instruction information including multiple thread information; the loading storage unit parsing the instruction information to obtain address information carried by different thread information from the instruction information; the loading storage unit using multiple preset bit fields of each output data channel to place the address information carried by the different thread information, and sending the address information to the second unit at a multiple rate; the second unit receiving the address information from the loading storage units in different first units, and returning request data at the address information indication to the corresponding storage unit in the first unit.

[0013] In one possible implementation, the loading storage unit parses the instruction information to obtain address information carried by different thread information, including: when the loading storage unit includes K output data channels and each output data channel contains P preset bit fields, K multiplied by P thread information is selected from the multiple thread information contained in the instruction information for parsing each time to obtain address information of K multiplied by P thread information; K and P are integers greater than 1; the loading storage unit uses multiple preset bit fields of each output data channel to place the address information carried by the different thread information, and sends the address information to the second unit at a multiple rate, including: the loading storage unit uses the P preset bit fields of each output data channel to place the address information carried by P thread information, and sends K multiplied by P address information to the second unit each time at a P-fold rate.

[0014] In one possible implementation, the second unit includes a cache, a data conversion module, and N merging modules. The second unit receives address information from the loading storage units in different first units and returns request data at the address information indication to the corresponding storage unit in the first unit. This includes: the merging module merging the address information from the loading storage units to generate a merged address request to the cache; the cache responding to the merged address request by returning the request data of the merged address request to the merging module; and the data conversion module obtaining the request data returned by the cache from the merging module and sending it to the corresponding storage unit in the first unit.

[0015] In one possible implementation, the instruction transmitter of the i-th first unit is connected to the i-th merging module of the second unit via the load storage unit of the i-th first unit, the cache of the second unit is connected to N merging modules of the second unit respectively, and the data conversion module of the second unit is connected to N merging modules of the second unit and N storage units of the first unit respectively, where i is any integer from 1 to N.

[0016] In one possible implementation, the merging module includes an expansion unit, a merging unit, a request buffer, and an offset unit. The expansion unit is used to perform cross-cache line judgment on multiple address information from the loading storage unit to obtain a first judgment result. The merging unit is used to merge multiple address information to obtain a merged address request when the first judgment result indicates that multiple address information is in the same cache line. The request buffer is used to record accompanying information of the merged address request and, in response to receiving request data returned by the cache, sends the accompanying information and the request data to the offset unit. The offset unit is used to generate a data mask signal based on the accompanying information and the request data, and the data mask signal is used to indicate the byte offset of storing the request data in the storage unit.

[0017] In one possible implementation, the offset unit is further configured to: determine, based on the request data, whether the request data of the plurality of thread information included in the instruction information has been returned to the data conversion module, and obtain a second determination result; if the second determination result indicates that all request data corresponding to the plurality of thread information has been returned to the data conversion module, generate a first identification signal; wherein, in response to receiving request data of any thread information returned by the request buffer, the offset unit sends the request data to the data conversion module.

[0018] In one possible implementation, the loading storage unit, the expanding unit, and the merging unit are connected in series, the request buffer is connected to the cache, the merging unit, and the offset unit, and the offset unit is connected to the data conversion module.

[0019] In one possible implementation, the data conversion module includes an accompanying information queue, a data queue, a control module, an address calculation module, a mask processing module, and a data processing module. The accompanying information queue stores accompanying information, a first identifier signal, and a data mask signal from the merging module; the data queue stores request data from the merging module. The address calculation module, connected to the accompanying information queue, determines the destination address of different thread information based on the accompanying information stored in the accompanying information queue. The destination address indicates the location where the request data is written to the storage unit. The mask processing module, connected to the accompanying information queue, matches the data mask signal stored in the accompanying information queue with the request data to obtain a matching result. The matching result indicates the correspondence between the destination address and the request data. The control module, connected to the accompanying information queue, generates a trigger signal indicating the completion of instruction information based on the first identifier signal stored in the accompanying information queue. The trigger signal triggers the data processing device to process the next instruction information. The data processing module, connected to the data queue, converts the request data stored in the data queue, expands it according to a preset direction, and writes it to the storage unit indicated by the destination address.

[0020] According to one aspect of this disclosure, an electronic device is provided, wherein the processor includes the data processing means described above.

[0021] According to one aspect of this disclosure, a chip is provided that includes the processor described above.

[0022] In embodiments of this disclosure, the data processing device includes a second unit and N first units. Each first unit includes an instruction transmitter, a loading storage unit, and a storage unit. The loading storage unit includes multiple output data channels, where N is an integer greater than 1. The instruction transmitter sends instruction information to the loading storage unit, and the instruction information includes multiple thread information. The loading storage unit parses the instruction information and obtains address information carried by different thread information from the instruction information. Multiple preset bit fields of each output data channel of the loading storage unit are used to store the address information carried by the different thread information, so that the loading storage unit sends the address information to the second unit at a multiple rate. The second unit receives the address information from the loading storage units in different first units and returns the request data at the address information indication to the corresponding storage unit in the first unit.

[0023] By setting multiple preset bit fields for the output data channel, each output data can store address information carried by different threads, supporting the sending of address information to the second unit at multiple times the rate each time. This improves the interface utilization of the loading memory unit, thereby increasing instruction execution efficiency and reducing time latency.

[0024] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0025] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the specification, serve to illustrate the technical solutions of this disclosure.

[0026] Figure 1 A schematic diagram of a data processing apparatus according to an embodiment of the present disclosure is shown.

[0027] Figure 2 This diagram illustrates the output data channel of the loading storage unit in the related art.

[0028] Figure 3 A schematic diagram of the output data channel of the loading storage unit according to an embodiment of the present disclosure is shown.

[0029] Figure 4 A schematic diagram of another data processing apparatus according to an embodiment of the present disclosure is shown.

[0030] Figure 5 A schematic diagram of a merging module according to an embodiment of the present disclosure is shown.

[0031] Figure 6 A schematic diagram of a data conversion module in related technologies is shown.

[0032] Figure 7 A schematic diagram of a data conversion module according to an embodiment of the present disclosure is shown.

[0033] Figure 8 A flowchart illustrating a data processing method according to an embodiment of the present disclosure is shown.

[0034] Figure 9 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0035] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0036] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0037] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0038] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0039] Figure 1 A schematic diagram of a data processing apparatus according to an embodiment of the present disclosure is shown, such as Figure 1 As shown, the data processing device includes a second unit 2 and N first units 1, such as first units 1_1 to first units 1_N. Each first unit 1 is a module capable of independently generating instructions. The second unit 2 works in conjunction with the first unit 1, and the transmission bandwidth of the first unit 1 is less than that of the second unit 2. Each first unit 1 includes an instruction transmitter 3, a loading storage unit 4, and a storage unit 5. For example, first unit 1_1 includes an instruction transmitter 3_1, a loading storage unit 4_1, and a storage unit 5_1; first unit 1_2 includes an instruction transmitter 3_2, a loading storage unit 4_2, and a storage unit 5_2; and so on, with first unit 1_N including an instruction transmitter 3_N, a loading storage unit 4_N, and a storage unit 5_N, where N is an integer greater than 1. Within each first unit 1, the instruction transmitter 3 is connected to the loading storage unit 4, and the second unit 2 is connected to both the loading storage unit 4 and the storage unit 5 within each first unit 1.

[0040] In one possible implementation, the instruction transmitter 3 sends instruction information to the loading storage unit 4, the instruction information including multiple thread information; the loading storage unit 4 parses the instruction information and obtains the address information carried by different thread information from the instruction information; multiple preset bit fields of each output data channel of the loading storage unit 4 are used to place the address information carried by the different thread information, so that the loading storage unit 4 sends the address information to the second unit 2 at a multiple rate; the second unit 2 receives the address information from the loading storage units 4 in different first units 1, and returns the request data at the address information indication to the corresponding storage unit 5 in the first unit 1.

[0041] By setting multiple preset bit fields for the output data channel, each output data can store address information carried by different threads, supporting the sending of address information to the second unit at multiple times the rate each time. This improves the interface utilization of the loading memory unit, thereby increasing instruction execution efficiency and reducing time latency.

[0042] In one possible implementation, the data processing device may be located in a processor, which may be a newly designed processor or an improved version of an existing processor chip. The types of processor chips may include, but are not limited to, central processing units (CPUs), graphics processing units (GPUs), general-purpose graphics processing units (GPGPUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), and field-programmable gate arrays (FPGAs).

[0043] In the example, it is assumed that the data processing device is located in the graphics processor. The data processing device can provide a loading function to load data stored externally to the graphics processor into the storage unit 5 of the data processing device inside the graphics processor through various levels of cache. For example, the data processing device can load a piece of data from the external memory of the graphics processor into any of its own storage units 5.

[0044] In one possible implementation, the instruction transmitter 3 can receive instruction information from other control units within the processor (e.g., stream processors or shaders) and send the instruction information to the corresponding load memory unit 4. Alternatively, the instruction transmitter 3 can also generate instruction information based on software code (e.g., instruction code pre-input by the user) and send the instruction information to the corresponding load memory unit 4. It should be understood that the instruction transmitter 3 can be designed according to the actual application scenario, and the embodiments of this disclosure are not limited in this regard.

[0045] In one possible implementation, for scenarios where the instruction information is loading data, for example, the data processing device loads a segment of data from the external memory of the graphics processor into any of its own storage units 5, or the data processing device loads a segment of data (e.g., data temporarily stored in the cache for previously executed instructions) from the cache of the graphics processor into any of its own storage units 5. In this scenario, the loading storage unit 4 parses the instruction information from the instruction transmitter 3 and obtains address information from the instruction information; the second unit 2 receives the address information from different loading storage units 4 in the first unit 1 and returns the request data at the address information indicated in the cache to the storage unit 5 in the first unit 1.

[0046] For example, instruction transmitter 3_1 can send instruction information to loading storage unit 4_1. Loading storage unit 4_1 parses the instruction information from instruction transmitter 3_1 and obtains address information from the instruction information. Loading storage unit 4_1 can send the obtained address information to second unit 2. Second unit 2 can retrieve the request data at the address indicated by the address information from the cache according to the address information and send it back to storage unit 5_1.

[0047] For example, instruction transmitter 3_2 can send instruction information to loading storage unit 4_2. Loading storage unit 4_2 parses the instruction information from instruction transmitter 3_2 and obtains address information from the instruction information. Loading storage unit 4_2 can send the obtained address information to second unit 2. Second unit 2 can retrieve the request data indicated by the address information from the cache according to the address information and send it back to storage unit 5_2.

[0048] Similarly, the instruction transmitter 3_N can send instruction information to the loading storage unit 4_N. The loading storage unit 4_N parses the instruction information from the instruction transmitter 3_N and obtains the address information from the instruction information. The loading storage unit 4_N can send the obtained address information to the second unit 2. The second unit 2 can retrieve the request data at the address indicated by the address information from the cache according to the address information and send it back to the storage unit 5_N.

[0049] In one possible implementation, each instruction message may include multiple thread information, and different thread information may carry different address information. For example, the instruction message may be encapsulated into a data packet according to a preset protocol format, and may include signals in multiple fields, such as: a first signal field Valid, a second signal field Enable, an identifier signal field Wave id, a mask information field Active mask, and a sideband data field.

[0050] The first signal field segment Valid has a bit width of 1 bit, which is used to indicate the validity of the instruction information sent by the instruction issuing module of the graphics processor. 1 indicates that the instruction information sent by the instruction issuing module of the graphics processor is valid, and 0 indicates that the instruction information sent by the instruction issuing module of the graphics processor is invalid.

[0051] The second signal field segment Enable has a bit width of 1 bit, which is used to indicate the validity of the instruction information received by the data processing device. 1 indicates that the instruction information received by the data processing device is valid, and 0 indicates that the instruction information received by the data processing device is invalid.

[0052] The width of the wave id identifier signal field can be 5 bits, which is used to distinguish instruction information corresponding to different sub-tasks.

[0053] The active mask field can be 32 bits wide and is used to indicate the validity of each thread information among the multiple thread information carried by the instruction information.

[0054] The sideband data field can be 202 bits wide and is used to describe the specific operational details or context of the instruction information, such as immediate values, mode flags, opcodes, address information in different thread information, and other additional information.

[0055] It should be understood that the embodiments of this disclosure do not limit the bit width of each field in the instruction information, and can be set according to the actual application scenario.

[0056] The loading storage unit 4 has multiple output data channels, and each output data channel has multiple preset bit fields. Different preset bit fields are used to store address information of different threads, so that the loading storage unit 4 can send address information to the second unit 2 at multiple times the rate.

[0057] In one possible implementation, when the loading storage unit 4 includes K output data channels and each output data channel contains P preset bit fields, where K and P are integers greater than 1, the loading storage unit 4 is used to: each time select K multiplied by P thread information from the multiple thread information contained in the instruction information for parsing to obtain address information of K multiplied by P thread information; the P preset bit fields of each output data channel of the loading storage unit 4 are used to place the address information carried by the P thread information, so that the loading storage unit 4 sends K multiplied by P address information to the second unit at a rate of P times each time.

[0058] Figure 2 A schematic diagram of the output data channel of the loading storage unit in the related technology is shown, such as... Figure 2 As shown, in the output data channels data0, data1, data2, and data3, only the lower 48 bits store address information. For example, the lower 48 bits of output data channel data0 store address information block id×4+0, the lower 48 bits of output data channel data1 store address information block id×4+1, the lower 48 bits of output data channel data2 store address information block id×4+2, and the lower 48 bits of output data channel data3 store address information block id×4+3. Therefore, in related technologies, the address information of up to 4 threads can be sent in each transmission of the loaded storage unit.

[0059] Figure 3 A schematic diagram showing the output data channel of the loading storage unit according to an embodiment of the present disclosure is shown, such as... Figure 3 As shown, assuming that the loading storage unit 4 includes 4 (e.g., K=4) output data channels, each output channel contains 2 (e.g., P=2) preset bit fields, the first preset bit field is [47:0] bit field, the second preset bit field is [111:64] bit field, the loading storage unit 4 supports double rate loading, and can store address information block id×4+0 in the first preset bit field of the output data channel data0, and store address information (block id+1)×4+0 in the second preset bit field of the output data channel data0;

[0060] Address information block id×4+1 can be stored in the first preset bit field of the output data channel data1, and address information (block id+1)×4+1 can be stored in the second preset bit field of the output data channel data1.

[0061] Address information block id×4+2 can be stored in the first preset bit field of the output data channel data2, and address information (block id+1)×4+2 can be stored in the second preset bit field of the output data channel data2.

[0062] Address information block id×4+3 can be stored in the first preset bit field of the output data channel data3, and address information (block id+1)×4+3 can be stored in the second preset bit field of the output data channel data3.

[0063] It can be seen that the address information is stored in the first and second preset bit fields of the output data channels data1 to data3 of the loading storage unit 4, and each transmission can support the transmission of address information of up to 2×4=8 threads.

[0064] It should be understood that the embodiments disclosed herein are for illustrative purposes only. Figure 3 For example, there are no specific restrictions on the number of output data channels K and the number of preset bit fields P, which can be set according to the actual application scenario.

[0065] In the example, the P-times loading function of the loading storage unit 4 satisfies the following constraints: the current instruction information received by the loading storage unit 4 is that the loading target is storage unit 5 and the current instruction information is a loading instruction; or, the current instruction is a prefetch instruction, wherein the prefetch instruction is used to preload the data to be used from main memory into the cache of the second unit 2 in order to reduce the latency when the instruction to access main memory is executed.

[0066] When the current instruction information meets the above conditions, the loading storage unit 4 can store the P×K thread information at the granularity of each frame according to the active mask field carried in the instruction information, to identify the validity of the address information of the P×K thread information issued by the loading storage unit 4. The address information can be confirmed by Base Addr + Offset + stride * add_first, where Base Addr represents the base address, Offset represents the offset address, and stride * add_first represents the jump address. Therefore, each calculation requires obtaining the base address (Base Addr) and offset address (Offset) of K thread information from P adjacent address blocks, performing addition preprocessing, and then adding the address information of each thread information with the jump address (stride * add_first).

[0067] When accessing registers, the base address (Base Addr) and offset address (Offset) of at least P×K thread information can be obtained each time in the loading memory unit 4. Otherwise, it will cause an imbalance between slow data acquisition by the front-end module and fast data processing by the back-end module inside the loading memory unit 4.

[0068] As can be seen, compared with the loading storage unit in the related technology, the loading storage unit 4 of the present disclosure can improve performance and reduce the delay of the loading storage unit 4 in processing loading instructions by increasing the interface utilization rate without adding extra resources when executing loading instructions.

[0069] Figure 4 A schematic diagram of another data processing apparatus according to an embodiment of the present disclosure is shown, such as Figure 4 As shown, the data processing device includes a second unit 2 and N first units 1, for example, first unit 1_1 to first unit 1_N. Each first unit 1 includes an instruction transmitter 3, a loading storage unit 4, and a storage unit 5. The second unit 2 includes a cache 7, a data conversion module 8, and N merging modules 6, where N is an integer greater than 1.

[0070] In this configuration, the instruction transmitter 3_i of the i-th first unit 1_i is connected to the i-th merging module 6_i of the second unit 2 via the loading storage unit 4_i of the i-th first unit 1_i. The cache 7 of the second unit 2 is connected to the N merging modules 6 of the second unit 2 (e.g., merging modules 6_1 to merging modules 6_N). The data conversion module 8 of the second unit 2 is connected to the N merging modules 6 of the second unit 2 (e.g., merging modules 6_1 to merging modules 6_N) and the N storage units 5 of the first unit 1 (e.g., storage units 5_1 to storage units 5_N). i is any integer from 1 to N.

[0071] like Figure 4 As shown, the instruction transmitter 3_1 of the first unit 1_1 is connected to the first merging module 6_1 of the second unit 2 via the loading storage unit 4_1; the instruction transmitter 3_2 of the second unit 1_2 is connected to the second merging module 6_2 of the second unit 2 via the loading storage unit 4_2; the instruction transmitter 3_3 of the third unit 1_3 is connected to the third merging module 6_3 of the second unit 2 via the loading storage unit 4_3; and so on, the instruction transmitter 3_N of the Nth unit 1_N is connected to the Nth merging module 6_N of the second unit 2 via the loading storage unit 4_N. The cache 7 of the second unit 2 is connected to merging modules 6_1 to merging modules 6_N respectively, and the data conversion module 8 of the second unit 2 is connected to merging modules 6_1 to merging modules 6_N and storage units 5_1 to storage units 5_N respectively.

[0072] The instruction transmitter 3, loading storage unit 4, and storage unit 5 included in each first unit 1, and the cache 7, data conversion module 8, and merging module 6 included in the second unit 2, can be implemented by integrated circuits composed of general analog components, digital circuit components, etc. This disclosure does not limit the specific implementation method.

[0073] In one possible implementation, for scenarios where the instruction information is loading data, for example, the data processing device loads a segment of data from the external memory of the graphics processor into any of its own storage units 5, or the data processing device loads a segment of data (e.g., data temporarily stored in the cache of the graphics processor's prior instruction) into any of its own storage units 5. In this scenario, the loading storage unit 4 parses the instruction information from the instruction transmitter 3 and obtains address information from the instruction information; the merging module 6 merges the address information from the loading storage unit 4 and generates a merge address request to the cache 7; the cache 7 responds to the merge address request and returns the request data of the merge address request to the merging module 6; the data conversion module 8 obtains the request data returned by the cache 7 from the merging module 6 and sends it to the corresponding storage unit 5 in the first unit 1.

[0074] like Figure 4 As shown, the instruction transmitter 3_1 can send instruction information to the loading storage unit 4_1. The loading storage unit 4_1 parses the instruction information from the instruction transmitter 3_1 and obtains address information from the instruction information. The loading storage unit 4_1 can send the obtained address information to the merging module 6_1. The merging module 6_1 merges the address information from the loading storage unit 4_1 and generates a merged address request to the cache 7. The cache 7 responds to the merged address request and returns the request data of the merged address request to the merging module 6_1. The data conversion module 8 obtains the request data returned by the cache 7 from the merging module 6_1 and stores it in the storage unit 5_1.

[0075] Similarly, instruction transmitter 3_2 can send instruction information to loading storage unit 4_2. Loading storage unit 4_2 parses the instruction information from instruction transmitter 3_2 and obtains address information from the instruction information. Loading storage unit 4_2 can send the obtained address information to merging module 6_2. Merging module 6_1 merges the address information from loading storage unit 4_2 and generates a merged address request to cache 7. Cache 7 responds to the merged address request and returns the request data of the merged address request to merging module 6_2. Data conversion module 8 obtains the request data returned by cache 7 from merging module 6_2 and stores it in storage unit 5_2.

[0076] Similarly, instruction transmitter 3_N can send instruction information to loading storage unit 4_N. Loading storage unit 4_N parses the instruction information from instruction transmitter 3_N and obtains address information from the instruction information. Loading storage unit 4_N can send the obtained address information to merging module 6_N. Merging module 6_N merges the address information from loading storage unit 4_N and generates a merged address request to cache 7. Cache 7 responds to the merged address request and returns the request data of the merged address request to merging module 6_N. Data conversion module 8 obtains the request data returned by cache 7 from merging module 6_N and stores it in storage unit 5_N.

[0077] Optionally, the loading storage unit 4 receives instruction information from the instruction transmitter 3, parses the instruction information, obtains the corresponding register result representing the address information, and sends it to the merging module 6. The merging module 6 receives the address information from the loading storage unit 4 and sends the address information to the cache 7 (e.g., the L1 cache) at a request granularity that does not cross cache lines. The cache 7 receives the merge address request from the merging module 6, retrieves the corresponding requested data from memory (DDR), and returns it to the merging module 6. The data conversion module 8 maps and stores the requested data returned by the cache 7 to the merging module 6, combining it with the corresponding accompanying information from the merging module 6, and finally sends it to the storage unit 5 for storage. The storage unit 5 can be used to store data from memory (DDR).

[0078] By setting up N merging modules 6 and data conversion modules 8 in the second unit 2 of the data processing device to work with N first units 1, the N first units 1 can share the same cache 7, eliminating the need to equip each first unit 1 with a separate cache, thus saving storage resources. Furthermore, by merging the address information of different thread information in instruction information from different first units 1, and using the merged address to request access to cache 7, the frequency of access to cache 7 is reduced, which helps to reduce the internal latency of the data processing device and improve the instruction execution efficiency of the data processing device.

[0079] In one possible implementation, Figure 5 A schematic diagram of a merging module according to an embodiment of the present disclosure is shown, such as... Figure 5 As shown, the merging module 6 includes an expansion unit 61, a merging unit 62, a request buffer 63, and an offset unit 64. The loading storage unit 4, the expansion unit 61, and the merging unit 62 are connected in series. The request buffer 63 is connected to the cache 7, the merging unit 62, and the offset unit 64. The offset unit 64 is connected to the data conversion module 8. Figure 5 (Not shown).

[0080] The merging module 6 is used for: the expanding unit 61 performing cross-cache line judgment on the address information of multiple (e.g., P×K) thread information from the loading storage unit 4 to obtain a first judgment result; the merging unit 62 merging the address information of multiple (e.g., P×K) thread information when the first judgment result indicates that the address information of multiple (e.g., P×K) thread information is in the same cache line to obtain a merged address request; the request buffer 63 recording the accompanying information of the merged address request, and in response to receiving the request data returned by the cache 7, sending the accompanying information and the request data to the offset unit 64; the offset unit 64 generating a data mask signal based on the accompanying information and the request data, the data mask signal being used to indicate the byte offset of storing the request data in the storage unit 5.

[0081] For example, to support the double-rate loading function, the merging module 6 can process the address information of P×K thread information transmitted by the loading storage unit 4 each time. For instance, the expanding unit 61 can add the address information to the burst length signal from the accompanying information and determine whether the addition result will cross different cache lines of cache 7 (e.g., level 1 cache), that is, whether it will be stored in different cache lines of cache 7 (i.e., cross-cache line judgment), and obtain a first judgment result. If the first judgment result indicates that the addition result will cross different cache lines of cache 7, then the P×K thread information is split for processing.

[0082] If the first judgment result indicates that the addition result will not cross different cache lines of cache 7, the merging unit 62 can simultaneously process the address merging after expanding P×K thread information. By setting the merging unit 62, the efficiency of the data processing device can be improved from processing K thread information in parallel to processing P×K thread information.

[0083] The request buffer 63 is designed by the merging module 6 for load instructions or atomic instructions. For instructions that return request data, it can record the accompanying information of the merge address request. When the returned request data is returned from the cache 7, the accompanying information and the request data are provided together to the offset unit 64. For example, the request buffer 63 can be used to request a corresponding request number for each merge address request, and when the request data is returned, it can look up the accompanying information of the corresponding merge address request based on the request number. The accompanying information comes from the instruction information of the instruction transmitter.

[0084] Offset unit 64 is a data mask signal generated by merging module 6 based on the request data and accompanying information returned by cache 7. The data mask signal is used to indicate the byte offset of storing the request data in the storage unit.

[0085] In this way, the request data returned by cache 7 can no longer be cached within the merging module 6. Instead, the accompanying information inside the request buffer 63 can be directly combined with the request data and sent to the data conversion module 8, which can greatly reduce internal storage consumption.

[0086] In one possible implementation, the offset unit 64 is further configured to: determine, based on the request data, whether the request data for multiple thread information included in the instruction information has been returned to the data conversion module 8, and obtain a second determination result; if the second determination result indicates that all request data corresponding to multiple thread information has been returned to the data conversion module 8, generate a first identification signal; wherein, in response to receiving request data for any thread information returned by the request buffer 63, the offset unit 64 sends the request data to the data conversion module 8.

[0087] In the example, assuming the instruction information includes 32 (e.g., 32) thread information items, since the preceding loading storage unit 4 selects 8 thread information items from 64 thread information items for processing each time—for example, selecting thread information items 1 to 8 the first time, thread information items 9 to 16 the second time, thread information items 17 to 24 the third time, and thread information items 25 to 32 the fourth time—the offset unit 64 can determine whether the 32 request data items of the current 32 thread information items have been returned based on the returned request data, and obtain a second judgment result. If the second judgment result indicates that the last request data item among the 32 request data items has been returned, then a first identification signal is generated when the last request data item is sent to the data conversion module 8.

[0088] In this way, the merging module 6 will collect all the request data of the thread information before sending the request data to the data conversion module 8 for writing. In addition, during this process, whenever the cache 7 returns a request data, it will return it to the data conversion module 8, which can save the request data collection process and reduce the delay time of the request data in the merging module 6.

[0089] Figure 6 A schematic diagram of a data conversion module in related technologies is shown, such as... Figure 6 As shown, the data conversion module includes an application module, an information management module, a tracking module, a data conversion and storage module, a read control module, and a data back-end processing module. The merging module continuously connects the application module, the information management module, and the tracking module. The information management module is connected to the application module and the data conversion and storage module. The data conversion and storage module is also connected to the data back-end processing module via the read control module. The back-end processing module is also connected to the tracking module.

[0090] The data conversion and storage module is used to store request data for each thread. When the merging module sends data that needs to be written to the storage unit, the data conversion and storage module first obtains the corresponding region code from the request module and collects the corresponding accompanying information from the information management module. At the same time, it writes the data into the corresponding region code in the data conversion and storage module for storage. When the data conversion and storage module sees the first identification signal, it writes the accompanying information of the current instruction information segment in the information management module into the read control module. The read control module is used to determine the data reading status. The read control module reads the data of the corresponding region code in the current accompanying information and sends the mask information field segment active mask in the accompanying information to the data back-end processing module. The data back-end processing module assembles and splices the data and sends it to the storage unit for storage. After all the data of an instruction information segment is sent to the storage unit, the tracking module processes the synchronization mechanism of the current instruction information segment to clear the synchronization counter information requested by the merging module.

[0091] Figure 7 A schematic diagram of a data conversion module according to an embodiment of the present disclosure is shown, such as... Figure 7 As shown, the data conversion module 8 includes an accompanying information queue 81, a data queue 82, a control module 83, an address calculation module 84, a mask processing module 85, and a data processing module 86. The accompanying information queue 81 is connected to the control module 83, the address calculation module 84, and the mask processing module 85, respectively, and the data queue 82 is connected to the data processing module 86. It should be understood that the control module 83, the address calculation module 84, the mask processing module 85, and the data processing module 86 can be interconnected within the data conversion module 8.

[0092] The accompanying information queue 81 is used to store accompanying information, a first identification signal, and a data mask signal from the merging module, and the data queue is used to store request data from the merging module.

[0093] The address calculation module 84 is connected to the accompanying information queue 81 and is used to determine the destination address of different thread information based on the accompanying information stored in the accompanying information queue 81. The destination address is used to indicate the location where the requested data is written to the storage unit 5.

[0094] The mask processing module 85 is connected to the accompanying information queue 81 and is used to match the data mask signal stored in the accompanying information queue 81 with the request data to obtain a matching result. The matching result is used to indicate the correspondence between the destination address and the request data.

[0095] The control module 83 is connected to the accompanying information queue 81 and is used to generate a trigger signal representing the completion of instruction information based on the first identification signal stored in the accompanying information queue 81. The trigger signal is used to trigger the data processing device to process the next instruction information. Since the front-end loading storage unit 4 selects a portion of the thread information from all the thread information of the instruction information for processing each time, the data conversion module 8 is not easily aware of the number of thread information of the instruction information. However, the trigger signal generated based on the first identification signal can be used to indicate that all the thread information of the instruction information has been executed, thereby instructing the processor's flow control mechanism (fence mechanism) to execute other instruction information in the next stage.

[0096] The data processing module 86 is connected to the data queue 82 and is used to convert and process the request data stored in the data queue 82, expand it according to a preset direction, and write it into the storage unit 5 indicated by the destination address.

[0097] For example, the data returned by the merging module 6, including accompanying information, a first identifier signal, a data mask signal, and request data, is first sent to the accompanying information queue 81 and the data queue 82. Based on the corresponding accompanying information, the address to be written to the storage unit 5 and the corresponding mask information field active mask are obtained. The address calculation module 84 can calculate the address of the storage unit 5 for different thread information based on the corresponding address information. The mask processing module 85 can match the request data with the corresponding data mask signal and match the byte-level mask information field active mask with the request data based on the data mask signal indicating the byte offset. The data processing module 86 can perform row and column transformation on the current request data, expanding the sent request data in the column direction and writing it to the storage unit 5. The control module 83 can generate a trigger signal based on the first identifier signal stored in the accompanying information queue 81 to determine whether the currently transmitted request data is the last piece of data in the current instruction information, so that the processor's flow control mechanism (fence mechanism) responds to the trigger signal to execute other instruction information in the next stage.

[0098] Compared to data conversion modules in related technologies, the data conversion module 8 of this embodiment reduces the storage logic of the data conversion and storage module, which can effectively reduce the area of ​​the data conversion module 8 and thus reduce its resource usage. Furthermore, reducing the data conversion and storage module reduces the logic of first collecting data and then reading it out, which can greatly improve the efficiency of writing data to the storage unit 5 from a time perspective.

[0099] The data processing apparatus of this disclosure can improve the parallelism of loading instructions by increasing the interface utilization of the loading storage unit 4. For example, it can improve the parallelism of K thread information to P×K thread information without increasing storage overhead, and can also reduce the latency inside the loading storage unit 4.

[0100] The merging module 6 of this data processing device can merge accesses to cache 7 in a single operation by using out-of-order (OOO) execution of data, i.e., merging address information from different threads within different instruction messages, thus reducing the frequency of accesses to cache 7. Furthermore, instruction information from different first units 1 shares the same cache 7, saving internal storage costs for instruction information. Moreover, returning data via out-of-order execution saves data collection time and reduces the latency of the merging module 6 executing loading instructions. Experiments have shown that the request path from the merging module 6 sending a merge address request to cache 7, and the return path from cache 7 returning requested data to the merging module 6, can each reduce latency by approximately two times.

[0101] The data conversion module 8 of this data processing device can save on the storage consumption of internal storage instruction information by adjusting the data storage method. Experiments have shown that the latency of writing data to the storage unit 5 of the data conversion module 8 can be significantly reduced, for example, from 19 clock cycles to 5 clock cycles. The area of ​​the data conversion module 8 can be reduced by approximately 20%.

[0102] By statistically analyzing the system operation time of the data processing device, from the time the instruction transmitter 3 issues the instruction to the time the requested data is written to the storage unit 5, the system latency is significantly reduced and the execution efficiency is significantly improved. For example, the overall latency of the data processing device can be reduced from 127 clock cycles to 75 clock cycles, and the execution efficiency can be improved by 41%.

[0103] As can be seen, the data processing apparatus of this embodiment optimizes the interface utilization of the loading storage unit 4 in executing loading instructions, optimizes the data flow execution operation within the merging module 6, and optimizes the data control and storage operation within the data conversion module 8. This allows the processor to improve overall efficiency and reduce time latency when executing loading instructions. Furthermore, it can reduce the area of ​​the merging module 6 and the data conversion module 8, saving storage resource overhead.

[0104] It is understood that the various method embodiments mentioned above in this disclosure can be combined with each other to form combined embodiments without violating the principle and logic. Due to space limitations, this disclosure will not elaborate further. Those skilled in the art will understand that in the above methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0105] In addition, this disclosure also provides data processing methods, electronic devices, computer-readable storage media, programs, corresponding technical solutions and descriptions, and see the corresponding records in the method section, which will not be repeated here.

[0106] Figure 8 A flowchart illustrating a data processing method according to an embodiment of this disclosure is shown, such as... Figure 8 As shown, the method is applied to a data processing device, which includes a second unit and N first units. Each first unit includes an instruction transmitter, a load storage unit, and a storage unit. The load storage unit includes multiple output data channels, where N is an integer greater than 1. The method includes:

[0107] In step S11, the instruction transmitter sends instruction information to the loading storage unit, the instruction information including multiple thread information;

[0108] In step S12, the loading storage unit parses the instruction information and obtains the address information carried by different thread information from the instruction information;

[0109] In step S13, the loading storage unit uses multiple preset bit fields of each output data channel to place the address information carried by the different thread information, and sends the address information to the second unit at a multiple rate.

[0110] In step S14, the second unit receives the address information from the loading storage unit in different first units, and returns the request data at the address information indication to the corresponding storage unit in the first unit.

[0111] In one possible implementation, step S12 may include: when the loading storage unit includes K output data channels and each output data channel contains P preset bit fields, K multiplied by P thread information is selected from the multiple thread information contained in the instruction information for parsing each time to obtain address information of K multiplied by P thread information; K and P are integers greater than 1; step S13 may include: the loading storage unit uses the P preset bit fields of each output data channel to place the address information carried by the P thread information, and sends K multiplied by P address information to the second unit each time at a rate of P times.

[0112] In one possible implementation, the second unit includes a cache, a data conversion module, and N merging modules. Step S14 may include: the merging module merging the address information from the loading storage unit to generate a merged address request to the cache; the cache responding to the merged address request by returning the request data of the merged address request to the merging module; and the data conversion module obtaining the request data returned by the cache from the merging module and sending it to the corresponding storage unit in the first unit.

[0113] In one possible implementation, the instruction transmitter of the i-th first unit is connected to the i-th merging module of the second unit via the load storage unit of the i-th first unit, the cache of the second unit is connected to N merging modules of the second unit respectively, and the data conversion module of the second unit is connected to N merging modules of the second unit and N storage units of the first unit respectively, where i is any integer from 1 to N.

[0114] In one possible implementation, the merging module includes an expansion unit, a merging unit, a request buffer, and an offset unit. The expansion unit is used to perform cross-cache line judgment on multiple address information from the loading storage unit to obtain a first judgment result. The merging unit is used to merge multiple address information to obtain a merged address request when the first judgment result indicates that multiple address information is in the same cache line. The request buffer is used to record accompanying information of the merged address request and, in response to receiving request data returned by the cache, sends the accompanying information and the request data to the offset unit. The offset unit is used to generate a data mask signal based on the accompanying information and the request data, and the data mask signal is used to indicate the byte offset of storing the request data in the storage unit.

[0115] In one possible implementation, the offset unit is further configured to: determine, based on the request data, whether the request data of the plurality of thread information included in the instruction information has been returned to the data conversion module, and obtain a second determination result; if the second determination result indicates that all request data corresponding to the plurality of thread information has been returned to the data conversion module, generate a first identification signal; wherein, in response to receiving request data of any thread information returned by the request buffer, the offset unit sends the request data to the data conversion module.

[0116] In one possible implementation, the loading storage unit, the expanding unit, and the merging unit are connected in series, the request buffer is connected to the cache, the merging unit, and the offset unit, and the offset unit is connected to the data conversion module.

[0117] In one possible implementation, the data conversion module includes an accompanying information queue, a data queue, a control module, an address calculation module, a mask processing module, and a data processing module. The accompanying information queue stores accompanying information, a first identifier signal, and a data mask signal from the merging module; the data queue stores request data from the merging module. The address calculation module, connected to the accompanying information queue, determines the destination address of different thread information based on the accompanying information stored in the accompanying information queue. The destination address indicates the location where the request data is written to the storage unit. The mask processing module, connected to the accompanying information queue, matches the data mask signal stored in the accompanying information queue with the request data to obtain a matching result. The matching result indicates the correspondence between the destination address and the request data. The control module, connected to the accompanying information queue, generates a trigger signal indicating the completion of instruction information based on the first identifier signal stored in the accompanying information queue. The trigger signal triggers the data processing device to process the next instruction information. The data processing module, connected to the data queue, converts the request data stored in the data queue, expands it according to a preset direction, and writes it to the storage unit indicated by the destination address.

[0118] This method is specifically technically related to the internal structure of computer systems and can solve technical problems of how to improve hardware computing efficiency or execution performance (including reducing data storage, reducing data transmission, and increasing hardware processing speed), thereby achieving technical effects that improve the internal performance of computer systems in accordance with natural laws.

[0119] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0120] This disclosure also proposes a computer-readable storage medium storing computer program instructions that, when executed by a processor, implement the above-described method. The computer-readable storage medium can be volatile or non-volatile.

[0121] This disclosure also proposes an electronic device, including: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to invoke the instructions stored in the memory to execute the above-described method.

[0122] This disclosure also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is run in a processor of an electronic device, the processor in the electronic device performs the above-described method.

[0123] Electronic devices can be provided as terminals, servers, or other forms of devices.

[0124] Figure 9 A block diagram of an electronic device 1900 according to an embodiment of the present disclosure is shown. For example, the electronic device 1900 may be provided as a server or a terminal device. (Refer to...) Figure 9 The electronic device 1900 includes a processing component 1922, which further includes one or more processors, and memory resources represented by memory 1932 for storing instructions, such as application programs, that can be executed by the processing component 1922. The application programs stored in memory 1932 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processing component 1922 is configured to execute instructions to perform the methods described above.

[0125] Electronic device 1900 may also include a power supply component 1926 configured to perform power management of electronic device 1900, a wired or wireless network interface 1950 configured to connect electronic device 1900 to a network, and an input / output interface 1958. Electronic device 1900 can operate on an operating system stored in memory 1932, such as a Microsoft Server operating system (Windows Server). TM Apple's graphical user interface-based operating system (Mac OS X) TM ), a multi-user, multi-process computer operating system (Unix) TM Linux is a free and open-source Unix-like operating system. TM ), an open-source Unix-like operating system (FreeBSD) TM (or similar.)

[0126] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by a processing component 1922 of an electronic device 1900 to perform the above-described method.

[0127] This disclosure can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of this disclosure.

[0128] Computer-readable storage media can be tangible devices capable of holding and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example, (but not limited to) electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination of the foregoing. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0129] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0130] Computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing the status information of the computer-readable program instructions to implement various aspects of this disclosure.

[0131] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0132] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0133] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0134] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0135] The computer program product can be implemented specifically through hardware, software, or a combination thereof. In one alternative embodiment, the computer program product is specifically embodied in a computer storage medium; in another alternative embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0136] The description of the various embodiments above tends to emphasize the differences between the various embodiments. The similarities or similarities between them can be referred to, and for the sake of brevity, they will not be repeated here.

[0137] Those skilled in the art will understand that, in the above-described method of the specific implementation, the order in which each step is written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0138] If the technical solution of this application involves personal information, the product using this technical solution has clearly informed the user of the personal information processing rules and obtained the user's voluntary consent before processing the personal information. If the technical solution of this application involves sensitive personal information, the product using this technical solution has obtained the user's separate consent before processing the sensitive personal information, and also meets the requirement of "express consent". For example, at personal information collection devices such as cameras, clear and prominent signs are set up to inform users that they have entered the scope of personal information collection and that personal information will be collected. If an individual voluntarily enters the collection scope, it is deemed that they have agreed to the collection of their personal information; or on the personal information processing device, with clear signs / information informing users of the personal information processing rules, authorization is obtained from the individual through pop-up information or by asking the individual to upload their personal information; wherein, the personal information processing rules may include information such as the personal information processor, the purpose of personal information processing, the processing method, and the types of personal information processed.

[0139] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A data processing apparatus, characterized in that, The data processing device includes a second unit and N first units. Each first unit includes an instruction transmitter, a loading storage unit, and a storage unit. The loading storage unit includes multiple output data channels, where N is an integer greater than 1. The instruction transmitter sends instruction information to the loading storage unit, and the instruction information includes multiple thread information. The loading storage unit parses the instruction information and obtains the address information carried by different thread information from the instruction information; Multiple preset bit fields of each output data channel of the loading storage unit are used to place the address information carried by the different thread information, so that the loading storage unit sends the address information to the second unit at a multiple rate; The second unit receives the address information from the loading storage unit in different first units, and returns the request data at the address information indication to the corresponding storage unit in the first unit.

2. The data processing apparatus according to claim 1, characterized in that, When the loading storage unit includes K output data channels, and each output data channel contains P preset bit fields, where K and P are integers greater than 1, the loading storage unit is used for: Each time, K multiplied by P thread information is selected from the multiple thread information contained in the instruction information for parsing to obtain the address information of K multiplied by P thread information; The P preset bit fields of each output data channel of the loading storage unit are used to store the address information carried by the P thread information, so that the loading storage unit sends K times P address information to the second unit at a rate of P times each time.

3. The data processing apparatus according to claim 1 or 2, characterized in that, The second unit includes a cache, a data conversion module, and N merging modules; The merging module merges the address information from the loading storage unit and generates a merged address request to the cache; The cache responds to the merge address request by returning the request data for the merge address request to the merging module; The data conversion module obtains the request data returned by the cache from the merging module and sends it to the storage unit in the corresponding first unit.

4. The data processing apparatus according to claim 3, characterized in that, The instruction transmitter of the i-th first unit is connected to the i-th merging module of the second unit via the loading storage unit of the i-th first unit. The cache of the second unit is connected to the N merging modules of the second unit respectively. The data conversion module of the second unit is connected to the N merging modules of the second unit and the storage units of the N first units respectively. i is any integer from 1 to N.

5. The data processing apparatus according to claim 3, characterized in that, The merging module includes an expansion unit, a merging unit, a request buffer, and an offset unit. The expansion unit performs cross-cache line judgment on multiple address information from the loading storage unit to obtain a first judgment result; When the first judgment result indicates that multiple address information is in the same cache line, the merging unit merges the multiple address information to obtain a merged address request; The request buffer records the accompanying information of the merged address request, and in response to receiving the request data returned by the cache, sends the accompanying information and the request data to the offset unit; The offset unit generates a data mask signal based on the accompanying information and the requested data. The data mask signal is used to indicate the byte offset of storing the requested data in the storage unit.

6. The data processing apparatus according to claim 5, characterized in that, The offset unit is also used for: Based on the request data, determine whether the request data containing the multiple thread information included in the instruction information has been returned to the data conversion module, and obtain a second determination result; If the second determination result indicates that all request data corresponding to the multiple thread information has been returned to the data conversion module, a first identification signal is generated; In response to receiving request data of any thread information returned by the request buffer, the offset unit sends the request data to the data conversion module.

7. The data processing apparatus according to claim 5, characterized in that, The loading storage unit, the expanding unit, and the merging unit are connected in series. The request buffer is connected to the cache, the merging unit, and the offset unit. The offset unit is connected to the data conversion module.

8. The data processing apparatus according to claim 3, characterized in that, The data conversion module includes an accompanying information queue, a data queue, a control module, an address calculation module, a mask processing module, and a data processing module. The accompanying information queue is used to store accompanying information, a first identification signal, and a data mask signal from the merging module, and the data queue is used to store request data from the merging module. The address calculation module is connected to the accompanying information queue and is used to determine the destination address of different thread information based on the accompanying information stored in the accompanying information queue. The destination address is used to indicate the location where the requested data is written to the storage unit. The mask processing module is connected to the accompanying information queue and is used to match the data mask signal stored in the accompanying information queue with the request data to obtain a matching result. The matching result is used to indicate the correspondence between the destination address and the request data. The control module is connected to the accompanying information queue and is used to generate a trigger signal representing the completion of the instruction information based on the first identification signal stored in the accompanying information queue. The trigger signal is used to trigger the data processing device to process the next instruction information. The data processing module is connected to the data queue and is used to transform the request data stored in the data queue, expand it according to a preset direction, and write it into the storage unit indicated by the destination address.

9. A data processing method, characterized in that, The method is applied to a data processing device, which includes a second unit and N first units. Each first unit includes an instruction transmitter, a load storage unit, and a storage unit. The load storage unit includes multiple output data channels, where N is an integer greater than 1. The method includes: The instruction transmitter sends instruction information to the loading storage unit, and the instruction information includes multiple thread information. The loading storage unit parses the instruction information and obtains the address information carried by different thread information from the instruction information; The loading storage unit uses multiple preset bit fields of each output data channel to place the address information carried by the different thread information, and sends the address information to the second unit at a multiple rate. The second unit receives the address information from the loading storage unit in different first units, and returns the request data at the address information indication to the corresponding storage unit in the first unit.

10. A processor, characterized in that, The processor includes the data processing apparatus as described in any one of claims 1 to 8.

11. A chip, characterized in that, The chip includes the processor as described in claim 10.

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