Bus access control device, chip and electronic equipment

Abstract

The invention discloses a bus access control device, a chip and electronic equipment, the bus access control device comprises a configuration module and a control module, the configuration module is used for receiving configuration information from a bus, updating access configuration according to the configuration information, and sending the configuration information to the control module; and the control module is used for receiving the access information, judging whether the access information is matched with the current access configuration according to the configuration information, and if so, sending the access information to the bus to realize the access of the host to the target slave. According to the bus access control device, updating switching of the access configuration can be achieved, normal operation of the chip is not affected when the access configuration is updated, the chip outputs an expected result, the reliability of the chip is improved, the application scene of the chip is expanded, and the application range of the chip is wide.

Description

Technical Field

[0001] This application relates to the field of bus communication technology, specifically to a bus access control device, chip, and electronic device. Background Technology

[0002] With the development of technology and the times, the complexity of various electronic systems is constantly increasing due to application requirements, thus raising the bar for precise control. In different application scenarios, the master can access different slave devices to perform operations such as reading and writing data. If an incorrect access operation is performed on a slave device under unexpected circumstances, it may cause internal chip failure. Conversely, if the master cannot operate on the slave device when data needs to be read or written, it will also produce unexpected results, leading to chip failure.

[0003] In related technologies, control of the host's access to the slave is controlled by adding control logic on the host side. However, this method usually completes the access configuration when the chip is first started and maintains the configuration information while the chip is working. If the access configuration is switched while the chip is working, it may cause the chip to malfunction and fail to operate normally. Summary of the Invention

[0004] In view of the above problems, this application provides a bus access control device, chip, and electronic device to solve the above technical problems.

[0005] In a first aspect, this application provides a bus access control device, which includes a configuration module and a control module;

[0006] The configuration module, connected to the bus, is used to receive configuration information from the bus, update the access configuration according to the configuration information, and send the configuration information to the control module. The access configuration is the access configuration of the master to multiple slave devices on the bus stored in the configuration module.

[0007] The control module, connected to the host and the bus, is used to receive access information from the host for the target slave on the bus, and determine whether the access information matches the host's current access configuration for the target slave based on the configuration information. If so, the access information is sent to the bus to enable the host to access the target slave.

[0008] This bus access control device can receive configuration information through a configuration module connected to the bus, thereby updating the master's access configuration to multiple slave devices on the bus stored in the configuration module. Then, the control module completes the master's access control to the slave devices according to the new configuration information, realizing the switching and updating of configuration information without affecting the operation of the chip, thus expanding the application scenarios of the chip.

[0009] Secondly, this application also provides a chip, including a chip body and the aforementioned bus access control device disposed on the chip body.

[0010] Thirdly, this application also provides an electronic device, including a device body and a bus access control device or chip as described above disposed on the device body.

[0011] The bus access control device provided in this application receives configuration information through a configuration module connected to the bus, and updates the access configuration of the master to multiple slave devices on the bus stored in the configuration module according to the configuration information. The control module receives the access information of the master for the target slave device, and completes the access control of the master to the target slave device according to the new configuration information. It can not only realize the updating and switching of access configuration, but also ensure that the normal operation of the chip is not affected when updating the access configuration, so that the chip outputs the expected results, improves the reliability of the chip, expands the application scenarios of the chip, and makes it widely applicable. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of an application scenario of the bus access control device provided in the embodiments of this application;

[0014] Figure 2 This is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0015] Figure 3 This is a schematic diagram of a bus access control device provided in the embodiments of this application;

[0016] Figure 4 This is a schematic diagram of a configuration module provided in an embodiment of this application;

[0017] Figure 5 This is a timing diagram illustrating the transmission of configuration information provided in the embodiments of this application;

[0018] Figure 6 This is a schematic diagram of a control module provided in an embodiment of this application;

[0019] Figure 7 This is another structural schematic diagram of the control module provided in the embodiments of this application;

[0020] Figure 8This is another schematic diagram of the bus access control device provided in the embodiments of this application;

[0021] Figure 9 This is a schematic diagram of a bus access control device provided in an embodiment of this application;

[0022] Figure 10 This is a schematic diagram of the interrupt control module provided in an embodiment of this application;

[0023] Figure 11 This is a schematic diagram of one possible data flow provided in the embodiments of this application. Detailed Implementation

[0024] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0025] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0026] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0027] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or device. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device that includes said element.

[0028] In the description of the embodiments of this application, the words "example" or "for example" are used to indicate exemplification, illustration, or description. Any embodiment or design described as "example" or "for example" in the embodiments of this application is not to be construed as being more preferred or having more advantages than another embodiment or design. The use of the words "example" or "for example" is intended to present relative concepts in a clear manner.

[0029] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.

[0030] It should be noted that in the embodiments of this application, "and / or" describes the relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after it are in an "or" relationship.

[0031] Before introducing the bus access control device, chip, and electronic device of this application, we will first introduce the relevant background information of the embodiments of this application.

[0032] With the development of technology and the times, the complexity of various electronic systems is constantly increasing due to application requirements, thus demanding ever-higher precision control. For example, in a microcontroller unit (MCU), there may be multiple master units (devices that actively issue commands to acquire data and perform other related operations). However, for slave units, not all master units can access them to read or write data in different application scenarios. If an incorrect access operation is performed on a slave unit under unexpected circumstances, it may cause internal chip failure. Conversely, if the slave unit cannot be accessed when data needs to be read or written, it will also produce unexpected results, leading to chip failure.

[0033] Therefore, in order to restrict and control the master's access to the slave, the following two methods are commonly used: one is to restrict the address space on the bus matrix or bus network. By sorting out the application scenario in the register-transfer level (RTL) code stage of the chip, the relevant address range is set on the bus matrix or bus network; the other is to add identification (ID) information to perform ID recognition on the slave side, so as to determine whether the access of the master corresponding to the ID is supported, that is, read and / or write operations.

[0034] However, both of these methods in the relevant technologies have certain drawbacks. For the first method, the address control restrictions of the bus matrix are designed during chip manufacturing and cannot be modified later. Therefore, it has significant limitations for flexible and ever-changing scenarios. At the same time, this method cannot restrict the access permissions of the master. For example, sometimes the master is not allowed to access the slave, while in certain situations the master is allowed to perform read or read-write operations. For the second method, in most chips, the number of slaves is greater than the number of masters. When the number of slaves is large and the number of masters that need to be modified is small, the ID-based method becomes very complex. In addition, the ID method on the slave side can only restrict the master's operation on the slave side, but cannot restrict the master from issuing the operation command. Therefore, even if the operation command issued by the master does not meet the requirements, the master will still try to access through the bus matrix. This will reduce the working efficiency of the bus matrix.

[0035] Based on the problems of the above two methods, related technologies control the host's access to the slave device by adding control logic on the host side. This method largely makes up for the previous shortcomings. However, this method usually completes the access configuration when the chip is first started and maintains the configuration information while the chip is working. However, in some special or flexible scenarios, it is often necessary to switch the access configuration while the chip is working. If the configuration is modified at this time, it is very likely to cause the chip to malfunction and fail to operate normally.

[0036] Based on this, embodiments of this application provide a bus access control device, a chip, and an electronic device, which will be described in detail below.

[0037] Please see Figure 1 , Figure 1This is a schematic diagram of an application scenario of the bus access control device provided in the embodiments of this application. The bus access control device 100 can be integrated into the chip 200. It is understood that the chip 200 can be a system on a chip (SOC), a system in package (SIP) chip, etc., and the specific chip can be determined according to the actual application scenario.

[0038] Specifically, such as Figure 2 As shown, the chip 200 may include a bus 210, a master 220, a central processing unit (CPU) 230, and multiple slave devices connected to the bus 210. It can be understood that... Figure 1 The example shown here only has 3 slave devices. In other application scenarios, the number of slave devices can be 2, 4 or more. The specific number can be set according to the actual application scenario, and there is no limit here.

[0039] The bus access control device 100 can be located on the output terminal of the host 220 in the data flow direction from the host 220 to the slave. That is, the host 220 can be connected to the bus 210 through the bus access control device 100. The chip 200 can configure the bus access control device 100 through the central processing unit (CPU) 230, thereby enabling the host 220 to control access to the slave based on the bus access control device 100.

[0040] Those skilled in the art will understand that Figure 1 and Figure 2 The corresponding application environment is merely one application scenario adapted to the solution of this application, and does not constitute a limitation on the application scenario of the solution of this application. The bus access control device 100 of this application or the chip 200 integrating the bus access control device 100 can be applied in application scenarios such as communication, audio amplifiers, display devices, and automobiles, and no specific limitation is made here.

[0041] Please see Figure 3 , Figure 3 This is a schematic diagram of a bus access control device provided in the embodiments of this application. The bus access control device 100 may include a configuration module 110 and a control module 120 connected in communication.

[0042] The configuration module 110 can also be connected to the bus 210 to receive configuration information from the bus 210, update the access configuration according to the configuration information, and send the configuration information to the control module 120. The access configuration is the access configuration of the master 220 to multiple slave devices on the bus 210 stored in the configuration module 110.

[0043] The control module 120 can also be connected to the host 220 and the bus 210 to receive access information from the host 220 for the target slave 240 on the bus 210, and determine whether the access information matches the current access configuration of the host 220 for the target slave 240 based on the configuration information from the configuration module 110. If so, the access information is sent to the bus 210 to realize the access of the host 220 to the target slave 240 based on the bus 210.

[0044] In this embodiment of the application, the access configuration of the host 220 to multiple slave devices on the bus 210 stored in the configuration module 110 can be configured through configuration information. Specifically, the configuration information can be issued by the central processing unit (CPU) 230 or by other unit modules in the chip 200.

[0045] In this embodiment, the central processing unit (CPU) 230 is used as an example. The CPU 230 can send configuration information to the bus 210, and then transmit the configuration information to the configuration module 110 via the bus 210. The configuration module 110 can update the access configuration of the host 220 to multiple slave devices on the bus 210 stored in itself based on the received configuration information. In addition, the configuration module 110 can also send the configuration information to the control module 120 for subsequent matching of access information and access configuration.

[0046] The control module 120 is connected to the host 220, thereby receiving access information from the host 220. This access information indicates that the host 220 currently wants to access a target slave 240 among multiple slaves, that is, to interact with the target slave 240. It is worth noting that... Figure 3 The slave device 2 shown is only one example of this application. In other application scenarios, the target slave device 240 can also be slave device 1, slave device 3 or other slave devices not shown. The number of target slave devices can also be 2, 3 or more. The number and selection of target slave devices can be determined according to the actual application scenario, and are not limited here.

[0047] In this embodiment of the application, when the host 220 needs to interact with the target slave 240, it can send an access request. The access request can carry access information for the target slave 240. The control module 120 can extract the access information from the access request and determine whether the access information matches the current access configuration of the host 220 for the target slave 240 according to the configuration information sent by the configuration module 110. In other words, it determines whether the current access request meets the requirements, that is, whether the host 220 can access the target slave 240 and interact with it.

[0048] If the access information matches the current access configuration, it means that the access request meets the requirements. The host 220 can access the target slave 240 and interact with it. The control module 120 can then transmit the access information to the bus 210, enabling the host 220 to access the target slave 240 based on the bus 210. In other words, the host 220 can interact with the target slave 240 based on the bus 210.

[0049] The bus access control device 100 provided in this application embodiment receives configuration information through a configuration module 110 connected to the bus 210, and updates the access configuration of the host 220 to multiple slave devices on the bus 210 stored in the configuration module 110 according to the configuration information. The control module 120 receives the access information of the host 220 for the target slave device 240, and completes the access control of the host 220 to the target slave device 240 according to the new configuration information. It can not only realize the updating and switching of access configuration, but also does not affect the normal operation of the chip when updating the access configuration, so that the chip outputs the expected result, improves the reliability of the chip, expands the application scenarios of the chip, and makes its application range wide.

[0050] Next, continue with Figure 3 The modules shown are described in detail, along with the specific implementation methods that may be used in practical applications.

[0051] Please see Figure 4 In some embodiments of this application, the configuration module 110 may include a configuration subunit 1101 and a configuration switching subunit 1102. The configuration subunit 1101 may be connected to the bus 210 and is used to receive and store configuration information, and to transmit configuration information to the configuration switching subunit 1102 in response to a transmission signal. The configuration switching subunit 1102 may be used to send a transmission signal to the configuration subunit 1101 when the status register of the control module 120 is in a valid state, and to update the access configuration according to the received configuration information. The status register is in the valid state when the control module 120 has completed the transmission of the previous access information or is in a non-working state.

[0052] In this embodiment of the application, the configuration subunit 1101 is connected to the bus 210 to receive and store configuration information. Specifically, the configuration subunit 1101 may be configured with a shadow register, and the configuration information from the bus 210 may be written into the shadow register for storage.

[0053] For example, the central processing unit (CPU) 230 can respond to a configuration update instruction by writing the configuration information carried in the configuration update instruction into the shadow register of the configuration subunit 1101 via bus 210. Since the configuration information is written to the shadow register for storage, it will not affect the normal operation of the chip.

[0054] It is understood that the shadow register in the embodiments of this application can be one, two or more, and the specific number can be determined according to the information type or amount of information in the configuration information, etc., which is not limited here.

[0055] In this embodiment of the application, in order to avoid affecting the previous access of the host 220 when updating the access configuration, a status register is configured for the control module 120, and the status register is used to characterize the working status of the control module 120.

[0056] It is understood that updating the access configuration when the control module 120 is idle or not working will not affect the host 220's previous access to the slave. Therefore, when the control module 120 is idle, for example, after the transmission of the host 220's previous access information has been completed, or when it is not working, the status register can be set to an active state. This active state can be used to indicate that the access configuration can be updated at present.

[0057] When the control module 120 is in a working state, such as when it is matching the access configuration of the previous access information, the status register can be set to an occupied state to indicate that the control module 120 is working. If the access configuration is updated at this time, it is easy to produce unexpected results and cause the chip to fail.

[0058] Therefore, when the configuration switching subunit 1102 detects that the status register is in an active state, it can send a transmission signal to the configuration subunit 1101. This transmission signal can be a pulse signal, which causes the configuration subunit 1101 to transmit the configuration information stored in the shadow register to the configuration switching subunit 1102 in response to the transmission signal, so as to update the access configuration of the host 220 to multiple slaves on the bus 210.

[0059] In this embodiment of the application, the configuration switching subunit 1102 may be configured with a real register, and the configuration subunit 1101 may, in response to the transmission signal, transmit the configuration information stored in the shadow register to the real register of the configuration switching subunit 1102 for storage, so as to realize the update of the access configuration.

[0060] If new configuration information is written to the shadow register of configuration subunit 1101, configuration switching subunit 1102 detects that the status register is in an occupied state. It needs to keep the current configuration information unchanged until the status register changes from the occupied state to the valid state before sending a transmission signal to configuration subunit 1101 to obtain the new configuration information and realize configuration update.

[0061] like Figure 5As shown, in one specific implementation, both the status register and the transmission signal can be represented as active high. When the status register changes from low to high, the configuration switching subunit 1102 is triggered to generate the transmission signal, so that the configuration information stored in the shadow register of the configuration subunit 1101 can be transmitted to the real register of the configuration switching subunit 1102 to complete the update of the access configuration.

[0062] Understandable. Figure 5 This is merely an example of how configuration information can be transmitted in this application; in actual applications... Figure 5 The generation of each signal shown can be designed according to the actual bus timing to achieve low latency. For example, taking the Advanced eXtensible Interface (AXI) bus read operation as an example, the last data read indication signal of the target slave corresponding to the previous access, i.e., the rlast signal, can be used as the key signal to trigger the state transition of the status register, that is, the status register will jump from low level to high level after the last data read; or the flag signal or flag bit of the previous access end can be used to trigger the state transition of the status register of the control module 120. The specific settings can be set according to the actual application scenario, and are not limited here.

[0063] To prevent accidental operations from writing unexpected configuration information, in some embodiments of this application, the configuration subunit 1101 may be configured with a first latch bit lock1. The configuration subunit 1101 may be used to: lock the configuration information based on the first latch bit lock1 after the configuration switching subunit 1102 updates the access configuration according to the received configuration information, and receive and store new configuration information after unlocking the first latch bit lock1.

[0064] In this embodiment of the application, after the configuration switching subunit 1102 updates the access configuration according to the configuration information, the configuration information in the configuration subunit 1101 can be locked by the first latch bit lock1. For example, when it is active high, the first latch bit lock1 is pulled high to lock the configuration information in the configuration subunit 1101. After locking, new configuration information is not allowed to be written. That is to say, even if the central processing unit (CPU) 230 sends new configuration information to the configuration subunit 1101 through the bus 210, the new configuration information cannot be written into the shadow register of the configuration subunit 1101.

[0065] If new configuration information needs to be written after locking, the first latch bit lock1 can be pulled low to unlock, or the latch can be unlocked by writing to the lock / unlock register corresponding to the first latch bit lock1. After unlocking, the central processing unit (CPU) 230 can issue new configuration information and write it to the shadow register of the configuration subunit 1101.

[0066] In some other embodiments of this application, the configuration switching subunit 1102 may be configured with a second latch bit lock2. The configuration switching subunit 1102 may be used to: after updating the access configuration according to the received configuration information, lock the configuration information based on the second latch bit lock2; and after unlocking the second latch bit lock2 and when the status register of the control module 120 is in a valid state, send a transmission signal to the configuration subunit 1101 to obtain new configuration information.

[0067] In this embodiment of the application, after the configuration switching subunit 1102 updates the access configuration according to the configuration information, the configuration information in the configuration switching subunit 1102, i.e. the access configuration, can be locked by the second latch bit lock2. For example, in the case of active low, the second latch bit lock2 is pulled low to lock the configuration information in the configuration switching subunit 1102. After locking, new configuration information is not allowed to be written. That is to say, even if the central processing unit (CPU) 230 writes new configuration information to the shadow register of the configuration subunit 1101 through the bus 210 and the status register of the control module 120 is in an active state, the new configuration information cannot be written to the real register of the configuration switching subunit 1102 for access configuration switching update.

[0068] If configuration information needs to be updated after locking, the second latch bit lock2 can be pulled high to unlock, or the lock can be unlocked by writing to the lock release register corresponding to the second latch bit lock2. After unlocking, if the status register of the control module 120 is in a valid state, the configuration switching subunit 1102 can send a transmission signal to the configuration subunit 1101, so that the new configuration information stored in the shadow register of the configuration subunit 1101 can be transmitted to the real register of the configuration switching subunit 1102, and the switching update of the access configuration can be realized through the new configuration information.

[0069] like Figure 6As shown, in some embodiments of this application, the control module 120 may include an address access control subunit 1201, which may be connected to the configuration module 110, the host 220 and the bus 210. The address access control subunit 1201 may be used to determine whether the access address carried in the access information belongs to the accessible address range in the current access configuration of the host 220 to the target slave 240. If so, the access information is sent to the bus 210.

[0070] In different application scenarios, the central processing unit (CPU) 230 or other unit modules can configure the allowed access address range of the host 220 stored in the configuration module 110 based on configuration information. Here, the allowed access address range of the host 220 is also the access address range that the slave device, such as the target slave device 240, can access. In this embodiment, the address access control subunit 1201 implements the address judgment function, comparing the access address carried in the access information sent by the host 220 with the accessible address range in the current access configuration of the host 220 for the target slave device 240. If the access address belongs to the accessible address range, that is, if the access address is within the accessible address range, the access information can be transmitted to the bus 210 to allow the host 220 to access the target slave device 240.

[0071] It is understandable that the host 220 may have different access permissions or operation permissions for different slave devices or different ranges of accessible addresses. Therefore, after the access address meets the requirements, the access permissions carried in the access information can be further judged.

[0072] In some embodiments of this application, the control module 120 may further include an access control subunit 1202, which may be connected to the configuration module 110 and the address access control subunit 1201. The address access control subunit 1201 may be used to send access information to the access control subunit 1202 when the access address is within the range of accessible addresses. The access control subunit 1202 may be used to determine whether the access permission carried in the access information belongs to the access permission range in the current access configuration of the host 220 to the target slave 240. If so, the access information is sent to the bus 210.

[0073] In different application scenarios, the access permission range of the host 220 allowed to access address range stored in the configuration module 110 can be configured by the central processing unit (CPU) 230 or other unit modules based on the configuration information, such as read-only, write-only, read-write, etc.

[0074] In this embodiment, after the access address of the host 220 falls within the accessible address range, the permission control subunit 1202 can perform permission judgment. The access permission carried in the access information issued by the host 220 is compared with the permission range in the host 220's current access configuration for the target slave 240. That is, the access permission carried in the access information is compared with the permission range configured for the access address. If the access permission falls within the set permission range, for example, if the access address is configured with read-only permission and the access permission carried in the access information is also read-only, then the address and permission of the host 220's current access are considered to meet the requirements. The access information is then transmitted to a downstream module, such as the bus 210, to allow the host 220 to access the target slave 240.

[0075] like Figure 8 As shown, in some embodiments of this application, the bus access control device 100 may further include an interrupt control module 130, which may be connected to the control module 120 and is used to generate an interrupt signal output when the access information does not match the current access configuration of the host 220 to the target slave 240.

[0076] In this embodiment of the application, when the access information of the host 220 does not match the current access configuration of the host 220 to the target slave 240, that is, when the access information does not meet the requirements, the interrupt control module 130 can generate an interrupt signal and output it to the target unit module (not shown in the figure) to prompt the target unit module that the access does not meet the requirements and to perform subsequent processing.

[0077] It is understood that the target unit module can be a central processing unit (CPU) 230 or other unit modules, which can be determined according to the actual application scenario. Based on the received interrupt signal, the target unit module can know that the access information does not meet the requirements or that an error has occurred in the access, and further processing is required.

[0078] As can be seen from the foregoing embodiments, the access information can carry an access address and access permissions. When both the access address and access permissions satisfy the current access configuration, the host 220 can access the target slave 240 via the bus 210. If either the access address or the access permissions does not satisfy the current access configuration, it means that the access information does not meet the requirements. Therefore, in some embodiments of this application, the interrupt control module 130 can be configured as follows:

[0079] An interrupt signal is generated in response to an address error interrupt event or a permission error interrupt event from the control module 120. The address error interrupt event indicates that the access address carried in the access information does not belong to the range of accessible addresses in the current access configuration, and the permission error interrupt event indicates that the access permission carried in the access information does not belong to the range of permissions in the current access configuration.

[0080] like Figure 9 As shown, the control module 120 includes an address access control subunit 1201 and a permission control subunit 1202, both of which can be connected to the interrupt control module 130. When the address access control subunit 1201 determines that the access address carried in the access information does not belong to the accessible address range in the current access configuration, it can generate an address error interrupt event and output it to the interrupt control module 130, thereby enabling the interrupt control module 130 to generate an interrupt signal based on the address error interrupt event.

[0081] When the address access control subunit 1201 determines that the access address carried in the access information belongs to the range of accessible addresses in the current access configuration, it outputs the access information to the permission control subunit 1202 for permission judgment. When the permission control subunit 1202 determines that the access permission carried in the access information does not belong to the permission range in the current access configuration, it can generate a permission error interrupt event and output it to the interrupt control module 130, so that the interrupt control module 130 can generate an interrupt signal based on the permission error interrupt event.

[0082] If the access control subunit 1202 determines that the access permission carried in the access information belongs to the permission range in the current access configuration, it can output the access information to the bus 210 to enable the host 220 to access the target slave 240.

[0083] In some embodiments of this application, the interrupt control module 130 may also be used to: record the access address when the access address carried in the access information does not belong to the range of accessible addresses in the current access configuration; and record the access permission and the access address corresponding to the access permission in the access information when the access permission carried in the access information does not belong to the range of permissions in the current access configuration.

[0084] In this embodiment, the interrupt control module 130 can also have an information recording function. Specifically, when the access address is incorrect, i.e., it does not belong to the range of accessible addresses in the current access configuration, the interrupt control module 130 can record the access address at this time. When the central processing unit (CPU) 230 or other unit modules detect an interrupt signal, they can read the access address that caused the erroneous access, so that the software can locate the error in the application operation in subsequent work. Similarly, when the permission judgment is incorrect, i.e. the access permission does not belong to the range of permissions in the current access configuration, the interrupt control module 130 can record the access permission at this time and the access address corresponding to the access permission. When the central processing unit (CPU) 230 or other unit modules detect an interrupt signal, they can read the access address and access permission that caused the permission error, so that the software can locate the error in the application operation in subsequent work.

[0085] like Figure 10 As shown in this embodiment, an address information recording register 1301 and a permission information recording register 1302 can be configured for the interrupt control module 130. When the access address is incorrect, the address information recording register 1301 records the incorrect access address; when the access permission is incorrect, the access permission is recorded by the permission information recording register 1302, and the access address corresponding to the incorrect access permission is also recorded by the address information recording register 1301.

[0086] In this embodiment, the interrupt control module 130 can perform interrupt control, including but not limited to an interrupt enable bit (used to enable or disable interrupts) and an interrupt status bit (used to record the event that generated the interrupt and whether an interrupt occurred). It can also record information; when an address or permission error occurs, in addition to returning an error signal to the bus 210 and generating an interrupt signal to implement an interrupt, it can also record the access address at the time of the error. If there is a permission error, it can also record the incorrect access permissions for the corresponding address segment at that time. The information recorded in the address information recording register 1301 and the permission information recording register 1302 can be obtained by reading the registers, thereby allowing for rapid error location and problem correction at the software level.

[0087] The following is based on Figure 11 The data flow illustrates the specific application of the bus access control device 100 provided in the embodiments of this application.

[0088] First, the central processing unit (CPU) 230 sends configuration information through the bus 210 to complete the configuration of the bus access control device 100, as shown in path ①. After the configuration is completed, the host 220 initiates an access operation to the target slave 240, as shown in path ②. This access operation carries the access address and access permissions. The bus access control device 100 judges the access address and access permissions. If the access address is within the configured accessible address range and the access permissions are within the configured permission range, the host 220 accesses the device normally, as shown in path ③. If either the access address or the access permissions do not meet the requirements, the access is prohibited, and an interrupt signal is generated to prompt the central processing unit (CPU) 230 or other unit modules to perform subsequent processing, as shown in path ④.

[0089] The bus access control device 100 provided in this application embodiment can configure different access addresses and access permissions in different application scenarios. The application scenarios are flexible and rich, while reducing the complexity of chip use and design. By using the information recording register, the convenience of use and debugging capability of the chip software level are improved from the application perspective, and problems that occur during operation can be discovered and solved more intuitively.

[0090] Based on the above embodiments, this application also provides a chip, which may include a chip body and such as Figures 1 to 10 The bus access control device 100 in any embodiment can switch and update configuration information without affecting the operation of the chip, thus expanding the application scenarios of the chip.

[0091] The chip can be an integrated circuit (IC), also known as a microcircuit, microchip, or wafer / chip. The chip can be, but is not limited to, a system-on-chip (SOC) or a system-in-package (SIP) chip.

[0092] Because the chip is equipped with the bus access control device 100 of the above embodiments, it has all the beneficial effects of the bus access control device 100 in any of the above embodiments, which will not be repeated here.

[0093] This application also provides an electronic device, which may include a device body and a bus access control device or chip, as described above, disposed on the device body. The electronic device may be, but is not limited to, a display device, an automotive central control screen, an automobile, a smart wearable device, a mobile terminal, or a smart home device.

[0094] Display devices include, but are not limited to, conference tablets and large commercial displays. Smart wearable devices include, but are not limited to, smartwatches, smart bracelets, and neck massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablets, and point-of-sale (POS) terminals. Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart robot vacuums, and smart lights.

[0095] Because the electronic device is equipped with the bus access control device of the above embodiments, it has all the beneficial effects of the bus access control device in any of the above embodiments, which will not be repeated here.

[0096] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A bus access control device, characterized in that, Includes configuration and control modules; The configuration module is connected to the bus and is used to receive configuration information from the bus, update the access configuration according to the configuration information, and send the configuration information to the control module. The access configuration is the access configuration of the host to multiple slave devices on the bus stored in the configuration module. The control module is connected to the host and the bus, and is used to receive access information from the host for a target slave on the bus, and determine whether the access information matches the host's current access configuration for the target slave according to the configuration information. If so, the access information is sent to the bus to enable the host to access the target slave.

2. The bus access control device according to claim 1, characterized in that, The configuration module includes a configuration subunit and a configuration switching subunit; The configuration subunit is connected to the bus and is used to receive and store the configuration information, and to transmit the configuration information to the configuration switching subunit in response to a transmission signal. The configuration switching subunit is used to send the transmission signal to the configuration subunit when the status register of the control module is in a valid state, and to update the access configuration according to the received configuration information, wherein the status register is in the valid state when the control module completes the transmission of the previous access information or is in a non-working state.

3. The bus access control device according to claim 2, characterized in that, The configuration switching subunit is configured with a real register, and the configuration subunit is configured with a shadow register corresponding to the real register; The shadow register is used to store the configuration information and, in response to the transmission signal, to transmit the configuration information to the real register to update the access configuration.

4. The bus access control device according to claim 2, characterized in that, The configuration subunit is configured with a first latch bit, and the configuration subunit is used to: lock the configuration information based on the first latch bit after the configuration switching subunit updates the access configuration according to the received configuration information; and to receive and store new configuration information after unlocking the first latch bit; or, The configuration switching subunit is configured with a second latch bit. The configuration switching subunit is used to: after updating the access configuration according to the received configuration information, lock the configuration information based on the second latch bit; and after unlocking the second latch bit and when the status register of the control module is in the valid state, send the transmission signal to the configuration subunit to obtain new configuration information.

5. The bus access control device according to claim 1, characterized in that, The control module includes an address access control subunit, which is connected to the configuration module and the host. The address access control subunit is used to determine whether the access address carried in the access information belongs to the accessible address range in the current access configuration of the host to the target slave. If so, the access information is sent to the bus.

6. The bus access control device according to claim 5, characterized in that, The control module further includes an access control subunit, which is connected to the configuration module and the address access control subunit; The address access control subunit is used to send the access information to the permission control subunit when the access address belongs to the range of accessible addresses; The access control subunit is used to determine whether the access permissions carried in the access information belong to the access scope of the host's current access configuration to the target slave. If so, the access information is sent to the bus.

7. The bus access control device according to any one of claims 1-6, characterized in that, The bus access control device further includes an interrupt control module connected to the control module, which generates an interrupt signal output when the access information does not match the host's current access configuration for the target slave.

8. The bus access control device according to claim 7, characterized in that, The interrupt control module is configured as follows: The interrupt signal is generated in response to an address error interruption event or a permission error interruption event from the control module, wherein the address error interruption event is used to indicate that the access address carried in the access information does not belong to the range of accessible addresses in the current access configuration, and the permission error interruption event is used to indicate that the access permission carried in the access information does not belong to the permission range in the current access configuration.

9. The bus access control device according to claim 7, characterized in that, The interrupt control module is used for: If the access address carried in the access information does not belong to the range of accessible addresses in the current access configuration, the access address is recorded; When the access permission carried in the access information does not fall within the permission range of the current access configuration, the access permission and the access address corresponding to the access permission in the access information are recorded.

10. A chip, characterized in that, It includes a chip body and a bus access control device as described in any one of claims 1-9 disposed on the chip body.

11. An electronic device, characterized in that, It includes a device body and a bus access control device as described in any one of claims 1-9 or a chip as described in claim 10, disposed on the device body.

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