Bandwidth prediction method and device, electronic equipment and medium
By acquiring data operation and latency information, and using LSTM and fully connected neural networks to predict the bandwidth of storage devices, the problem of long bandwidth verification cycles for storage devices is solved, enabling fast and efficient bandwidth verification and device parameter adjustment.
Patent Information
- Application Number
- CN202511028056.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-24
- Publication Date
- 2025-11-11
AI Technical Summary
The bandwidth verification cycle for storage devices is long and the verification efficiency is low, resulting in a significant waste of time and manpower in the verification process.
By acquiring pre-configured data operation information and latency information, the system uses long short-term memory networks and fully connected neural networks to predict the data operation duration of storage devices, and combines this with initialization information to quickly determine bandwidth.
It eliminates the need for a physical simulation environment, shortens bandwidth verification time, improves verification efficiency, reduces hardware resource consumption and verification costs, allows for timely adjustment of equipment parameters, and shortens the R&D cycle.
Smart Images
Figure CN120930569A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, and in particular to a bandwidth prediction method, apparatus, electronic device, and medium. Background Technology
[0002] Chip performance is a comprehensive reflection of a chip's efficiency, speed, and other characteristics when executing its designed functions. It encompasses multiple aspects, including processing speed and data transfer rate, and directly determines the overall operating efficiency of the device. Chip performance verification is a critical step in design and manufacturing, ensuring that the chip meets design specifications under various conditions, identifying problems early to optimize the design, and reducing costs. Among these, the bandwidth of a storage device refers to the amount of data transmitted per unit time, a core indicator of its transmission capacity, reflecting the speed of data exchange with external systems. Bandwidth verification ensures that the storage device performs as expected within its design specifications, avoiding performance problems caused by insufficient bandwidth in practical applications. In related technologies, testers need to construct scenarios according to design specifications, define parameters and stimuli to input into the device under test (DUT), compile and simulate the DUT, and then check the results to determine if the bandwidth meets the standards. This process consumes a significant amount of time and manpower, resulting in low verification efficiency. Summary of the Invention
[0003] This application provides a bandwidth prediction method, apparatus, electronic device, and medium to at least solve the problems of long bandwidth verification cycle and low verification efficiency of storage devices.
[0004] This application provides a bandwidth prediction method, including:
[0005] Obtain pre-configured data operation information and latency information, as well as the initialization information of the target storage device. The data operation information is used to indicate the data operations to be performed by the target storage device, and the latency information is used to indicate the reference latency for the target storage device to perform the data operations.
[0006] Based on initialization information, data operation information, and latency information, the duration of data operation performed on the target storage device is predicted to obtain the predicted duration.
[0007] Based on the data operation information, determine the amount of data transferred during the data operation performed by the target storage device;
[0008] The bandwidth of the target storage device is determined based on the prediction duration and data volume.
[0009] This application also provides a bandwidth prediction apparatus, comprising:
[0010] The acquisition module is used to acquire pre-configured data operation information and latency information, as well as the initialization information of the target storage device. The data operation information is used to indicate the data operation to be performed by the target storage device, and the latency information is used to indicate the reference latency for the target storage device to perform the data operation.
[0011] The prediction module is used to predict the duration of data operations performed on the target storage device based on initialization information, data operation information, and latency information, and obtain the predicted duration.
[0012] The first determining module is used to determine the amount of data transmitted during the data operation process of the target storage device based on the data operation information.
[0013] The second determining module is used to determine the bandwidth of the target storage device based on the prediction duration and data volume.
[0014] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of any of the above-described bandwidth prediction methods.
[0015] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described bandwidth prediction methods.
[0016] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described bandwidth prediction methods.
[0017] This application predicts the duration of data operations performed on the target storage device based on pre-configured data operation information, latency information, and initialization information. The predicted duration is then used to determine the bandwidth of the target storage device based on the data volume corresponding to the data operation information and the predicted duration. Compared to related technologies that require constructing verification scenarios (including extensive hardware environment configurations, such as building a complete simulation environment containing processors, interface protocols, and storage devices) and inputting verification stimuli into the target storage device through physical simulation, this application eliminates the need for a physical simulation environment. During bandwidth verification, bandwidth can be quickly predicted based on the acquired data operation information, latency information, and initialization information, effectively shortening bandwidth verification time, avoiding the time-consuming environment setup and signal transmission stages of physical simulation, improving bandwidth verification efficiency, reducing hardware resource consumption, and lowering verification costs. Furthermore, the rapid verification process allows for timely verification of results and adjustment of device parameters during the design or debugging phase, accelerating the device development cycle. Attached Figure Description
[0018] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 A flowchart illustrating a bandwidth prediction method provided in this application embodiment;
[0020] Figure 2 A schematic diagram of a duration prediction model provided in an embodiment of this application;
[0021] Figure 3 A flowchart illustrating a training method for a duration prediction model provided in this application embodiment;
[0022] Figure 4 This is a schematic diagram illustrating the determination of predicted duration using a duration prediction model, as provided in an embodiment of this application.
[0023] Figure 5 This is a schematic diagram of the structure of a bandwidth prediction device provided in an embodiment of this application;
[0024] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation
[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.
[0026] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.
[0027] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0028] First, the application scenarios of the embodiments of this application will be introduced by way of example.
[0029] Chip performance is a comprehensive reflection of a chip's efficiency, speed, power consumption, reliability, and other characteristics when executing its designed functions. It encompasses multiple aspects, including processing speed, computing power, data transfer rate, power consumption level, response time, and stability, directly determining the overall operating efficiency of a device. Chip performance verification, as an indispensable and crucial step in the chip design and manufacturing process, primarily aims to ensure that the chip's performance under various operating conditions meets design specifications and expected requirements. Comprehensive performance verification can identify design flaws and potential problems in advance, thereby optimizing chip design, reducing manufacturing costs, and improving product quality to meet customer needs and ensure smooth system integration. Therefore, chip verification is particularly critical for chip design and manufacturing.
[0030] Bandwidth of a storage device refers to the amount of data that the device can transmit per unit of time. It is a core indicator for measuring the data transfer capability of a storage device, reflecting the speed at which the storage device exchanges data with external components (such as chips, processors, and other storage components). Bandwidth verification ensures that the storage device performs its intended transmission capacity within its design specifications, avoiding performance problems caused by insufficient bandwidth in practical applications.
[0031] In actual verification, verification personnel need to construct corresponding performance verification scenarios based on the performance indicators specified in the design specifications for different scenarios, clarify the parameters and verification stimuli for each scenario, and then input the verification stimuli into the storage device under test for bandwidth verification compilation and simulation. Finally, the simulation results are checked to determine whether the bandwidth of the storage device meets the expected design target. This process often consumes a lot of time and manpower, resulting in low bandwidth verification efficiency.
[0032] In view of this, embodiments of this application provide a bandwidth prediction method to shorten the bandwidth testing cycle and improve testing efficiency.
[0033] It should be noted that the bandwidth prediction method provided in this embodiment of the invention can be executed by a bandwidth prediction device. This device can be implemented as part or all of an electronic device through software, hardware, or a combination of both. The electronic device can be a server or a terminal. In this embodiment, the server can be a single server or a server cluster composed of multiple servers. The terminal can be a smartphone, personal computer, tablet computer, wearable device, or other intelligent hardware device such as a smart robot. The following method embodiments will use an electronic device as an example for explanation.
[0034] According to an embodiment of the present invention, a bandwidth prediction method embodiment is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.
[0035] This embodiment provides a bandwidth prediction method that can be used in the aforementioned electronic devices, such as servers. Figure 1 This is a flowchart of a bandwidth prediction method provided by an embodiment of the present invention, such as... Figure 1 As shown, the process includes:
[0036] S101, obtain pre-configured data operation information and latency information, as well as the initialization information of the target storage device.
[0037] Specifically, the target storage device can be a Non-Volatile Memory Express (NVMe) solid-state drive, a Redundant Array of Independent Disks (RAID), or something similar.
[0038] Data operation information is used to instruct the target storage device on the data operation to be performed. This data operation can be a data read operation, which involves reading data from the target storage device and then sending that data to the device that requested the read. Alternatively, it can be a data write operation, which involves the target storage device retrieving data from the device that requested the write and then writing that data to the target storage device.
[0039] In the following embodiments, this application takes an NVMe solid-state drive as the target storage device as an example to illustrate the bandwidth prediction method provided in the embodiments of this application.
[0040] In NVMe SSDs, the NVMe controller, as the core component, is responsible for managing and processing data transfer and command execution between the requesting device and the storage media (such as flash memory) in the target storage device. Based on the NVMe protocol, the NVMe controller reads SQ commands from the requesting device's Submission Queue (SQ) and parses each field from the SQ command. The NVMe controller performs corresponding data operations based on the parsed fields. For data read operations, the NVMe controller reads data from the flash memory and sends it to the requesting device; for data write operations, the NVMe controller retrieves data from the requesting device and writes it to the flash memory. After a data read or write operation is completed, the NVMe controller sends a CQ command to the requesting device's Completion Queue (CQ) and reports a Message Signaled Interrupts-Extended (MSI-X) to the requesting device, indicating that the task corresponding to the current SQ command has been completed.
[0041] Data operation information can include the type of data operation (such as reading data, writing data, etc.), the number of commands, and the amount of data involved in each command. For example, the data operation information may contain 10 data write commands, each command involving 5 physical pages, and each physical page corresponding to 4KB of data.
[0042] Initialization information refers to the key parameter settings of the target storage device during startup or initial configuration, reflecting the hardware characteristics and operating environment configuration of the target storage device, including but not limited to queue configuration information (such as queue depth), register configuration information (such as clock frequency), interrupt configuration information (such as interrupt response mode), etc.
[0043] Latency information is used to indicate the reference latency for the target storage device to perform data operations. Here, the reference latency can be understood as the latency caused by the physical layer in the actual working scenario of the target storage device. For example, the transmission delay of electrical signals in the wiring inside the storage device, the switching delay of hardware units such as gate circuits and flip-flops, and the alignment time caused by the offset of clock signals inside different modules.
[0044] S102, based on initialization information, data operation information and latency information, predict the duration of data operation performed by the target storage device to obtain the predicted duration.
[0045] For example, the NVMe controller moves N SQ read commands from the requesting device's SQ queue, each SQ read command reading M physical pages of data from the flash memory. Under the control of the NVMe controller, the data of the M physical pages is moved from the flash memory to the requesting device. After all the data from the N SQ read commands has been moved from the flash memory to the requesting device, the NVMe controller sends a CQ command to the requesting device's CQ queue and reports an MSI-X interrupt to the requesting device, indicating that the operation of the current SQ command has been completed. The time taken from the NVMe controller reading the first SQ command to the NVMe controller sending the last CQ command to the requesting device and reporting the MSI-X interrupt is the duration of the NVMe SSD performing the data operation.
[0046] S103, Based on the data operation information, determine the amount of data transmitted during the data operation performed by the target storage device.
[0047] Specifically, the amount of data transmitted refers to the total size of data transferred from the data source to the destination when the target storage device performs the current data operation.
[0048] In one possible implementation, the data operation information includes the number of commands in the read submission queue, the number of physical pages for each command to perform data operations, and the amount of data corresponding to each physical page.
[0049] Specifically, the commit queue is used to receive and temporarily store commands awaiting execution. The number of commands read from the commit queue by the target storage device refers to the total number of data operation commands read from the target storage device's commit queue that are awaiting execution by the target storage device, reflecting the total amount of tasks that the target storage device needs to process. For example, if the target storage device reads 10 read commands awaiting execution from the commit queue, then the number of commands read from the commit queue is 10.
[0050] A physical page is the basic unit of data storage in a target storage device. The number of physical pages used for data operations by each command refers to the number of physical pages that the target storage device needs to access during the execution of each command. For example, if the first command needs to access 5 physical pages, then the number of physical pages used for data operations by this command is 5.
[0051] The number of physical pages refers to the amount of data that each physical page can store.
[0052] In S103 above, the number of transmissions is determined as follows:
[0053] The amount of data transferred during the data operation on the target storage device is determined based on the number of commands in the read submission queue, the number of physical pages operated on by each command, and the amount of data corresponding to each physical page.
[0054] For example, if the data operation information contains 16 data write commands, each command involves 8 physical pages, and each physical page corresponds to 4KB of data, then the amount of data transferred is 16 × 8 × 4 = 512KB.
[0055] S104, determine the bandwidth of the target storage device based on the prediction duration and data volume.
[0056] Specifically, the bandwidth of a target storage device refers to the amount of data that the target storage device can transmit per unit of time, and it is an important indicator for measuring the data transmission capability of a storage device.
[0057] For example, the ratio between the amount of data and the prediction duration can be used as the bandwidth of the target storage device.
[0058] In this embodiment, the duration of data operations performed by the target storage device is predicted based on the acquired pre-configured data operation information, latency information, and initialization information. Further, the bandwidth of the target storage device is obtained based on the data volume corresponding to the data operation information and the predicted duration. Compared to related technologies that require constructing verification scenarios (including extensive hardware environment configuration, such as building a complete simulation environment containing processors, interface protocols, and storage devices) and inputting verification stimuli into the target storage device's physical simulation, this application does not rely on a physical simulation environment. During bandwidth verification, bandwidth can be quickly predicted based on the acquired data operation information, latency information, and initialization information, effectively shortening bandwidth verification time, avoiding the time-consuming environment setup and signal transmission stages in physical simulation, improving bandwidth verification efficiency, reducing hardware resource consumption, and lowering verification costs. Furthermore, the rapid verification process allows for timely verification of results and adjustment of device parameters during the design or debugging phase, accelerating the device development cycle.
[0059] In some embodiments, in S102 above, the duration of data operation performed by the target storage device is predicted based on initialization information, data operation information, and latency information to obtain the predicted duration, specifically including the following a1-a3:
[0060] a1, based on initialization information, data operation information, and delay information, obtain the timing characteristics between initialization information, data operation information, and delay information.
[0061] Specifically, the temporal characteristics of initialization information, data operation information, and latency information demonstrate the correlation between these three information over time. For example, as the queue depth corresponding to the target storage device in the initialization information increases, the command processing latency decreases. Different commands executed in the data operation information will also result in variations in latency.
[0062] In one possible implementation, the initialization information includes queue configuration information, register configuration information, and interrupt configuration information.
[0063] Specifically, queue configuration information refers to the parameter settings used to manage the command queue in the target storage device, including but not limited to queue depth (i.e., the maximum number of commands it can hold), queue priority rules, commit queue base address, and completion queue base address. For example, if the queue depth of the target storage device is 20, it can store 20 commands to be executed, and the highest priority command is processed first.
[0064] Register configuration information refers to the parameter settings of the registers corresponding to the target storage device. Registers are hardware units in the target storage device used to temporarily store data and control instructions. Register configuration information includes, but is not limited to, clock frequency, data transfer mode, controller enable information, and controller status information. For example, the frequency of the registers corresponding to the target storage device may be 2GHz, and the data transfer mode may be parallel transmission.
[0065] Interrupt configuration information refers to the settings regarding the interrupt mechanism of the target storage device. Interrupt configuration information includes, but is not limited to, interrupt triggering methods (such as level triggering, edge triggering, etc.) and interrupt priorities.
[0066] In a1 above, based on the initialization information, data operation information, and delay information, the timing characteristics between the initialization information, data operation information, and delay information are obtained, including:
[0067] The queue configuration information, register configuration information, interrupt configuration information, data operation information, and latency information are input into a pre-built Long Short-Term Memory (LSTM) network to obtain the temporal features.
[0068] Specifically, Long Short-Term Memory (LSTM) networks are a special type of Recurrent Neural Network (RNN) with unique advantages in processing sequential data. In the embodiments of this application, the LSTM model can effectively process and predict complex sequential data, thereby improving simulation efficiency and accuracy. By introducing a gating mechanism, the LSTM model can effectively capture dependencies over long time spans. This is particularly important for processing input data during bandwidth verification, as the behavior of storage devices is often influenced by historical stimulus signals (i.e., historical input data). The LSTM model can remember long-term stimulus patterns, thus more accurately predicting the bandwidth of the storage device. Furthermore, the length of the stimulus signals (i.e., input data) during the verification process is often variable. The LSTM model can handle variable-length input sequences, automatically adjusting the processing method according to the length of the input sequence, without needing to pad all sequences to the same length, thus improving flexibility and efficiency.
[0069] In this way, LSTM can be used to uncover the deep correlation between initialization information, data operation information, and latency information in the time dimension. For example, it can identify the subtle changes in the impact of the increase in the number of physical pages in data operations on the duration when the register clock frequency in the initialization information is increased, thereby improving the accuracy of predicting the time required for the target storage device to perform data operations.
[0070] a2, based on the temporal features, obtain the scene features corresponding to the temporal features.
[0071] Specifically, scenario features are used to describe the characteristics of a scenario comprised of initialization information, data operation information, and latency information, and can reflect the typical characteristics of that scenario. For example, the characteristics of a batch sequential read scenario include a large number of commands and contiguous physical pages.
[0072] In one possible implementation, in a2 above, scene features corresponding to the temporal features are obtained based on the temporal features. Specific steps include:
[0073] First, perform a preset number of self-attention operations on the temporal features to obtain attention matrices corresponding to the preset number of self-attention operations.
[0074] Specifically, the elements in the attention matrix represent the association weights between information at different time points in the temporal features.
[0075] For example, the vector matrix corresponding to the temporal features is subjected to a preset number of self-attention operations. In each self-attention operation, the similarity between each element in the vector matrix and other elements is calculated (e.g., through dot product operation) to obtain the attention matrix for this operation.
[0076] It should be noted that this application does not impose a specific limit on the number of self-attention operations, which can be adjusted according to the actual situation. For example, three self-attention operations are performed on time-series features to analyze the feature correlations in the short, medium, and long term.
[0077] Then, the attention matrices corresponding to the preset number of self-attention operations are concatenated to obtain the concatenated attention matrix.
[0078] Specifically, attention matrices obtained from multiple self-attention operations are combined into a new matrix according to certain dimensions. For example, multiple attention matrices can be concatenated column-wise or row-wise. For instance, three 3×3 attention matrices obtained from three self-attention operations can be concatenated into a 3×9 matrix.
[0079] Finally, a linear transformation is performed on the concatenated attention matrix to obtain the scene features corresponding to the temporal features.
[0080] In this way, self-attention operations can uncover important correlation information in timing features. Through multiple self-attention operations, this information can be mined from different angles. For example, in obtaining the correlation between the number of commands and latency, the impact of initialization information on this correlation can be captured, thus providing a basis for the accuracy of predicting the time taken for the target storage device to perform data operations.
[0081] a3, based on timing and scenario characteristics, predicts the duration of data operations performed on the target storage device to obtain the predicted duration.
[0082] In one possible implementation, in a3 above, the duration of data operations performed on the target storage device is predicted based on timing and scenario characteristics to obtain the predicted duration. Specific steps include the following b1-b2:
[0083] b1, based on temporal and scene features, yields the fused features.
[0084] Specifically, fused features refer to features obtained by fusing temporal features and scene features through a preset fusion method. Fusion features include both the temporal correlation patterns described by temporal features and the specific operational scenarios represented by scene features.
[0085] In one possible implementation, in b1 above, the fused features are obtained based on temporal and scene features. Specific steps include:
[0086] First, the vector matrix corresponding to the temporal features and the vector matrix corresponding to the scene features are added together and then normalized to obtain the first vector matrix.
[0087] Specifically, the first vector matrix is the matrix obtained by adding the vector matrices corresponding to the temporal features and the vector matrices corresponding to the scene features and then performing layer normalization, which eliminates the numerical differences between different feature dimensions.
[0088] Then, a nonlinear transformation is performed on the first vector matrix to obtain the second vector matrix.
[0089] Specifically, by using activation functions (such as linear rectified functions, sigmoid functions, etc.) to process the first vector matrix, a second vector matrix is obtained, which can better reflect the complex relationship between temporal features and scene features.
[0090] Finally, the fused features are obtained based on the first vector matrix and the second vector matrix.
[0091] Specifically, the fused features include all the temporal and scene information of the scene to be predicted.
[0092] Optionally, the first vector matrix and the second vector matrix are added together and then subjected to layer normalization again to obtain the fused features.
[0093] In another possible implementation, the vector matrix corresponding to the temporal features and the vector matrix corresponding to the scene features can be fused by concatenating the two vector matrices end to end to form the vector matrix corresponding to the fused features, thus obtaining the fused features.
[0094] b2 inputs the fused features into a pre-built fully connected neural network to obtain the prediction duration.
[0095] Specifically, a fully connected neural network is a neural network model in which all neurons in each layer are fully connected. For example, a fully connected neural network includes an input layer, hidden layers, and an output layer. In this embodiment, the fully connected neural network can be a model trained using multiple fusion features and the actual duration of data operations performed on storage devices corresponding to each fusion feature, capable of outputting a predicted duration based on the input fusion features.
[0096] For example, the fused features are used as input to the input layer of a fully connected neural network. The number of neurons in the input layer is the same as the dimension of the fused feature vector. Then, the fused features undergo non-linear transformation of the input through the activation function in the hidden layer, and finally the predicted duration is obtained through the calculation of the output layer.
[0097] In this embodiment, by utilizing the temporal characteristics between initialization information, data operation information, and latency information, the dynamic correlation between these three information in the time dimension can be captured. Furthermore, by combining the scenario characteristics corresponding to the initialization information, data operation information, and latency information, the execution time can be predicted for different scenarios. By combining temporal characteristics and scenario features, the execution time of data operations on the target storage device can be predicted, thereby improving the accuracy of the prediction.
[0098] For example, in S102 above, the predicted duration is obtained in the following manner:
[0099] The initialization information, data operation information, and latency information are input into the pre-built duration prediction model to obtain the predicted duration.
[0100] like Figure 2 As shown, the duration prediction model includes a Long Short-Term Memory (LSTM) network, a Transformer, and a fully connected neural network. In the duration prediction model, the LSTM model, the Transformer, and the fully connected neural network are connected sequentially. The LSTM model and the Transformer model are used to obtain fused features based on initialization information, data manipulation information, and latency information. The fully connected neural network is used to obtain the predicted duration based on the fused features.
[0101] In this embodiment, the duration prediction model is a trained model. During the training of the duration prediction model, the initialization information (such as queue configuration information, register configuration information, interrupt configuration information), data operation information, and latency information in the training set are used as inputs. The actual duration in the training set is the predicted value of the duration prediction model, i.e., the sample label.
[0102] When training the duration prediction model, the training samples are first vectorized. Then, the vectors corresponding to the initialization information, data operation information (such as the number of SQ commands read, the number of pages moved by SQ commands, and the page size), and latency information are sequentially input into the duration prediction model. After calculation by the duration prediction model, the predicted duration will be output. This predicted duration will have an error compared with the actual duration in the training set. The error is calculated using a loss function, and then the backpropagation algorithm is used to optimize the parameters in the duration prediction model, finally obtaining the trained duration prediction model.
[0103] In the Transformer model, the self-attention mechanism enables the model to establish a direct connection between any two points in a sequence, regardless of their temporal distance. This helps the model better understand the global context, thus predicting the behavior of storage devices more accurately. Furthermore, the Transformer model allows for parallel processing of inputs at all time steps, significantly improving training speed, especially on large-scale datasets. Through parallel computation, the Transformer model can significantly reduce training time and save device validation time.
[0104] Figure 3 This is a flowchart illustrating a training method for a duration prediction model. Figure 3 In this context, the training process of the duration-based training model includes the following steps:
[0105] S301, construct multiple test scenarios, and determine the initialization parameters and data operation information corresponding to each test scenario as excitation signals input into the storage device to obtain the duration corresponding to the test scenario.
[0106] S302, obtain the latency information corresponding to each test scenario, and use the initialization parameters, data operation information, latency information and duration corresponding to each test scenario as the training set.
[0107] Specifically, the latency information corresponding to each test scenario is determined based on the actual duration of data operations performed by the storage device in that test scenario.
[0108] S303, the initial duration prediction model is trained using the training set to obtain the duration prediction model.
[0109] In this way, the duration prediction model trained on the training set can be used to determine the predicted duration of the target storage device.
[0110] The following is an exemplary description of the entire process of obtaining the predicted duration using a duration prediction model, using a specific embodiment.
[0111] Assuming that initialization information, data operation information (including the number of SQ commands read, the number of physical pages moved by SQ commands, and the size of the physical pages), and latency information are used as model inputs, and each input vector has a dimension of M, then the overall input of the model can be represented by an N×M vector matrix X(x1, x2, ..., x...). N Represent the vector matrix X(x1,x2,...,x) as follows: N Input into the LSTM model, such as Figure 4 As shown. The LSTM model, in time, adapts to the input vector x. iEncode the inputs, i∈[1,N], and analyze the temporal relationships between each input. j Let y be the intermediate vector at time j. i Let y be the output vector at time i, and let y be the output vector at each time step i. i The output vector matrix Y(y1,y2,...,y) is formed. N ), i∈[1,N], j∈[0,N].
[0112] The output vector matrix Y(y1,y2,...,y) of the LSTM model N The input vector matrix Y(y1, y2, ..., y) is the input vector matrix of the Transformer model. In the Transformer model, the input vector matrix Y(y1, y2, ..., y) is first processed... N The self-attention operation is performed using the following formula:
[0113]
[0114] Where Attention(Q,K,V) is the attention matrix, Q is the query vector, K is the key vector, V is the value vector, and d k It is the number of columns in K, i.e., the vector dimension.
[0115] Perform n self-attention operations on the vector matrix Y to obtain n Attention(Q,K,V) matrices, namely Attention1(Q,K,V), Attention2(Q,K,V), ..., Attention... n (Q,K,V). These n Attention(Q,K,V) matrices are concatenated and passed to a linear layer for linear transformation to obtain the vector matrix Z = Linear(Attention1(Q,K,V),Attention2(Q,K,V),...,Attention...). n (Q,K,V)). The vector matrix Z has the same dimensions as the vector matrix Y.
[0116] Add vector matrix Y to vector matrix Z, then perform layer normalization to obtain vector matrix Y' = LayerNorm(Y+Z). Input vector matrix Y' into a feed-forward neural network (FFN) to obtain vector matrix Z' = max(0,Y'W1+b1)W2+b2, where W1 and W2 are the weight matrices of the first and second linear transformation layers, respectively, and b1 and b2 are the bias vectors of the first and second linear transformation layers, respectively. Add vector matrix Y' to vector matrix Z', then perform layer normalization to obtain vector matrix Y” = LayerNorm(Y'+Z'). Vector matrix Y” is the output vector matrix of the Transformer model, containing all temporal and scene information of the performance scenario to be predicted. Finally, input the output vector matrix Y” of the Transformer model into a fully connected neural network to predict the time required for data operations on the storage device.
[0117] In some embodiments, the bandwidth prediction method provided in this application further includes the following c1-c2:
[0118] c1 retrieves the wiring delay, switching delay, and clock synchronization delay of the target storage device.
[0119] Specifically, wiring delay refers to the time delay caused by factors such as wire length, parasitic capacitance / resistance, and signal frequency when electrical signals are transmitted through the metal interconnects inside a storage device. Signals do not propagate instantaneously in the wires, and long-distance or high-density wiring can significantly accumulate this delay.
[0120] Switching delay refers to the time required for a transistor in a storage device (such as a Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) to go from on to off, or from off to on. It is determined by characteristics such as the transistor's threshold voltage and drive current. For example, the flip-flop used for command parsing in an NVMe controller contains multiple transistors; the time it takes for the flip-flop to stabilize from the input signal triggering is the switching delay.
[0121] Clock synchronization delay refers to the delay in a synchronous circuit caused by variations in the path length of the clock signal to different modules within the device, load differences, etc., resulting in discrepancies in the actual clock reception time of each module, or by the data signal not being strictly aligned with the clock signal. Clock synchronization delay affects the accuracy of data sampling and is a critical latency factor for high-speed interfaces (such as flash memory interfaces). For example, the SQ command read module and data cache module of an NVMe controller share the same clock source, but the wiring length of the clock signal to the two modules is different, causing the data cache module to receive the clock 50 picoseconds later than the SQ command read module. In this case, data needs to wait for clock alignment when read from the cache, resulting in a 50 picosecond clock synchronization delay.
[0122] In one possible implementation, in c1 above, the transmission delay is obtained as follows:
[0123] First, obtain the wiring parameters of the target storage device.
[0124] Specifically, wiring parameters are parameters used to describe the physical characteristics of the metal interconnects inside the target storage device, including but not limited to the physical length of the interconnects, cross-sectional width, wire spacing, and resistivity of the conductive material.
[0125] Then, based on the wiring parameters, timing analysis is performed on the target storage device to obtain the transmission delay.
[0126] Optionally, the timing analysis function of Electronic Design Automation (EDA) tools can be used to simulate the critical path (such as the path of "SQ command reception → flash memory read → data transmission to requesting device") corresponding to the target storage device based on the routing parameters of the target storage device. The total time for signal transmission on the critical path can be used as the routing transmission delay.
[0127] In one possible implementation, the switching delay in c1 above is obtained as follows:
[0128] First, obtain the transistor parameters of all transistors in the target storage device.
[0129] Among them, transistor parameters are physical parameters used to describe the electrical characteristics of transistors, including but not limited to geometric parameters (such as channel length, width, etc.) and electrical parameters (such as threshold voltage, drain capacitance, etc.).
[0130] Then, based on the parameters of each transistor, the state switching process of the transistor is simulated using the Simulation Program with Integrated Circuit Emphasis (SPICE) tool. The time from the input signal transition to the stable output signal is recorded, which is the switching delay of the transistor.
[0131] For example, using the SPICE tool, the time taken for a transistor to switch from on to off, or from off to on, is recorded as the switching delay of the transistor.
[0132] Finally, based on the switching delays of all transistors and the logical relationships between them, the switching delay of the target memory device is obtained.
[0133] For example, the logical relationship between the transistors can be serial, parallel, etc. If the transistors are connected serially, the switching delays of all transistors are summed to obtain the switching delay of the target memory device. If the transistors are connected in parallel, the maximum value among the switching delays of all transistors is taken as the switching delay of the target memory device.
[0134] In one possible implementation, the clock synchronization delay in c1 above is obtained as follows:
[0135] First, obtain the clock network parameters of the target storage device.
[0136] Specifically, clock network parameters are the physical characteristics and design parameters of the clock signal transmission path within the target storage device. For example, clock network parameters include, but are not limited to, clock source parameters (such as crystal oscillator frequency) and clock tree topology.
[0137] It should be noted that the embodiments of this application do not limit the specific implementation method for obtaining the wiring parameters, transistor parameters, and clock network parameters of the target storage device. For example, they can be obtained through the design documents of the target storage device.
[0138] Then, based on the clock network parameters, a clock tree analysis tool is used to perform timing analysis on the clock network to obtain the clock synchronization delay of the target storage device.
[0139] Specifically, clock tree analysis tools are used to verify and analyze the timing characteristics of chip clock networks and can calculate the time delay of clock signals arriving at each module.
[0140] For example, the maximum value of the clock signal arrival delays at each module is used as the clock synchronization delay of the target storage device.
[0141] c2 determines the delay information based on the wiring transmission delay, switching delay, and clock synchronization delay.
[0142] For example, the wiring transmission delay, switching delay, and clock synchronization delay are summed, and the summed delay is used as the reference delay to obtain the delay information.
[0143] In other embodiments, the latency information can also be determined in the following way:
[0144] First, using test cases, logical simulation and physical simulation are performed on the target storage device to obtain the duration corresponding to the logical simulation and the duration corresponding to the physical simulation.
[0145] Then, the delay information is determined based on the duration corresponding to the logic simulation and the duration corresponding to the physical simulation.
[0146] For example, the delay obtained by subtracting the duration corresponding to the logic simulation from the duration corresponding to the physical simulation is used as the reference delay, thereby obtaining the delay information.
[0147] Of course, the reference delay can also be determined based on historical experience. This application does not specifically limit the specific implementation method for determining the delay information.
[0148] In this embodiment, the latency generated at the physical layer of the target storage device is considered. A reference latency is determined by utilizing the wiring parameters, transistor parameters, and clock network parameters of the target storage device. This reference latency is introduced when predicting the duration of data operations performed by the target storage device, thereby improving the accuracy of the prediction.
[0149] The above mainly describes the solution provided by the embodiments of this application from a methodological perspective.
[0150] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.
[0151] This application also provides a bandwidth prediction device for implementing the above embodiments and preferred embodiments, which will not be repeated hereafter. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.
[0152] This embodiment provides a bandwidth prediction device, such as... Figure 5 As shown, it includes:
[0153] The acquisition module 501 is used to acquire pre-configured data operation information and latency information, as well as the initialization information of the target storage device. The data operation information is used to indicate the data operation to be performed by the target storage device, and the latency information is used to indicate the reference latency for the target storage device to perform the data operation.
[0154] The prediction module 502 is used to predict the duration of data operations performed on the target storage device based on initialization information, data operation information, and latency information, and obtain the predicted duration.
[0155] The first determining module 503 is used to determine the amount of data transmitted during the data operation process of the target storage device based on the data operation information.
[0156] The second determining module 504 is used to determine the bandwidth of the target storage device based on the prediction duration and data volume.
[0157] The apparatus provided in this application predicts the duration of data operations performed on the target storage device based on pre-configured data operation information, latency information, and initialization information. Further, the bandwidth of the target storage device is obtained based on the data volume corresponding to the data operation information and the predicted duration. Compared to related technologies that require constructing verification scenarios (including extensive hardware environment configuration, such as building a complete simulation environment containing processors, interface protocols, and storage devices) and inputting verification stimuli into the target storage device through physical simulation, this application does not rely on a physical simulation environment. During bandwidth verification, bandwidth can be quickly predicted based on the acquired data operation information, latency information, and initialization information, effectively shortening bandwidth verification time, avoiding the time-consuming environmental setup and signal transmission stages in physical simulation, improving bandwidth verification efficiency, reducing hardware resource consumption, and lowering verification costs. Furthermore, the rapid verification process allows for timely verification of results and adjustment of device parameters during the design or debugging phase, accelerating the device development cycle.
[0158] In one possible implementation, the prediction module 502 is specifically used to obtain the temporal characteristics between the initialization information, data operation information, and delay information based on the initialization information, data operation information, and delay information.
[0159] Based on the temporal features, the scene features corresponding to the temporal features are obtained;
[0160] Based on timing and scenario characteristics, the duration of data operations performed on the target storage device is predicted to obtain the predicted duration.
[0161] In one possible implementation, the prediction module 502 is specifically used to perform a preset number of self-attention operations on the temporal features to obtain attention matrices corresponding to the preset number of self-attention operations.
[0162] The attention matrices corresponding to the preset number of self-attention operations are concatenated to obtain the concatenated attention matrix;
[0163] A linear transformation is performed on the concatenated attention matrix to obtain the scene features corresponding to the temporal features.
[0164] In one possible implementation, the prediction module 502 is specifically used to obtain fused features based on temporal features and scene features;
[0165] The fused features are input into a pre-built fully connected neural network to obtain the prediction duration.
[0166] In one possible implementation, the vector matrix corresponding to the temporal features and the vector matrix corresponding to the scene features are added together and then normalized at each layer to obtain the first vector matrix.
[0167] A nonlinear transformation is performed on the first vector matrix to obtain the second vector matrix;
[0168] The fusion features are obtained based on the first vector matrix and the second vector matrix.
[0169] In one possible implementation, the initialization information includes queue configuration information, register configuration information, and interrupt configuration information. The prediction module 502 is specifically used to input the queue configuration information, register configuration information, interrupt configuration information, data operation information, and latency information into a pre-built long short-term memory network to obtain temporal features.
[0170] In one possible implementation, the acquisition module 501 is further configured to acquire the wiring transmission delay, switching delay, and clock synchronization delay of the target storage device.
[0171] The device also includes a third determining module, used to determine delay information based on wiring transmission delay, switching delay and clock synchronization delay.
[0172] For a description of the features in the embodiment corresponding to the bandwidth prediction device, please refer to the relevant description in the embodiment corresponding to the bandwidth prediction method, which will not be repeated here.
[0173] Embodiments of this application also provide an electronic device, such as... Figure 6 As shown, it includes a memory 10 and a processor 20, the memory 10 storing a computer program, and the processor 20 being configured to run the computer program to perform the steps in any of the above-described bandwidth prediction method embodiments.
[0174] Embodiments of this application also provide a computer-readable storage medium storing a computer program configured to execute the steps in any of the above-described bandwidth prediction method embodiments at runtime.
[0175] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.
[0176] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described bandwidth prediction method embodiments.
[0177] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps in any of the above-described bandwidth prediction method embodiments.
[0178] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0179] The bandwidth prediction method, apparatus, electronic device, and medium provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.
Claims
1. A bandwidth prediction method, characterized in that, The method includes: Obtain pre-configured data operation information and latency information, as well as initialization information of the target storage device, wherein the data operation information is used to indicate the data operation to be performed by the target storage device, and the latency information is used to indicate the reference latency for the target storage device to perform the data operation; Based on the initialization information, the data operation information, and the latency information, the duration for the target storage device to perform the data operation is predicted to obtain the predicted duration. Based on the data operation information, determine the amount of data transmitted by the target storage device during the execution of the data operation; The bandwidth of the target storage device is determined based on the predicted duration and the amount of data.
2. The method according to claim 1, characterized in that, The step of predicting the duration of the data operation performed by the target storage device based on the initialization information, the data operation information, and the latency information to obtain the predicted duration includes: Based on the initialization information, the data operation information, and the delay information, the timing characteristics between the initialization information, the data operation information, and the delay information are obtained; Based on the temporal features, scene features corresponding to the temporal features are obtained; Based on the time-series characteristics and the scenario characteristics, the duration of the data operation performed by the target storage device is predicted to obtain the predicted duration.
3. The method according to claim 2, characterized in that, The step of obtaining the scene features corresponding to the temporal features based on the temporal features includes: Perform a preset number of self-attention operations on the temporal features to obtain attention matrices corresponding to the preset number of self-attention operations; The attention matrices corresponding to the preset number of self-attention operations are concatenated to obtain the concatenated attention matrix; A linear transformation is performed on the concatenated attention matrix to obtain the scene features corresponding to the temporal features.
4. The method according to claim 2 or 3, characterized in that, The step of predicting the duration of the data operation performed on the target storage device based on the time-series characteristics and the scenario characteristics, to obtain the predicted duration, includes: Based on the temporal features and the scene features, the fused features are obtained; The fused features are input into a pre-constructed fully connected neural network to obtain the predicted duration.
5. The method according to claim 4, characterized in that, The step of obtaining the fused features based on the temporal features and the scene features includes: The vector matrix corresponding to the temporal features and the vector matrix corresponding to the scene features are added together and then normalized to obtain the first vector matrix; A nonlinear transformation is performed on the first vector matrix to obtain the second vector matrix; The fusion feature is obtained based on the first vector matrix and the second vector matrix.
6. The method according to claim 2 or 3, characterized in that, The initialization information includes queue configuration information, register configuration information, and interrupt configuration information. The step of obtaining the timing characteristics between the initialization information, the data operation information, and the delay information based on the initialization information, the data operation information, and the delay information includes: The queue configuration information, register configuration information, interrupt configuration information, data operation information, and latency information are input into a pre-constructed long short-term memory network to obtain the timing features.
7. The method according to claim 6, characterized in that, The method further includes: Obtain the wiring transmission delay, switching delay, and clock synchronization delay of the target storage device; The delay information is determined based on the wiring transmission delay, the switching delay, and the clock synchronization delay.
8. A bandwidth prediction device, characterized in that, The device includes: The acquisition module is used to acquire pre-configured data operation information and latency information, as well as initialization information of the target storage device. The data operation information is used to indicate the data operation to be performed by the target storage device, and the latency information is used to indicate the reference latency for the target storage device to perform the data operation. The prediction module is used to predict the duration of the data operation performed by the target storage device based on the initialization information, the data operation information, and the latency information, and to obtain the predicted duration. The first determining module is used to determine the amount of data transmitted by the target storage device during the execution of the data operation based on the data operation information. The second determining module is used to determine the bandwidth of the target storage device based on the predicted duration and the data volume.
9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the bandwidth prediction method as described in any one of claims 1-7 when executing the computer program.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the bandwidth prediction method as described in any one of claims 1-7.