Semiconductor device and memory

Abstract

The disclosure provides a semiconductor device and a memory, and relates to the technical field of memories.A semiconductor device comprises a multilayer wiring structure on a semiconductor substrate, the multilayer wiring structure comprising a first wiring layer and a second wiring layer formed on different metal layers; N parallel data lines running in a first direction, each parallel data line being divided into M segments; and a plurality of connection units for connecting the N parallel data lines of the M segments; for each segment of the N parallel data lines, the N parallel data lines of each segment are divided into a plurality of groups with M parallel data lines as a group, and the plurality of groups of M parallel data lines are arranged in a second direction.The disclosure can reduce the influence of the coupling effect between data lines without increasing the device and power consumption, and can avoid the error flip of signals on the data bus.

Description

Technical Field

[0001] This disclosure relates to the field of memory technology, and more particularly to a semiconductor device and a memory. Background Technology

[0002] In the field of memory technology, memories such as Dynamic Random Access Memory (DRAM) typically include a memory array for storing data, data input / output circuitry, and related timing control circuitry. Data is often transmitted through relatively long metal lines from the memory array's data input / output interface within the memory chip. During transmission, the parasitic capacitance between adjacent lines can cause data transmission to become faster or slower, or even result in data flipping, leading to DRAM malfunctions and reduced reliability.

[0003] In related technologies, shielding is typically performed during layout to reduce inter-line coupling effects. However, this method is prone to conflicts between traces and shielding, resulting in poor performance of existing shielding methods.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] This disclosure provides a semiconductor device and memory that at least partially reduces the impact of line-to-line coupling capacitance.

[0006] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0007] According to one aspect of this disclosure, a semiconductor device is provided, comprising:

[0008] A multilayer wiring structure on a semiconductor substrate, the multilayer wiring structure including a first wiring layer and a second wiring layer formed on different metal layers;

[0009] N parallel data lines running along the first direction, each parallel data line is divided into M segments;

[0010] Multiple connection units are used to connect N parallel data lines of segment M;

[0011] For each segment of N parallel data lines, the N parallel data lines of each segment are divided into multiple groups of M parallel data lines, where M≤N, M>2, and M and N are positive integers.

[0012] For a group of M parallel data lines, one of the parallel data lines is located in the second routing layer, and the parallel data line has first static routing on both sides of the second direction; M-1 parallel data lines in the group of M parallel data lines are located in the first routing layer, and the M-1 parallel data lines have second static routing on one side of the second direction, wherein the second direction is perpendicular to the first direction of the N parallel data lines.

[0013] In some exemplary embodiments of this disclosure, for each set of parallel data lines, one of the parallel data lines is arranged in a third direction corresponding to the second static wiring, and the M-1 parallel data lines are arranged in a third direction corresponding to the first static wiring of one of the parallel data lines on one side of the second direction, wherein the third direction is perpendicular to the second direction.

[0014] In some exemplary embodiments of this disclosure, the number of the first static wiring corresponding to the M-1 parallel data lines is ≤ M-1.

[0015] In some exemplary embodiments of this disclosure, when the second static wiring is disposed on the side away from the next group of M parallel data lines of the current group, the M-1 parallel data lines located in the last group of M parallel data lines are disposed on the side away from the second static wiring in the second direction.

[0016] In some exemplary embodiments of this disclosure, when the second static wiring is disposed on the side of the next group of M parallel data lines close to the current group, a fourth static wiring is disposed on the side of the M-1 parallel data lines of the first group of M parallel data lines away from the second static wiring.

[0017] In some exemplary embodiments of this disclosure, the number of the first static wirings is ≤ M-1 within a set of M parallel data lines.

[0018] In some exemplary embodiments of this disclosure, the number of connection units is M-1, and the plurality of connection units are sequentially connected between N parallel data lines in adjacent segments. Each connection unit includes a through hole disposed in an insulating layer between the first wiring layer and the second wiring layer, and the through hole is filled with conductive material.

[0019] In some exemplary embodiments of this disclosure, the connection unit includes a data driving unit, the number of which is M+1, and the M+1 data driving units are connected to the ends of the first segment of N parallel data lines, between the N parallel data lines of adjacent segments, and to the ends of the last segment of N parallel data lines.

[0020] In some exemplary embodiments of this disclosure, the multilayer wiring structure further includes a zeroth wiring layer, and the data driving unit is disposed on the zeroth wiring layer.

[0021] In some exemplary embodiments of this disclosure, an insulating layer is provided between the zero wiring layer, the first wiring layer, and the second wiring layer;

[0022] For a parallel data line in different segments, the insulating layer is provided with a first connecting hole and a second connecting hole, and the first connecting hole and the second connecting hole are filled with conductive material;

[0023] Wherein, one end of the first connecting hole is connected to the first end of the corresponding data driving unit, and the other end of the first connecting hole is connected to the parallel data line in the first wiring layer; one end of the second connecting hole is connected to the second end of the corresponding data driving unit, and the other end of the second connecting hole is connected to the parallel data line in the second wiring layer.

[0024] In some exemplary embodiments of this disclosure, the semiconductor device further includes a memory array and input / output pads, wherein the N parallel data lines connect the memory array and the input / output pads.

[0025] In some exemplary embodiments of this disclosure, the storage array includes a plurality of storage cells, wherein each storage cell corresponds one-to-one with the N parallel data lines;

[0026] The semiconductor device further includes latches coupled to the input / output pads and data selectors corresponding to each memory bank, wherein each of the parallel data lines includes a global input / output line, and each of the data selectors is connected to the latches through the global input / output line.

[0027] According to another aspect of this disclosure, a memory is provided, comprising: a semiconductor device as described above.

[0028] In this embodiment, the semiconductor device includes a multilayer wiring structure on a semiconductor substrate, N parallel data lines running along a first direction, and multiple connection units. The multilayer wiring structure includes a first wiring layer and a second wiring layer formed on different metal layers. Each parallel data line is divided into M segments. Multiple connection units are used to connect the N parallel data lines in the M segments. For each segment of N parallel data lines, the N parallel data lines in each segment are divided into multiple groups of M parallel data lines, where M≤N, M>2, and M and N are positive integers. For a group of M parallel data lines, one of the parallel data lines in the group of M parallel data lines is located on the second wiring layer, and the parallel data line has first static wiring on both sides of the second direction. M-1 parallel data lines in the group of M parallel data lines are located on the first wiring layer, and the M-1 parallel data lines have second static wiring on one side of the second direction, which is perpendicular to the first direction of the N parallel data lines. This disclosure reduces the influence of coupling effects between data lines and avoids erroneous signal flipping on the data bus by segmenting the data lines without increasing the number of devices or power consumption.

[0029] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0030] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0031] Figure 1 This diagram illustrates the layout of a parallel data bus with added static traces.

[0032] Figure 2 This diagram illustrates the structure of a semiconductor device provided in an embodiment of the present disclosure.

[0033] Figure 3 Show Figure 2 A schematic diagram showing the distribution of data lines and power lines at point A.

[0034] Figure 4 Show Figure 2 A schematic diagram showing the distribution of data lines and power lines at point B.

[0035] Figure 5 Show Figure 2 A schematic diagram showing the distribution of data lines and power lines at point C.

[0036] Figure 6 This diagram illustrates a structural schematic of an example of a semiconductor device provided in an embodiment of this disclosure.

[0037] Figure 7 This diagram illustrates a second example of a semiconductor device provided in an embodiment of the present disclosure.

[0038] Figure 8 This diagram illustrates the structure of an exemplary semiconductor device according to an embodiment of the present disclosure.

[0039] Figure 9 This diagram illustrates the structure of a semiconductor device example four provided in this disclosure.

[0040] Figure 10 This diagram illustrates the structure of another semiconductor device provided in an embodiment of the present disclosure.

[0041] Figure 11 This diagram illustrates the structure of a memory provided in an embodiment of the present disclosure.

[0042] Figure 12 A schematic diagram of a data I / O path is shown in one embodiment of this disclosure.

[0043] The reference numerals in the attached figures are explained as follows:

[0044] 100, Memory array; 101, Memory cell; 200, Parallel data line; 210, First static routing; 220, Second static routing; 230, Third static routing; 240, Fourth static routing; 300, Connector unit; 400, Input / output pads; 500, Substrate; 1101, SSA; 1102, Data selector; 1103, Latch. Detailed Implementation

[0045] Preferred embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0046] The terms "first" and "second" used herein are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0047] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0048] The following disclosure provides many different implementations or examples for carrying out different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or reference letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0049] like Figure 2 As shown, memories such as Dynamic Random Access Memory (DRAM) typically include a memory array 100 for storing data, data input / output pads 400, and related timing control circuitry. Within the memory chip, data is often transmitted over long metal lines from the memory array 100 to the data input / output pads 400. During data transmission, parasitic capacitance exists between adjacent data lines, known as the coupling effect. Due to this coupling effect, the data bus may experience slower or slower transmission speeds, or even serious consequences such as data flipping, leading to DRAM malfunctions and reducing the effectiveness of DRAM data storage and transmission.

[0050] The coupling capacitance between data lines increases with the length of the trace. For critical signals like data buses, this coupling capacitance is fatal to the normal operation of the circuit: if one parallel trace flips or remains unchanged, while the two adjacent traces flip in opposite directions, the inter-line coupling capacitance will affect the flipping speed of that trace, and in more serious cases, it will cause the signal on that trace to flip incorrectly. For example, if odd and even data buses have different flipping directions, and data bus 0 (even data bus) and data bus 1 (odd data bus) have different flipping directions, and data bus 1 flips in reverse while data bus 0 and data bus 2 both flip in opposite directions, the inter-line coupling capacitance will slow down the flipping speed of data bus 1, and the signal on data bus 1 may also flip incorrectly. As another example, if the data on data bus 0 is 0 and data bus 0 has not flipped, while the data on data bus 1 flips from 0 to 1, the inter-line coupling capacitance will easily cause the signal on data bus 0 to flip incorrectly.

[0051] In related technologies, there are many methods to reduce coupling effects. One method is to perform shielding during layout, and another is to delay or stagger the flip-off times of each data line. For the first method, static traces can be inserted between adjacent data lines; however, during the design process, trace conflicts with shielding can easily occur, preventing the achievement of optimal shielding. The second method can reduce the slow flip-off time of the data bus, but it increases the transmission latency of the bus.

[0052] Figure 1 This diagram illustrates the layout of a parallel data bus with added static traces. Figure 1 This section uses an example of N parallel data buses to illustrate the implementation of shielding during layout in related technologies. N parallel data lines represent the number of parallel data lines from... Figure 2 The long BUS trace from the storage array 100 to the input / output pads 400, Scheme 1 and Scheme 2 represent the cross-section of the long BUS trace in the physical layer corresponding to the dashed box. Both schemes can reduce the coupling effect.

[0053] like Figure 1 As shown in Scheme 1, only 5 of the N data lines are shown, namely BUS <0> ~BUS <4> Among them, BUS <1> BUS <3> Located in the first wiring layer Metal1, BUS <0> BUS <2> BUS <4> Located on the second wiring layer, Metal2, static traces are installed around each BUS data line, for example... Figure 1The VSS in the diagram. In Scheme 2, only 7 of the N data lines are shown, namely BUS. <0> ~BUS <6> Among them, BUS <1> BUS <2> BUS <4> BUS <5> Located in the first wiring layer Metal1, BUS <0> BUS <3> BUS <6> Located in the second routing layer (Metal2), due to limited trace space, static traces are only installed around the data lines in the second routing layer (Metal2), such as... Figure 1 In Metal2, the BUS <0> BUS <3> BUS <6> VSS is set up around it, while BUS is in Metal1. <1> and BUS <2> BUS <4> and BUS <5> The Coupling effect still exists between them.

[0054] As can be seen, inserting static traces (called static traces) between data lines can isolate the simultaneously flipping data buses, reducing data flipping problems caused by coupling capacitance between data buses. However, this method still causes a significant coupling effect when faced with long traces or trace limitations.

[0055] In this disclosure, in response to issues such as trace limitations and device miniaturization in layout shielding, how to design a shielding method that is widely adaptable and can effectively reduce the coupling effect has become an urgent technical problem to be solved.

[0056] It should be noted that this disclosure uses a long trace in DRAM from the storage array 100 storing data to the data input / output pad 400 as an example for illustration. It is also applicable to other situations where long traces are used for data transmission, and this disclosure does not make any specific limitations.

[0057] In order to at least partially solve the aforementioned technical problems, this disclosure reduces the coupling effect between adjacent data buses by segmenting the data bus, thereby improving the effectiveness and reliability of semiconductor devices and memories.

[0058] In this embodiment, the semiconductor device includes a multilayer wiring structure on a semiconductor substrate 500, N parallel data lines 200 traced along a first direction D1, and a plurality of connection units 300. The multilayer wiring structure includes a first wiring layer Metal1 and a second wiring layer Metal2 formed on different metal layers. Each parallel data line 200 is divided into M segments. The plurality of connection units 300 are used to connect the N parallel data lines 200 of the M segments. For each segment of N parallel data lines 200, the N parallel data lines 200 of each segment are divided into multiple groups of M parallel data lines 200, where M≤N, M>2, and M、 N is a positive integer; for a group of M parallel data lines 200, one of the parallel data lines 200 is located in the second routing layer Metal2, and the parallel data line 200 has first static routing 210 on both sides of the second direction D2; M-1 parallel data lines 200 in the group of M parallel data lines 200 are located in the first routing layer Metal1, and the M-1 parallel data lines 200 have second static routing 220 on one side of the second direction D2, the second direction D2 being perpendicular to the first direction D1 of the N parallel data lines 200, wherein the first direction D1 can be referenced. Figures 2-5 , Figures 7-9 For the second direction D2, please refer to... Figures 3-5 , Figures 7-9 This disclosure reduces the impact of coupling effects between data lines by segmenting the data lines, without increasing the number of components or power consumption, and avoids erroneous signal toggling on the data bus.

[0059] The following detailed description of this exemplary implementation method is provided in conjunction with the accompanying drawings and embodiments.

[0060] Figure 2 This diagram illustrates the structure of a semiconductor device provided in an embodiment of the present disclosure. Figures 3-5 Show respectively Figure 2 A schematic diagram showing the distribution of data and power lines at points A, B, and C. (See diagram below.) Figures 2-5 As shown, the semiconductor device provided in this embodiment may include:

[0061] A multilayer wiring structure on a semiconductor substrate 500, the multilayer wiring structure including a first wiring layer Metal1 and a second wiring layer Metal2 formed on different metal layers;

[0062] N parallel data lines 200 are routed along the first direction D1, and each parallel data line 200 is divided into M segments;

[0063] Multiple connection units 300 are used to connect N parallel data lines 200 of segment M;

[0064] For each segment of N parallel data lines 200, the N parallel data lines 200 of each segment are divided into multiple groups of M parallel data lines 200, where M≤N, M>2, and M and N are positive integers.

[0065] For a group of M parallel data lines 200, one of the parallel data lines 200 is located in the second routing layer Metal2, and the parallel data line 200 has a first static routing 210 on both sides of the second direction D2; M-1 parallel data lines 200 in the group of M parallel data lines 200 are located in the first routing layer Metal1, and the M-1 parallel data lines 200 have a second static routing 220 on one side of the second direction D2, wherein the second direction D2 is perpendicular to the first direction D1 of the N parallel data lines 200.

[0066] The semiconductor substrate 500 may be bulk silicon or SOI (silicon-on-insulator). In some embodiments, the semiconductor substrate 500 may be a silicon substrate or may contain other materials, such as, but not limited to, silicon germanium, SGOI (silicon germanium-on-insulator), indium antimonide, lead telluride complex, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0067] like Figures 2-5 As shown, the routing direction of the N parallel data lines 200 is defined as the first direction D1, the length or width direction of the semiconductor substrate 500 is defined as the second direction D2, and the thickness direction of the semiconductor substrate 500 is defined as the third direction D3. The first direction D1, the second direction D2, and the third direction D3 are perpendicular to each other.

[0068] The multilayer wiring structure may include a first wiring layer Metal1 and a second wiring layer Metal2, or other wiring layers. The multilayer wiring layers may be stacked along a third direction D3. The multilayer wiring layers may also be distributed on different surfaces of the semiconductor substrate 500. For example, the first wiring layer Metal1 and the second wiring layer Metal2 may be formed on the upper side of the semiconductor substrate 500, and the zeroth wiring layer may be formed on the lower layer of the semiconductor substrate 500.

[0069] The metal layer may include, but is not limited to, at least one of titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), cobalt (Co), and combinations thereof.

[0070] It should be noted that in DRAM, such as DDR memory, during the semiconductor manufacturing process, a single chip is obtained by dicing a wafer. The chip's memory array 100 may include multiple memory banks 101, also known as banks. Each memory bank 101 may include multiple memory cells composed of word lines (WL) and bit lines (BL) for storing data. The aforementioned memory array 100 is connected to input / output pads 400 via N parallel data lines 200. A memory may include multiple memory arrays 100, for example, two. This disclosure does not limit the number of memory banks 101 included in each memory array 100; for example, it may include eight memory banks 101, or it may include sixteen memory banks 101.

[0071] For example, when the bit width of DDR memory is 64 bits, it can be composed of 8 8-bit chips, called a Rank, and N=8 can be determined.

[0072] In one feasible implementation, each parallel data line 200 is divided into M segments, where M > 2. The number of M segments can be determined according to actual needs. Here, M segments refer to the number of segments of each parallel data line 200 in the first direction D1. For example, the parallel data line 200 can be divided into 3 segments, 4 segments, etc.

[0073] Multiple connection units 300 can connect N parallel data lines 200 in M ​​segments, meaning that the same parallel data lines 200 in different segments of different wiring layers can be connected through the connection units 300. It should be noted that the number of connection units 300 can be determined according to the specific situation.

[0074] Parallel data lines 200 in different segments of the same wiring layer can be obtained when forming the corresponding wiring layer by etching the metal layer, or they can be connected by connection units to form parallel data lines 200 in the same wiring layer but different segments. This disclosure does not make any specific limitations.

[0075] In one embodiment, continue to refer to Figures 3-5 For each segment of N parallel data lines 200, the N parallel data lines 200 of each segment are divided into multiple groups of M parallel data lines 200, where M≤N, M>2, and M and N are positive integers. It should be noted that the number of parallel data lines 200 in each group can be the same or different, depending on the actual situation, and this disclosure does not impose specific limitations.

[0076] In one embodiment, for each set of parallel data lines, one of the parallel data lines corresponds to the second static wiring in a third direction, and M-1 parallel data lines correspond to the first static wiring on one side of the second direction in a third direction.

[0077] In one feasible implementation, the number of first static wiring 220 corresponding to M-1 parallel data lines is ≤ M-1.

[0078] For example, the 8-bit parallel data line 200 can be divided into 3 segments, with each segment consisting of 3 parallel data lines 200 as a group. In this case, the number of parallel data lines 200 in each of the two groups is 3, and the number of parallel data lines 200 in the remaining group is 2.

[0079] For example, if the 16-bit parallel data line 200 is divided into 4 segments, and each segment of the 16-bit parallel data line 200 is divided into 4 groups of 4 parallel data lines 200, the number of parallel data lines 200 in each group is 4.

[0080] After dividing the N parallel data lines 200 of each segment into multiple groups, the multiple groups of N parallel data lines 200 can be arranged sequentially on the semiconductor substrate 500 along the second direction D2.

[0081] For a group of M parallel data lines 200, one of the parallel data lines 200 can be placed on the second routing layer, and M-1 of the parallel data lines 200 can be placed on the first routing layer. One of the parallel data lines 200 has first static routing 210 on both sides of the second direction; the M-1 parallel data lines 200 have second static routing 220 on one side of the second direction, wherein the second direction D2 is perpendicular to the first direction D1 of the N parallel data lines 200. The first static routing 210 and the second static routing 220 can be power lines, such as VSS.

[0082] One of the M parallel data lines 200 in the above set can be any one of the M parallel data lines 200, or it can be the one with a smaller or larger sequence number among the M parallel data lines 200. This disclosure does not make any specific limitation.

[0083] It should be noted that the first static wiring 210 and the second static wiring 220 of the parallel data lines 200 in adjacent groups can be shared or set separately.

[0084] The following is a reference appendix. Figures 3-5 The implementation method of shielding processing by segmentation in the embodiments of this disclosure will be described in detail.

[0085] like Figure 3 As shown, in the first segment of N parallel data lines 200, data lines 1 to M are designated as the first group of parallel data lines 200, and data lines J to N are designated as the last group of parallel data lines 200, where J = NM(M-1)+1. The arrangement of the second group of parallel data lines 200 to the (M-1)th group of parallel data lines 200 can be referenced from the first group of parallel data lines 200, and will not be elaborated here.

[0086] For the first segment of N parallel data lines 200, in the first group of M parallel data lines 200, data line 1 is placed on the second routing layer Metal2, and first static routing 210 is set on both sides of data line 1 in the second direction D2. Data lines 2 to M are placed on the first routing layer Metal1. Second static routing 220 is set on the side of data line 2 away from data line M, and second static routing 220 is set on the side of data line M away from data line 2. For the Mth group of parallel data lines 200, the number of parallel data lines 200 is less than or equal to M. If the number of parallel data lines 200 in the Mth group of parallel data lines 200 is equal to M, the remaining M parallel data lines 200 can be arranged sequentially with reference to the first group of parallel data lines 200. If the number of parallel data lines 200 in the Mth group of parallel data lines 200 is less than M, the Jth parallel data line 200 is placed on the second routing layer Metal2, and the remaining parallel data lines 200 are placed on the first routing layer Metal1.

[0087] like Figure 4 As shown, in the second segment of N parallel data lines 200, data lines 2 to M+1 are designated as the first group of parallel data lines 200, and data lines J+1 to N and data line 1 are designated as the last group of parallel data lines 200. The first parallel data line 200 in each group of parallel data lines 200 is placed on the second routing layer Metal2, and a first static routing 210 is provided on both sides of the aforementioned parallel data line 200. The remaining parallel data lines 200 in each group of parallel data lines 200 are placed on the first routing layer Metal1, and a second static routing 220 is provided on both sides of the remaining parallel data lines 200.

[0088] like Figure 5 As shown, the grouping and arrangement of the data lines in the third segment of N parallel data lines 200 are similar to those in the first and second segments of N data lines, and will not be elaborated here.

[0089] By using the shielding method described above, the coupling effect of data transmission can be reduced to (M-1) / M.

[0090] It should be noted that, Figures 3-5 The serial numbers of the data lines are only schematic representations of possible values. The serial numbers of data lines in different positions can be determined according to the actual situation and should not be used as a limitation on the scope of protection of this disclosure.

[0091] In some embodiments, the arrangement of data lines in each segment of N parallel data lines 200, in addition to adopting... Figures 3-5 Besides arranging the data lines sequentially according to their serial numbers, they can also be arranged according to data lines within a fixed group. For example, the serial numbers of the data lines within each group are the same in different segments. It can be understood that when M=3, data lines 1 to 3 can be used as the first group of parallel data lines 200. In the first segment of N parallel data lines 200, data line 1 is placed on the second routing layer Metal2, with first static routing 210 on both sides of data line 1. Data lines 2 to 3 are placed on the first routing layer Metal1, and data lines 2 and 3 as a whole... Second static routing 220 is set on both sides; in the second segment of N parallel data lines 200, data line 2 is set on the second routing layer Metal2, and first static routing 210 is set on both sides of data line 2. Data lines 1 and 3 are set on the first routing layer Metal1, and second static routing 220 is set on both sides of the whole; in the third segment of N parallel data lines 200, data line 3 is set on the second routing layer Metal2, and data lines 1 and 2 are set on the first routing layer Metal1, and second static routing 220 is set on both sides of the whole. At the same time, data lines 4 to 6 can be used as the second group of parallel data lines 200. The arrangement of data lines 4 to 6 can refer to the arrangement of data lines 1 to 3, and will not be described again here.

[0092] In this embodiment, the semiconductor device includes a multilayer wiring structure on a semiconductor substrate 500, N parallel data lines 200 traced along a first direction D1, and a plurality of connection units 300. The multilayer wiring structure includes a first wiring layer Metal1 and a second wiring layer Metal2 formed on different metal layers. Each parallel data line 200 is divided into M segments. The plurality of connection units 300 are used to connect the N parallel data lines 200 in the M segments. For each segment of N parallel data lines 200, the N parallel data lines 200 in each segment are divided into multiple groups of M parallel data lines 200, where M≤N. M > 2, where M and N are positive integers; for a group of M parallel data lines 200, one of the parallel data lines 200 is located on the second routing layer Metal2, and the parallel data line 200 has first static routing 210 on both sides of the second direction D2; M-1 parallel data lines 200 are located on the first routing layer Metal1, and the M-1 parallel data lines 200 have second static routing 220 on one side of the second direction D2, which is perpendicular to the first direction D1 of the N parallel data lines 200. This disclosure reduces the influence of coupling effects between data lines and avoids erroneous signal toggling on the data bus by segmenting the data lines without increasing the number of devices or power consumption.

[0093] In one feasible implementation, in the same group of parallel data lines 200, one of the parallel data lines 200 disposed on the second wiring layer Metal2 is disposed opposite to the second static wiring 220 disposed on the first wiring layer Metal1 along the third direction D3, and the first static wiring 210 disposed on the second wiring layer Metal2 is disposed opposite to M-1 parallel data lines 200 disposed on the first wiring layer Metal1 along the third direction D3, so as to further reduce the influence of coupling effect between data lines.

[0094] Figure 6 This diagram illustrates a structural schematic of an example of a semiconductor device provided in an embodiment of this disclosure. Figure 6 As shown, the semiconductor device includes N parallel data lines 200 running along a first direction D1. Each parallel data line 200 is divided into 3 segments, and the 3 segments of the N parallel data lines 200 are connected by multiple connection units 300. Figure 6The image shows a portion of the data lines (BUS). <0> ~BUS <8> The arrangement of data lines in each segment. In the first segment with N parallel data lines (200), the BUS... <0> ~BUS <2> As the first set of parallel data lines 200, BUS <3> ~BUS <5> As the second set of parallel data lines 200, BUS <6> As the third set of parallel data lines 200, BUS <0> BUS <3> BUS <6> The BUS is positioned on the second wiring layer Metal2, with first static wiring 210 provided on both sides of the data line. <1> BUS <2> Placed on the first wiring layer Metal1 and in BUS <1> away from the bus <2> A second static cabling 220 is installed on one side of the bus. <4> BUS <5> Placed on the first wiring layer Metal1 and in BUS <4> and BUS <5> A second static wiring 220 is set on both sides. The arrangement of the N parallel data lines 200 in the second and third segments is similar and will not be described again here.

[0095] exist Figure 6 In the middle, the bus on Metal2 level <0> BUS <3> BUS <6> The second static wiring 220, which corresponds to the first wiring layer Metal1, is arranged along the third direction D3, so that the data lines located in the second wiring layer Metal2 are surrounded by static wiring, thereby further reducing the coupling effect between data lines and improving the reliability of the semiconductor device.

[0096] Continue to refer to Figures 3-5 In one embodiment, when the second static wiring 220 is disposed on the side away from the next group of M parallel data lines 200 of the current group, the M-1 parallel data lines 200 located in the last group of M parallel data lines 200 are disposed on the side away from the second static wiring 220 in the second direction D2.

[0097] For example, when M-1 parallel data lines 200 in the Mth group are arranged in the first wiring layer Metal1, if the second static wiring 220 in each group is arranged on a side away from the next group of parallel data lines 200, then Figure 3 Data line N in the middle Figure 4 Data cable 1 in the middle Figure 5 In the data line 2, the side of the three parallel data lines 200 away from the second static wiring 220 is exposed. External environment, electromagnetic interference and other conditions may affect the data transmitted in the three parallel data lines 200. A third static wiring 230 can be set on the side of the three parallel data lines 200 away from the second static wiring 220 to reduce the impact on the parallel data lines 200 and improve system reliability.

[0098] In one embodiment, when the second static wiring 220 is disposed on the side of the next group of M parallel data lines 200 close to the current group, a fourth static wiring 240 is disposed on the side of the M-1 parallel data lines 200 of the first group of M parallel data lines 200 away from the second static wiring 220.

[0099] For example, if the second static wiring 220 in each group is located on the side closer to the next group of parallel data lines 200, then Figure 3 Data cable 2 in the middle Figure 4 Data cable 3 in the middle Figure 5 The side of data line 4 away from the second static wiring 220 is exposed. At this time, a fourth static wiring 240 can be set on the side of the three parallel data lines 200 away from the second static wiring 220 to reduce the impact of external environmental factors on the data transmission of the parallel data lines 200 and improve system reliability.

[0100] To deepen the understanding of the arrangement of the parallel data lines 200 and static wiring in this disclosure, the following will be combined with... Figures 7 to 9 Please provide a detailed explanation.

[0101] Figure 7 This diagram illustrates a structural schematic of a second example of a semiconductor device provided in an embodiment of this disclosure. Figure 7 In this configuration, the number N of parallel data lines 200 is 8, and each parallel data line 200 is divided into 3 segments, which can correspond to... Figure 2 At points A, B, and C, each parallel data line 200 is divided into three groups. The first and second groups each contain three parallel data lines 200, while the third group contains two data lines. Figure 7 China adopts BUS Let 200 represent the i-th parallel data line, where i = {1, 2, ..., n}, and VSS is used to represent static routing.

[0102] For parallel data line 200 at point A, BUS <0> BUS <3> and BUS <6> Located on the second wiring layer Metal2, BUS <0> BUS <3> and BUS <6> The first static wiring 210 is set on both sides of the BUS. <1> BUS <2> BUS <4> BUS <5> BUS <7> Located in the first wiring layer Metal1, BUS <2> and BUS <4> Between, BUS <5> and BUS <7> A second static wiring 220 is set between them, in the BUS <1> away from the bus <2> A second static wiring 220 is installed on one side of the BUS. <7> away from the bus <5> A third static cabling 230 is installed on one side. Among them, the BUS... <0> BUS <3> BUS <6> The second static wiring 220 in the first wiring layer Metal1 is set along the third direction D3 (that is, the two are in the same position in the second direction D2, but different in the third direction D3), and the parallel data line 200 set in the first wiring layer Metal1 is set along the third direction D3 corresponding to the first static wiring 210 in the second wiring layer Metal2 (that is, the two are in the same position in the second direction D2, but different in the third direction D3).

[0103] The arrangement of static wiring at points B and C is the same as that at point A. The only difference is that the different data lines need to be placed on the second wiring layer, Metal2. This will not be elaborated further here.

[0104] The number of first static wirings 210 corresponding to the parallel data lines 200 of the first wiring layer Metal1 can be the same as the number of parallel data lines 200, and the two are set in a one-to-one correspondence; the number of first static wirings 210 corresponding to the parallel data lines 200 of the first wiring layer Metal1 can also be less than the number of parallel data lines 200. For example, if one first static wiring 210 is set to correspond to the parallel data lines 200 of the first wiring layer Metal1, then the first static wiring 210 can cover the area where the parallel data lines 200 of the first wiring layer Metal1 are located, that is, one first static wiring 210 corresponds to two parallel data lines 200.

[0105] Figure 8 This diagram illustrates the structure of Example 3 of a semiconductor device provided in an embodiment of this disclosure. Figure 8 In the example, the number N of parallel data lines 200 is 8, and each parallel data line 200 is divided into 3 segments, which can correspond to... Figure 2 At points A, B, and C, each parallel data line 200 is divided into three groups. The first and second groups each contain three parallel data lines 200, while the third group contains two data lines. Figure 8 China adopts BUS Let 200 represent the i-th parallel data line, where i = {1, 2, ..., n}, and VSS is used to represent static routing.

[0106] For parallel data line 200 at point A, BUS <0> BUS <3> and BUS <6> Located on the second wiring layer Metal2, BUS <0> BUS <3> and BUS <6> The first static wiring 210 is set on both sides of the BUS. <1> BUS <2> BUS <4> BUS <5> BUS <7> Located in the first wiring layer Metal1, BUS <2> and BUS <4> Between, BUS <5> and BUS <7> A second static wiring 220 is set between them, in the BUS <7> away from the bus <5> A second static wiring 220 is installed on one side of the BUS. <1> away from the bus <2> A fourth static cabling 240 is installed on one side. Among them, the BUS... <0> BUS <3> BUS <6> The second static wiring 220 in the first wiring layer Metal1 is set along the third direction D3, and the parallel data line 200 set in the first wiring layer Metal1 is set along the third direction D3, corresponding to the first static wiring 210 located in the second wiring layer Metal2.

[0107] The arrangement of static wiring at points B and C is the same as that at point A. The only difference is that the different data lines need to be placed on the second wiring layer, Metal2. This will not be elaborated further here.

[0108] The number of first static wirings 210 corresponding to the parallel data lines 200 of the first wiring layer Metal1 can be the same as the number of parallel data lines 200, and the two are set in a one-to-one correspondence; the number of first static wirings 210 corresponding to the parallel data lines 200 of the first wiring layer Metal1 can also be less than the number of parallel data lines 200. For example, if one first static wiring 210 is set to correspond to the parallel data lines 200 of the first wiring layer Metal1, then the first static wiring 210 can cover the area where the parallel data lines 200 of the first wiring layer Metal1 are located, that is, one first static wiring 210 corresponds to two parallel data lines 200.

[0109] Figure 9 This diagram illustrates a structural schematic of Example 4 of a semiconductor device provided in an embodiment of this disclosure. Figure 9 In this configuration, the number N of parallel data lines 200 is 8. Each parallel data line 200 is divided into 4 segments, each segment is further divided into 2 groups, and each group contains four parallel data lines 200. Figure 9 China adopts BUS Let 200 represent the i-th parallel data line, where i = {1, 2, ..., n}, and VSS is used to represent static routing.

[0110] For the first segment of parallel data line 200, BUS <0> and BUS <4> Located on the second wiring layer Metal2, BUS <0> A first static cabling 210 is installed on one side of the BUS. <4> Three first static cabling lines 210 are installed on each side of the BUS. <1> ~BUS <3> BUS <5> ~BUS <7> Located in the first wiring layer Metal1, BUS <3> and BUS <5> A second static cabling 220 is set between them, in the BUS <1> away from the bus <2> A second static wiring 220 is installed on one side of the BUS. <7> away from the bus <6> A third static wiring 230 is installed on one side.

[0111] The arrangement of the second to fourth static wiring segments is the same as that of the first static wiring segment. The only difference is that the different data lines are placed on the second wiring layer, Metal2. This will not be elaborated further here.

[0112] The number of first static wirings 210 in the second wiring layer can be the same as the number of parallel data lines 200 in the corresponding first wiring layer, that is, the first static wirings 210 and the parallel data lines 200 correspond one-to-one; or it can be less than the number of parallel data lines 200 in the corresponding first wiring layer, that is, one first static wiring 210 corresponds to multiple parallel data lines 200. This disclosure does not make any specific limitation.

[0113] It should be noted that the arrangement order of the parallel data lines 200 in each segment and the arrangement method of the fourth static wiring 240 can be referred to the description in the aforementioned embodiments, and will not be repeated here.

[0114] The connection methods for each of the parallel data lines 200 are described in detail below.

[0115] In one embodiment, the number of connection units 300 is M-1, and the M-1 connection units 300 are sequentially connected between N parallel data lines 200 in adjacent segments. Each connection unit 300 includes a through hole disposed in an insulating layer between the first wiring layer Metal1 and the second wiring layer Metal2, and the through hole is filled with conductive material.

[0116] For example, each connecting hole connects to the same parallel data line 200 in an adjacent segment at both ends. For instance, in... Figure 7 In the middle, one end of a connecting hole can be connected to the BUS in Metal1 at point A. <1> The other end can be connected to the BUS in Metal2 at point B. <1> .

[0117] In one embodiment, a metal layer is deposited on a semiconductor substrate 500. By etching the metal layer, a first wiring layer Metal1 with the aforementioned arrangement of parallel data lines 200 and static wiring can be obtained. Further, an insulating layer can be added to the first wiring layer Metal1, a metal layer is deposited on the insulating layer, and the metal layer is etched to obtain a second wiring layer Metal2 with the aforementioned arrangement of parallel data lines 200 and static wiring.

[0118] The insulating layer may be made of, but is not limited to, at least one or a combination of silicon oxide, silicon oxynitride, and a low-k material having a lower dielectric constant than silicon oxide.

[0119] The metal layer may be made of at least one or more of the following metal materials, including but not limited to aluminum (Al), tungsten (Wo), and copper (Cu).

[0120] In this embodiment of the disclosure, by providing a through hole in the insulating layer between the first wiring layer Metal1 and the second wiring layer Metal2 to connect adjacent segments of parallel data lines 200, the same parallel data lines 200 in different layers are connected, thereby improving the reliability of the connection of multiple segments of parallel data lines 200.

[0121] Continue to refer to Figure 6 In one embodiment, the connection unit 300 includes a data driving unit, and the number of multiple data driving units is M+1. The M+1 data driving units are connected to the end of the first segment of N parallel data lines 200, between the adjacent segments of N parallel data lines 200, and to the end of the last segment of N parallel data lines 200.

[0122] like Figure 6 As shown, the data driving unit can be implemented using a buffer. A buffer can include a cascade of an even number of inverter chains. The input and output of the buffer are in phase, which can increase the signal driving capability and also modify the signal timing.

[0123] In this embodiment of the disclosure, N parallel data lines 200 of adjacent segments are connected by a data driving unit. Based on the connection of the parallel data lines 200 of adjacent segments, the delay of the parallel data lines 200 can be further reduced and the circuit driving capability can be improved.

[0124] In one embodiment, the multilayer wiring structure further includes a zeroth wiring layer, Metal0 (…). Figure 6 (Not shown), the data-driven unit BUFFER is set on the zero-level wiring layer Metal0.

[0125] The zero wiring layer Metal0 can be disposed between the first wiring layer Metal1 and the semiconductor substrate 500, or it can be disposed on the surface of the semiconductor substrate 500 away from the first wiring layer Metal1. This disclosure does not make any specific limitation.

[0126] In one embodiment, an insulating layer is provided between the zero wiring layer Metal0, the first wiring layer Metal1, and the second wiring layer Metal2; for a parallel data line 200 in different segments, the insulating layer has a first connecting hole and a second connecting hole, which are filled with conductive material; wherein, one end of the first connecting hole is connected to the first end of the corresponding data driving unit, and the other end of the first connecting hole is connected to a parallel data line 200 in the first wiring layer Metal1; one end of the second connecting hole is connected to the second end of the corresponding data driving unit, and the other end of the second connecting hole is connected to a parallel data line 200 in the second wiring layer Metal2.

[0127] In this embodiment of the disclosure, adjacent segments of the same parallel data line 200 can be connected via a data driving unit, a first connecting hole, and a second connecting hole. For example, in Figure 7 In the middle, the BUS at point A (Metal1) can be connected through the first connecting hole. <1> One end of the data drive unit is connected to the BUS of Metal2 at point B via the second connecting hole. <1> Electrical connection can be achieved at the other end of the data driving unit by filling the first and second connecting holes with conductive material.

[0128] It should be noted that the selection of materials for insulating layers, conductive materials, etc. can be referred to the aforementioned embodiments, and will not be repeated here.

[0129] Figure 10 A schematic diagram of the structure of another semiconductor device provided in an embodiment of this disclosure is shown. For example... Figure 10 As shown, the semiconductor device may include only M-1 data driving units connected between adjacent parallel data lines, but this disclosure does not make any specific limitation.

[0130] In one embodiment, the semiconductor device further includes a memory array 100 and input / output pads 400, wherein N parallel data lines 200 connect the memory array 100 and the input / output pads 400.

[0131] In one embodiment, the memory array 100 includes a plurality of memory banks 101, wherein each memory bank 101 corresponds one-to-one with N parallel data lines 200; the semiconductor device also includes a latch 1103 coupled to an input / output pad 400 and a data selector 1102 corresponding one-to-one with each memory bank 101, wherein each parallel data line includes a global input / output line, and each data selector 1102 is connected to the latch 1103 through the global input / output line.

[0132] The location of the data bus is explained below.

[0133] In one exemplary embodiment, the memory array may include a plurality of memory banks 101, wherein each memory bank 101 corresponds one-to-one with a plurality of parallel data buses; the memory may also include a latch 1103 and a data selector 1102 corresponding one-to-one with each memory bank 101, wherein each data bus includes a global input / output line, and each data selector 1102 is connected to the latch 1103 through the global input / output line.

[0134] For example, such as Figure 11 As shown, the memory array 100 includes eight banks 101, namely bank 1 to bank 8. Each bank 101 may include multiple memory cells composed of word lines and bit lines and eight LIOs (Local I / O), meaning that each bank 101 can output 8 bits of data in parallel. Each bank 101 is connected to a multiplexer (MUX) 1102 via multiple parallel data buses. It should be noted that a second sensor amplifier (SSA) 1101 can be connected between the bank 101 and the data selector 1102. Data can be read from the bank 101, and the read data passes through the first sensor amplifier, the second sensor amplifier 1101, and the data selector 1102 inside the bank 101 to reach the latch 1103, and then is output to the data input / output (DQ) pads 400.

[0135] It should be noted that the second sensitive amplifier is a bank-level amplification circuit. Based on the first sensitive amplifier SA (sensor amplifier) ​​on the bit line in the memory bank, it further amplifies the data read from the memory bank to its full swing before sending it to the data selector 1102. The data selector 1102 can control the reading and writing of data by selecting the control signals RDEN (read enable signal) and WREN (write enable signal). The data selector 1102 includes AND logic. When the read control signal RDEN is high, the read control signal RDEN is ANDed with the read data before being output to the latch 1103. The data selector 1102 also outputs the latch enable signal Latch Enable to the latch 1103.

[0136] For example, refer to Figure 12 After data is read from the storage cell of memory bank 101, it is amplified from the bit line (BL) by the first sensitive amplifier SA and then sent to the LIO (Local I / O, LIO is the data bus inside memory bank 101). It first passes through the LSA (not in the memory bank 101) inside the memory bank 101. Figure 11 As shown, the LSA (data gate circuit inside the memory bank) sends data from memory bank 101 to MIO (data bus coupled to memory bank 101 and data selector 1102), then amplifies it to full swing via the second sensitive amplifier SSA 1101, and then performs precharge-evaluation (a type of memory read operation) processing via data selector 1102. Figure 12 As shown, after receiving the high RDEN signal, the data selector 1102 reads the data and then sends it to the latch 1103 via GIO (Global IO, GIO is the data bus between MUX 1102 and latch 1103) for latching. After that, it goes through parallel-to-serial conversion (P2S) and impedance matching (OCD) and finally outputs the data to the DQ pad 400 (P2S and OCD are not shown in the figure).

[0137] The data selector 1102 selects RDEN and WREN to control whether the data is read or written. The Mux module also includes AND logic, which performs a calculation on RDEN / WREN and the data and then sends the result to latch 1103.

[0138] It should be noted that the complete data routing path is from BL to LIO, then to MIO, and finally to GIO (also called the datapath, global input / output line). LIO and MIO are relatively short, while the GIO routing path is the longest. This disclosure primarily focuses on improvements to the GIO segment from MUX 1102 to latch 1103. That is, segmented processing is performed on the parallel data lines of the GIO, but this disclosure is not limited to this.

[0139] In this embodiment, by segmenting some parallel data lines of the Global Input / Output Line (GIO) and performing shielding on some data lines, the impact of inter-line coupling is reduced, and the impact of inter-line coupling on data transmission is also reduced to a certain extent. The static routing arrangement is the same in different segments, and only the arrangement of the shielded data lines needs to be adjusted, effectively reducing the process difficulty.

[0140] Those skilled in the art will understand that various aspects of the present invention can be implemented as systems, methods, or program products. Therefore, various aspects of the present invention can be specifically implemented in the following forms: entirely in hardware, entirely in software (including firmware, microcode, etc.), or in a combination of hardware and software, collectively referred to herein as "circuit," "module," or "system."

[0141] Furthermore, embodiments of this disclosure also provide a memory. In one embodiment, the memory can be combined with... Figures 2-12 Any of the semiconductor devices provided in the above embodiments shown.

[0142] In one feasible implementation, the memory can be either non-volatile or volatile. Non-volatile memory includes flash memory such as NOR Flash and NAND Flash, or read-only memory such as PROM (Programmable Read-Only Memory), EAROM (Electrically Alterable Read-Only Memory), EPROM (Erasable Programmable Read-Only Memory), and EEPROM (Electrically Erasable Programmable Read-Only Memory). Taking NOR flash memory as an example, it can be a non-volatile memory based on the CHE (Channel Hot Electron) effect. Volatile memory can be DRAM.

[0143] In another feasible implementation, the memory may include the aforementioned semiconductor device, wherein each parallel data line in the semiconductor device is divided into M segments, and multiple connection units connect the M segments to the N parallel data lines to reduce inter-line coupling effects. The semiconductor device is described in the relevant sections of the embodiments of this disclosure and will not be repeated here.

[0144] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. This disclosure is not limited to the specific steps and structures described above and shown in the figures. Those skilled in the art can make various changes, modifications, and additions after understanding the spirit of this disclosure. Furthermore, for the sake of brevity, detailed descriptions of known technologies are omitted here.

[0145] In the several embodiments provided in this disclosure, it should be understood that the disclosed circuits, units, and devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the couplings or direct couplings or communication connections shown or discussed may be indirect couplings or communication connections between devices or units through some ports, and may be electrical, mechanical, or other forms.

[0146] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0147] In addition, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0148] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

[0149] Therefore, the scope of protection of this disclosure should be determined by the scope of the claims. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A semiconductor device, characterized in that, include: A multilayer wiring structure on a semiconductor substrate, the multilayer wiring structure including a first wiring layer and a second wiring layer formed on different metal layers; N parallel data lines running along the first direction, each parallel data line is divided into M segments; Multiple connection units are used to connect N parallel data lines of segment M; For each segment of N parallel data lines, the N parallel data lines of each segment are divided into multiple groups of M parallel data lines, where M≤N, M>2, and M and N are positive integers. For a group of M parallel data lines, one of the parallel data lines in the group of M parallel data lines is located in the second routing layer, and the one parallel data line has first static routing on both sides of the second direction; M-1 parallel data lines in the group of M parallel data lines are located in the first routing layer, and the M-1 parallel data lines have second static routing on one side of the second direction, wherein the second direction is perpendicular to the first direction of the routing of the N parallel data lines; In each set of parallel data lines, one of the parallel data lines is arranged in a third direction corresponding to the second static wiring, and the M-1 parallel data lines are arranged in a third direction corresponding to the first static wiring of one of the parallel data lines on one side of the second direction, wherein the third direction is perpendicular to the second direction.

2. The semiconductor device according to claim 1, characterized in that, The number of the first static wiring corresponding to the M-1 parallel data lines is ≤ M-1.

3. The semiconductor device according to claim 1, characterized in that, When the second static routing is located on the side away from the next group of M parallel data lines in the current group, the M-1 parallel data lines located in the last group of M parallel data lines are provided with a third static routing on the side away from the second static routing in the second direction.

4. The semiconductor device according to claim 1, characterized in that, When the second static routing is located on the side of the next group of M parallel data lines close to the current group, the fourth static routing is located on the side of the M-1 parallel data lines of the first group away from the second static routing.

5. The semiconductor device according to claim 1, characterized in that, The number of connection units is M-1, and the multiple connection units are sequentially connected between N parallel data lines in adjacent segments. Each connection unit includes a through hole disposed in an insulating layer between the first wiring layer and the second wiring layer, and the through hole is filled with conductive material.

6. The semiconductor device according to claim 1, characterized in that, The connection unit includes multiple data driving units, the number of which is M+1. The M+1 data driving units are connected to the ends of the first segment of N parallel data lines, between the N parallel data lines of adjacent segments, and to the ends of the last segment of N parallel data lines.

7. The semiconductor device according to claim 6, characterized in that, The multi-layer cabling structure further includes a zero-level cabling layer, and the data driving unit is disposed on the zero-level cabling layer.

8. The semiconductor device according to claim 7, characterized in that, An insulating layer is provided between the zero wiring layer, the first wiring layer and the second wiring layer; For a parallel data line in different segments, the insulating layer is provided with a first connecting hole and a second connecting hole, and the first connecting hole and the second connecting hole are filled with conductive material; Wherein, one end of the first connecting hole is connected to the first end of the corresponding data driving unit, and the other end of the first connecting hole is connected to the parallel data line in the first wiring layer; one end of the second connecting hole is connected to the second end of the corresponding data driving unit, and the other end of the second connecting hole is connected to the parallel data line in the second wiring layer.

9. The semiconductor device according to any one of claims 1-8, characterized in that, The semiconductor device further includes a memory array and input / output pads, wherein the N parallel data lines connect the memory array and the input / output pads.

10. The semiconductor device according to claim 9, characterized in that, The storage array includes multiple storage cells, wherein each storage cell corresponds one-to-one with the N parallel data lines; The semiconductor device further includes latches coupled to the input / output pads and data selectors corresponding to each memory bank, wherein each of the parallel data lines includes a global input / output line, and each of the data selectors is connected to the latches through the global input / output line.

11. A memory, characterized in that, Includes the semiconductor device as described in any one of claims 1 to 10.

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