Offset colar for memory system

Abstract

The invention relates to an offset pillar for a memory system. A memory system may include a memory device composed of an interface die and one or more memory dies stacked atop the interface die. The interface die may include a power post coupled with a power supply and configured to route power to each of the stacked dies. The interface die may be larger than the stacked die (e.g., in a horizontal direction) such that the power posts are positioned near a periphery of the stacked die and "offset" from the respective power posts of the stacked die.

Description

[0001] Cross-reference

[0002] This patent application claims priority to U.S. Patent Application No. 19 / 178,669, filed April 14, 2025, entitled “Offset Pillars for a Memory System”, and U.S. Patent Application No. 63 / 645,689, filed May 10, 2024, entitled “Offset Pillars for an Memory System”, each of which is assigned to its assignee and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to offset columns in memory systems. Background Technology

[0004] Memory devices are used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, typically represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored by the memory cell. To store information, the memory device can write states (e.g., program, set, assign) to the memory cell. To access the stored information, the memory device can read (e.g., sense, detect, retrieve, determine) the states from the memory cell. Summary of the Invention

[0005] Describe a device. The device may include: an interface die; a first memory die coupled to the interface die, the first memory die including: a plurality of first conductive pillars, each including a set of first power pillars coupled to the interface die and first thermal pillars decoupled from the interface die; and a first wiring structure configured to be electrically coupled to the set of first power pillars and the first thermal pillars; and a second memory die coupled to the first memory die, the second memory die including: a plurality of second conductive pillars, each including second power pillars vertically aligned with and connected to the first wiring structure and a set of second thermal pillars each vertically aligned with a corresponding power pillar in the set of first power pillars and decoupled from the first memory die; and a second wiring structure configured to be electrically coupled to the second power pillars and the set of second thermal pillars.

[0006] Describe an apparatus. The apparatus may include: a plurality of stacked memory dies, wherein each of the plurality of stacked memory dies includes a corresponding power rail: a first power ridge coupled to each of the plurality of stacked memory dies, wherein the first power ridge is located in a first plane and wherein the first power ridge is configured to route a first power signal between each corresponding power rail of the plurality of stacked memory dies; a second power ridge coupled to a subset of the plurality of stacked memory dies, wherein the second power ridge is located in a second plane and wherein the second power ridge is configured to route the first power signal between the corresponding power rail of each of the subset of the plurality of stacked memory dies; a first plurality of power pillars coupled to and offset from the first power ridge and the second power ridge of the plurality of stacked memory dies, wherein each of the first plurality of power pillars is configured to route the first power signal between a first power rail of the first memory die and the second power ridge; and a first hot pillar coupled to the first power rail of the first memory die of the plurality of stacked memory dies, wherein the first hot pillar is located in the second plane.

[0007] Describe a device. The device may include: an interface die; a first memory die coupled to the interface die, the first memory die including: a plurality of first conductive pillars, each including a set of first power pillars coupled to the interface die and a set of first thermal pillars decoupled from the interface die; and a first wiring structure configured to be electrically coupled to the set of first power pillars and the first thermal pillars; a second memory die coupled to the first memory die, the second memory die including: a plurality of second conductive pillars, each including second power pillars vertically aligned with and connected to the first thermal pillars and a set of second thermal pillars, each vertically aligned with a corresponding power pillar in the set of first power pillars and decoupled from the first memory die; and a second wiring structure configured to be electrically coupled to the second power pillars and the set of first power pillars and the first thermal pillars. The first memory die is electrically coupled to a second hot post; and a third memory die coupled to the second memory die, the third memory die comprising: a plurality of third conductive posts, each including a third power post vertically aligned with and connected to the second power post and a set of third hot posts each vertically aligned with and decoupled from the second memory die of a corresponding hot post in the set of second hot posts; and a third wiring structure configured to electrically connect the third power posts and the set of third hot posts, wherein the first memory die includes a first memory cell, the second memory die includes a second memory cell vertically aligned with the first memory cell, and the third memory die includes a third memory cell vertically aligned with the second memory cell, and wherein the interface die includes a circuit system vertically aligned with the first hot post. Attached Figure Description

[0008] Figure 1 Examples of systems that support offset columns of memory systems, based on the examples disclosed herein, are presented.

[0009] Figure 2A and 2B Examples of offset pillar architectures for supporting memory systems are shown, based on the examples disclosed herein.

[0010] Figure 3 Examples of offset pillar architectures for supporting memory systems are shown, based on the examples disclosed herein.

[0011] Figure 4 Examples of offset pillar architectures for supporting memory systems are shown, based on the examples disclosed herein. Detailed Implementation

[0012] Some memory devices may include one or more dies in a stacked configuration. For example, a high-bandwidth memory (HBM) device may include an interface die coupled to a power supply and may include one or more dies (e.g., a core die, a second die, a third die, etc.) stacked on top of the interface die. The stacked dies may include a corresponding memory array (e.g., a memory bank, a DRAM memory bank) and the interface die may include circuitry (e.g., complementary metal-oxide-semiconductor (CMOS) circuitry) for accessing the corresponding memory array. In some examples, the dies may be coupled to corresponding pillars that can route power (e.g., power pillars) between dies or provide a thermal barrier between dies (e.g., thermal dies).

[0013] Conventional stacked memory devices can route power between dies using power ridges that extend from the interface die to the topmost stacked die in a single vertical plane. Due to the configuration of the power ridges, there are few suitable locations on the memory device to position them. Therefore, such power ridges are typically located near the middle of the die (e.g., in the horizontal direction), requiring power to travel both vertically (e.g., upwards from the interface die) and horizontally (e.g., outwards from the power ridge) to power the components of the respective memory die. Thus, determining the placement of the power ridges increases the design complexity of the memory device, and the additional distance the power travels (e.g., in the horizontal direction) degrades the overall performance of the device. The resistance of the conductive path in the power grid can affect the power consumed by the memory device. Therefore, memory devices with reduced resistance in their power grids are desirable.

[0014] This document describes a stacked memory device with additional power pillars at the interface die. In some instances, the memory system may include a memory device comprising an interface die, on top of which one or more memory dies are stacked. The interface die may be coupled to multiple power pillars, each of which is coupled to a first stacked memory die (e.g., a first memory die). Some of the power pillars coupled to the interface die may be within a power ridge, while others may be outside the power ridge but still connected to a power delivery network. Having multiple power pillar connections between the interface die and the first stacked memory dies reduces the resistance of the power delivery network and improves the performance of the memory system. The power pillars may be connected to (e.g., coupled to) a power supply and can provide power to each of the dies stacked on the interface die. The power pillars may route power using corresponding power pillars that are “offset” from each other (e.g., in the vertical direction). That is, the configuration of the interface die may allow multiple paths (e.g., through-silicon vias (TSVs)) to extend from the power pillars and connect to the power supply.

[0015] These additional power connection points can deliver power to the stacked dies in a more uniform manner, which improves the overall performance of the memory device. Furthermore, because the interface die can be (e.g., horizontally) larger than the die stacked on top of it, the additional power pillars can be positioned relatively close to the periphery of the stacked dies without increasing the overall size of the memory device. Therefore, implementing the offset pillars described herein can increase the number of power connection points of the memory device and improve its overall performance without increasing its size.

[0016] Beyond their application in the memory systems described herein, offset columns in memory systems can often be implemented to improve the performance of various electronic devices and systems, including artificial intelligence (AI) applications, augmented reality (AR) applications, virtual reality (VR) applications, and games. Some electronic device applications, including high-performance applications such as AI, AR, VR, and games, are associated with relatively high processing requirements to meet user expectations. Therefore, improving the processing power of electronic devices by reducing response time, improving power consumption, reducing complexity, increasing data throughput or access speed, reducing communication time, or increasing memory capacity or density, as well as other performance metrics, can improve user experience or appeal. Implementing the techniques described herein can improve the performance of electronic devices by providing additional power connections at or near the periphery of the memory device, which can reduce processing or latency, improve response time, or otherwise improve user experience and other benefits.

[0017] The features of this disclosure are described and illustrated in the context of systems and architectures. The features of this disclosure are further described and illustrated in the context of various architectures supporting offset pillars in memory systems.

[0018] Figure 1This describes an example of system 100, which supports offset pillars of memory systems according to the examples disclosed herein. System 100 may include portions of electronic devices, such as computing devices, mobile computing devices, wireless communication devices, graphics processing devices, vehicles, smartphones, wearable devices, internet-connected devices, vehicle controllers, single-chip system (SoC) or other fixed or portable electronic systems, and other examples. System 100 includes a host device 105, a memory device 110, and one or more channels 115 coupling the host device 105 to the memory device 110 (e.g., for supporting communication coupling). System 100 may include any number of one or more memory systems 110 coupled to the host system 105.

[0019] Host system 105 may include one or more components (e.g., circuitry, processing circuitry, one or more processing components) that use memory to perform processes, any or more of which may be referred to or included in processor 125. Processor 125 may include at least one of one or more processing elements that can be co-located or distributed, including general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, controllers, discrete gate or transistor logic, one or more discrete hardware components or combinations thereof. Processor 125 may be an instance of a central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or SoC or components thereof, and other instances thereof.

[0020] Host system 105 may also include at least one of one or more components (e.g., circuitry, logic, instructions) that implement the functions of an external memory controller (e.g., a host system memory controller), which may be referred to as or included in host system controller 120. For example, host system controller 120 may issue commands or other signaling for operating memory system 110, such as write commands, read commands, configuration signaling, or other operational signaling. In some instances, host system controller 120 or the associated functions described herein may be implemented by or be part of processor 125. For example, host system controller 120 may be hardware, instructions (e.g., software, firmware), or a combination thereof implemented by processor 125 or other components of host system 105. In various instances, host system 105 or host system controller 120 may be referred to as a host.

[0021] Memory system 110 provides physical memory locations (e.g., addresses) that can be used or referenced by system 100. Memory system 110 may include memory system controller 140 and one or more memory devices 145 (e.g., memory packages, memory dies, memory chips) operable to store data. Memory system 110 may be configured to operate with different types of host systems 105 and may respond to commands from host system 105 (e.g., from host system controller 120). For example, memory system 110 (e.g., memory system controller 140) may receive write commands instructing memory system 110 to store data received from host system 105, or read commands instructing memory system 110 to provide data stored in memory device 145 to host system 105, or refresh commands instructing memory system 110 to refresh data stored in memory device 145, as well as other types of commands and operations.

[0022] The memory system controller 140 may include at least one of one or more components (e.g., circuitry, logic, instructions) operable to control the operation of the memory system 110. The memory system controller 140 may include hardware or instructions supporting the memory system 110 in performing various operations, and is operable to receive, transmit, or respond to commands, data, or control information related to the operation of the memory system 110. The memory system controller 140 is operable to communicate with one or more of the host system controller 120, one or more memory devices 145, or processor 125. In some instances, the memory system controller 140 may cooperate with the host system controller 120, the local controller 150 of the memory device 145, or any combination thereof to control the operation of the memory system 110. Although instances of the memory system controller 140 are described as a separate component of the memory system 110, in some instances, functional aspects of the memory system 110 may be implemented by at least one of the processor 125, the host system controller 120, one or more local controllers 150, or any combination thereof.

[0023] Each memory device 145 may include a local controller 150 and one or more memory arrays 155. The memory array 155 may be a collection of memory cells (e.g., a two-dimensional array, a three-dimensional array), wherein each memory cell is operable to store data (e.g., as one or more storage bits). Each memory array 155 may include memory cells of various architectures, such as random access memory (RAM) cells, dynamic RAM (DRAM) cells, synchronous dynamic RAM (SDRAM) cells, static RAM (SRAM) cells, ferroelectric RAM (FeRAM) cells, magnetic RAM (MRAM) cells, resistive RAM (RRAM) cells, phase-change memory (PCM) cells, chalcogenide memory cells, NOR memory cells, NAND memory cells, or any combination thereof.

[0024] Local controller 150 may include at least one of one or more components (e.g., circuitry, logic, instructions) operable to control the operation of memory device 145. In some instances, local controller 150 is operable to communicate with memory system controller 140 (e.g., to receive or transmit data or commands, or both). In some instances, memory system 110 may not include memory system controller 140, and local controller 150 or host system controller 120 may perform the functions of memory system controller 140 described herein. In some instances, local controller 150 or memory system controller 140, or both, may include decoding components operable to access addresses of memory array 155, sensing components for sensing the state of memory cells in memory array 155, writing components for writing state to memory cells in memory array 155, or various other components operable to support the described operations of memory system 110.

[0025] The host system 105 (e.g., host system controller 120) and the memory system 110 (e.g., memory system controller 140) may use one or more channels 115 to convey information (e.g., data, commands, control information, configuration information, timing information). Each channel 115 may be an instance of a transmission medium carrying information, and each channel 115 may contain one or more signal paths (e.g., transmission medium, electrical conductor, conductive path) between terminals (e.g., nodes, pins, contacts) associated with components of the system 100. Terminals may be instances of conductive input or output points of devices of the system 100, and terminals may be operable as part of channel 115. To support communication via channel 115, host system 105 (e.g., host system controller 120) and memory system 110 (e.g., memory system controller 140) may include receivers (e.g., latches) for receiving signals, transmitters (e.g., drivers) for transmitting signals, decoders for decoding or demodulating received signals or encoders for encoding or modulating signals to be transmitted, and other components that support signaling via channel 115, which may be included in the respective interface portions of the respective systems.

[0026] Channel 115 may be dedicated to conveying one or more types of information, and channel 115 may include unidirectional channels, bidirectional channels, or both. For example, channel 115 may include one or more command / address channels, one or more clock signal channels, one or more data channels, and other channels or combinations thereof. In some instances, channel 115 may be configured to supply power from one system to another (e.g., from host system 105 to memory system 110, depending on the regulated voltage). In some instances, at least a subset of channels 115 may be configured according to protocols (e.g., logical protocols, communication protocols, operational protocols, industry standards) that support the configuration operation of host system 105 and memory system 110 and the interaction between host system 105 and memory system 110.

[0027] This document describes a stacked memory device 145 having additional power pillars at the interface die. In some instances, the memory system 110 may include the memory device 145, which includes an interface die with one or more memory dies stacked on top of it. The interface die may be coupled to multiple power pillars, each of which is coupled to a first stacked memory die (e.g., a first memory die). Some of the power pillars coupled to the interface die may be within a power ridge, while others may be outside the power ridge but still connected to a power delivery network. Having multiple power pillar connections between the interface die and the first stacked memory dies reduces the resistance of the power delivery network and improves the performance of the memory system 110. The power pillars may be connected to (e.g., coupled to) a power supply and can provide power to each of the dies stacked on the interface die. The power pillars may route power using corresponding power pillars that are “offset” from each other (e.g., in the vertical direction). That is, the configuration of the interface die may allow multiple paths (e.g., through-silicon vias (TSVs)) to extend from the power pillars and connect to the power supply. Therefore, implementing the offset column described herein can increase the number of power connection points of the memory device 145 and improve the overall performance of the memory system 110 without increasing its size.

[0028] Figure 2A An example of an offset column architecture 200-a supporting a memory system, based on the examples disclosed herein, is shown. Architecture 200-a may illustrate a top view of a stacked memory device. In some examples, architecture 200-a may illustrate one or more power ridges 205 and one or more rails 210 (e.g., one or more power rails 210). Architecture 200-a may illustrate one or more stacked dies (e.g., interface dies and one or more memory dies stacked on top), and the power ridges 205 and rails 210 may route power from a power supply to each die. In some examples, the power ridges 205 and rails 210 may route power from one or more power columns, as described herein. Implementing the offset columns described herein can increase the number of power connection points of a memory device and improve the overall performance of the associated memory system while increasing their size.

[0029] In some examples, the memory device may include one or more power ridges. As used herein, a power ridge may refer to one or more coplanar power pillars coupled to a corresponding die and configured to route power upwards from the power source through the memory die stack (e.g., to the corresponding die). An interface die is located at the bottom of the memory die stack. The interface die may be coupled to a relatively larger number of power pillars than a conventional memory system, which improves the uniformity of power delivery to the stacked dies and provides other benefits. That is, the interface die may be coupled to multiple power pillars (e.g., some power pillars are within the power ridges and some are outside the power ridges), the power pillars may additionally be conductive pillars, or referred to as connection points for power, and each of these connection points (e.g., each of the power pillars of the interface die) may be coupled to one or more power ridges extending upwards along the die stack. Thus, the power pillars coupled to the interface die can route power to the stacked dies using the power ridges, and the power ridges can route power to each of the stacked dies using power ridges and rails. Because the interface die can be coupled to multiple power pillars, the resistance of the power delivery network can be reduced, which can improve the performance of the memory device.

[0030] A memory device may include one or more power ridges 205 and one or more rails 210. As used herein, a power ridge 205 may refer to a region or structure that couples power. Alternatively or additionally, a rail 210 may refer to a wiring structure, a power rail, or another structure configured to receive power signals from one or more of the power ridges 205. For example, a power supply may provide power to a power ridge 205 (e.g., via a power post coupled to an interface die), and the power ridge 205 may route power signals to the stacked dies in a vertical direction (e.g., upward along the die stack). Each power ridge 205 and each rail 210 may receive power signals and may route power signals across the respective die (e.g., from the power ridge 205 outward, in a horizontal direction). As described herein, the presence and positioning of power posts coupled to the interface die may improve the uniformity of power delivery to the die via the respective power ridges 205 and rails 210.

[0031] In some instances, the memory device may include one or more I / O areas 215. Each I / O area 215 may each include one or more pads (e.g., I / O pads) associated with a corresponding memory array. For example, a memory array positioned on a stack of dies may receive and transmit signaling via one or more I / O pads of a corresponding I / O area 215. Implementing the offset pillars described herein can increase the number of power connection points of the memory device and improve the overall performance of the associated memory system without increasing their size.

[0032] Figure 2BAn example of an offset pillar architecture 200-b supporting a memory system, based on the examples disclosed herein, is shown. Architecture 200-b may illustrate aspects of interface die 220, first memory die 225, and second memory die 230. In some examples, architecture 200-b may illustrate one or more power ridges 205 and one or more rails 210. Architecture 200-b may also illustrate one or more power ridges 235 and power rails 240 coupled to interface die 220. For example, Figure 2B Can be Figure 2A An exploded isometric view of architecture 200-a as illustrated herein. In some examples, power ridge 205 and rail 210 may route power received from one or more power pillars (e.g., via power ridge 235). Implementing the offset pillars described herein can increase the number of power connection points of a memory device and improve the overall performance of the associated memory system without increasing their size.

[0033] In some examples, the memory device may include one or more power ridges 205 and 235. As used herein, power ridges 205 and 235 may refer to one or more coplanar power pillars coupled to and configured to route power from a power source (e.g., to the corresponding die). Power ridges 205 and 235 may be coupled to one or more power pillars of interface die 220, as described herein. In some examples, the power pillars may not be coplanar with power ridge 235. More precisely, the power pillars may be “offset” so that power can be routed from the power source to the first memory die 225 and the second memory die 230 via a non-linear path. Alternatively or additionally, power ridge 205 may refer to a power ridge extending in a first direction (e.g., a horizontal direction) and power ridge 235 may refer to a power ridge extending in a second direction (e.g., a vertical direction). In some examples, the term “power ridge” may refer to a combination of power ridges 205 and 235.

[0034] For reference Figure 2A The power supply can provide power to a power ridge 235 (e.g., via a power post coupled to interface die 220), and the power ridge 235 can route power signals to the first memory die 225 and the second memory die 230 in a vertical direction (e.g., upward along the die stack). Each memory die may include a corresponding power ridge 205 and rail 210, and can receive power signals from the power ridge 235 and can route power signals across the corresponding die (e.g., from the power ridge outward, in a horizontal direction). As described herein, the presence and positioning of the power post coupled to interface die 220 can improve the uniformity of power delivery to the die via the corresponding power ridge 205 and rail 210.

[0035] In some examples, interface die 220 may include power rails 240 (e.g., a fourth power rail, a back-side redistribution layer (BS-RDL)). Power rails 240 may be coupled to one or more power ridges 235. That is, power ridges 235 may be coupled to power via one or more power posts of interface die 220, and may also be coupled to power rails 240. Thus, power ridges 235 may route power signals (e.g., a first power signal) from power to the first memory die 225 and the second memory die 230, and may also route power signals (e.g., a second power signal) from power rails 240 to the first memory die 225 and the second memory die 230. As described herein, power ridges 205 and rails 210 may route power signals to the respective memory dies. By connecting power ridges 235 to power rails 240, additional voltage (e.g., increased voltage) can be provided to the first memory die 225 and the second memory die 230.

[0036] Figure 3 An example of an architecture 300 supporting offset pillars for a memory system, based on the examples disclosed herein, is shown. Architecture 300 may illustrate a side view of an aspect of a stacked memory device. In some examples, architecture 300 may illustrate an interface die 305 and one or more stacked dies 310 above (e.g., on top) the interface die 305. The interface die 305 may be coupled to a power supply (not shown). In some examples, the interface die 305 and the stacked dies 310 may include or otherwise couple to one or more power ridges 315, one or more power pillars 320, and one or more thermal pillars 325. In some examples, the power ridges 315 and power pillars 320 may route power from the interface die 305 to each of the stacked dies 310. Additionally or alternatively, the thermal pillars 325 may provide insulation benefits to the interface die 305, the stacked dies 310, or both. Implementing the offset pillars described herein can increase the number of power connection points of a memory device and improve the overall performance of the associated memory system without increasing its size.

[0037] As described herein, power ridge 315 may refer to one or more coplanar power pillars coupled to and configured to route power (e.g., to the corresponding die). For example, power ridge 315-a may extend through interface die 305 and N stacked memory dies 310. Therefore, power ridge 315-a may contain N+1 power pillars. Alternatively, power ridge 315-b may extend through N stacked memory dies 310. That is, power ridge 315-b may not extend through interface die 305 and therefore may contain N power pillars.

[0038] In some examples, power pillars 320 may be coupled to the power supply of the associated memory device. As described herein, interface die 305 may be coupled to a relatively larger number of power pillars than a conventional memory system, which improves the uniformity of power delivery to the stacked dies 310 and other benefits. That is, interface die 305 may be coupled to multiple power pillars 320 that serve as connection points for power supplies. Power pillars 320 may, for example, route power signals to power ridges 315-b, and power ridges 315-b may route power signals to each memory die in the stacked memory dies 310. (See reference...) Figure 2A and 2B The description states that power ridge 205 and rail 210 can further route power signals within the respective die. Because power ridge 315-b and power pillar 320 are not coplanar, power ridge 315-b (e.g., the power pillar of power ridge 315-b) and power pillar 320 can be essentially “offset”.

[0039] Alternatively, the associated memory device may include one or more thermal pillars 325. In some examples, the thermal pillar 325 may be structurally similar to the power pillar 320, but may not extend through the interface die 305 or the corresponding stacked die 310. That is, power signals cannot be routed through the thermal pillar 325, and the thermal pillar 325 may serve as additional capacitance to receive power signals and store (e.g., temporary storage) the memory device. In some instances, the thermal pillar 325 may also serve as a thermal barrier between the corresponding stacked dies 310 and between the stacked dies 310 and the interface die 305. Implementing the offset pillars described herein can increase the number of power connection points of the memory device and improve the overall performance of the associated memory system without increasing their size.

[0040] Figure 4An example of an architecture 400 supporting offset pillars for a memory system, based on the examples disclosed herein, is shown. Architecture 400 may illustrate a side view of an aspect of a stacked memory device. In some examples, architecture 400 may illustrate an interface die 405 and one or more stacked dies 410 above (e.g., on top of) the interface die 405. For example, architecture 400 may illustrate a first memory die 410-a, a second memory die 410-b, and a third memory die 410-c. Interface die 405 may be coupled to a power supply 435. In some examples, interface die 405 and stacked dies 410 may include or otherwise couple to one or more power ridges 415, one or more power pillars 420, and one or more thermal pillars 430. In some examples, power ridges 415 and power pillars 420 may route power from interface die 405 to each of the stacked dies 410. Alternatively, the hot post 430 may provide insulation benefits to the interface die 405, the stacked die 410, or both. Implementing the offset post described herein can increase the number of power connection points of a memory device and improve the overall performance of the associated memory system without increasing its size.

[0041] In some examples, interface die 405 may be coupled to power supply 435. Power supply 435 may provide power to each of interface die 405 and stacked dies 410. In some examples, power supply 435 may include one or more bumps (e.g., one or more power bumps) or one or more microbumps (e.g., one or more micro power bumps). Interface die 405 may include wiring structure 450-a coupled to power supply 435. In some examples, wiring structure 450-a may be, or may be referred to as, a voltage rail or any structure configured to carry (e.g., route) power signals.

[0042] Alternatively, interface die 405 may include circuitry 440 for accessing one or more of the stacked dies 410. In some instances, circuitry 440 may include CMOS circuitry (e.g., CMOS diffused circuitry). Circuitry 440 may be positioned on the top side (e.g., upper side) of interface die 405 and may be aligned (e.g., vertically aligned) with power ridge 415.

[0043] The first memory die 410-a may include a hot post 430-a and one or more power posts 420. For example, the memory die 410-a may include power posts 420-a, 420-b, and 420-c. Power posts 420-a, 420-b, and 420-c may be horizontally aligned and coupled to the power supply 435 via the interface die 405 and may be configured to route power signals to at least the first memory die 410-a. In some instances, power posts 420-a, 420-b, and 420-c may each be associated with a corresponding path 460. That is, each path 460 may be an aperture or location in which the corresponding power post 420 may receive power signals from the interface die 405. For example, because the power post 420 is inherently conductive, it may be configured to route power signals received from the power supply 435. In some examples, path 460-a may be associated with power post 420-a (e.g., substantially aligned with power post 420-a), path 460-b may be associated with power post 420-b (e.g., substantially aligned with power post 420-b), and path 460-c may be associated with power post 420-c (e.g., substantially aligned with power post 420-c).

[0044] In some examples, the first memory die 410-a may include a wiring structure 450-b coupled to power pillars 420-a, 420-b, and 420-c. The wiring structure 450-b may receive power signals from power supply 435 (e.g., via power pillars 420 of the first memory die 410-a) and provide (e.g., route) the power signals to the first memory die 410-a. For example, the first memory die 410-a may include a memory array 445-a substantially aligned (e.g., vertically) with at least power pillars 420-a and 420-b. In some examples, the wiring structure 450-b may be, or may be referred to as, a voltage rail or any structure configured to carry (e.g., route) power signals.

[0045] The first memory die 410-a may include a hot post 430-a. The hot post 430-a may be coupled to the wiring structure 450-b, but may be decoupled from the interface die 405. That is, the hot post 430-a may receive a power signal from the wiring structure 450-b and may store a capacitor associated with the power signal for use by the memory array 445-a or another component of the first memory die 410-a.

[0046] The second memory die 410-b may include a power pillar 420-d (offset from power pillar 420-a) and one or more hot pillars 430. For example, the memory die 410-b may include hot pillars 430-b, 430-c, and 430-d. Power pillars 420-d and hot pillars 430-b, 430-c, and 430-d may be horizontally aligned. Power pillar 420-d may be included in a power ridge 415 and may be vertically aligned with hot pillar 430-a (e.g., above hot pillar 430-a). In some examples, power pillar 420-d may be coupled to power supply 435 via interface die 405 and the first memory die 410-a and may be configured to route power signals to at least the second memory die 410-b.

[0047] In some instances, power post 420-d may be associated with path 460-d. That is, path 460-d may be a hole or location in which power post 420-d can receive power signals from interface die 405 and first memory die 410-a. For example, because power post 420-d is inherently conductive, it may be configured to route power signals received from power supply 435.

[0048] In some examples, the second memory die 410-b may include a wiring structure 450-c coupled to power pillars 420-d. The wiring structure 450-c is a component that receives power signals from power supply 435 (e.g., via power pillars 420 of the first memory die 410-a and power pillars 420-d of the second memory die 410-b) and provides (e.g., routes) the power signals to the second memory die 410-b. For example, the second memory die 410-b may include a memory array 445-b substantially aligned (e.g., vertically) with at least hot pillars 430-b and 430-c. In some examples, the wiring structure 450-c may be, or may be referred to as, a voltage rail or any structure configured to carry (e.g., route) power signals.

[0049] The second memory die 410-b may include hot pillars 430-b, 430-c, and 430-d. Hot pillars 430-b, 430-c, and 430-d may be coupled to the wiring structure 450-c, but may be decoupled from the first memory die 410-a. That is, hot pillars 430-b, 430-c, and 430-d may receive power signals from the wiring structure 450-c and may store capacitors associated with the power signals for use by the memory array 445-b or another component of the second memory die 410-b.

[0050] The third memory die 410-c may include power pillars 420-e and one or more hot pillars 430. For example, memory die 410-c may include hot pillars 430-e, 430-f, and 430-g. Power pillars 420-e and hot pillars 430-e, 430-f, and 430-g may be aligned horizontally. Power pillar 420-e may be included in a power ridge 415 and may be vertically aligned with power pillar 420-d (e.g., above power pillar 420-d). In some examples, power pillar 420-e may be coupled to power supply 435 via interface die 405, first memory die 410-a, and second memory die 410-b, and may be configured to route power signals to at least the third memory die 410-c.

[0051] In some instances, power post 420-e may be associated with path 460-e. That is, path 460-e may be a hole or location in which power post 420-e can receive power signals from interface die 405, first memory die 410-a, and second memory die 410-b. For example, because power post 420-e is inherently conductive, it may be configured to route power signals received from power supply 435.

[0052] In some examples, the third memory die 410-c may include a wiring structure 450-d coupled to power pillars 420-e. The wiring structure 450-d is a component that receives power signals from power supply 435 (e.g., via power pillars 420 of the first memory die 410-a, power pillars 420-d of the second memory die 410-b, and power pillars 420-e of the third memory die 410-c) and provides (e.g., routes) the power signals to the third memory die 410-c. For example, the third memory die 410-c may include a memory array 445-c substantially aligned (e.g., vertically) with at least hot pillars 430-e and 430-f. In some examples, the wiring structure 450-d may be, or may be referred to as, a voltage rail or any structure configured to carry (e.g., route) power signals.

[0053] The third memory die 410-c may include hot pillars 430-e, 430-f, and 430-g. Hot pillars 430-e, 430-f, and 430-g may be coupled to wiring structure 450-d but decoupled from the second memory die 410-b. That is, hot pillars 430-e, 430-f, and 430-g may receive power signals from wiring structure 450-d and may store capacitors associated with the power signals for use by memory array 445-c or another component of the third memory die 410-c.

[0054] In some examples, each of the stacked dies 410 may include one (or more) regions where the vias 460 cannot exist. For example, a region may be referred to as a restricted area (KOZ) 455. Due to manufacturing constraints, product specifications, or both, KOZ 455 cannot contain the vias 460 and therefore cannot contain the hot pillars 420. However, interface die 405 may not contain a KOZ 455, or may contain a KOZ relatively smaller than that of the stacked die 410 or located in a different position from the KOZ of the stacked die 410. Therefore, interface die 405 may contain a TSV under the KOZ 455 of the stacked die 410. This allows additional power pillars (e.g., power pillars 420-a, 420-b, and 420-c) to exist, thereby increasing the number of power supply connection points 435 without increasing the size of the associated memory device.

[0055] It should be noted that the aspects described herein describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, portions from two or more of the methods may be combined.

[0056] This describes a device. An overview of aspects of the device described herein is provided below:

[0057] Aspect 1: A device comprising: an interface die; a first memory die coupled to the interface die, the first memory die comprising: a plurality of first conductive posts, each including a set of first power posts coupled to the interface die and first thermal posts decoupled from the interface die; and a first wiring structure configured to be electrically coupled to the set of first power posts and the first thermal posts; and a second memory die coupled to the first memory die, the second memory die comprising: a plurality of second conductive posts, each including second power posts vertically aligned with and connected to the first thermal posts and connected to the first wiring structure and a set of second thermal posts each vertically aligned with a corresponding power post in the set of first power posts and decoupled from the first memory die; and a second wiring structure configured to be electrically coupled to the second power posts and the set of second thermal posts.

[0058] Aspect 2: The device according to Aspect 1 further comprises: a third memory die coupled to the second memory die, the third memory die comprising: a plurality of third conductive pillars, each comprising a third power pillar vertically aligned with and connected to the second power pillar and a set of third hot pillars vertically aligned with and decoupled from the second memory die of a corresponding hot pillar in the set of second hot pillars; and a third wiring structure configured to electrically connect the third power pillars and the set of third hot pillars.

[0059] Aspect 3: The device according to any one of aspects 1 to 2, wherein the first memory die includes a first memory bank and the second memory die includes a second memory bank vertically aligned with the first memory bank.

[0060] Aspect 4: The device according to any one of aspects 1 to 3, wherein the interface die includes a circuit system vertically aligned with the first hot post.

[0061] Aspect 5: The device according to any one of Aspects 1 to 4 further comprises: a set of first paths extending through the interface die and vertically aligned with the set of first power posts, wherein a power signal is configured to route from one or more power bumps coupled to the interface die to the set of first power posts via each of the set of first paths; and a second path extending through the first memory die and vertically aligned with the second power post, wherein the power signal is configured to route from the one or more power bumps coupled to the interface die to the second power post via the second path.

[0062] Aspect 6: The device according to any one of aspects 1 to 5 further comprises: a power rail located on the upper surface of the first memory die, wherein a set of first power pillars is configured to route a second power signal from the power rail to the second wiring structure.

[0063] Aspect 7: The device according to any one of aspects 1 to 6, wherein the second hot column of the set of second hot columns is adjacent to the second power column.

[0064] Aspect 8: The device according to any one of aspects 1 to 7, wherein the distance between the third power column of the first power column in the set of first power columns and the first edge of the first memory die is less than a threshold.

[0065] Aspect 9: The device according to any one of aspects 1 to 8, wherein: the second power column is positioned in a first vertical plane; and the first power column of the group of first power columns is positioned in a second vertical plane, the first vertical plane comprising a greater number of power columns than the second vertical plane.

[0066] Aspect 10: The device according to aspect 9, wherein: the first hot column is positioned in the first vertical plane; and the second hot column of the group of second hot columns is positioned in the second vertical plane, the second vertical plane comprising a greater number of hot columns than the first vertical plane.

[0067] Aspect 11: The device according to any one of aspects 1 to 10 further comprises: a plurality of power bumps coupled to the interface die.

[0068] Aspect 12: The device according to any one of aspects 1 to 11, wherein the first heat column is below the second power column.

[0069] Aspect 13: The device according to any one of aspects 1 to 12, wherein the plurality of first conductive posts extend between the interface die and the first memory die.

[0070] This describes a device. An overview of aspects of the device described herein is provided below:

[0071] Aspect 14: An apparatus comprising: a plurality of stacked memory dies, wherein each of the plurality of stacked memory dies includes a corresponding power rail; a first power ridge coupled to each of the plurality of stacked memory dies, wherein the first power ridge is located in a first plane and wherein the first power ridge is configured to route a first power signal between each corresponding power rail of the plurality of stacked memory dies; a second power ridge coupled to a subset of the plurality of stacked memory dies, wherein the second power ridge is located in a second plane and wherein the second power ridge is configured to route the first power signal between the corresponding power rail of each of the subset of the plurality of stacked memory dies; a first plurality of power pillars coupled to and offset from the first power ridge and the second power ridge of the plurality of stacked memory dies, wherein each of the first plurality of power pillars is configured to route the first power signal between a first power rail of the first memory die and the second power ridge; and a first hot pillar coupled to the first power rail of the first memory die of the plurality of stacked memory dies, wherein the first hot pillar is located in the second plane.

[0072] Aspect 15: The apparatus of aspect 14 further comprises: a first path extending through the first memory die, wherein the first power ridge is configured to route the first power signal from the first power rail to a second power rail of a second memory die among the plurality of stacked memory dies via the first path; a second path extending through the second memory die, wherein the first power ridge is configured to route the first power signal from the second power rail to a third power rail of a third memory die among the plurality of stacked memory dies via the second path; and a third path extending through the second memory die, wherein the second power ridge is configured to route the first power signal from the second power rail to the third power rail via the third path.

[0073] Aspect 16: The device according to aspect 15 further includes: a plurality of fourth paths extending through each of the first plurality of power pillars coupled to the first memory die, wherein the second power ridge is configured to route the first power signal from the first power rail to the third power rail through the plurality of fourth paths.

[0074] Aspect 17: The device according to any one of aspects 14 to 16 further comprises: a fourth power rail located on the upper surface of the first memory die, wherein the first power ridge is configured to route a second power signal from the fourth power rail to a second power rail of a second memory die among the plurality of stacked memory dies.

[0075] Aspect 18: The device according to aspect 17, wherein the second of the plurality of hot columns is adjacent to the first power column of the second power ridge.

[0076] Aspect 19: The device according to aspect 18, wherein the first power column of the second power ridge is offset in the horizontal direction from the first power column of the first plurality of power columns.

[0077] Aspect 20: The apparatus according to any one of aspects 18 to 19, wherein: the first memory die includes a circuit system positioned vertically below the second power ridge; and the second memory die of the plurality of stacked memory dies includes a memory cell array positioned vertically below the second heat column.

[0078] Aspect 21: The device according to any one of aspects 14 to 20 further comprises: a plurality of hot pillars coupled to a second memory die in the plurality of stacked memory dies, wherein each of the plurality of hot pillars is positioned above a corresponding power pillar in the first plurality of power pillars.

[0079] Aspect 22: The device according to any one of aspects 14 to 21, wherein the distance between the second power column of the first plurality of power columns and the first edge of the first memory die is less than a threshold.

[0080] Aspect 23: The apparatus according to any one of aspects 14 to 22, wherein: the first power ridge includes a second plurality of power pillars, each of the second plurality of power pillars being positioned between corresponding memory dies in the plurality of stacked memory dies; and the second power ridge includes a third plurality of power pillars, each of the third plurality of power pillars being positioned between corresponding memory dies in the subset of the plurality of stacked memory dies, wherein the second plurality of power pillars includes a greater number of power pillars than the third plurality of power pillars.

[0081] Aspect 24: The device according to any one of aspects 14 to 23 further comprises: a plurality of power bumps, wherein the first power rail is coupled to the plurality of power bumps.

[0082] Aspect 25: The apparatus according to any one of aspects 14 to 24, wherein the first hot column is adjacent to the first power column of the first power ridge.

[0083] Aspect 26: The device according to any one of aspects 14 to 25, wherein the first hot column is below the second power column of the second power ridge.

[0084] Aspect 27: The apparatus according to any one of aspects 14 to 26, wherein the first memory die includes an interface die.

[0085] Aspect 28: The device according to aspect 27, wherein the first plurality of power pillars are positioned between the interface die and the first memory die among the plurality of stacked memory dies.

[0086] Aspect 29: The device according to any one of aspects 14 to 28, wherein the first power column of the first plurality of power columns is adjacent to the first hot column.

[0087] This describes a device. An overview of aspects of the device described herein is provided below:

[0088] Aspect 30: A device comprising: an interface die; a first memory die coupled to the interface die, the first memory die comprising: a plurality of first conductive posts, each including a set of first power posts coupled to the interface die and a first thermal post decoupled from the interface die; and a first wiring structure configured to be electrically coupled to the set of first power posts and the first thermal post; a second memory die coupled to the first memory die, the second memory die comprising: a plurality of second conductive posts, each including a second power post vertically aligned with and connected to the first thermal post and a set of second thermal posts, each vertically aligned with a corresponding power post in the set of first power posts and decoupled from the first memory die; and a second wiring structure configured to be electrically coupled to the second power posts and the first thermal post. The first memory die is electrically coupled to a set of second hot pillars; and a third memory die coupled to the second memory die, the third memory die comprising: a plurality of third conductive pillars, each including a third power pillar vertically aligned with and connected to the second power pillar and a set of third hot pillars each vertically aligned with and decoupled from the second memory die; and a third wiring structure configured to electrically connect the third power pillars and the set of third hot pillars, wherein the first memory die includes a first memory cell, the second memory die includes a second memory cell vertically aligned with the first memory cell, and the third memory die includes a third memory cell vertically aligned with the second memory cell, and wherein the interface die includes a circuit system vertically aligned with the first hot pillar.

[0089] The information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or signaling symbols referred to throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, a signal can represent a signal bus, where the bus can have various bit widths.

[0090] The terms "electronic communication," "conductive contact," "connection," and "coupling" refer to a relationship between components that supports the flow of signals between them. Components are considered to be in electronic communication (e.g., conductive contact, connection, coupling) if there is any electrical path (e.g., conductive path) between components that can support the flow of signals (e.g., charge, current, voltage) between them at any time. Based on the operation of a device containing connected components, the conductive path between components in electronic communication (e.g., conductive contact, connection, coupling) can be open or closed. The conductive path between connected components can be a direct conductive path between components or an indirect conductive path including intermediate components (e.g., switches, transistors, or other components). In some instances, the signal flow between connected components can be interrupted for a period of time, for example, using one or more intermediate components (e.g., switches or transistors).

[0091] The term "isolation" refers to a relationship between components in which signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, when a switch positioned between two components is turned on, the components separated by the switch are isolated from each other. When components isolate two components, the components can cause changes that prevent signals from flowing between other components using previously permitted conductive paths.

[0092] The term "coupling" (e.g., "electrical coupling") can refer to a condition that changes from an open-circuit relationship between components (where signals cannot currently be transmitted between components, e.g., via a conductive path) to a closed-circuit relationship between components (where signals can be transmitted between components, e.g., via a conductive path). When a component, such as a controller, couples other components together, the component can trigger a change that allows signals to flow between the other components via conductive paths that were previously not permitted to allow signals to flow.

[0093] The term "layer" or "layer hierarchy" can refer to an organization of geometry (e.g., relative to a substrate) such as a layer or sheet. Each layer or hierarchy may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or hierarchy may be a three-dimensional structure in which two dimensions are greater than the third, such as a thin film. Layers or hierarchy may contain different elements, components, or materials. In some instances, a layer or hierarchy may consist of two or more sublayers or sub-hierarchies.

[0094] The devices discussed herein (including memory arrays) can be formed on semiconductor substrates, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate (e.g., silicon-on-glass (SOG) or silicon-on-sapphire (SOS)) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species, including (but not limited to) phosphorus, boron, or arsenic.

[0095] The switching components (e.g., transistors) discussed herein may be field-effect transistors (FETs) and may include a source (e.g., a source terminal), a drain (e.g., a drain terminal), a channel between the source and drain, and a gate (e.g., a gate terminal). The conductivity of the channel can be controlled (e.g., modulated) by applying a voltage to the gate, which in some instances can cause the channel to become conductive. Examples of the switching components may be n-type FETs or p-type FETs.

[0096] The descriptions presented herein, taken in conjunction with the accompanying drawings, illustrate exemplary configurations and do not represent all instances that may be implemented or that are within the scope of the claims. The “Detailed Description” section contains specific details used to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0097] In the accompanying drawings, similar components or features may have the same reference numerals. Similar components can be distinguished by following the reference numeral with one or more dashes and additional markings to differentiate them. If only a first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of any additional reference numerals.

[0098] The functions described herein can be implemented in hardware, software executed by a processing system (e.g., one or more processors, one or more controllers, control circuitry, processing circuitry, logic circuitry), firmware, or any combination thereof. If implemented in software executed by a processing system, the functions can be stored as one or more instructions (e.g., code) on or transmitted via a computer-readable medium. Due to the nature of software, the functions described herein can be implemented using software executed by a processing system, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions can be physically located at various locations, including distributed portions of the functions implemented at different physical locations.

[0099] The descriptive blocks and modules described herein may be implemented or executed using one or more processors (e.g., DSPs, ASICs, FPGAs), discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof, designed to perform the functions described herein. A processor may be an instance of a microprocessor, controller, microcontroller, state machine, or other type of processor. A processor may also be implemented as at least one of one or more computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0100] As used herein (included in the claims), the word "or" in a list of items (e.g., a list of items beginning with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0101] As used herein (included in the claims), the article “a” preceding a noun is open-ended and should be understood to refer to “at least one” or “one or more” of those nouns. Therefore, the terms “a,” “at least one,” “one or more,” and “at least one of one or more” are interchangeable. For example, if a claim describes a “component” performing one or more functions, then each of the individual functions can be performed by a single component or any combination of components. Therefore, the term “component” having a characteristic or performing a function can refer to “at least one of one or more components” having a particular characteristic or performing a particular function. The subsequent use of the term “the / said” to refer to a component introduced by the article “a” can refer to any or all of one or more components. For example, a component introduced by the article “a” can be understood to mean “one or more components,” and the subsequent reference to “the / said” in a claim can be understood to be equivalent to referring to “at least one of the one or more components.” Similarly, the subsequent use of the term "the / said" to refer to a component introduced as "one or more components" can refer to any or all of the one or more components. For example, the subsequent reference to "one or more components" in a claim can be understood as equivalent to referring to "at least one of the one or more components".

[0102] Computer-readable media includes both non-transitory computer storage media and communication media, encompassing any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media can be any available media or combination of media accessible by a computer. For example, but not limited to, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media or combination of media that can be used to carry or store desired program code elements in the form of instructions or data structures and are accessible by a computer or one or more processors.

[0103] Descriptions and figures are provided to enable those skilled in the art to make or use this disclosure. Those skilled in the art will understand that various modifications to this disclosure are possible, and that the techniques disclosed herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: Interface bare die; A first memory die, coupled to the interface die, the first memory die comprising: A plurality of first conductive pillars, comprising a set of first power pillars coupled to the interface die and a first thermal pillar decoupled from the interface die; and A first wiring structure configured to be electrically coupled to the set of first power pillars and the first thermal pillars; and A second memory die, coupled to the first memory die, the second memory die comprising: A plurality of second conductive pillars, each comprising a second power pillar vertically aligned with and connected to the first wiring structure, and a set of second heat pillars each vertically aligned with a corresponding power pillar in the set of first power pillars and decoupled from the first memory die; and A second wiring structure is configured to be electrically coupled to the second power pillar and the set of second thermal pillars.

2. The device according to claim 1, further comprising: A third memory die, coupled to the second memory die, the third memory die comprising: A plurality of third conductive pillars, comprising a third power pillar vertically aligned with and connected to the second power pillar and the second wiring structure, and a set of third hot pillars each vertically aligned with a corresponding hot pillar in the set of second hot pillars and decoupled from the second memory die; and A third wiring structure is configured to electrically connect the third power column and the set of third heat columns.

3. The device of claim 1, wherein the first memory die includes a first memory cell and the second memory die includes a second memory cell vertically aligned with the first memory cell.

4. The device of claim 1, wherein the interface die includes a circuit system vertically aligned with the first hot post.

5. The device according to claim 1, further comprising: A set of first paths extending through the interface die and vertically aligned with the set of first power posts, wherein power signals are configured to route from one or more power bumps coupled to the interface die to the set of first power posts via each of the first paths; and A second path extends through the first memory die and is vertically aligned with the second power post, wherein the power signal is configured to be routed via the second path from one or more power bumps coupled to the interface die to the second power post.

6. The device according to claim 1, further comprising: A power rail is positioned on the upper surface of the first memory die, wherein a set of first power pillars is configured to route a second power signal from the power rail to the second wiring structure.

7. The device of claim 1, wherein the second hot column of the group of second hot columns is adjacent to the second power column.

8. The device of claim 1, wherein the distance between the third power column of the first power column group and the first edge of the first memory die is less than a threshold.

9. The device according to claim 1, wherein: The second power supply post is positioned in the first vertical plane; and The first power column in the group of first power columns is positioned in the second vertical plane, and the first vertical plane includes more power columns than the second vertical plane.

10. The device according to claim 9, wherein: The first hot column is positioned in the first vertical plane; and The second heat column in the set of second heat columns is positioned in the second vertical plane, and the second vertical plane includes a greater number of heat columns than the first vertical plane.

11. The device according to claim 1, further comprising: Multiple power bumps are coupled to the interface die.

12. The device of claim 1, wherein the first heat column is below the second power column.

13. The device of claim 1, wherein the plurality of first conductive posts extend between the interface die and the first memory die.

14. An apparatus comprising: Multiple stacked memory dies, wherein each of the multiple stacked memory dies includes a corresponding power rail: A first power ridge is coupled to each of the plurality of stacked memory dies, wherein the first power ridge is located in a first plane and wherein the first power ridge is configured to route a first power signal between each corresponding power rail of the plurality of stacked memory dies. A second power ridge coupled to a subset of the plurality of stacked memory dies, wherein the second power ridge is located in a second plane and wherein the second power ridge is configured to route the first power signal between the respective power rails of each memory die in the subset of the plurality of stacked memory dies. A plurality of power pillars coupled to a first memory die in the plurality of stacked memory dies and offset from the first power ridge and the second power ridge, wherein each of the plurality of power pillars is configured to route the first power signal between the first power rail of the first memory die and the second power ridge. and A first hot pillar is coupled to the first power rail of the first memory die in the plurality of stacked memory dies, wherein the first hot pillar is located in the second plane.

15. The device according to claim 14, further comprising: A first path extends through the first memory die, wherein the first power ridge is configured to route the first power signal from the first power rail to a second power rail of a second memory die among the plurality of stacked memory dies via the first path. A second path extends through the second memory die, wherein the first power ridge is configured to route the first power signal from the second power rail to the third power rail of a third memory die among the plurality of stacked memory dies via the second path. and A third path extends through the second memory die, wherein the second power ridge is configured to route the first power signal from the second power rail to the third power rail via the third path.

16. The device according to claim 15, further comprising: A plurality of fourth paths extend through each of the first plurality of power pillars coupled to the first memory die, wherein the second power ridge is configured to route the first power signal from the first power rail to the third power rail via the plurality of fourth paths.

17. The device according to claim 14, further comprising: A fourth power rail is located on the upper surface of the first memory die, wherein the first power ridge is configured to route a second power signal from the fourth power rail to a second power rail of a second memory die among the plurality of stacked memory dies.

18. The device of claim 17, wherein the second of the plurality of hot columns is adjacent to the first power column of the second power ridge.

19. The device of claim 18, wherein the first power post of the second power ridge is offset in the horizontal direction from the first power post of the first plurality of power posts.

20. An apparatus comprising: Interface bare die; A first memory die, coupled to the interface die, the first memory die comprising: A plurality of first conductive pillars, comprising a set of first power pillars coupled to the interface die and a first thermal pillar decoupled from the interface die; and A first wiring structure is configured to be electrically coupled to the set of first power pillars and the first thermal pillars; A second memory die, coupled to the first memory die, the second memory die comprising: A plurality of second conductive pillars, each comprising a second power pillar vertically aligned with and connected to the first wiring structure, and a set of second heat pillars each vertically aligned with a corresponding power pillar in the set of first power pillars and decoupled from the first memory die; and A second wiring structure, configured to be electrically coupled to the second power pillar and the set of second thermal pillars; and A third memory die, coupled to the second memory die, the third memory die comprising: A plurality of third conductive pillars, comprising a third power pillar vertically aligned with and connected to the second power pillar and the second wiring structure, and a set of third hot pillars each vertically aligned with a corresponding hot pillar in the set of second hot pillars and decoupled from the second memory die; and A third wiring structure is configured to electrically connect the third power post and the set of third hot posts, wherein the first memory die includes a first memory cell, the second memory die includes a second memory cell vertically aligned with the first memory cell, and the third memory die includes a third memory cell vertically aligned with the second memory cell, and wherein the interface die includes a circuit system vertically aligned with the first hot post.

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