Memory controller, memory system and control method thereof

Abstract

Embodiments of the present disclosure disclose a memory controller, a memory system and a control method thereof, the memory controller configured to: control a memory device to perform a read operation using a first read voltage corresponding to a first data state of a memory cell; obtaining a first number of storage units with threshold voltages smaller than or equal to the first reading voltage, and obtaining a second number of storage units with threshold voltages larger than the first reading voltage; determining a difference value between the second number and the first number; and acquiring a voltage deviation value from a mapping table according to the difference value.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to memory controllers, memory systems and control methods thereof, and readable storage media. Background Technology

[0002] Memory devices are storage devices used to preserve information in modern information technology. Some semiconductor memories, such as non-volatile memories, have gradually become mainstream products in the memory market due to their high storage density, controllable production costs, suitable erase / reset speeds, and retention characteristics. However, as people's demands for storage devices continue to increase, there is still much room for improvement in memory devices and their systems. Summary of the Invention

[0003] According to some aspects of embodiments of the present disclosure, a memory controller is provided, the memory controller being configured to: control a memory device to perform a read operation using a first read voltage corresponding to a first data state of a memory cell; obtain a first number of memory cells with a threshold voltage less than or equal to the first read voltage; obtain a second number of memory cells with a threshold voltage greater than the first read voltage; determine a difference between the second number and the first number; and obtain a voltage offset value from a mapping table based on the difference.

[0004] In some embodiments, the mapping table includes a first mapping table storing: a first numerical range and a voltage offset value corresponding to the first numerical range; the memory controller is configured to: multiply the difference by an association coefficient to obtain a feature value; and in response to the feature value being within the first numerical range, obtain the voltage offset value corresponding to the first numerical range according to the first mapping table.

[0005] In some embodiments, each storage cell in the memory device is configured to store one of a plurality of data states; the correlation coefficient corresponds to the data state, and the correlation coefficients corresponding to different data states are not equal.

[0006] In some embodiments, the plurality of data states include 2 n Data states, through 2 n -1 read voltage distinguishes each of the multiple data states; the characteristic value corresponding to the i-th read voltage is the same as that of the 2nd read voltage. n The sum of the characteristic values ​​corresponding to the -i read voltages is zero; where n is an integer greater than 1 and i is less than 2. n -1 is a positive integer, and i is related to the 2 n -i is not equal.

[0007] In some embodiments, the first mapping table stores a first numerical range of the first data state and stores the voltage offset value corresponding to the first numerical range; the voltage offset values ​​are stored in the first mapping table in ascending order.

[0008] In some embodiments, the 2 n -1 read voltage is divided into multiple groups; a first mapping table stores a first numerical range corresponding to the read voltage of a group, and a first numerical range corresponds to the voltage offset value of the group; the voltage offset value of the read voltage of the highest data state of the group is stored in ascending order; the memory controller is further configured to: perform a read operation with the first read voltage corresponding to the highest data state in the group; and in response to the feature value being within the first numerical range, obtain the voltage offset value of the group corresponding to the first numerical range.

[0009] In some embodiments, at least a portion of the voltage offset values ​​corresponding to the read voltage of the highest data state in the group are linearly related to at least a portion of the voltage offset values ​​corresponding to the read voltages of other data states in the group.

[0010] In some embodiments, the mapping table includes a second mapping table, the second mapping table including: a second numerical range, and a voltage offset value corresponding to the second numerical range; the memory controller is configured to: in response to the difference being within the second numerical range, obtain the voltage offset value corresponding to the second numerical range according to the second mapping table.

[0011] In some embodiments, the memory controller is configured to enable a single-level read operation mode and control the memory device to perform a single-level read operation using the first read voltage.

[0012] In some embodiments, the memory controller is further configured to sum the first read voltage with the voltage offset value to obtain a second read voltage.

[0013] According to some aspects of embodiments of this disclosure, a memory system is provided, including a memory device and a memory controller coupled thereto; the memory device includes a plurality of memory cells configured to store one of a plurality of data states; the memory controller is configured to: control the memory device to perform a read operation using a first read voltage corresponding to a first data state among the plurality of data states; obtain a first number of memory cells with a threshold voltage less than or equal to the first read voltage; obtain a second number of memory cells with a threshold voltage greater than the first read voltage; determine a difference between the second number and the first number; and obtain a voltage offset value from a mapping table based on the difference.

[0014] In some embodiments, the mapping table includes a first mapping table storing: a first numerical range and a voltage offset value corresponding to the first numerical range; the memory controller is configured to: multiply the difference by an association coefficient to obtain a feature value; and in response to the feature value being within the first numerical range, obtain the voltage offset value corresponding to the first numerical range according to the first mapping table.

[0015] In some embodiments, the correlation coefficient corresponds to a data state, and the correlation coefficients corresponding to different data states are not equal.

[0016] In some embodiments, the plurality of data states include 2 n Data states, through 2 n -1 read voltage distinguishes each of the multiple data states; the characteristic value corresponding to the i-th read voltage is the same as that of the 2nd read voltage. n The sum of the characteristic values ​​corresponding to the -i read voltages is zero; where n is an integer greater than 1 and i is less than 2. n -1 is a positive integer, and i is related to the 2 n -i is not equal.

[0017] In some embodiments, the first mapping table stores a first numerical range of the first data state and stores the voltage offset value corresponding to the first numerical range; the voltage offset values ​​are stored in the first mapping table in ascending order.

[0018] In some embodiments, the 2 n -1 read voltage is divided into multiple groups; a first mapping table stores a first numerical range corresponding to the read voltage of a group, and a first numerical range corresponds to the voltage offset value of the group; the voltage offset values ​​of the read voltage of the highest data state of the group are stored in ascending order; the memory controller is further configured to: perform a read operation with the first read voltage corresponding to the highest data state in the group; and in response to the feature value being within the first numerical range, obtain the voltage offset value of the group corresponding to the first numerical range.

[0019] In some embodiments, at least a portion of the voltage offset values ​​corresponding to the read voltage of the highest data state in the group are linearly related to at least a portion of the voltage offset values ​​corresponding to the read voltages of other data states in the group.

[0020] In some embodiments, the mapping table includes a second mapping table, the second mapping table including: a second numerical range, and a voltage offset value corresponding to the second numerical range; the memory controller is configured to: in response to the difference being within the second numerical range, obtain the voltage offset value corresponding to the second numerical range according to the second mapping table.

[0021] In some embodiments, the memory controller is further configured to send a first operation command to the memory device; the memory device is configured to enable a single-level read operation mode in response to the first operation command.

[0022] In some embodiments, the memory controller is further configured to sum the first read voltage with the voltage offset value to obtain a second read voltage; the memory device is configured to perform a reread operation using the second read voltage.

[0023] According to some aspects of embodiments of this disclosure, a control method for a memory system is provided, including:

[0024] A read operation is performed using a first read voltage corresponding to a first data state of a storage cell; a first number of storage cells with a threshold voltage less than or equal to the first read voltage is obtained, and a second number of storage cells with a threshold voltage greater than the first read voltage is obtained; the difference between the second number and the first number is determined; and a voltage offset value is obtained from a mapping table based on the difference.

[0025] In some embodiments, the mapping table includes a first mapping table, which stores a first numerical range and a voltage offset value corresponding to the first numerical range; obtaining the voltage offset value from the mapping table based on the difference includes: multiplying the difference by an association coefficient to obtain a feature value; and in response to the feature value being within the first numerical range, obtaining the voltage offset value corresponding to the first numerical range based on the first mapping table.

[0026] In some embodiments, each storage unit is configured to store one of a plurality of data states; the correlation coefficient corresponds to the data state, and the correlation coefficients corresponding to different data states are not equal.

[0027] In some embodiments, the plurality of data states include 2 n Data states, through 2 n -1 read voltage distinguishes each of the multiple data states; the characteristic value corresponding to the i-th read voltage is the same as that of the 2nd read voltage. n The sum of the characteristic values ​​corresponding to the -i read voltages is zero; where n is an integer greater than 1 and i is less than 2. n -1 is a positive integer, and i is related to the 2 n -i is not equal.

[0028] In some embodiments, the first mapping table stores a first numerical range of the first data state and stores the voltage offset value corresponding to the first numerical range; the voltage offset values ​​are stored in the first mapping table in ascending order.

[0029] In some embodiments, the 2 n -1 read voltage is divided into multiple groups; a first mapping table stores a first numerical range of read voltages for a group, and a first numerical range corresponds to the voltage offset value of the group; the voltage offset value of the read voltage of the highest data state of the group is stored in ascending order; the control method further includes: performing a read operation with the first read voltage corresponding to the highest data state in the group; and in response to the feature value being within the first numerical range, obtaining the voltage offset value of the group corresponding to the first numerical range.

[0030] In some embodiments, at least a portion of the voltage offset values ​​corresponding to the read voltage of the highest data state in the group are linearly related to at least a portion of the voltage offset values ​​corresponding to the read voltages of other data states in the group.

[0031] In some embodiments, the mapping table includes a second mapping table, the second mapping table including: a second numerical range, and a voltage offset value corresponding to the second numerical range; obtaining the voltage offset value from the mapping table based on the difference includes: in response to the difference being within the second numerical range, obtaining the voltage offset value corresponding to the second numerical range based on the second mapping table.

[0032] In some embodiments, the control method further includes: a memory controller sending a first operation command to a memory device; and the memory device responding to the first operation command by enabling a single-level read operation mode.

[0033] In some embodiments, the control method further includes: a memory controller summing the first read voltage with the voltage offset value to obtain a second read voltage; and a memory device using the second read voltage to perform a reread operation.

[0034] According to some aspects of embodiments of the present disclosure, a readable storage medium is provided that stores a computer program, wherein the calculation and the program, when executed, implement the control method.

[0035] This disclosure provides a memory controller configured to control a memory device to perform a read operation using a first read voltage corresponding to a first data state of a memory cell, obtain a first number of memory cells with a threshold voltage less than or equal to the first read voltage, and obtain a second number of memory cells with a threshold voltage greater than the first read voltage; obtain a voltage offset value from a related mapping table based on the difference between the second number and the first number, and perform a reread operation by summing the voltage offset value with the first read voltage to obtain a second read voltage, thereby correcting read errors of the first read voltage; reduce the access time of the related mapping table, improve the operating speed of the device, and optimize the user experience. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of an exemplary system according to an embodiment of the present disclosure;

[0037] Figure 2a This is a schematic diagram of an exemplary memory card according to an embodiment of the present disclosure;

[0038] Figure 2b This is a schematic diagram of an exemplary solid-state drive according to an embodiment of the present disclosure;

[0039] Figure 3 This is a schematic diagram of an exemplary memory device according to an embodiment of the present disclosure;

[0040] Figure 4 This is an exemplary cross-sectional schematic diagram of a storage cell array according to an embodiment of the present disclosure;

[0041] Figure 5 This is a schematic diagram of another exemplary memory device according to embodiments of the present disclosure;

[0042] Figure 6 This is a schematic diagram of an exemplary memory system according to an embodiment of the present disclosure;

[0043] Figure 7 This is an exemplary operation diagram shown according to an embodiment of the present disclosure;

[0044] Figure 8 This is a schematic diagram of a threshold voltage distribution according to an embodiment of the present disclosure;

[0045] Figure 9 This is an embodiment of the intended rereading representation shown in this disclosure;

[0046] Figures 10 to 14 This is a schematic diagram illustrating an information reading method according to an embodiment of the present disclosure;

[0047] Figure 15 This is a mapping representation schematic shown according to an embodiment of the present disclosure;

[0048] Figure 16 This is an operational schematic diagram shown according to an embodiment of the present disclosure;

[0049] Figure 17 This is another mapping representation intention shown according to embodiments of this disclosure;

[0050] Figure 18 This is a schematic diagram of correlation coefficients shown according to embodiments of this disclosure;

[0051] Figure 19This is another operational schematic diagram shown according to an embodiment of the present disclosure;

[0052] Figure 20 This is a schematic diagram illustrating an exemplary control method for a memory system according to an embodiment of the present disclosure. Detailed Implementation

[0053] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0054] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0055] It should be understood that when a component or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other components or layers, it may be directly on, adjacent to, connected to, or coupled to other components or layers, or there may be intervening components or layers. Conversely, when a component is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other components or layers, there are no intervening components or layers.

[0056] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the negative forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0057] It should be understood that the phrases "some embodiments" or "an embodiment" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "some embodiments" or "an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure.

[0058] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory device 104. The memory device 104 may include, but is not limited to: 2D or 3D NAND (Not-And) memory, NOR (Non-Non) memory, ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), phase-change memory (PCM), resistive random access memory (RRAM), and other types of memory.

[0059] According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs), which are used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays.

[0060] The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) relating to data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with external devices (e.g., host 108) according to specific communication protocols. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Devices (IDE) protocol, Firewire protocol, etc.

[0061] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2aIn one example shown, the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 2b In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include components for connecting the SSD 206 to a host computer (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0062] The memory device 104 of this disclosure is explained using NAND (Not-And) type memory as an example. The memory device 104 of this disclosure may include other types of memory. Figure 3 A schematic circuit diagram of an exemplary memory device 300, including peripheral circuitry, is shown according to some aspects of this disclosure. The memory device 300 may be... Figure 1 An example of memory device 104 is provided. Memory device 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 is illustrated as a three-dimensional NAND-type memory cell array, wherein the memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0063] In some implementations, each memory cell 306 is a single-cell memory (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 306 is a two-cell memory (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-bit memory cell (TLC)), or four bits per cell (also known as a four-bit memory cell (QLC)). Each MLC may be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC may be programmed to write one of three possible nominal storage values ​​into the cell, while a fourth nominal storage value in addition to these three nominal storage values ​​may be used to indicate an erase state.

[0064] like Figure 3 As shown, each NAND memory string 308 may include a lower select gate (BSG) 310 at its source end and an upper select gate (TSG) 312 at its drain end. BSG 310 and TSG 312 may be configured to activate a selected NAND memory string 308 during read and program operations. In some embodiments, the sources of NAND memory strings 308 within the same memory block 304 are coupled via a common source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 within the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each NAND memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having TSG 312) or a deselection voltage (e.g., 0V) to the corresponding TSG 312 via one or more TSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having BSG 310) or a deselection voltage (e.g., 0V) to the corresponding BSG 310 via one or more BSG lines 315.

[0065] like Figure 3As shown, NAND memory strings 308 can be organized into multiple memory blocks 304, each of which may have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) can be used to bias and couple the source line 314 of the selected memory block and the unselected memory blocks on the same plane as the selected memory block. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations.

[0066] Figure 4 A schematic cross-sectional view of an exemplary memory cell array 301 including NAND memory strings 308 is shown, according to some aspects of this disclosure. Figure 4 As shown, the NAND memory string 308 may include a stacked structure 410, which includes multiple gate layers 411 and multiple insulating layers 412 stacked alternately in sequence, and a memory string 308 perpendicularly penetrating the gate layers 411 and insulating layers 412. The gate layers 411 and insulating layers 412 may be stacked alternately, with adjacent gate layers 411 separated by an insulating layer 412. The number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410 determines the number of memory cells included in the memory cell array 301.

[0067] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as an upper select gate line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a lower select gate line, and the gate layer 411 extending laterally between the upper and lower select gate lines may serve as a word line layer.

[0068] In some embodiments, the stacked structure 410 may be disposed on the substrate 401. The substrate 401 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0069] In some embodiments, the NAND memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel vias filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0070] Return to reference Figure 3 The peripheral circuitry 302 can be coupled to the memory cell array 301 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313, and by sensing voltage and / or current signals from each target memory cell 306. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 5 Additional peripheral circuitry not shown.

[0071] Page buffer / sensor amplifier 504 can be configured to read data from and program (write) data to memory cell array 301 according to control signals from control logic 512. In one example, page buffer / sensor amplifier 504 can store programming data (write data) to be programmed into memory cell array 301. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 506 can be configured to be controlled by control logic 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0072] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of memory blocks 304. The row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive BSG lines 315 and TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform programming operations on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, channel boost voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0073] Control logic 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic 512 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic 512, as well as to buffer status information received from control logic 512 and relay it to the host. Interface 516 can also be coupled to column decoder / bitline driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory cell array 301.

[0074] In some embodiments, the storage cells of a NAND type memory can be classified into single-level storage cells (one-bit storage cell), double-level storage cells (two-bit storage cells), triple-level storage cells (three-bit storage cells), quadruple-level storage cells (four-bit storage cells), and five-level storage cells (five-bit storage cells) according to storage density. However, regardless of whether it is a single-level or multi-level storage cell, its read operation can be performed on a page-by-page basis. Specifically, when performing a read operation, a read voltage is applied to the word line (i.e., the selected word line) coupled to the selected page in the memory device 104. When the read voltage reaches the threshold voltage of the plurality of storage cells coupled to the selected word line, or when the number of storage cells that do not reach the threshold voltage is within an allowable range, the read operation of the entire page ends. The storage cell can be an n-bit storage cell, and the storage cell has 2 bits including an erase state. n Data states, through 2 n -1 read voltage reads n bits of stored data. For example, the first read voltage is between the threshold voltages of the erase state and the first data state. When the first read voltage is applied to the word line, the memory cell in the erase state is turned on, and the memory cell in the first data state is not turned on. The erase state and the first data state are distinguished and read out.

[0075] It should be noted that during the read operation, memory cells that do not reach the target threshold voltage are marked as error bits. To prevent read errors, an error correction code (ECC) is introduced. When the number of error bits is less than or equal to the maximum number of failure bits that the error correction code can correct, all error bits in the read operation can be corrected, thus enabling correct data reading.

[0076] In some embodiments, the host 108 sends a read command (or read instruction, read request) to the memory controller 106 according to the current user command requirements. The memory controller 106 transmits the read control command, including information such as a logical address-physical address mapping table, to the memory device 104 through interface 516, controlling the memory device 104 to perform a read operation on the memory cell corresponding to the corresponding physical address. The memory device 104 then sends the read data back to the memory controller 106 through interface 516. The memory controller 106 then feeds the data back to the host 108 via an interface such as PCIe or SATA. Specifically, the memory controller 106 sends the read control command to the control logic of the memory device through interface 516. The control logic applies a relevant operating voltage to the selected word line or bit line according to the relevant physical address, thereby performing a read operation on the corresponding memory cell. The operating voltage can be generated by the control logic according to the relevant read voltage mapping table, controlled by a voltage generator, and then applied to the word line of the corresponding address after decoding by a row decoder, or applied to the bit line of the corresponding address after decoding by a column decoder.

[0077] In some other embodiments, when the memory device 104 reads a corresponding memory cell under the control of the memory controller 106, a read error occurs. At this time, the memory controller 106 (or the error correction module in the memory controller 106) responds to the read operation failure and controls the memory device 104 to perform error correction. The error correction mode may include ECC error correction.

[0078] Figure 6 A block diagram is provided showing a memory controller 106 applied to a memory system 102. (Refer to...) Figure 6 As shown, the memory system 102 includes a memory controller 106 and a memory device 104, which can be coupled in any suitable manner. In this embodiment, the memory controller 106 includes a host I / F 1061, a memory I / F 1062, a control unit 1063, an error correction (ECC) module 1064, a data buffer 1067, and an internal bus 1060. The error correction module 1064 includes an encoding unit 1065 and a decoding unit 1066. The host I / F 1061 outputs commands and user data (write data) received from the host 108 to the internal bus 1060, and sends user data (read data) read from the memory device 104 and responses from the control unit 1063 back to the host 108.

[0079] The memory I / F controls the processes of writing user data to and reading from the memory device 104 based on instructions from the control unit 1063. The control unit 1063, such as a central processing unit (CPU) or microprocessor (MPU), controls the memory system 102 as a whole. The control unit 1063 performs control based on commands received from the host 108 via the host I / F 1061. For example, the control unit 1063 instructs the memory I / F 1062 to write user data to the memory device 104 and perform parity checking based on commands from the host 108. Furthermore, the control unit 1063 instructs the memory device 104 to perform programming operations on the memory I / F 1062 according to the command from the host 108. After the memory device 104 completes the programming operation, it updates the physical address-logical address mapping table and feeds it back to the data buffer 1067 for storage through the memory I / F 1062; or the control unit 1063 instructs the memory device 104 to read user data and parity check from the memory device 104 according to the command from the host 108.

[0080] The error correction module 1064 includes an encoding unit 1065 and a decoding unit 1066. The encoding unit 1065 can encode user data of a predetermined size written on the same page to generate parity data, and can generate parity data based on programmed data. The parity data is written to the page containing the user data that forms the basis of the encoding, and the decoding unit 1066 uses the parity data for decoding. The data buffer 1067 temporarily stores user data received from the host 108 before storing it in the memory device 104, and temporarily stores data read from the memory device 104 before sending it to the host 108.

[0081] According to some aspects of embodiments of this disclosure, Figure 7 A schematic diagram illustrating an exemplary operational flow for handling read operation failures in a memory system 102 is shown. (Combined with...) Figure 7As shown, when the memory controller 106 controls the memory device 104 to perform a read operation, it first performs a default read operation on the memory cell at the corresponding physical address. If the default read fails, it accesses the read retry table (RRT) to obtain the voltage offset value, sums it with the default read voltage to obtain the read retry voltage, and performs a read retry operation. The default read voltage is the calibration value during the factory test of the memory device and is stored in the memory device for use by the memory controller or the peripheral circuits of the memory device. The read retry operation and the default read operation can be performed using hard bit decoding (HB decode). If the read retry operation fails, a soft decode operation (soft decode flow) or soft decision operation is performed. The soft decode operation can include hard bit read (HB read), where hard read data is performed using hard decoding or the LLR (Log likelihood Rate) table is not updated according to the LDPC algorithm. The soft decode operation can also include soft bit read (SB read), where soft read data is performed using soft decoding. If the soft decode operation fails, redundant arrays of data are recovered. Independent Disks (RAID) operation or Redundant Array of Independent NAND (RAIN) technology is performed. If the RAID or RAIN operation fails, the ECC error correction operation stops and the read fails because it cannot correct the error. The memory controller 106 sends a read fail or UECC signal to the host 108.

[0082] For example, RAID can be disk-level data recovery. A storage device 104 can act as a disk, and multiple disks can form a disk array. When data is read incorrectly from one or more disks, the erroneous data can be recovered using checksum data and data from the unaffected disks. The checksum data can be generated during the disk write phase based on the write data. RAID can also be referred to as NAND-level RAID. For the storage device 104, including a NAND storage array, checksum data can be generated during the programming phase based on programming data for multiple data blocks. This checksum data can be stored in the over-provisioning (OP) area of ​​the storage device 104. A data block can include data from one storage cell or multiple storage cells on a word line. When data is read incorrectly from one or more data blocks, the erroneous data can be recovered using the checksum data and the unaffected data.

[0083] Error correction operations such as rereading, finding the optimal read voltage, software decoding, and RAID can be performed by the error correction module 1064 (e.g., an ECC module) in the memory controller 106, controlling the memory device 104. Control commands are sent from the memory controller 106 to the memory device 104 via interface 516, and the memory device 104 feeds back the read information to the memory controller 106 via interface 516. It should be noted that subsequent operations can be stopped once any of the rereading, software decoding, or RAID operations are successfully completed.

[0084] In some embodiments, a software decoding operation can be understood as performing data re-decoding via a decoding unit 1066 (e.g., a software decoder) in the memory controller 106, and then performing a read operation based on the re-decoded data. RAID or RAIN operations can be understood as mirroring the data through secondary encoding, reconstructing the stored data and its parity check data. Typically, the re-encoding of the stored data for a redundant array is performed in the data buffer 1067 of the memory controller 106.

[0085] In some embodiments, Figure 8 This diagram illustrates the threshold voltage distribution for the eight data states of a TLC memory cell. The horizontal axis represents voltage, and the vertical axis represents the number of memory cells. (Refer to...) Figure 8 As shown, Gray code encoding rules can be applied when programming memory cells. Taking the three-bit Gray code used in a three-bit TLC memory cell as an example, the encodings 111, 011, 001, 000, 010, 110, 100, and 101 correspond to the erase state (L0) and seven storage states (L1-L7), respectively. As mentioned earlier, reading the eight threshold voltage distributions corresponding to the eight data states (one erase state and seven storage states) requires seven read voltages (or, 7th-order read voltages) Rd1 to Rd7. If the threshold voltage is less than Rd1, it is the L0 data state; if the threshold voltage is between Rd1 and Rd2, it is the L1 data state; and if the threshold voltage is greater than Rd7, it is the L7 data state. For memory cells with higher storage bits, such as QLC memory cells, which have 16 data states, 16 data states are distinguished using 15 read voltages from Rd1 to Rd1. It should be noted that, based on the read logic of multi-bit storage cells, after multiple read voltages are read, all data states are distinguished. The read voltage can be located between the threshold voltage distributions of two data states, such as at a trough. A read voltage can correspond to any one or two of its adjacent data states. For example, read voltage Rd7 can correspond to data state L7, or it can correspond to data state L6, or it can be described as the read voltage between data states L7 and L6. In this embodiment, for ease of explanation, Rd7 corresponds to data state L7, and Rd1 corresponds to data state L1, which will not be repeated hereafter.

[0086] In some embodiments, the three types of pages corresponding to the three-bit memory cells can be mapped to seven read voltages using a three-bit Gray code encoding rule. Specifically, the next page (LP) corresponds to the first read voltage Rd1 and the fifth read voltage Rd5; the middle page (MP) corresponds to the second read voltage Rd2, the fourth read voltage Rd4, and the sixth read voltage Rd6; and the previous page (UP) corresponds to the third read voltage Rd3 and the seventh read voltage Rd7. It should be noted that the number of corresponding read voltages will be adjusted accordingly after the encoding rule is changed. When applying read voltages for read operations, they can be applied page by page. For example, Rd1 and Rd5 corresponding to page LP can be applied to read page LP. If the threshold voltage is less than Rd1, it is read as 1; if the threshold voltage is between Rd1 and Rd5, it is read as 0; and if the threshold voltage is greater than Rd5, it is read as 0. Similarly, Rd2, Rd4, and Rd6 corresponding to page MP can be applied. If the threshold voltage is less than Rd2, it is read as 1; if the threshold voltage is between Rd2 and Rd4, it is read as 0; if the threshold voltage is between Rd4 and Rd6, it is read as 1; and if the threshold voltage is greater than Rd6, it is read as 0. After applying the read voltages corresponding to LP, MP, and UP, the read data is summarized and decoded to read the bit values ​​of each data state, such as 111 for L0.

[0087] In some embodiments, Figure 7 If the default read operation fails to read data correctly using the default read voltage, a reread operation can be performed for error correction. The process of determining the reread voltage in the reread operation may include: the error correction module 1064 in the memory controller 106 obtains the corresponding voltage offset value by querying the corresponding reread table. This voltage offset value can be a positive or negative offset value. It is then summed with the default read voltage to obtain the reread voltage. The memory controller 106 controls the memory device 104 to perform a reread operation on the memory cell at the corresponding physical address using this reread voltage. The default read voltage may be the default read voltage value obtained by the memory device 104 or the memory system 102 during the factory testing phase based on the threshold voltage distribution after the programming operation. Each default read voltage may be located at the trough voltage of the threshold voltage distribution during the test. For example, the default read voltage Rd1 may be located at or near the trough between the threshold voltage distribution corresponding to the L0 state and the threshold voltage distribution corresponding to the L1 state. Each default read voltage is stored in a certain storage area of ​​the memory device 104 for use by the memory controller 106 or the peripheral circuits of the memory device 104. The reason for the error in reading the default voltage may be that the default reading voltage is not at the trough due to the offset of the threshold voltage distribution, which makes it impossible to distinguish the data state correctly. The offset of the threshold voltage distribution may be caused by temperature changes or reading interference.

[0088] Figure 9The exemplary form of a read-back table shown is for illustrative purposes only, and the embodiments disclosed herein do not limit the form of the read-back table. The read-back table can store or record multiple read voltages to distinguish multiple data states of a memory cell, such as... Figure 9 The memory controller 106 stores the voltage offset values ​​corresponding to the read voltages RL1 to Rd7. RR-m entries store each read voltage offset value. Rd1 to Rd7 are used to read data from the TLC memory cell. The seven read voltages are used to distinguish the eight data states, including the erase state. It should be noted that the memory controller 106 can use a polling method when querying the reread table. A reread table can include multiple sub-tables, such as m sub-tables, or... Figure 9 The table contains multiple rows of settings from RR-1 to RR-m, where m is a natural number greater than 1. Each sub-table may include a voltage offset value for the corresponding data state of the corresponding storage unit. The system sequentially queries from the first sub-table to the m-th sub-table, obtaining a voltage offset value for each query. This voltage offset value is then added to the default read voltage to obtain a reread voltage, which the memory device 104 uses for reading. A single reread operation can have up to m sub-read operations, and this embodiment does not limit this. For example, V1 in the reread table is a voltage offset value for the read voltage Rd1. When polling the reread table, the system can start from RR-1 of the first index and sequentially query RR-m to obtain the reread voltage for rereading until the read is successful. Alternatively, the system can locate a specific index in the reread table based on certain preset conditions, obtaining a segment of the reread table index entries without loading all index entries.

[0089] In some embodiments, the reread table may correspond to the default read voltage of each data state, and the reread voltage is obtained by summing the default read voltage with the voltage offset value recorded in the reread table. The default read voltage is the calibration value during the factory test of the memory device 104. The reference value for summing the default read voltage with the voltage offset value in the reread table may be different for each data state, that is, the default read voltage corresponding to each data state may be different. In other embodiments, after a read failure of a memory cell, the reread voltage is obtained by querying the reread table to get the voltage offset value based on the read voltage at the time of the read failure, and then summing it with the current read voltage to obtain the reread voltage. The current read voltage at the time of the read failure may be any value and may not be equal to the default read voltage. For example, the voltage for performing the default read operation may be the aforementioned default read voltage, or the voltage after the default read voltage offset, or other voltages such as the trial read voltage. There is no restriction on the voltage value. For example, the default read operation may be performed with the read voltage corresponding to a selected data state (first data state) among multiple data states. The first data state may be the L7 state, and the first read voltage may be Rd7. Rd7 may be the default read voltage value or other voltage values.

[0090] In some embodiments, when programming a memory cell, writing can be performed according to a data randomization mode. When programming a memory cell of the smallest programming unit (or smallest programming region) within the memory device 104, the memory cell of the smallest programming unit is all the memory cells on a word line or the memory cells on a portion of a word line that can be independently read and written. The number of memory cells corresponding to each data state is equal or approximately equal within a certain error range. Memory cells whose target data state is the erase state are not programmed. For TLC memory cells, the threshold voltage distribution after programming can be as follows: Figure 8 As shown, the threshold voltage distribution of each data state is a normal distribution or a normal distribution within a certain error range, and the peak areas of the threshold voltage distribution of each data state are equal or approximately equal within a certain error range. Figure 8 In this system, the total number of memory cells in the smallest programming unit can be counted as Z. The TLC has a total of 8 data states, and the number of memory cells corresponding to each data state can be configured as Z / 8. During subsequent read operations, the expected number of memory cells for each data state is Z / 8. However, due to the threshold voltage offset, if the read voltage is still determined by a randomly distributed threshold voltage distribution, the number of memory cells corresponding to some data states may differ significantly from Z / 8. This could lead to some memory cells programmed as Li states being read as Lj states during the read process, or some memory cells programmed as Lj states being read as Li states. Li states and Lj states are adjacent data states.

[0091] In some embodiments, Figure 10This diagram illustrates the number of data states corresponding to each data state in a TLC memory cell. The horizontal axis represents the data states, and the vertical axis represents the number of memory cells (bit count). Based on the random distribution programming logic, when the threshold voltage of the memory cell does not shift or is not considered, the bit count of each data state read can be recorded as the expected count, which can be the expected number set during programming. The actual bit count of each data state read is the actual count. Due to the shift in threshold voltage, the actual count of some data states may be more or less than the expected count, and the difference between the two may be large enough to exceed the predetermined deviation range, leading to a read error. For example, the actual count of data state L7 is less than the expected count, and the difference exceeds the predetermined deviation range; the actual count of data state L6 is more than the expected count, and the difference exceeds the predetermined deviation range. In other embodiments, the expected quantity may be a set value calibrated during the factory testing phase of the memory device 104 or the memory system 102. The set value may be set according to the Gray code encoding rules of the memory cell. The expected quantity may be stored as a set value in a certain storage area of ​​the memory device 104 for the memory controller 106 to call.

[0092] In some embodiments, a mapping table can be established based on the difference between the expected and actual number of data states, and the corresponding read voltage offset value, to replace... Figure 9 The reread table shown is a mapping table that stores multiple value ranges, each corresponding to a voltage offset value. The access speed of the mapping table is greater than that of the reread table, thus improving the overall operation speed. For specific examples, please refer to... Figure 10 As shown, when multiple read voltages are applied and read errors occur, the actual and expected quantities for each data state are counted. For example, the number of memory cells corresponding to the L7 state is Z1, and the expected quantity is Z / 8. Based on the difference between Z1 and Z / 8, the relevant mapping table is accessed. When the difference is within a certain value range, the voltage offset value corresponding to that value range is obtained. The voltage offset value is summed with the corresponding read voltage to obtain a new read voltage for rereading and error correction of the memory cells. The expected quantity, value range, and corresponding voltage offset value are calibration values ​​from the factory testing phase and are stored in a certain storage area of ​​the memory device 104 for use by the memory controller 106.

[0093] In some embodiments, during a reread operation, it is not necessary to apply all read voltages before counting the actual number of reads. The memory controller 106 can control the memory device 104 to enable Single Level Read (SLR) mode. The memory device 104 responds to the operation instruction by using read voltages to perform a single-level read operation on the memory cell at the corresponding address. The single-level read operation may include reading at least one bit of stored data in the memory cell with a single read voltage. In other words, this is equivalent to configuring the memory cell as SLC for reading, using a single read voltage, counting the read bit information, and reading memory cells with a threshold voltage lower than or equal to the read voltage as 1, and reading memory cells with a threshold voltage higher than the read voltage as 0. No multi-level read voltages are applied before counting the bit information. This disclosure provides a memory controller 106 and a memory system 102. For the error correction process of reread operation, a single-level read operation is performed for a read voltage. The number of memory cells read as 1 is counted, and the number of memory cells read as 0 is counted. A mapping relationship between the difference between the two counts and the voltage offset value is established and a corresponding mapping table is formed. The read voltage offset value is determined by querying the mapping table based on the actual read difference to obtain the reread voltage, thereby improving the operation speed.

[0094] According to some aspects of embodiments of this disclosure, Figure 1 A memory controller 106 is provided, configured to: control a memory device 104 to perform a read operation using a first read voltage corresponding to a first data state of a memory cell; obtain a first number of memory cells with a threshold voltage less than or equal to the first read voltage; obtain a second number of memory cells with a threshold voltage greater than the first read voltage; determine the difference between the second number and the first number; and obtain a voltage offset value from a mapping table based on the difference.

[0095] The first read voltage is Figure 7 The voltage at which a data read error occurs during the default read operation is the read voltage to be corrected. This voltage can be the default read voltage stored in the memory device 104, or another read voltage to be corrected. This application does not impose specific limitations on the read voltage value. The first read voltage is combined with the voltage offset value obtained from the relevant mapping table to obtain the second read voltage. The second read voltage is used for rereading and error correction. If the rereading with the second read voltage passes, the error correction is successful; otherwise, the software decoding operation can continue the error correction. The first read voltage can be... Figure 8Any one of the reading voltages Rd1 to Rd7 shown, that is, any one of Rd1 to Rd7 that needs to be reread after an error occurs during the default read operation, can be recorded as the first reading voltage of this disclosure. The data state corresponding to the first reading voltage is the first data state or the selected data state. For example, when the first data state is L7, the corresponding reading voltage Rd7 is the first reading voltage Rd7; when the first data state is L6, the corresponding first reading voltage is Rd6.

[0096] like Figure 11 As exemplified, a single-level read operation is performed on the memory cell at the corresponding address using the first read voltage Rd7 corresponding to the L7 data state. Memory cells located to the left of Rd7, with a threshold voltage less than or equal to Rd7, are turned on and the read is successful. The number of memory cells that are successfully read at this time can be counted as, for example, the first number. Memory cells located to the right of Rd7, with a threshold voltage greater than Rd7, are not turned on and the read is unsuccessful. The number of memory cells that are unsuccessful at this time can be counted as, for example, the second number.

[0097] In some embodiments, the first and second numbers of Rd7 in the TLC memory cells can be referenced. Figure 12 As shown, the first count and the second count are the actual counts read. Different reading voltages or different threshold voltage offsets will result in different first and second counts. The first count corresponds to a calibrated first expected count, and the second count corresponds to a calibrated second expected count. Combined with... Figure 8 The threshold voltage distribution of TLC memory cells is shown. Taking the threshold voltage distribution corresponding to all data states as the statistical object, the number of memory cells with a threshold voltage less than or equal to Rd7 is... Figure 11 The first expected number of Rd7 cells can be 7Z / 8, and the number of memory cells with a threshold voltage greater than Rd7 is... Figure 11The second expected quantity of Rd7 can be Z / 8, and the difference between the second expected quantity Z / 8 and the first expected quantity 7Z / 8 is -6Z / 8. This expected quantity is determined based on the programming logic of random distribution mentioned above, is calibrated during the factory test phase, and is stored in a certain storage area of ​​the memory device 104. It can also be any other value calibrated during the factory test. For example, the first expected quantity of the read voltage Rd6 corresponding to the L6 data state is 6Z / 8, and the second expected quantity is 2Z / 8, with a difference of -4Z / 8. When the threshold voltage distribution shifts, if a read operation is performed again with Rd7 or Rd6 to obtain the first and second quantities, the first quantity is not equal to the first expected quantity, the second quantity is not equal to the second expected quantity, and the difference ΔZ between the second quantity and the first quantity will also not be equal to the expected difference. The difference ΔZ can be used to characterize the degree of shift of the threshold voltage trough relative to the first read voltage. A mapping table is generated by mapping this difference ΔZ to the voltage offset value. After subsequent reads of different first read voltages and obtaining the difference ΔZ, the corresponding voltage offset value can be obtained by looking up the mapping table.

[0098] In some embodiments, refer to Figure 13 As shown, taking the threshold voltage distribution of two adjacent data states Li and Lj as an example, V0 is the trough voltage between the two threshold voltage distributions. This trough voltage is the optimal read voltage for this threshold voltage distribution. The first read voltage to be corrected is located at VA or VB due to the offset of the threshold voltage distribution, causing a read error. It can be understood that when the first read voltage is located at VA, it needs to be offset to the right to obtain the optimal read voltage, and when the first read voltage is located at VB, it needs to be offset to the left to obtain the optimal read voltage. The difference between VA and V0 can be ΔV, and the difference between VB and V0 can also be ΔV. The change in the number of memory cells caused by the voltage offset ΔV from V0 is defined as ΔS. For example, ΔS is the number of memory cells with threshold voltages between VA and V0, and ΔS is the number of memory cells with threshold voltages between V0 and VB. The number of memory cells with threshold voltages less than or equal to V0 is denoted as Zi, and the number of memory cells with threshold voltages greater than V0 is denoted as Zj. When reading at the first read voltage VB, the first number of memory cells with a threshold voltage less than or equal to VB is Zi + ΔS, and the second number of memory cells with a threshold voltage greater than VB is Zj - ΔS. The difference between the second number and the first number is ΔZ_B = Zj - Zi - 2ΔS. When reading at the first read voltage VA, the first number of memory cells with a threshold voltage less than or equal to VA is Zi - ΔS, and the second number of memory cells with a threshold voltage greater than VA is Zj + ΔS. The difference between the second number and the first number is ΔZ_A = Zj - Zi + 2ΔS. Zj and Zi are calibration values, and ΔS is a statistical value based on the actual read information. The difference ΔZ and ΔS have a corresponding relationship.

[0099] In some embodiments, for example, the storage unit has 2 n Data states, through 2 n -1 read voltage distinguishes each of the multiple data states; Li is the i-th data state, Lj is the j-th data state, and the first quantity Zi corresponding to the trough voltage V0 is Z*j / 2. n The total number of storage units in the smallest programming unit is Z, which is the calibrated expected number. The second quantity corresponding to V0 is Zj = Z*(1-j / 2). n The difference between the second quantity and the first quantity is Zj - Zi = Z * (1 - 2j / 2) n The larger the threshold voltage offset, the larger ΔS (ΔS is a positive value); as ΔS changes, the difference ΔZ between the second quantity and the first quantity also changes. Different differences between the second quantity and the first quantity can be tested, along with the corresponding voltage offset value. The first read voltage and the voltage offset value are summed to obtain the trough voltage or a voltage close to the trough. The voltage offset value can be positive or negative. There is a mapping relationship between the difference and the voltage offset value. After obtaining the difference corresponding to a certain first read voltage, the voltage offset value can be obtained according to this mapping relationship. The first read voltage and the voltage offset value are then summed to obtain the second read voltage for error correction.

[0100] In some embodiments, refer to Figure 14As shown, the intercept between the trough voltage V0 and the peak voltage Lj can be divided into multiple parts or multiple voltage intervals. The ranges of any two voltage intervals can be equal or unequal. The range of the difference ΔZ between the second quantity and the first quantity corresponding to each voltage interval is tested. At least the minimum and maximum values ​​of each voltage interval are tested to obtain the numerical range (range of values, range of values) of the difference ΔZ. The numerical range of the difference ΔZ can be recorded to form a mapping table. When the difference ΔZ is negative, its absolute value can be recorded to form a mapping table. The mapping table also records the voltage offset value corresponding to the numerical range. This voltage offset value can be the offset value of any value in the voltage range relative to V0. Taking voltage range V2 to V3 out of the six voltage ranges between V0 and Vj shown in the figure as an example, when the first read voltage Rdj corresponding to data state Lj is within voltage range V2 to V3, at least the difference ΔZ between the second quantity and the first quantity corresponding to Rdj = V2, and the difference ΔZ between the second quantity and the first quantity corresponding to Rdj = V3 are tested. The two differences constitute a numerical range, and the voltage offset value corresponding to this numerical range can be any value in the range (V2-V0) to (V3-V0), including but not limited to 1 / 2(V3-V2). For other voltage ranges, the numerical range of the difference can also be tested with reference to voltage range V2 to V3. Multiple numerical ranges and the voltage offset values ​​corresponding to each numerical range are recorded and a mapping table is generated. The mapping table can be calibrated and generated during the factory testing stage and stored in the memory device 104 for the memory controller 106 to call.

[0101] The difference ΔZ between the second quantity and the first quantity is multiplied by the correlation coefficient Sr (scaled ratio) for normalization, so that the values ​​of each numerical interval converge to a smaller numerical interval. The numerical interval multiplied by the correlation coefficient is the first numerical interval, and the original numerical interval without the correlation coefficient is the second numerical interval. The voltage offset values ​​corresponding to the first and second numerical intervals are the same. The correlation coefficient, also called the normalization coefficient or convergence coefficient, is calibrated during the factory testing phase and stored in the storage device for use by the memory controller 106. The second mapping table can be as follows: Figure 15 As shown, the first mapping table can be described later. Figure 17 As shown, Figure 17 The Index in the second mapping table can be compared with... Figure 15 The first mapping table in the example corresponds to; Figure 17 The voltage offset values ​​corresponding to Index0 and Index1 are... Figure 15 The offset values ​​of Index0 and Index1 can be equal. The first numerical interval can be represented by y, and the second numerical interval can be represented by x. y14=x14*Sr; y13=x13*Sr, y1=x1*Sr.

[0102] In some embodiments Figure 15 and Figure 17 The example mapping table can be adapted to a TLC memory cell, storing the voltage offset values ​​Rd7_offset for Rd7 and Rd3_offset for Rd3 corresponding to the UP page. In other embodiments, the mapping table may store only the voltage offset value of a single read voltage, or the voltage offset values ​​of all read voltages.

[0103] In some embodiments, refer to Figure 15 As shown, the mapping table may include a second mapping table, which includes a second numerical range and a voltage offset value corresponding to the second numerical range. The memory controller 106 is configured to: in response to a difference being within the second numerical range, obtain the voltage offset value corresponding to the second numerical range according to the second mapping table. In some embodiments, the memory controller 106 is further configured to: sum the first read voltage with the voltage offset value to obtain a second read voltage.

[0104] Combination Figure 16 As shown, the embodiments of this disclosure for Figure 13 The reread operation is improved. When the default read operation fails with the first read voltage, the memory controller 106 sends an operation command and address information to the memory device 104. The memory device 104 responds to the operation command by initiating a single-level read operation and applying the first read voltage to the memory cell at the corresponding address. The peripheral circuitry of the memory device 104 reads memory cells with a threshold voltage less than or equal to the first read voltage as 1, and reads memory cells with a threshold voltage greater than the first read voltage as 0. The number of 1s is counted as the first quantity, and the number of 0s is counted as the second quantity. The first and second quantities are then sent to the memory controller 106. Alternatively, the memory controller 106 can count the first and second quantities based on the read results of 1s and 0s. The memory controller 106 subtracts the second quantity from the first quantity to obtain a difference value ΔZ. If ΔZ is negative, its absolute value can be used. The memory controller 106 accesses its internal data buffer or RAM, or accesses the DRAM stored in the memory system 102. Figure 15 The example second mapping table stores voltage offset values ​​corresponding to the first read voltage, or voltage offset values ​​corresponding to the data state to which the first read voltage belongs. It determines which second numerical interval the difference ΔZ belongs to, obtains the voltage offset value corresponding to the second numerical interval to which the difference ΔZ belongs, and sums the first read voltage with the voltage offset value to obtain the second read voltage for rereading and error correction. In some specific examples, when the memory system 102 is powered off, the second mapping table can be stored in the memory device 104.

[0105] For example, after reading with the first reading voltage Rd7 and obtaining the difference ΔZ, access... Figure 15 The example second mapping table obtains a voltage offset value Rd7_offset of -48eV when ΔZ is greater than or equal to x14, 40eV when ΔZ is less than or equal to x1, and -40eV when ΔZ ∈ [x13, x14]. When ΔZ is at the endpoint of the second numerical range, its corresponding voltage offset value can be arbitrarily selected, and no further value is obtained after successful reading. If rereading fails after loading the index to which ΔZ belongs, other indices can be loaded for rereading until successful. If rereading still fails after loading all indices, it indicates that the current first reading voltage cannot correct errors by loading the voltage offset value through the second mapping table, and software decoding can be initiated. The difference ΔZ can also be accessed when using the first reading voltage Rd3 to read and obtain the difference. Figure 15 The second mapping table shown retrieves the Rd3_offset value for rereading and error correction. When applying other read voltages such as Rd1, Rd2, Rd4, etc., other second mapping tables containing the corresponding read voltage offset values ​​can be accessed.

[0106] In some embodiments, refer to Figure 17 As shown, the mapping table includes a first mapping table, which stores a first numerical range and a voltage offset value corresponding to the first numerical range. The memory controller 106 is configured to multiply the difference by an association coefficient to obtain a feature value; in response to the feature value being within the first numerical range, the voltage offset value corresponding to the first numerical range is obtained according to the first mapping table. After reading and obtaining the difference ΔZ between the second quantity and the first quantity using the first read voltage, ΔZ is multiplied by the association coefficient Sr to obtain the feature value ΔZ*Sr, and then accessed. Figure 17 The example first mapping table stores a voltage offset value corresponding to the first read voltage, and the first numerical range corresponding to the voltage offset value is... Figure 15 The product of the second numerical interval of the second mapping table and the correlation coefficient. Figure 15 The second numerical interval of the second mapping table can be regarded as its product with the correlation coefficient multiplied by 1; determine which first numerical interval the feature value ΔZ*Sr belongs to, obtain the voltage offset value corresponding to the first numerical interval to which the feature value ΔZ*Sr belongs, and obtain the second reading voltage by summing the first reading voltage and the voltage offset value for rereading and error correction.

[0107] For example, when the difference ΔZ is read and obtained with the first reading voltage Rd7, the characteristic value ΔZ*Sr is calculated, and access is performed. Figure 16The example first mapping table obtains a voltage offset value Rd7_offset of -48eV when ΔZ*Sr is greater than or equal to y14, 40eV when ΔZ*Sr is less than or equal to y1, and -40eV when ΔZ*Sr ∈ [y13, y14]. When ΔZ*Sr is at the endpoint of the first numerical range, its corresponding voltage offset value can be arbitrarily selected, and no further value is obtained after successful reading. If rereading fails after loading the index to which ΔZ*Sr belongs, other indices can be loaded for rereading until successful. If rereading still fails after loading all indices, it indicates that the current first reading voltage cannot be corrected by the first mapping table, and software decoding can be initiated. The feature value ΔZ*Sr can also be accessed after applying the first reading voltage Rd3 to read and obtain it. Figure 16 The first mapping table shown obtains the Rd3_offset value for rereading and error correction. When other read voltages such as Rd1, Rd2, Rd4, etc. are applied, other first mapping tables containing the corresponding read voltage offset values ​​can be accessed. This embodiment does not limit the specific values ​​of the numerical ranges; the numerical ranges can be calibrated during the factory testing phase. For example, y1 can be 14536, y12 can be 20902, and y13 can be 22199. The value range of each range can be equal or unequal. The definition and calibration of the correlation coefficients will be discussed later. Figure 18 illustrate.

[0108] In some embodiments, each storage cell in the memory device 104 is configured to store one of a plurality of data states; the correlation coefficient corresponds to the data state, and the correlation coefficients corresponding to different data states are not equal. In some embodiments, the plurality of data states include 2 n Data states, through 2 n -1 read voltage distinguishes each data state among multiple data states; the characteristic value corresponding to the i-th read voltage is the same as that of the 2nd read voltage. n The sum of the characteristic values ​​corresponding to the -i read voltages is zero; where n is an integer greater than 1 and i is less than 2. n -1 is a positive integer, and i is related to the 2 n -i is not equal.

[0109] Specifically, refer to Figure 18 As shown, the read level can be Figure 8The read voltages Rd1 to Rd7 shown correspond to data states L1 to L7, respectively. Taking Rd1 as an example, in an ideal state where the threshold voltage distribution has no offset, memory cells with a threshold voltage less than or equal to Rd1 are read as "1", and the number is the first expected number. Memory cells with a threshold voltage greater than Rd1 are read as "0", and the number is the second expected number. The expected total number is Z, which can be the total number of memory cells in the smallest programming unit. For the i-th read voltage, the first expected number is Z*i / 2. n The second expected quantity is Z*(1-i / 2) n The difference between the second expected quantity and the first expected quantity is Z*(1-2i / 2). n ), i can be less than or equal to 2 n A positive integer; the value of the first expected quantity / the total expected quantity is i / 2. n The value of the second expected quantity / the total expected quantity is 1 - i / 2 n The value of (second expected quantity - first expected quantity) / total expected quantity is 1 - 2i / 2 n In this embodiment of the disclosure, a correlation coefficient Sr is set such that Sr*(1-2i / 2) n ) = 1 / 2 n Then Sr = (1 / 2 n ) / (1-2i / 2 n ) = 1 / (2 n -2i); when i = 2 n -i, Sr = 1 / (2i-2 n However, when i is 2 n When / 2, Sr is 1, at which point the difference between the second expected quantity and the first expected quantity is 0; thus enabling the construction Figure 17 The first numerical range of the first mapping table takes values ​​around Z / 8, and all of them are positive, which reduces the difficulty of calibrating and testing the first mapping table. Figure 18 The data shown corresponds to TLC storage units. Taking Rd1 as an example, i = 1, 2 n =8, the calculated first expected quantity / total expected quantity is 1 / 8, the second expected quantity / total expected quantity is 7 / 8, the difference to the total expected quantity is 3 / 4, and Sr is 1 / 6; the calculated data for Rd7 are 7 / 8, 1 / 8, -3 / 4, and -1 / 6 respectively. The Sr values ​​of Rd1 and Rd7 are opposites, but their absolute values ​​are equal. The Sr value differs for different reading voltages.

[0110] for Figure 15The second mapping table shown, when calibrating its second numerical range, can test multiple read voltages and corresponding voltage offset values, record the difference ΔZ between the second and first quantities, and take the absolute value when the difference ΔZ is negative; the second numerical range and corresponding voltage offset values ​​can be calibrated based on the difference ΔZ (or its absolute value) to generate a second mapping table stored in the memory device 104 for recall by the memory controller 106; for Figure 17 The first mapping table shown requires multiplying the difference ΔZ by the correlation coefficient Sr (Sr can be positive or negative) during the calibration of its first numerical range. Based on ΔZ*Sr, the first numerical range and corresponding voltage offset value are calibrated, and the first mapping table is generated and stored in the memory device 104 for use by the memory controller 106. The mapping table can be loaded into the data buffer or RAM, or the DRAM of the memory system 102, for use by the memory controller 106. During error correction, the difference ΔZ is read and obtained using the first read voltage. If the first mapping table is called, the difference ΔZ is multiplied by the correlation coefficient Sr to obtain the feature value ΔZ*Sr. Based on ΔZ*Sr, the first numerical range of the first mapping table is determined, and the corresponding index is loaded to obtain the voltage offset value for rereading and error correction. It can be understood that multiplying the difference ΔZ by the correlation coefficient 1 corresponds to... Figure 15 The second mapping table is shown.

[0111] In some embodiments, Figure 19 An example of the first read voltage error correction operation provided in this embodiment is shown. The memory controller 106 controls the memory device 104 to perform a single-state read of the memory cell at the relevant address with the first read voltage. The memory controller 106 obtains a first quantity (count1) and a second quantity (count0) and calculates the feature value ΔZ*Sr. It then queries the first mapping table according to the feature value to obtain the voltage offset value. The first read voltage and the voltage offset value are summed to obtain the second read voltage. The second read voltage is reread and it is determined whether the error correction is successful.

[0112] The first or second mapping table in this embodiment has a smaller data volume compared to a general reread table, which can reduce the data space occupied by the mapping table; and when rereading and correcting the first read voltage, the corresponding mapping table can be accessed and the value range can be located according to the difference ΔZ or the feature value ΔZ*Sr, and the voltage offset value of the corresponding value range can be loaded, which can eliminate the need to load the entire mapping table, thereby improving the error correction rate and improving the user experience.

[0113] In some embodiments, the first mapping table stores a first numerical range of a first data state and the voltage offset value corresponding to the first numerical range; the voltage offset values ​​are stored in the first mapping table in ascending order. The first numerical range can be arranged in ascending order, and the corresponding read voltages can be arranged in ascending order, facilitating the lookup and location of the first numerical range. A first mapping table can be configured for a single read voltage. For example, a first mapping table may only record the voltage offset value Rd7_offset corresponding to Rd7 and the corresponding first numerical range. For error correction of read voltages Rd1 to Rd7, seven first mapping tables can be configured for adaptation. A second mapping table can be configured for a single read voltage.

[0114] In some embodiments, the 2 n -1 read voltage is divided into multiple groups; a first mapping table stores a first numerical range corresponding to the read voltage of a group, and a first numerical range corresponds to the voltage offset value of the group; the voltage offset value of the read voltage of the highest data state of the group is stored in ascending order; the memory controller 106 is further configured to: perform a read operation with the first read voltage corresponding to the highest data state in the group; and obtain the voltage offset value of the group corresponding to the first numerical range in response to a feature value within the first numerical range.

[0115] The group that reads the voltage can be Figure 8 The pages shown can be divided into three pages (three groups) for the seven read voltages Rd1 to Rd7 of the TLC. The LP page corresponds to Rd1 and Rd5, which can correspond to the L1 and L5 data states; the MP page corresponds to Rd2, Rd4, and Rd6; and the UP page corresponds to Rd3 and Rd7. For the same page, the threshold voltage distributions corresponding to its data states have similar offset trends or degrees, and can be applied to the same numerical range. For example, the offset direction of the threshold voltage distribution corresponding to the L3 data state can be the same as the offset direction of the threshold voltage distribution corresponding to the L7 data state, and the degree of contraction or expansion of the threshold voltage distribution peak corresponding to the L3 data state can be the same as or similar to the peak of the threshold voltage distribution corresponding to the L7 data state. In this way, the same numerical range can be used to simplify the mapping table. Figure 17The first mapping table shown records Rd7_offset and Rd3_offset for the read voltages Rd7 and Rd3 corresponding to the UP page. For the same first numerical range or the same index, there is one corresponding Rd7_offset and one Rd3_offset. For error correction of Rd7 and Rd3, the voltage offset value of the required first numerical range can be obtained by querying the first mapping table respectively; or, only Rd7 corresponding to the highest state L7 of the UP page is used for reading, the difference ΔZ is determined, the required first numerical range is determined, and the corresponding Rd7_offset is obtained, and other voltage offset values ​​of the same index are automatically obtained, that is, all voltage offset values ​​corresponding to the required index are obtained, without needing to determine the difference ΔZ and look up the table for other data states lower than the highest state in the same page. For example, using the difference ΔZ determined by Rd7, the feature value ΔZ*Sr∈[y13, y14], the Rd7_offset of -40mV and the Rd3_offset of -10mV are obtained. For example, the Rd2_offset, Rd4_offset, and Rd6_offset corresponding to the MP page can be recorded. Rd6 can be used to read and determine the difference ΔZ, determine the required first numerical range, and obtain the Rd2_offset, Rd4_offset, and Rd6_offset corresponding to the first numerical range. In some embodiments, for Figure 15 The second mapping table shown uses Rd7 to determine the difference ΔZ, where ΔZ∈[x13, x14], and obtains -40mV for Rd7_offset and -10mV for Rd3_offset.

[0116] In some embodiments, at least a portion of the voltage offset values ​​corresponding to the read voltage of the highest data state in the group have a linear relationship with at least a portion of the voltage offset values ​​corresponding to the read voltages of other data states in the group, facilitating the calibration and lookup of the mapping table. (Refer to...) Figure 17 The first mapping table and Figure 15 The second mapping table shown, from Index1 to Index5, shows that for every 8 eV increase in Rd7_offset, Rd3_offset increases by 2 eV. This pattern may not exist in the first numerical interval. Following this pattern, one Rd7_offset and one Rd3_offset can be recorded, and the remaining voltage offset values ​​can be calculated accordingly.

[0117] In some embodiments, the memory controller 106 is configured to enable a single-level read (SLR) operation mode and control the memory device 104 to perform a single-level read operation using the first read voltage. The memory controller 106 sends an operation instruction to the memory device 104 to enable the single-level read operation mode. Upon receiving the instruction, the memory device 104 enables the single-level read mode, receives the address information to be operated on and the first read voltage information, performs a single-level read operation on the memory cells at the relevant addresses using the first read voltage, reads memory cells with a threshold voltage less than or equal to the first read voltage as 1, reads memory cells with a threshold voltage greater than the first read voltage as 0, counts the number of 1s as a first quantity, and counts the number of 0s as a second quantity.

[0118] According to some aspects of embodiments of this disclosure, Figure 1 and Figure 6 A memory system 102 is provided, including a memory device 104 and a memory controller 106 coupled thereto. The memory device 104 includes a plurality of memory cells configured to store one of a plurality of data states. The memory controller 106 is configured to: control the memory device 104 to perform a read operation using a first read voltage corresponding to a first data state among the plurality of data states; obtain a first number of memory cells with a threshold voltage less than or equal to the first read voltage; obtain a second number of memory cells with a threshold voltage greater than the first read voltage; determine the difference between the second number and the first number; and obtain a voltage offset value from a mapping table based on the difference. The memory controller 106 sends an operation command, address information, and a first read voltage value to the memory device 104. The memory device 104 receives the operation command and activates the single-state read operation mode. It uses the first read voltage to perform a single-level read operation on the memory cell at the corresponding address information. The memory cell with a threshold voltage less than or equal to the first read voltage is read as 1, and the memory cell with a threshold voltage greater than the first read voltage is read as 0. The number of 1s is counted as the first number, and the number of 0s is counted as the second number. The memory device 104 or the memory controller 106 calculates the difference ΔZ between the second number and the first number. The memory controller 106 queries the second mapping table based on the difference ΔZ to obtain the voltage offset value, and sums it with the first read voltage to obtain the second read voltage for rereading and error correction. Alternatively, the memory controller 106 queries the first mapping table based on the feature value ΔZ*Sr to obtain the voltage offset value for rereading and error correction.

[0119] In some embodiments, the mapping table includes a first mapping table storing: a first numerical range and a voltage offset value corresponding to the first numerical range; the memory controller 106 is configured to: multiply the difference by an association coefficient Sr to obtain a feature value; and in response to the feature value being within the first numerical range, obtain the voltage offset value corresponding to the first numerical range according to the first mapping table.

[0120] In some embodiments, the correlation coefficient corresponds to a data state, and the correlation coefficients corresponding to different data states are not equal.

[0121] In some embodiments, the plurality of data states include 2 n Data states, through 2 n -1 read voltage distinguishes each of the multiple data states; the characteristic value corresponding to the i-th read voltage is the same as that of the 2nd read voltage. n The sum of the characteristic values ​​corresponding to the -i read voltages is zero; where n is an integer greater than 1 and i is less than 2. n -1 is a positive integer, and i is related to the 2 n -i is not equal.

[0122] In some embodiments, the first mapping table stores a first numerical range of the first data state and stores the voltage offset value corresponding to the first numerical range; the voltage offset values ​​are stored in the first mapping table in ascending order.

[0123] In some embodiments, the 2 n -1 read voltage is divided into multiple groups; a first mapping table stores a first numerical range corresponding to the read voltage of a group, and a first numerical range corresponds to the voltage offset value of the group; the voltage offset values ​​of the read voltage of the highest data state of the group are stored in ascending order; the memory controller 106 is further configured to: perform a read operation with the first read voltage corresponding to the highest data state in the group; and in response to the feature value being within the first numerical range, obtain the voltage offset value of the group corresponding to the first numerical range.

[0124] In some embodiments, at least a portion of the voltage offset values ​​corresponding to the read voltage of the highest data state in the group are linearly related to at least a portion of the voltage offset values ​​corresponding to the read voltages of other data states in the group.

[0125] In some embodiments, the mapping table includes a second mapping table, the second mapping table including: a second numerical range, and a voltage offset value corresponding to the second numerical range; the memory controller 106 is configured to: in response to the difference being within the second numerical range, obtain the voltage offset value corresponding to the second numerical range according to the second mapping table.

[0126] In some embodiments, the memory controller 106 is further configured to send a first operation command to the memory device 104; the memory device 104 is configured to enable a single-level read operation mode in response to the first operation command.

[0127] In some embodiments, the memory controller 106 is further configured to sum the first read voltage with the voltage offset value to obtain a second read voltage; and the memory device 104 is configured to perform a reread operation using the second read voltage.

[0128] According to some aspects of embodiments of this disclosure, Figure 20 A control method for a memory system 102 is provided, comprising: performing a read operation using a first read voltage corresponding to a first data state of a memory cell; obtaining a first number of memory cells with a threshold voltage less than or equal to the first read voltage; obtaining a second number of memory cells with a threshold voltage greater than the first read voltage; determining the difference between the second number and the first number; and obtaining a voltage offset value from a mapping table based on the difference.

[0129] In some embodiments, the mapping table includes a first mapping table, which stores a first numerical range and a voltage offset value corresponding to the first numerical range; obtaining the voltage offset value from the mapping table based on the difference includes: multiplying the difference by an association coefficient to obtain a feature value; and in response to the feature value being within the first numerical range, obtaining the voltage offset value corresponding to the first numerical range based on the first mapping table.

[0130] In some embodiments, each storage unit is configured to store one of a plurality of data states; the correlation coefficient corresponds to the data state, and the correlation coefficients corresponding to different data states are not equal.

[0131] In some embodiments, the plurality of data states include 2 n Data states, through 2 n -1 read voltage distinguishes each of the multiple data states; the characteristic value corresponding to the i-th read voltage is the same as that of the 2nd read voltage. n The sum of the characteristic values ​​corresponding to the -i read voltages is zero; where n is an integer greater than 1 and i is less than 2. n -1 is a positive integer, and i is related to the 2n -i is not equal.

[0132] In some embodiments, the first mapping table stores a first numerical range of the first data state and stores the voltage offset value corresponding to the first numerical range; the voltage offset values ​​are stored in the first mapping table in ascending order.

[0133] In some embodiments, the 2 n -1 read voltage is divided into multiple groups; a first mapping table stores a first numerical range of read voltages for a group, and a first numerical range corresponds to the voltage offset value of the group; the voltage offset value of the read voltage of the highest data state of the group is stored in ascending order; the control method further includes: performing a read operation with the first read voltage corresponding to the highest data state in the group; and in response to the feature value being within the first numerical range, obtaining the voltage offset value of the group corresponding to the first numerical range.

[0134] In some embodiments, at least a portion of the voltage offset values ​​corresponding to the read voltage of the highest data state in the group are linearly related to at least a portion of the voltage offset values ​​corresponding to the read voltages of other data states in the group.

[0135] In some embodiments, the mapping table includes a second mapping table, the second mapping table including: a second numerical range, and a voltage offset value corresponding to the second numerical range; obtaining the voltage offset value from the mapping table based on the difference includes: in response to the difference being within the second numerical range, obtaining the voltage offset value corresponding to the second numerical range based on the second mapping table.

[0136] In some embodiments, the control method further includes: the memory controller 106 sending a first operation command to the memory device 104; and the memory device 104 responding to the first operation command by enabling a single-level read operation mode.

[0137] In some embodiments, the control method further includes: the memory controller 106 sums the first read voltage with the voltage offset value to obtain a second read voltage; and the memory device 104 performs a reread operation using the second read voltage.

[0138] According to some aspects of embodiments of the present disclosure, a readable storage medium is provided that stores a computer program, wherein the calculation and the program, when executed, implement the control method of the memory system 102.

[0139] The memory device 104 may include NAND memory, and the memory cells of the NAND memory may include floating-gate type memory cells with floating-gate transistors or charge-trapping type memory cells with charge-trapping transistors.

[0140] The storage medium can be a ferroelectric random access memory (FRAM), a magnetic random access memory (MRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM), etc.; or it can be any device including one or any combination of the above-mentioned memory devices 104.

[0141] In some embodiments, executable instructions may take the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0142] As an example, executable instructions may, but do not necessarily, correspond to files in a file system. They may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a Hyper Text Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple collaborative files (e.g., a file that stores one or more modules, subroutines, or code sections).

[0143] As an example, executable instructions can be deployed to execute on a single electronic device, or on multiple electronic devices located in one location, or on multiple electronic devices distributed across multiple locations and interconnected via a communication network.

[0144] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A memory controller, characterized in that, The memory controller is configured to: The control memory device performs a read operation using a first read voltage corresponding to a first data state of the memory cell; A first number of memory cells with a threshold voltage less than or equal to the first read voltage is obtained, and a second number of memory cells with a threshold voltage greater than the first read voltage is obtained. Determine the difference between the second quantity and the first quantity; as well as The voltage offset value is obtained from the mapping table based on the difference.

2. The memory controller according to claim 1, characterized in that, The mapping table includes a first mapping table, which stores: a first numerical range and a voltage offset value corresponding to the first numerical range; the memory controller is configured to: The feature value is obtained by multiplying the difference by the correlation coefficient; In response to the feature value being within the first numerical range, the voltage offset value corresponding to the first numerical range is obtained according to the first mapping table.

3. The memory controller according to claim 2, characterized in that, Each storage cell in the memory device is configured to store one of a plurality of data states; the correlation coefficient corresponds to the data state, and the correlation coefficients corresponding to different data states are not equal.

4. The memory controller according to claim 3, characterized in that, The multiple data states include 2 n Data states, through 2 n -1 read voltage distinguishes each of the multiple data states; the characteristic value corresponding to the i-th read voltage is the same as that of the 2nd read voltage. n The sum of the characteristic values ​​corresponding to the -i read voltages is zero; where n is an integer greater than 1 and i is less than 2. n -1 is a positive integer, and i is related to the 2 n -i is not equal.

5. The memory controller according to claim 4, characterized in that, The first mapping table stores a first numerical range of the first data state, and stores the voltage offset value corresponding to the first numerical range; the voltage offset values ​​are stored in the first mapping table in order of magnitude.

6. The memory controller according to claim 4, characterized in that, The 2 n -1 read voltage is divided into multiple groups; a first mapping table stores a first value range corresponding to the read voltage of a group, and a first value range corresponds to the voltage offset value of the group; the voltage offset values ​​of the highest data state read voltage of the group are stored in ascending order; the memory controller is further configured to: The read operation is performed using the first read voltage corresponding to the highest data state in the group; In response to the feature value being within the first numerical range, the voltage offset value of the group corresponding to the first numerical range is obtained.

7. The memory controller according to claim 6, characterized in that, At least a portion of the voltage offset values ​​corresponding to the highest data state read voltage in the group are linearly related to at least a portion of the voltage offset values ​​corresponding to the read voltages of other data states in the group.

8. The memory controller according to claim 1, characterized in that, The mapping table includes a second mapping table, which includes a second numerical range and a voltage offset value corresponding to the second numerical range; the memory controller is configured to: In response to the difference being within the second numerical range, the voltage offset value corresponding to the second numerical range is obtained according to the second mapping table.

9. The memory controller according to claim 1, characterized in that, The memory controller is configured to: The single-level read operation mode is enabled, and the memory device is controlled to perform a single-level read operation using the first read voltage.

10. The memory controller according to claim 1, characterized in that, The memory controller is also configured to: The second reading voltage is obtained by summing the first reading voltage with the voltage offset value.

11. A memory system, characterized in that, include: Memory devices; and the memory controller coupled thereto; The memory device includes a plurality of memory cells, which are configured to store one of a plurality of data states. The memory controller is configured to: The memory device is controlled to perform a read operation using a first read voltage corresponding to a first data state among the plurality of data states; A first number of memory cells with a threshold voltage less than or equal to the first read voltage is obtained, and a second number of memory cells with a threshold voltage greater than the first read voltage is obtained. Determine the difference between the second quantity and the first quantity; as well as The voltage offset value is obtained from the mapping table based on the difference.

12. The memory system according to claim 11, characterized in that, The mapping table includes a first mapping table, which stores: a first numerical range and a voltage offset value corresponding to the first numerical range; the memory controller is configured to: The feature value is obtained by multiplying the difference by the correlation coefficient; as well as In response to the feature value being within the first numerical range, the voltage offset value corresponding to the first numerical range is obtained according to the first mapping table.

13. The memory system according to claim 12, characterized in that, The correlation coefficient corresponds to the data state, and the correlation coefficients for different data states are not equal.

14. The memory system according to claim 13, characterized in that, The multiple data states include 2 n Data states, through 2 n -1 read voltage distinguishes each of the multiple data states; the characteristic value corresponding to the i-th read voltage is the same as that of the 2nd read voltage. n The sum of the characteristic values ​​corresponding to the -i read voltages is zero; where n is an integer greater than 1 and i is less than 2. n -1 is a positive integer, and i is related to the 2 n -i is not equal.

15. The memory system according to claim 14, characterized in that, The first mapping table stores a first numerical range of the first data state, and stores the voltage offset value corresponding to the first numerical range; the voltage offset values ​​are stored in the first mapping table in order of magnitude.

16. The memory system according to claim 14, characterized in that, The 2 n -1 read voltage is divided into multiple groups; a first mapping table stores a first value range corresponding to the read voltage of a group, and a first value range corresponds to the voltage offset value of the group; the voltage offset values ​​of the highest data state read voltage of the group are stored in ascending order; the memory controller is further configured to: Perform a read operation using the first read voltage corresponding to the highest data state in the group; and In response to the feature value being within the first numerical range, the voltage offset value of the group corresponding to the first numerical range is obtained.

17. The memory system according to claim 16, characterized in that, At least a portion of the voltage offset values ​​corresponding to the highest data state read voltage in the group are linearly related to at least a portion of the voltage offset values ​​corresponding to the read voltages of other data states in the group.

18. The memory system according to claim 11, characterized in that, The mapping table includes a second mapping table, which includes a second numerical range and a voltage offset value corresponding to the second numerical range; the memory controller is configured to: In response to the difference being within the second numerical range, the voltage offset value corresponding to the second numerical range is obtained according to the second mapping table.

19. The memory system according to claim 11, characterized in that, The memory controller is also configured to: Send a first operation command to the memory device; The memory device is configured to enable a single-level read operation mode in response to the first operation command.

20. The memory system according to claim 11, characterized in that, The memory controller is also configured to: The second read voltage is obtained by summing the first read voltage with the voltage offset value; The memory device is configured to perform a reread operation using the second read voltage.

21. A control method for a memory system, characterized in that, include: A read operation is performed using a first read voltage corresponding to the first data state of the storage cell; A first number of memory cells with a threshold voltage less than or equal to the first read voltage is obtained, and a second number of memory cells with a threshold voltage greater than the first read voltage is obtained. Determine the difference between the second quantity and the first quantity; The voltage offset value is obtained from the mapping table based on the difference.

22. The control method according to claim 21, characterized in that, The mapping table includes a first mapping table, which stores: a first numerical range and a voltage offset value corresponding to the first numerical range; obtaining the voltage offset value from the mapping table based on the difference includes: The feature value is obtained by multiplying the difference by the correlation coefficient; and In response to the feature value being within the first numerical range, the voltage offset value corresponding to the first numerical range is obtained according to the first mapping table.

23. The control method according to claim 22, characterized in that, Each storage unit is configured to store one of multiple data states; the correlation coefficient corresponds to the data state, and the correlation coefficients corresponding to different data states are not equal.

24. The control method according to claim 23, characterized in that, The multiple data states include 2 n Data states, through 2 n -1 read voltage distinguishes each of the multiple data states; the characteristic value corresponding to the i-th read voltage is the same as that of the 2nd read voltage. n The sum of the characteristic values ​​corresponding to the -i read voltages is zero; where n is an integer greater than 1 and i is less than 2. n -1 is a positive integer, and i is related to the 2 n -i is not equal.

25. The control method according to claim 24, characterized in that, The first mapping table stores a first numerical range of the first data state, and stores the voltage offset value corresponding to the first numerical range; the voltage offset values ​​are stored in the first mapping table in order of magnitude.

26. The control method according to claim 24, characterized in that, The 2 n -1 read voltage is divided into multiple groups; a first mapping table stores a first value range of the read voltage of a group, and a first value range corresponds to the voltage offset value of the group; The voltage offset values ​​of the highest data state read voltage of the group are stored in ascending order; The control method further includes: The read operation is performed using the first read voltage corresponding to the highest data state in the group; as well as In response to the feature value being within the first numerical range, the voltage offset value of the group corresponding to the first numerical range is obtained.

27. The control method according to claim 26, characterized in that, At least a portion of the voltage offset values ​​corresponding to the highest data state read voltage in the group are linearly related to at least a portion of the voltage offset values ​​corresponding to the read voltages of other data states in the group.

28. The control method according to claim 21, characterized in that, The mapping table includes a second mapping table, which includes a second numerical range and a voltage offset value corresponding to the second numerical range; obtaining the voltage offset value from the mapping table based on the difference includes: In response to the difference being within the second numerical range, the voltage offset value corresponding to the second numerical range is obtained according to the second mapping table.

29. The control method according to claim 21, characterized in that, The control method further includes: The memory controller sends a first operation command to the memory device; In response to the first operation command, the memory device enables a single-level read operation mode.

30. The control method according to claim 21, characterized in that, The control method further includes: The memory controller sums the first read voltage with the voltage offset value to obtain the second read voltage; The memory device uses the second read voltage to perform a reread operation.

31. A readable storage medium, characterized in that, The readable storage medium stores a computer program, and when the calculation and the program are executed, they implement the control method as described in any one of claims 21 to 30.

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