Pre-charging method and programming method of 3D memory device

Abstract

The invention provides a pre-charging method and a programming method of a 3D memory device. The 3D memory device includes an upper-segment word line group, a middle dummy word line group, a lower-segment word line group, and a bottom dummy word line group. The pre-charging method comprises the following steps: selecting a word line for programming; judging whether the selected word line is in an upper-section word line group or a lower-section word line group; when the word line is an upper segment word line group, pre-charging conduction voltage is applied to the middle virtual word line, so that a channel of the middle virtual word line is opened for pre-charging; and when the word line is the lower segment word line group, applying a pre-charge shutdown voltage to the middle virtual word line to close the channel thereof without pre-charge. The method is suitable for the 3D NAND flash memory with high capacity and high efficiency.

Description

Technical Field

[0001] This invention relates to a method of operating a memory device, and more particularly to a pre-charging method for a 3D memory device. Background Technology

[0002] Before programming the memory, i.e., before applying the programming pulse, a precharge operation is typically performed. Precharge is crucial for mitigating programming interference. Insufficient precharge capability exacerbates programming interference and also raises the high bound of the erase state of memory cells. This results in a loss of read space (window).

[0003] Currently, to achieve high capacity, 3D NAND memory devices have increased the number of stacked layers and adopted a multi-deck structure. For example... Figure 1 In the simplified structure shown, from top to bottom, the components are: upper word line group (WL) 2, middle virtual word line group (MDWL) 6, lower word line group (WL) 4, and bottom virtual word line group (BDWL) 8. The pre-charge voltage is typically applied from the common source line (CSL) on the source side to further expel electrons from channel 9. During the pre-charge operation, the bottom virtual word line (BDWL) 8 and the middle virtual word line (MDWL) 6 are turned on, allowing the pre-charge voltage to be fully applied to channel 9.

[0004] In other words, during the pre-charge operation, a voltage needs to be applied to the selected intermediate virtual word line group (MDWL) 6 in the joint layer to turn it on. This allows the pre-charge voltage to be applied to channel 9 from the common source line (CSL) side. Therefore, the threshold voltage of the selected intermediate virtual word line group (MDWL) 6 in the joint layer can impact the pre-charge capability.

[0005] In traditional methods, for the intermediate virtual word lines (MDWL) 6 in the connection layer, during the programming of the entire word line, even when the upper word line 2 has been programmed and the lower word line (WL) 4 is being programmed, these intermediate virtual word lines (MDWL) 6 are always continuously turned on and off. At this time, due to the down-coupling A effect, the excess pre-charge generated by turning the intermediate virtual word lines (MDWL) 6 on and off will interfere with the boundary word line 2a adjacent to the intermediate virtual word lines (MDWL) 6. That is, because of the increase in the channel potential Pch, electrons move towards the memory cells on the adjacent boundary word line 2a. This will raise the upper bound of the erase (ER) state of that memory cell.

[0006] Therefore, maintaining the pre-charge capability of the upper word line and avoiding interference with word lines adjacent to the middle virtual word line are important issues. Summary of the Invention

[0007] As described above, according to an embodiment of the present invention, a pre-charging method for a 3D memory device is provided. The 3D memory device includes at least an upper word line group, an intermediate virtual word line group, a lower word line group, and a bottom virtual word line group arranged sequentially. The pre-charging method includes: selecting a word line from the upper word line group and the lower word line group for programming; determining whether the selected word line is located in the upper word line group or the lower word line group; when the word line is located in the upper word line group, applying a pre-charging on voltage to the intermediate virtual word line group, such that the pre-charging voltage reaches the corresponding channel of the intermediate virtual word line group; and when the word line is located in the lower word line group, applying a pre-charging off voltage to the intermediate virtual word line group, such that the pre-charging voltage does not reach the corresponding channel of the intermediate virtual word line group.

[0008] According to another embodiment of the present invention, a pre-charging method for a 3D memory device is provided. The 3D memory device includes at least: a multi-segment word line group, a plurality of intermediate virtual word line groups, and a bottom virtual word line group, wherein the bottom virtual word line group is located below the lowest segment of the multi-segment word line group, and each of the plurality of intermediate virtual word line groups is disposed between every two segments of the multi-segment word line group. The pre-charging method includes: selecting a word line from the multi-segment word line group for programming; determining that the selected word line is a segment of the multi-segment word line group; applying a pre-charging on voltage to each intermediate virtual word line group located below the segment, such that the pre-charging voltage reaches the corresponding channel of each intermediate virtual word line group below the segment; and applying a pre-charging off voltage to each intermediate virtual word line group located above the segment, such that the pre-charging voltage does not reach the corresponding channel of each intermediate virtual word line group above the segment.

[0009] According to another embodiment of the present invention, a programming method for a 3D memory device is provided. The 3D memory device includes at least an upper word line group, a middle virtual word line group, a lower word line group, and a bottom virtual word line group arranged sequentially. The programming method includes: selecting a word line from the upper word line group and the lower word line group for programming; determining whether the selected word line is located in the upper word line group or the lower word line group; when the word line is located in the upper word line group, applying a pre-charge on voltage to the middle virtual word line, such that the pre-charge voltage reaches the corresponding channel of the middle virtual word line; when the word line is located in the lower word line group, applying a pre-charge off voltage to the middle virtual word line, such that the pre-charge voltage does not reach the corresponding channel of the middle virtual word line; and after ending the application of the pre-charge voltage, applying a programming voltage to the selected word line.

[0010] According to an embodiment of the present invention, in the above-described pre-charging method or programming method, the 3D memory device further includes a common source line, from which the pre-charging voltage is applied.

[0011] According to an embodiment of the present invention, in the above-described pre-charge method or programming method, the pre-charge turn-on voltage is much smaller than the voltage used to program the selected word line, and the pre-charge turn-off voltage is 0V.

[0012] According to an embodiment of the present invention, in the above-described pre-charging method or programming method, during pre-charging, the pre-charging conduction voltage is further applied to the bottom virtual word line group.

[0013] According to an embodiment of the present invention, in the above-described pre-charge method or programming method, the memory device has an array composed of multiple memory cells, wherein the multiple memory cells are single-level cells, double-level cells, triple-level cells, or quadruple-level cells. According to an embodiment of the present invention, in the above-described pre-charge method or programming method, the memory device is a 3D NAND memory device.

[0014] Based on the embodiments of the present invention, in a 3D memory device with a multi-segment word line group structure, during the pre-charge phase, the intermediate virtual word line layer is appropriately controlled to be either turned on or off based on the position of the selected word line to be programmed, thereby controlling the pre-charge operation. This maintains the pre-charge capability of the upper word lines and avoids interference with word lines adjacent to the intermediate virtual word lines. Attached Figure Description

[0015] Figure 1 This is an illustrative diagram explaining the interference of precharge with programming.

[0016] Figure 2 A schematic diagram of the memory structure related to each word line is drawn.

[0017] Figure 3 A structural diagram of each character's lines is shown.

[0018] Figure 4 A schematic diagram illustrating the application of embodiments of the present invention.

[0019] Figure 5A and Figure 5B This is a waveform diagram of a pre-charging method according to an embodiment of the present invention.

[0020] Figure 6 A comparative graph showing experimental results between the conventional pre-charging method and the pre-charging method of the present invention is provided.

[0021] Figure 7 This is a schematic diagram illustrating a variation of the pre-charging method of the present invention.

[0022] Explanation of reference numerals in the attached figures:

[0023] 2. 110: Upper section word line group

[0024] 2a: Boundary line

[0025] 4. 112: Lower word line group

[0026] 6, 114: Middle Virtual Character Line Group

[0027] 8, 116: Bottom Virtual Character Line Group

[0028] 9, 120, 120A, 220: Channels

[0029] 10: Dielectric layer core

[0030] 20: Channel Layer

[0031] 30: Charge trapping layer

[0032] 100, 200: 3D memory devices

[0033] 110A, 112A, 210-3A: Selected word lines

[0034] 210-1, 210-2, 210-3, 210-4, ..., 210-n: Word line groups

[0035] 220-1, 220-2, 220-3, ..., 220-m: Intermediate Virtual Character Line Group

[0036] 230: Bottom Virtual Character Line

[0037] 240: Top Virtual Text Line

[0038] WL0~WL95: Word lines

[0039] DWLB0~DWLB2: Bottom Virtual Text Lines

[0040] DWLT0~DWLT2: Top Virtual Word Line

[0041] CSL: Common Source Line

[0042] SSL, SSL0, SSL1, SSL2: Select line

[0043] GSL: Global Source Line

[0044] GBL: Global Bitline

[0045] VC: Vertical Channel

[0046] A: Downcoupling effect

[0047] VPASSP: Through voltage

[0048] VPGM: Programming Voltage

[0049] Vpre_on: Precharge on-state voltage

[0050] Vpre_off: Precharge off voltage

[0051] VPRE: Precharge Voltage Detailed Implementation

[0052] The following explanation uses 3D NAND flash memory as an example, but the present invention is not limited to this; any 3D memory structure can be applied. Furthermore, the present invention can also be applied to 2D memory.

[0053] Figure 2 The illustration depicts a memory architecture as an application example of an embodiment of the present invention, illustrating a partial structure of a 3D NAND flash memory. Furthermore, this embodiment of the present invention describes a multi-segment structure, while... Figure 2 This is just one example. Therefore, for a two-segment 3D NAND flash memory, it consists of two segments. Figure 1 The structure shown is as follows. That is, above the virtual word lines DWLT0~DWLT2, and between the select line SSL0, a structure equivalent to word lines WL0~WL95 is further stacked to form two segments of 3D NAND flash memory. The layers of virtual word lines DWLT0~DWLT2 between the multiple word lines of the upper and lower segments can also be called connection layers. Furthermore, if there are three or more segments, they are continuously stacked in this manner.

[0054] The following is a simple explanation of the structure of a single paragraph. For example... Figure 2The schematic structure of the 3D NAND flash memory device shown has multiple word lines WL0 to WL95 (96 words as an example) formed in the vertical z-direction, and a vertical channel VC is also formed along the vertical z-direction. Each word line extends in the xy-plane. In addition, bottom virtual word lines DWLB1 and DWLB0 are arranged below word line WL0, and top virtual word lines DWLT1 and DWLT0 are arranged above word line WL95. Although two bottom virtual word lines and two top virtual word lines are shown here, their number is not particularly limited and can be adjusted appropriately according to needs.

[0055] In addition, 3D NAND flash memory devices may also include a common source line (CSL) that connects all source lines together. 3D NAND flash memory devices may also include select lines SSL0, SSL1, SSL2, etc., which can be positioned above the top virtual word line DWLT2. A global source line (GSL) can also be formed below the bottom virtual word line, and a global bit line (GBL) can be formed above the top virtual word line to connect each bit line. Figure 2 The structure of the 3D NAND flash memory device shown is only for the convenience of understanding the relationship between a segment of word lines (data word lines) WL0~WL95 and virtual word lines, and is not intended to limit the scope of the present invention.

[0056] Figure 3 A schematic diagram illustrating the structure of each character's lines is provided. Figure 2 An enlarged view of the letter outline. (See image below.) Figure 3 The 3D NAND flash memory device includes multiple word lines WL0 to WL95, which are traversed by a vertical channel VC. The vertical channel VC has a dielectric core 10, a channel layer 20 surrounding the dielectric core 10, and a charge trapping layer 30 between each word line WL0 to WL95 and the channel layer 20. The channel layer 20 is formed, for example, of polysilicon, and the charge trapping layer is formed, for example, of an oxide-nitride-oxide (ONO) layer. The structure illustrated herein is merely one example of a 3D NAND flash memory device to which the programming method of the present invention can be applied; the method of the present invention is not limited to any particular memory structure.

[0057] Figure 4 A schematic diagram illustrating the application of embodiments of the present invention is shown. For example... Figure 4As shown, the 3D memory device 100 includes at least an upper word line group 110, a middle virtual word line group 114, a lower word line group 112, and a bottom virtual word line group 116 arranged sequentially. Each word line may include multiple word lines. In this example, the drain side is above the 3D memory device 100, and the source side is below the 3D memory device 100. Furthermore, only the necessary configuration, namely a schematic diagram of the positional relationship between the word lines and the channel 120, is shown for the 3D memory device 100. Other components of the 3D memory device 100 not shown can be referenced from existing structures developed for the future, and their description is omitted here.

[0058] Furthermore, in this example, the 3D memory device 100 is illustrated by a two-segment stacked 3D NAND flash memory device, i.e., two... Figure 2 , Figure 3 The illustrated structures are stacked together. Furthermore, an example of memory programming is programming each word line WL sequentially from the upper word line group 110 to the lower word line group 112. Additionally, during programming, a so-called Increment Step Programming Pulse (ISPP) method can be used to program the selected word lines.

[0059] Figure 5A and Figure 5B This is a waveform diagram of a pre-charging method according to an embodiment of the present invention. According to an embodiment of the present invention, in order to reduce interference to the boundary word lines (such as 110A) adjacent to the intermediate virtual word line group 114 during the pre-charging operation, the on and off states of the intermediate virtual word line group 114 are controlled.

[0060] like Figure 4 and Figure 5A As shown, when programming each word line WL, each word line WL from the upper word line group 110 to the lower word line group 112 is programmed sequentially. Figure 5A Only representative word lines are shown; not all word lines WL are illustrated. A pre-charge voltage VPRE is applied from the common source line CSL before programming, which is then input to channel (vertical channel) 120.

[0061] First, a word line to be programmed is sequentially selected from the upper word line group 110 and the lower word line group 112. Then, it is determined whether the word line is located in the upper word line group 110 or the lower word line group 112. For example, when the selected word line 110A is located in the upper word line group 110, a precharge turn-on voltage Vpre_on is applied to the intermediate virtual word line group (MDWL) 114 during the precharge phase to turn on its corresponding channel 120A. Furthermore, for precharge, the bottom virtual word line group (BDWL) 116 is also turned on by applying the precharge turn-on voltage Vpre_on. Additionally, since the memory cells on the lower word line group 112 have not yet been programmed and are in the erase (ER) state, their corresponding channels are also on. Therefore, by turning on the intermediate virtual word line group (MDWL) 114, the pre-charge voltage VPRE applied from the common source line CSL can reach the channel 120A corresponding to the intermediate virtual word line group (MDWL) 114. Thus, for example, before programming the select word line 110A in the upper word line group 110, pre-charging is performed by turning on the virtual word line group (MDWL) 114. In this way, the channel corresponding to the virtual word line group (MDWL) 114 can be sufficiently boosted by the pre-charge voltage VPRE, further eliminating electrons still present in the channel to reduce programming interference. Furthermore, this also maintains the pre-charge capability of the upper word line group 110.

[0062] Furthermore, the precharge turn-on voltage Vpre_on only needs to be sufficient to turn on the memory cell coupled to the intermediate virtual word line group (MDWL) 114, thereby enabling its channel 120A. Additionally, the voltage value of the precharge turn-on voltage Vpre_on can be much smaller than the programming voltage VPGM to avoid malfunctions to the intermediate virtual word line group (MDWL) 114.

[0063] In addition, such as Figure 5A As shown, the programming phase begins after the pre-charging phase. At this time, a programming voltage VPGM is applied to the selected word line 110A for programming, and a pass voltage VPASP is applied to the unselected word lines (including the programmed word lines in the upper word line group 110 and the unprogrammed word lines in the lower word line group 112). Furthermore, a pass voltage VPASP is also applied to the intermediate virtual word line group (MDWL) 114 and even the bottom virtual word line group (BDWL) 116. The pass voltage VPASP keeps the word lines in an unselected state.

[0064] In addition, such as Figure 5BAs shown, when the selected word line 112A is located in the lower word line group 112, a precharge shutdown voltage Vpre_off is applied to the intermediate virtual word line group (MDWL) 114 during the precharge phase to shut down its channel 120A. Furthermore, to perform precharge, the bottom virtual word line group (BDWL) 116 is also turned on by applying a precharge turn-on voltage Vpre_on. Additionally, in the lower word line group 112, the memory cells connected to the word lines below the selected word line 112A are not yet programmed and are in the erase (ER) state, so their corresponding channels are also open. Therefore, the precharge voltage VPRE applied from the common source line CSL only reaches the channels corresponding to the word lines below the selected word line 112A.

[0065] Furthermore, because the intermediate virtual word line group (MDWL) 114 is subject to a precharge shutdown voltage Vpre_off, the corresponding channel will not be turned on, and the precharge voltage VPRE cannot reach it. Therefore, the upper word line 110A adjacent to the intermediate virtual word line group (MDWL) 114 will not interfere with its programmed state due to downward coupling. Thus, interference with the word line 110A adjacent to the intermediate virtual word line group 114 can be avoided.

[0066] Similarly, as Figure 5B As shown, the programming phase begins after the pre-charging phase. At this time, a programming voltage VPGM is applied to the selected lower word line 112A for programming, and a pass voltage VPASSP is applied to the unselected word lines (including the programmed word lines in the upper word line group 110 and the unprogrammed word lines in the lower word line group 112). Furthermore, a pass voltage VPASSP is also applied to the intermediate virtual word line group (MDWL) 114 and even the bottom virtual word line group (BDWL) 116. The pass voltage VPASSP keeps the word lines in an unselected state.

[0067] Figure 6 This is a comparative graph illustrating experimental results between a conventional pre-charging method and the pre-charging method of this invention. Figure 6 The vertical axis represents the bit count, and the horizontal axis represents the threshold voltage Vt. Furthermore, Figure 6 This indicates the erase (ER) and programming (A~G) status of the memory cells on each word line. Figure 6 The image above shows the experimental results using the traditional pre-charging method. Figure 6 The following is a graph showing the experimental results of the pre-charging method according to an embodiment of the present invention.

[0068] from Figure 6As can be seen above, in the two-segment stacked structure, when programming the lower word line, the intermediate virtual word line remains conductive during the precharge phase. Therefore, the precharge voltage interferes with the programmed upper word line adjacent to the intermediate virtual word line. As a result, the erase state ER and the programming state A become too close, potentially causing the read boundary to overlap and leading to erroneous reads.

[0069] Figure 6 As can be seen below, using the pre-charging method of this embodiment, during the pre-charging stage, a pre-charging turn-on voltage Vpre_on is applied to the intermediate virtual word line 114 only when the upper word line 110 is programmed, in order to enable its channel and pre-charge the channel. However, when the lower word line 110 is programmed, a pre-charging turn-off voltage Vpre_off is applied to the intermediate virtual word line 114 to disable its channel, and the channel is not pre-charged. Therefore, in this case, the programmed upper word line adjacent to the intermediate virtual word line will not be interfered with due to unnecessary pre-charging operations.

[0070] Figure 7 This is a schematic diagram illustrating a variation of the pre-charging method of the present invention. In this example, the 3D memory device 200 includes multiple word line groups 210-1, 210-2, ..., 210-n (n-group). Furthermore, between each pair of word line groups 210-1, 210-2, ..., 210-n, multiple intermediate virtual word line groups 220-1, 220-2, ..., 220-m (m-group) are also included. For example, an intermediate virtual word line group 220-2 is provided between a word line group 210-2 and a word line group 210-3. Additionally, a bottom virtual word line group 230 is provided below the lowest word line group 210-1 of the multiple word line groups 210-1, 210-2, ..., 210-n. Furthermore, in one embodiment, a top virtual word line group 240 is provided above the uppermost word line group 210-n of the multiple word line groups 210-1, 210-2, ..., 210-n. Similarly, other components of the 3D memory device 200 not shown can be referenced from existing structures developed for the future, and their descriptions are omitted here.

[0071] In this example, the vertical stacking structure is described horizontally; that is, word line group 210-n is the top segment of the entire stacking structure, while word line group 210-1 is the bottom segment. Each segment of multiple word line groups 210-1, 210-2, ..., 210-n can also include multiple word lines. Each of the intermediate virtual word line groups 220-1, 220-2, ..., 220-m can also include multiple intermediate virtual word lines. The bottom virtual word line group 230 can include multiple bottom virtual word lines. The top virtual word line group 240 can include multiple top virtual word lines.

[0072] Furthermore, in this embodiment, the voltage waveforms used during the pre-charging and programming phases can be referenced. Figure 5A and Figure 5B For example, similar to the embodiment described above, a pre-charge voltage VPRE is applied from the common source line CSL to pre-charge channel 220 before programming. First, word lines are selected from multiple word line groups 210-1, 210-2, ..., 210-n for programming. For example, word lines are selected sequentially (from top to bottom) from multiple word line groups 210-n, 210-(n-1), ..., 210-2, 210-1, and word line 210-3A is selected. Next, it is determined that the selected word line 210-3a is a segment of the multiple word line groups 210-n, 210-(n-1), ..., 210-2, 210-1. In this example, it is word line group 210-3.

[0073] Next, a pre-charge turn-on voltage Vpre_on is applied to each intermediate virtual word line group 220-2, 220-1 and the bottom virtual word line 230 located below the word line group 210-3, so that the pre-charge voltage VPRE reaches the corresponding channel of each intermediate virtual word line 220-2, 220-1 below the word line group 210-3. This maintains the pre-charge capability of the word line group 210-3. Furthermore, a pre-charge turn-off voltage Vpre_off is applied to each intermediate virtual word line group 220-3, ..., 220-m located above the word line group 210-3 to turn off its channel. This prevents the pre-charge voltage VPRE from reaching the corresponding channel of each intermediate virtual word line 220-3, ..., 220-m above the word line group 210-3. This also avoids interference with word lines adjacent to the intermediate virtual word line groups 220-3, ..., 220-m.

[0074] The above embodiments use 3D NAND flash memory devices as illustrative examples, but the present invention is not limited to NAND flash memory devices, and other types of memory can also be applied, such as 3D NOR flash memory devices.

[0075] Furthermore, in the memory devices to which the pre-charging method of the present invention is applicable, the memory cells constituting the memory devices can also be single-level cells (SLC) that store 1 bit, multiple-level cells (MLC) that store 2 bits, triple-level cells (TLC) that store 3 bits, or quad-level cells (QLC) that store 4 bits, etc.

[0076] In summary, based on the embodiments of the present invention, in a 3D memory device with a multi-segment word line group structure, during the pre-charge phase, the intermediate virtual word line layer is appropriately controlled to be either turned on or off based on the position of the selected word line to be programmed, thereby controlling the pre-charge operation. This maintains the pre-charge capability of the upper word lines and avoids interference with word lines adjacent to the intermediate virtual word lines.

Claims

1. A pre-charging method for a 3D memory device, wherein the 3D memory device includes at least an upper word line group, a middle virtual word line group, a lower word line group, and a bottom virtual word line group arranged sequentially, the pre-charging method comprising: Select character lines from the upper character line group and the lower character line group for programming; Determine whether the selected character line is located in the upper segment character line group or the lower segment character line group; When the word line is located in the upper word line group, a pre-charge conduction voltage is applied to the middle virtual word line group so that the pre-charge voltage reaches the corresponding channel of the middle virtual word line group. as well as When the word line is located in the lower word line group, a pre-charge shutdown voltage is applied to the intermediate virtual word line group so that the pre-charge voltage does not reach the corresponding channel of the intermediate virtual word line group.

2. The pre-charging method for a 3D memory device according to claim 1, wherein the 3D memory device further includes a common source line, and the pre-charging voltage is applied from the common source line.

3. The pre-charge method for a 3D memory device according to claim 1, wherein the pre-charge on-state voltage is much smaller than the voltage used to program the selected word line, and the pre-charge off-state voltage is 0V.

4. The pre-charging method for a 3D memory device according to claim 1, wherein during pre-charging, the pre-charging conduction voltage is further applied to the bottom virtual word line group.

5. The pre-charging method for a 3D memory device according to claim 1, wherein the 3D memory device has an array of multiple memory cells, wherein the multiple memory cells are single-level cells, double-level cells, triple-level cells, or quadruple-level cells.

6. The pre-charging method for a memory device according to claim 1, wherein the 3D memory device is a 3D NAND memory device.

7. A programming method for a 3D memory device, wherein the 3D memory device includes at least an upper word line group, a middle virtual word line group, a lower word line group, and a bottom virtual word line group arranged sequentially, the programming method comprising: Select character lines from the upper character line group and the lower character line group for programming; Determine whether the selected character line is located in the upper segment character line group or the lower segment character line group; When the word line is located in the upper word line group, a pre-charge conduction voltage is applied to the middle virtual word line so that the pre-charge voltage reaches the corresponding channel of the middle virtual word line group; When the word line is located in the lower word line group, a pre-charge shutdown voltage is applied to the intermediate virtual word line group so that the pre-charge voltage does not reach the corresponding channel of the intermediate virtual word line group. as well as After the application of the pre-charge voltage is completed, a programming voltage is applied to the selected word line.

8. The programming method of the 3D memory device according to claim 7, wherein the 3D memory device further includes a common source line from which the precharge voltage is applied.

9. The programming method for a 3D memory device according to claim 7, wherein the precharge turn-on voltage is much smaller than the voltage used to program the selected word line, and the precharge turn-off voltage is 0V.

10. The programming method for a 3D memory device according to claim 7, wherein during precharging, the precharging conduction voltage is further applied to the bottom virtual word line group.

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