Channel liner for select gate threshold voltage tuning

Abstract

The invention relates to a channel liner for select gate threshold voltage tuning. Various applications may include a memory device having a string of memory cells coupled to a stack of drain-side select gate (SGD) transistors. The threshold voltage of the SGD transistors can be tuned to a sequence of threshold voltages by high-k dielectric pads adjacent to and in contact with selected one or more SGD transistors of the stack. Additional apparatus, systems, and methods are discussed.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to memory devices, and more specifically, to the design of components of memory devices. Background Technology

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory requires power to maintain its data and includes random access memory (RAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM), etc. Non-volatile memory can retain stored data when not powered and includes flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), and resistive variable memory, such as phase-change random access memory (PCRAM), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), or 3D XPoint. TM Memory, etc.

[0003] Flash memory is used as a non-volatile memory for a wide range of electronic applications. Flash memory devices typically contain one or more groups of single-transistor, floating-gate, or charge-trapping memory cells that allow for high memory density, high reliability, and low power consumption. Two common types of flash memory array architectures include NAND and NOR architectures, named after the logical form of the basic memory cell configuration that arranges each architecture. The memory cells of a memory array are typically arranged in a matrix. In one example, the gate of each floating-gate memory cell in a row of the array is coupled to an access line (e.g., a word line). In a NOR architecture, the drain of each memory cell in a column of the array is coupled to a data line (e.g., a bit line). In a NAND architecture, the drain of each memory cell in a string of the array is coupled together in series from source to drain between the source line and the data line.

[0004] Compared to planar structures, using a 3D architecture for memory devices (such as NAND memory devices) can provide increased capacity. Memory arrays for 3D structures can comprise memory cells stacked vertically as strings of memory cells. When selecting one or more strings for accessing a given memory cell, a gating structure can be located at the top and bottom of these strings, with the memory cell storing data between the top and bottom. The gating structure can include one or more select-gate transistors whose drains are coupled to data lines (e.g., bit lines) at one end of the string, and one or more select-gate transistors whose sources are coupled to source lines at the other end of the string. Drain-side select-gate transistors whose drains are coupled to the data lines of the memory cell string are referred to herein as SGD transistors, and source-side select-gate transistors whose sources are coupled to the source lines of the memory cell string are referred to herein as SGS transistors. Design improvements to the gating structure (e.g., SGD transistors or SGS transistors) can enhance control over the operation of the memory cell strings of the memory device. Summary of the Invention

[0005] An exemplary embodiment of the disclosed subject matter is a memory device comprising: a plurality of select-gate transistors vertically arranged in a stack to a string of memory cells; a channel structure extending vertically in the stack, the channel structure being arranged as a transistor channel structure for each of the plurality of select-gate transistors; and a dielectric pad adjacent to and contacting the transistor channel structure of one or more of the plurality of select-gate transistors, the dielectric pad being structured relative to the channel structure to provide a configuration of one or more of the plurality of select-gate transistors being high threshold voltage select-gate transistors, medium threshold voltage select-gate transistors, or low threshold voltage select-gate transistors.

[0006] Another exemplary embodiment of the disclosed subject matter is a memory device comprising: a plurality of select-gate transistors vertically arranged in a stack to a string of memory cells; a channel structure extending vertically in the stack, the channel structure being arranged as a transistor channel structure for each of the plurality of select-gate transistors; and a dielectric pad adjacent to and contacting the transistor channel structure of one or more of the plurality of select-gate transistors, the dielectric pad comprising a high-k dielectric material, the dielectric pad having a thickness originating from the channel structure and a length along the channel structure to provide one or more threshold voltage values ​​for the plurality of select-gate transistors.

[0007] Another exemplary embodiment of the disclosed subject matter is a method comprising: forming a plurality of select-gate transistors vertically arranged in a stack to a string of memory cells; forming a channel structure extending vertically in the stack, the channel structure being arranged as a transistor channel structure for each of the plurality of select-gate transistors; and forming a dielectric pad adjacent to and contacting the transistor channel structure of one or more of the plurality of select-gate transistors, the dielectric pad being structured relative to the channel structure to provide a configuration of one or more of the plurality of select-gate transistors being high threshold voltage select-gate transistors, medium threshold voltage select-gate transistors, or low threshold voltage select-gate transistors. Attached Figure Description

[0008] The accompanying drawings, which are not necessarily drawn to scale, illustrate, rather than limit, the various embodiments discussed in this document in a general manner.

[0009] Figures 1 to 8 Examples of memory devices having a plurality of select-gate transistors arranged vertically in a stack to a string of memory cells according to various embodiments are described, wherein a dielectric pad is adjacent to and contacts a transistor channel structure of one or more of the plurality of select-gate transistors.

[0010] Figure 9 This is a flowchart illustrating the features of an example method for forming a memory device having one or more select gate transistors with tuning threshold voltages, according to various embodiments.

[0011] Figure 10 This is a flowchart illustrating the features of an example method for forming a memory device having a plurality of select gate transistors that can be formed with a selected threshold voltage sequence, according to various embodiments.

[0012] Figure 11 The block diagram illustrates an example machine having one or more memory devices with structured dielectric pads according to various embodiments, the dielectric pads being implemented to tune the threshold voltage of one or more drain-side select gate transistors. Detailed Implementation

[0013] The following detailed description refers to the accompanying drawings, which illustrate various possible embodiments. These embodiments are described in sufficient detail to enable those skilled in the art to practice these and other embodiments. Other embodiments may be utilized, and structural, logical, mechanical, and electrical changes may be made to these embodiments. As used herein, the term "horizontal" is defined as a plane parallel to a conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term "vertical" refers to a direction perpendicular to the horizontal as defined above. Various features may have components perpendicular to their structural orientation. The various embodiments are not necessarily mutually exclusive, as some embodiments may be combined with one or more other embodiments to form new embodiments. Therefore, the following detailed description should not be construed as limiting.

[0014] Both NOR and NAND flash memory arrays are accessed via a decoder that activates a specific memory cell by selecting an access line (WL) coupled to the gate of that cell. In a NOR flash memory array, once activated, the selected memory cell places its data value on the data line, causing different currents to flow depending on the programmed state of the specific cell. In a NAND flash memory array, a relatively high bias voltage is applied to the drain-side select gate (SGD) line. At a specified on-state voltage, the access line coupled to the gate of each group of unselected memory cells is driven to operate each group of unselected memory cells as turn-on transistors (e.g., to conduct current regardless of their stored data values). Current then flows through each series-coupled group in the line between the source and data lines, limited only by the selected memory cell in each group, thereby placing the current-encoded data value of the selected memory cell on the data line.

[0015] Each flash memory cell in a NOR or NAND architecture semiconductor memory array can be individually or collectively programmed into one or more programmed states. For example, a single-level cell (SLC) can represent one of two programmed states (e.g., 1 or 0), which represents one data bit. Flash memory cells can also represent more than two programmed states, allowing for the fabrication of higher-density memories without increasing the number of memory cells, because each cell can represent more than one binary digit (e.g., more than one bit). Such cells may be referred to as multi-state memory cells, multi-bit cells, or multi-level cells (MLCs). In some instances, an MLC is referred to as a memory cell that can store two data bits per cell (e.g., one of four programmed states). MLC is used in its broader context herein to refer to any memory cell(s) that can store more than one data bit per cell (i.e., can represent more than two programmed states). In this document, a memory cell that can store two data bits per cell (e.g., one of four programmed states) is referred to as a dual-level cell (DLC). A three-level cell (TLC) is a memory cell that can store three data bits per cell (e.g., one of eight programmable states). A four-level cell (QLC) can store four data bits per cell, and a five-level cell (PLC) can store five data bits per cell.

[0016] In a string of memory cells in a 3D memory device (e.g., 3D NAND memory), access to the string can be controlled by one or more SGD transistors coupled to the string of memory cells to operate on the memory cells within the string. In a stack of SGD transistor cells, the optimal Vt window and Vt configuration of the SGD transistor cells should be used for good operation of the memory array and to avoid boost leakage, slow programming problems, or reliability issues. The Vt window of the transistor provides a range of Vt values ​​from a minimum voltage to a maximum voltage. The window can be divided into three Vt regions: low Vt, medium Vt, and high Vt. Low Vt is the range from the minimum value of the Vt window to a value located approximately one-third of the way down the window relative to the minimum value. Medium Vt is the range approximately one-third of the Vt window below a threshold value for the minimum high Vt, while high Vt is the range from the threshold value of the Vt window to its maximum value. The window can be divided into three regions according to a factor different from one-third, or into other regions with a different number of regions than the three. The Vt configuration of an SGD cell can be achieved using a sequence of SGD transistors having, for example, a Vt sequence of (high Vt, high Vt, low or medium Vt, medium Vt, low Vt…). Various sequences can be used depending on the application of the SGD transistor stack. Conventional processing techniques adjust the Vt of SGD transistors through boron implantation. However, achieving a specified Vt is challenging and controlling boron diffusion is difficult. Furthermore, the lateral contact processing of the gate of the SGD transistor cell uses a high diffusion temperature to allow dopant to diffuse upwards from the source side, which is located at the bottom of the vertical string of SGD transistor cells, memory cells, and SGS transistor cells. The lateral contact processing of the gate of the SGD transistor cell also uses a lower Vt for SGS transistors, which exacerbates the SGD Vt problem and makes achieving a lower SGS Vt but a higher SGD Vt even more challenging.

[0017] In various embodiments, a high-k dielectric film may be used as a channel pad adjacent to and contacting the transistor channel structure of one or more transistors to adjust the Vt of these transistors. The channel pad may be located on one side of the transistor channel structure opposite to the side of the transistor channel structure where the gates of one or more transistors are located. The high-k dielectric is a dielectric material having a dielectric constant greater than that of silicon dioxide, which has a dielectric constant of approximately 3.9. A stack of multiple transistors may include a channel structure providing a transistor channel for each of the multiple transistors. The multiple transistors may be structured with a dielectric fill adjacent to the channel structure. The dielectric fill may be a structured fill volume around the transistor. The high-k dielectric channel pad may be structured with varying thicknesses within the dielectric fill to adjust the Vt of the transistor adjacent to the channel pad. In a transistor sequence where each transistor in a high-k dielectric channel pad is adjacent to a sequence of transistors and each transistor has the same thickness, the high-k dielectric pad can provide a common Vt value for the transistors in the sequence that differs from the values ​​of transistors not in the sequence. Alternatively, the high-k dielectric pad can vary its thickness along the length of its contact with the sequence to provide transistors in the sequence with different Vt values ​​that differ from those of transistors not in the sequence. Each of the multiple transistors can be formed with substantially the same structure, but with variations, for example, in doping, to achieve a low or medium Vt for the corresponding transistor not adjacent to the high-k dielectric pad. The transistors can be metal-oxide-semiconductor field-effect transistors (MOSFETs), floating-gate transistors, charge-trapping cells, or similar transistor cells. The stack of multiple transistors can be an SGD transistor disposed above and coupled to a string of memory cells in a memory array of a memory device. One or more SGS transistors can be disposed below and coupled to a string of memory cells.

[0018] High-k dielectric pads can be implemented as, but are not limited to, AlO within the dielectric fill adjacent to the SGD transistor. x Film. The dielectric filler can be a non-high-k material, such as, but not limited to, silicon oxide. The high-k pad adjacent to the transistor channel is AlO. x In the case of the film, the inventors have evaluated a Vt increase of up to 1.5V. Other high-k films or combinations of high-k films can be used. The high-k pad is essentially unaffected by diffusion, thus allowing the process of optimizing the Vt of a lower SGS transistor in a manner almost independent of tuning the SGD transistor to a relatively high Vt, where the SGD transistor and the SGS transistor belong to the same string. The high-k pad adjacent to the SGD transistor provides a mechanism for tuning the Vt of the SGD transistor, which can be a different mechanism than that used for tuning the SGS transistor. Vt tuning is the setting or adjustment of the Vt of a transistor, which can be performed during transistor manufacturing.

[0019] Different Vt values ​​can be achieved for SGD transistors of desired specifications by controlling the thickness of the dielectric pads adjacent to and in contact with the SGD transistors. Vt adjustment provided by controlling the thickness of the dielectric pads for multiple SGD transistors makes it possible to achieve different cell Vt configurations as desired for a given specification. Stacks of multiple SGD transistors can be structured with high-k pads in pillars arranged on pillars containing strings of memory cells. The stack can contain several SGD transistor cells targeted with, for example, a Vt sequence of (high, low, low), (high, medium, medium), (medium, high, low), or other sequences. High-k dielectric pads can also be used in structures where multiple SGD transistor cells are integrated in the same pillars as the array of memory cells.

[0020] Figures 1 to 8 This describes an embodiment of an example memory device having a plurality of select-gate transistors vertically arranged in a stack to a string of memory cells and a channel structure extending vertically in the stack, wherein the channel structure is arranged as a transistor channel structure for each of the plurality of select-gate transistors. The memory device may include a dielectric pad adjacent to and contacting the transistor channel structure of one or more of the plurality of select-gate transistors, wherein the dielectric pad is structured relative to the channel structure to provide a configuration of one or more of the plurality of select-gate transistors, including high-threshold voltage select-gate transistors, medium-threshold voltage select-gate transistors, or low-threshold voltage select-gate transistors. The dielectric pad may comprise a high-k dielectric material. The channel structure may be structured horizontally around a dielectric filler along the vertical length of the channel. The dielectric filler may contain the dielectric pad and a dielectric region below the bottommost select-gate transistor of the plurality of select-gate transistors, wherein the dielectric region is a non-high-k dielectric. The non-high-k dielectric region may be, but is not limited to, silicon oxide. Except for the region occupied by the dielectric pad, the dielectric filler may be a non-high-k dielectric.

[0021] Figure 1The arrangement 100 in the memory device is described. Arrangement 100 has SGD transistors 104-0, 104-1, 104-2, 104-3, and 104-4 vertically positioned above and coupled to the memory cells, wherein the memory cells are arranged above one or more SGD transistors coupled to the source lines of the memory device. The SGD transistors 104-0, 104-1, 104-2, 104-3, and 104-4 arranged in a vertical stack can be coupled to digital lines above the SGD transistors 104-0, 104-1, 104-2, 104-3, and 104-4. A channel structure 110 may be vertically arranged in a stack of SGD transistors 104-0, 104-1, 104-2, 104-3, and 104-4, such that the channel structure 110 provides a transistor channel for the SGD transistors 104-0, 104-1, 104-2, 104-3, and 104-4. An isolation region 125 separates each of the SGD transistors 104-0, 104-1, 104-2, 104-3, and 104-4 from its immediate neighbor. A gate dielectric material 107 provides a gate dielectric for each of the SGD transistors 104-0, 104-1, 104-2, 104-3, and 104-4. The gate dielectric material 107 may be arranged to extend continuously in a vertical stack of SGD transistors 104-0, 104-1, 104-2, 104-3, and 104-4, directly contacting the isolation region 125. Alternatively, the gate dielectric material 107 may be segmented and vertically located between the isolation regions 125. The SGD transistors 104-0, 104-1, 104-2, 104-3, and 104-4 may each include gates 105-0, 105-1, 105-2, 105-3, and 105-4, separated from the channel structure 110 by the gate dielectric material 107.

[0022] The gate 105-0 of SGD transistor 104-0 is coupled to SGD select line SGDL 10. The gate 105-1 of SGD transistor 104-1 is coupled to SGD select line SGDL 11. The gate 105-2 of SGD transistor 104-2 is coupled to SGD select line SGDL 12. The gate 105-3 of SGD transistor 104-3 is coupled to SGD select line SGDL 13. The gate 105-4 of SGD transistor 104-4 is coupled to SGD select line SGDL 14. SGL 12, SGL 13, and SGL 14 are coupled together to provide the same voltage to the gates of SGD transistors 104-2, SGD transistor 104-3, and SGD transistor 104-4. Alternatively, none of the gates of the SGD transistors are coupled together, or different numbers of gates of the SGD transistors are coupled together. Although Figure 1An arrangement 100 with five SGD transistors is shown, but arrangement 100 may have more or fewer than five SGD transistors.

[0023] Arrangement 100 may include SGD transistors 104-0, 104-1, 104-2, 104-3, and 104-4 formed around dielectric filler 120. In the manufacturing process, dielectric filler 120 may be formed after the SGD transistors are formed. Dielectric filler 120 may include dielectric pad 115 and dielectric region 122. Dielectric pad 115 may be a high-k dielectric pad and dielectric region 122 may be a non-high-k dielectric region. Dielectric pad 115 may extend from above SGD transistor 104-4 and below SGD transistor 104-2, SGD transistor 104-4 being the topmost select-gate transistor among a plurality of select-gate transistors in arrangement 100, and SGD transistor 104-2 being the bottommost transistor in a sequence of SGD transistors 104-4, SGD transistor 104-3, and SGD transistor 104-2 arranged vertically directly from the topmost select-gate transistor. The dielectric pad 115 does not contact the SGD transistors 104-0 and 104-1 located below the sequence. The dielectric pad 115 is formed to have a thin thickness in the horizontal direction along its length to tune the Vt of SGD transistors 104-2, 104-3, and 104-4 to a different Vt than that of SGD transistors 104-0 and 104-1. The thickness can be approximately one-third of the radius of the dielectric filler 120. Other thicknesses can be used. The choice of thinness and thickness depends on the material of the dielectric pad 115. For AlO x The dielectric pad thickness can be selected to be related to 1 nm. Thick thicknesses can be 1 nm or higher, while thin thicknesses can be less than 1 nm down to a few angstroms. Other thin and thick values ​​can be used in the formation of the dielectric pad 115 depending on the specifications of the memory device's pillars. Thin thicknesses provide a lower Vt increase relative to the non-pad region of the dielectric pad 115 compared to thicker thicknesses. The Vt of the SGD transistor can be tuned by changing the thickness of the dielectric pad 115.

[0024] Figure 2The arrangement 200 in the memory device is described. Arrangement 200 has SGD transistors 204-0, 204-1, 204-2, 204-3, and 204-4 vertically positioned above and coupled to the memory cells, wherein the memory cells are arranged above one or more SGD transistors coupled to the source lines of the memory device. The SGD transistors 204-0, 204-1, 204-2, 204-3, and 204-4 arranged in a vertical stack can be coupled to digital lines above the SGD transistors 204-0, 204-1, 204-2, 204-3, and 204-4. The channel structure 210 can be vertically arranged in the stack of SGD transistors 204-0, 204-1, 204-2, 204-3, and 204-4, such that the channel structure 210 provides a transistor channel for the SGD transistors 204-0, 204-1, 204-2, 204-3, and 204-4. An isolation region 225 separates each of the SGD transistors 204-0, 204-1, 204-2, 204-3, and 204-4 from its immediate neighbor. The channel structure 210 can be arranged to extend continuously in the vertical stack of SGD transistors 204-0, 204-1, 204-2, 204-3, and 204-4. Gate dielectric material 207 provides a gate dielectric for each of SGD transistors 204-0, 204-1, 204-2, 204-3, and 204-4. Gate dielectric material 207 may be arranged to extend continuously in a vertical stack of SGD transistors 204-0, 204-1, 204-2, 204-3, and 204-4, vertically contacting isolation regions 225. Alternatively, gate dielectric material 207 may be segmented and vertically located between isolation regions 225. SGD transistors 204-0, 204-1, 204-2, 204-3, and 204-4 may respectively include gates 205-0, 205-1, 205-2, 205-3, and 205-4 separated from the channel structure 210 by gate dielectric material 207.

[0025] The gate 205-0 of SGD transistor 204-0 can be coupled to SGD select line SGDL 20. The gate 205-1 of SGD transistor 204-1 can be coupled to SGD select line SGDL 21. The gate 205-2 of SGD transistor 204-2 can be coupled to SGD select line SGDL 22. The gate 205-3 of SGD transistor 204-3 can be coupled to SGD select line SGDL 23. The gate 205-4 of SGD transistor 204-4 can be coupled to SGD select line SGDL 24. SGL 22, SGL 23, and SGL 24 can be coupled together to provide the same voltage to the gates of SGD transistors 204-2, SGD transistor 204-3, and SGD transistor 204-4. Alternatively, none of the gates of the SGD transistors are coupled together, or different numbers of gates of the SGD transistors are coupled together. Although Figure 2 An arrangement 200 with five SGD transistors is shown, but arrangement 200 may have more or fewer than five SGD transistors.

[0026] Arrangement 200 may include SGD transistors 204-0, 204-1, 204-2, 204-3, and 204-4 formed around dielectric filler 220. In the manufacturing process, dielectric filler 220 may be formed after the SGD transistors are formed. Dielectric filler 220 may include dielectric pad 215 and dielectric region 222. Dielectric pad 215 may be a high-k dielectric pad and dielectric region 222 may be a non-high-k dielectric region. Dielectric pad 215 may extend from above SGD transistor 204-4 and below SGD transistor 204-2, SGD transistor 204-4 being the topmost select-gate transistor among a plurality of select-gate transistors in arrangement 200, and SGD transistor 204-2 being the bottommost transistor in a sequence of SGD transistors 204-4, SGD transistor 204-3, and SGD transistor 204-2 arranged vertically directly from the topmost select-gate transistor. The dielectric pad 215 does not contact the SGD transistors 204-0 and 204-1 located below the sequence. The dielectric pad 215 is formed to have a thickness in the horizontal direction along its length to adjust the Vt of SGD transistors 204-2, 204-3, and 204-4 to a different Vt than that of SGD transistors 204-0 and 204-1. The thickness can be greater than approximately one-third and less than half the radius of the dielectric filler 220. Other thickness ranges can be used. The Vt of the SGD transistors can also be tuned by changing the thickness of the dielectric pad 215. The choice of thinness and thickness can depend on the material of the dielectric pad 215. For AlO xThe dielectric pad thickness can be selected to be related to 1 nm. Thick thicknesses can be 1 nm or higher, while thin thicknesses can be less than 1 nm down to a few angstroms. Other thin and thick values ​​can be used in the formation of the dielectric pad 215 depending on the specifications of the memory device's pillars. Thin thicknesses provide a lower Vt increase relative to the non-pad area compared to thicker thicknesses.

[0027] Figure 3 The arrangement 300 in the memory device is described. Arrangement 300 has SGD transistors 304-0, 304-1, 304-2, 304-3, and 304-4 vertically positioned above and coupled to the memory cells, wherein the memory cells are arranged above one or more SGD transistors coupled to the source lines of the memory device. The SGD transistors 304-0, 304-1, 304-2, 304-3, and 304-4 arranged in a vertical stack can be coupled to digital lines above the SGD transistors 304-0, 304-1, 304-2, 304-3, and 304-4. The channel structure 310 can be vertically arranged in the stack of SGD transistors 304-0, 304-1, 304-2, 304-3, and 304-4, such that the channel structure 310 provides a transistor channel for the SGD transistors 304-0, 304-1, 304-2, 304-3, and 304-4. An isolation region 325 separates each of the SGD transistors 304-0, 304-1, 304-2, 304-3, and 304-4 from its immediate neighbor. The channel structure 310 can be arranged to extend continuously in the vertical stack of SGD transistors 304-0, 304-1, 304-2, 304-3, and 304-4. Gate dielectric material 307 provides a gate dielectric for each of SGD transistors 304-0, 304-1, 304-2, 304-3, and 304-4. Gate dielectric material 307 may be arranged to extend continuously vertically in contact with isolation regions 325 in a vertical stack of SGD transistors 304-0, 304-1, 304-2, 304-3, and 304-4. Alternatively, gate dielectric material 307 may be segmented vertically located between isolation regions 325. SGD transistors 304-0, 304-1, 304-2, 304-3, and 304-4 may respectively include gates 305-0, 305-1, 305-2, 305-3, and 305-4 separated from the channel structure 310 by gate dielectric material 307.

[0028] The gate 305-0 of SGD transistor 304-0 can be coupled to SGD select line SGDL 30. The gate 305-1 of SGD transistor 304-1 can be coupled to SGD select line SGDL 31. The gate 305-2 of SGD transistor 304-2 can be coupled to SGD select line SGDL 32. The gate 305-3 of SGD transistor 304-3 can be coupled to SGD select line SGDL 33. The gate 305-4 of SGD transistor 304-4 can be coupled to SGD select line SGDL 34. SGL 32, SGL 33, and SGL 34 can be coupled together to provide the same voltage to the gates of SGD transistors 304-2, SGD transistor 304-3, and SGD transistor 304-4. Alternatively, none of the gates of the SGD transistors are coupled together, or different numbers of gates of the SGD transistors are coupled together. Although Figure 3 An arrangement 300 with five SGD transistors is shown, but the arrangement 300 may have more or fewer than five SGD transistors.

[0029] Arrangement 300 may include SGD transistors 304-0, 304-1, 304-2, 304-3, and 304-4 formed around dielectric filler 320. In the manufacturing process, dielectric filler 320 may be formed after the SGD transistors are formed. Dielectric filler 320 may include dielectric pad 315 and dielectric region 322. Dielectric pad 315 may be a high-k dielectric pad and dielectric region 322 may be a non-high-k dielectric region. Dielectric pad 315 may extend from above SGD transistor 304-4 and below SGD transistor 304-2, SGD transistor 304-4 being the topmost select-gate transistor among a plurality of select-gate transistors in arrangement 300, and SGD transistor 304-2 being the bottommost transistor in a sequence of SGD transistors 304-4, SGD transistor 304-3, and SGD transistor 304-2 arranged vertically directly from the topmost select-gate transistor. The dielectric pad 315 does not contact the SGD transistors 304-0 and 304-1 located below the sequence. The dielectric pad 315 is formed to have a thickness in the horizontal direction along its length to tune the Vt of SGD transistors 304-2, 304-3, and 304-4 to a different Vt than that of SGD transistors 304-0 and 304-1. The thickness of the dielectric pad 315 is filled with dielectric filler 320 and positioned to contact the dielectric region 322, thereby increasing the Vt of SGD transistors 304-2, 304-3, and 304-4 to a high value relative to the Vt of the adjacent non-pad region SGD transistors.

[0030] Figure 4The arrangement 400 in the memory device is described. Arrangement 400 has SGD transistors 404-0, 404-1, 404-2, 404-3, and 404-4 vertically positioned above and coupled to the memory cells, wherein the memory cells are arranged above one or more SGD transistors coupled to the source lines of the memory device. The SGD transistors 404-0, 404-1, 404-2, 404-3, and 404-4 arranged in a vertical stack can be coupled to digital lines above the SGD transistors 404-0, 404-1, 404-2, 404-3, and 404-4. The channel structure 410 can be vertically arranged in the stack of SGD transistors 404-0, 404-1, 404-2, 404-3, and 404-4, such that the channel structure 410 provides a transistor channel for the SGD transistors 404-0, 404-1, 404-2, 404-3, and 404-4. An isolation region 425 separates each of the SGD transistors 404-0, 404-1, 404-2, 404-3, and 404-4 from its immediate neighbor. The channel structure 410 can be arranged to extend continuously in the vertical stack of SGD transistors 404-0, 404-1, 404-2, 404-3, and 404-4. Gate dielectric material 407 provides a gate dielectric for each of SGD transistors 404-0, 404-1, 404-2, 404-3, and 404-4. Gate dielectric material 407 may be arranged to extend continuously in a vertical stack of SGD transistors 404-0, 404-1, 404-2, 404-3, and 404-4, vertically contacting isolation regions 425. Alternatively, gate dielectric material 407 may be segmented vertically between isolation regions 425. SGD transistors 404-0, 404-1, 404-2, 404-3, and 404-4 may respectively include gates 405-0, 405-1, 405-2, 405-3, and 405-4 separated from the channel structure 410 by gate dielectric material 407.

[0031] Each gate of SGD transistors 404-0, 404-1, 404-2, 404-3, and 404-4 can be coupled to an SGD select line assigned to each of SGD transistors 404-0, 404-1, 404-2, 404-3, and 404-4. Selectors on the SGD select lines can be coupled together to provide the same voltage to the gate of the corresponding selected SGD transistor. Alternatively, the gates of the SGD transistors are not coupled together. Although... Figure 4 An arrangement 400 with five SGD transistors is shown, but the arrangement 400 may have more or fewer than five SGD transistors.

[0032] Arrangement 400 may include SGD transistors 404-0, 404-1, 404-2, 404-3, and 404-4 formed around dielectric filler 420. In the manufacturing process, dielectric filler 420 may be formed after the SGD transistors are formed. Dielectric filler 420 may include dielectric pad 415 and dielectric region 422. Dielectric pad 415 may be a high-k dielectric pad and dielectric region 422 may be a non-high-k dielectric region. Dielectric pad 415 may extend from above SGD transistor 404-4 to below SGD transistor 404-0. SGD transistor 404-4 is the topmost select-gate transistor among a plurality of select-gate transistors in arrangement 400, and SGD transistor 404-0 is the bottommost transistor in a vertically arranged stack of SGD transistors 404-0, SGD transistor 404-1, SGD transistor 404-2, SGD transistor 404-3, and SGD transistor 404-4. The dielectric pad 415 is formed to have a thickness in the horizontal direction along its length to tune the Vt of all SGD transistors in the stack. The thickness of the dielectric pad 415 is horizontally filled with dielectric filler 420 and positioned to contact dielectric region 422 below the bottommost SGD transistor 404-0 in the stack. This provides a high Vt for all transistors in the stack of SGD transistors 404-0, 404-1, 404-2, 404-3, and 404-4.

[0033] Figure 5The arrangement 500 in the memory device is described. Arrangement 500 has SGD transistors 504-0, 504-1, 504-2, 504-3, and 504-4 vertically positioned above and coupled to the memory cells, wherein the memory cells are arranged above one or more SGD transistors coupled to the source lines of the memory device. The SGD transistors 504-0, 504-1, 504-2, 504-3, and 504-4 arranged in a vertical stack can be coupled to digital lines above the SGD transistors 504-0, 504-1, 504-2, 504-3, and 504-4. The channel structure 510 can be vertically arranged in the stack of SGD transistors 504-0, 504-1, 504-2, 504-3, and 504-4, such that the channel structure 510 provides a transistor channel for the SGD transistors 504-0, 504-1, 504-2, 504-3, and 504-4. An isolation region 525 separates each of the SGD transistors 504-0, 504-1, 504-2, 504-3, and 504-4 from its immediate neighbor. The channel structure 510 can be arranged to extend continuously in the vertical stack of SGD transistors 504-0, 504-1, 504-2, 504-3, and 504-4. Gate dielectric material 507 provides a gate dielectric for each of SGD transistors 504-0, 504-1, 504-2, 504-3, and 504-4. Gate dielectric material 507 may be arranged to extend continuously in a vertical stack of SGD transistors 504-0, 504-1, 504-2, 504-3, and 504-4, vertically contacting isolation regions 525. Alternatively, gate dielectric material 507 may be segmented and vertically located between isolation regions 525. SGD transistors 504-0, 504-1, 504-2, 504-3, and 504-4 may respectively include gates 505-0, 505-1, 505-2, 505-3, and 505-4 separated from the channel structure 510 by gate dielectric material 507.

[0034] Each gate of SGD transistors 504-0, 504-1, 504-2, 504-3, and 504-4 can be coupled to an SGD select line assigned to each of SGD transistors 504-0, 504-1, 504-2, 504-3, and 504-4. Selectors on the SGD select lines can be coupled together to provide the same voltage to the gate of the corresponding selected SGD transistor. Alternatively, the gates of the SGD transistors are not coupled together. Although... Figure 5 An arrangement 500 with five SGD transistors is shown, but arrangement 500 may have more or fewer than five SGD transistors.

[0035] Arrangement 500 may include SGD transistors 504-0, 504-1, 504-2, 504-3, and 504-4 formed around dielectric filler 520. In the manufacturing process, dielectric filler 520 may be formed after the SGD transistors are formed. Dielectric filler 520 may include dielectric pad 515 and dielectric region 522. Dielectric pad 515 may be a high-k dielectric pad and dielectric region 522 may be a non-high-k dielectric region. Dielectric pad 515 may extend from above SGD transistor 504-4 to below SGD transistor 504-0, SGD transistor 504-4 being the topmost select-gate transistor among a plurality of select-gate transistors in arrangement 500, and SGD transistor 504-0 being the bottommost transistor in a vertically arranged stack of SGD transistors 504-0, SGD transistor 504-1, SGD transistor 504-2, SGD transistor 504-3, and SGD transistor 504-4. The dielectric pad 515 may be formed to have a thin or thick thickness, without filling the dielectric filler 520 in the horizontal direction. The dielectric region 522 may be formed such that the dielectric pad 515 is above the dielectric region 522 and the dielectric pad 515 separates the SGD transistor from the dielectric region 522 along the dielectric pad 515. The Vt of all SDG transistors is tuned by forming a dielectric pad 515 with a specific thickness. The Vt of the SGD transistor can be tuned by changing the thickness of the dielectric pad 515 without filling the dielectric filler 520 with the dielectric pad 515.

[0036] Figure 6The arrangement 600 in the memory device is described. Arrangement 600 has SGD transistors 604-0, 604-1, 604-2, 604-3, and 604-4 vertically positioned above and coupled to the memory cells, wherein the memory cells are arranged above one or more SGD transistors coupled to the source lines of the memory device. The SGD transistors 604-0, 604-1, 604-2, 604-3, and 604-4 arranged in a vertical stack can be coupled to digital lines above the SGD transistors 604-0, 604-1, 604-2, 604-3, and 604-4. The channel structure 610 can be vertically arranged in the stack of SGD transistors 604-0, 604-1, 604-2, 604-3, and 604-4, such that the channel structure 610 provides a transistor channel for the SGD transistors 604-0, 604-1, 604-2, 604-3, and 604-4. An isolation region 625 separates each of the SGD transistors 604-0, 604-1, 604-2, 604-3, and 604-4 from its immediate neighbor. The channel structure 610 can be arranged to extend continuously in the vertical stack of SGD transistors 604-0, 604-1, 604-2, 604-3, and 604-4. Gate dielectric material 607 provides a gate dielectric for each of SGD transistors 604-0, 604-1, 604-2, 604-3, and 604-4. Gate dielectric material 607 may be arranged to extend continuously in a vertical stack of SGD transistors 604-0, 604-1, 604-2, 604-3, and 604-4, vertically contacting isolation regions 625. Alternatively, gate dielectric material 607 may be segmented vertically located between isolation regions 625. SGD transistors 604-0, 604-1, 604-2, 604-3, and 604-4 may respectively include gates 605-0, 605-1, 605-2, 605-3, and 605-4 separated from the channel structure 610 by gate dielectric material 607. SGD transistors 604-0, 604-1, 604-2, 604-3, and 604-4 can be structured to provide a Vt sequence configuration in a stack of SGD transistors 604-0, 604-1, 604-2, 604-3, and 604-4. The configuration can be a medium, high, or low Vt sequence.

[0037] Each gate of SGD transistors 604-0, 604-1, 604-2, 604-3, and 604-4 can be coupled to an SGD select line assigned to each of SGD transistors 604-0, 604-1, 604-2, 604-3, and 604-4. Selectors on the SGD select lines can be coupled together to provide the same voltage to the gate of the corresponding selected SGD transistor. Alternatively, the gates of the SGD transistors are not coupled together. Although... Figure 6 An arrangement 600 with five SGD transistors is shown, but arrangement 600 may have more or fewer than five SGD transistors.

[0038] Arrangement 600 may include SGD transistors 604-0, 604-1, 604-2, 604-3, and 604-4 formed around dielectric filler 620. In the manufacturing process, dielectric filler 620 may be formed after the SGD transistors are formed. Dielectric filler 620 may include dielectric pad 615 and dielectric region 622. Dielectric pad 615 may be a high-k dielectric pad and dielectric region 622 may be a non-high-k dielectric region. Dielectric pad 615 may extend from above SGD transistor 604-2 and below SGD transistor 604-1, SGD transistor 604-2 being the intermediate SGD transistor among a plurality of SGD transistors in arrangement 600, and SGD transistor 604-1 being the intermediate SGD transistor above the bottommost SGD transistor 604-0 in the stack. Dielectric pad 615 may be formed to have a thickness that fills dielectric filler 620 in the horizontal direction. Dielectric region 622 may be formed on and in contact with dielectric pad 615, and may also be formed below and in contact with dielectric pad 615. The Vt of SGD transistors 604-1 and 604-2 is tuned to high Vt. The Vt of SGD transistors 604-3 and 604-4 may be tuned to medium Vt via a tuning mechanism adjacent to the doped channel structure 610 of SGD transistors 604-3 and 604-4 or without using a high-k dielectric pad (e.g., dielectric pad 615). The Vt of SGD transistor 604-0 may be tuned to low Vt via a tuning mechanism adjacent to the doped channel structure 610 of SGD transistor 604-0 or without using a high-k dielectric pad (e.g., dielectric pad 615). Doping may be performed prior to the formation of dielectric pad 615. Various Vt-tuning doping may include, but is not limited to, boron doping.

[0039] Figure 7The arrangement 700 in the memory device is described. Arrangement 700 has SGD transistors 704-0, 704-1, 704-2, 704-3, and 704-4 vertically positioned above and coupled to the memory cells, wherein the memory cells are arranged above one or more SGD transistors coupled to the source lines of the memory device. The SGD transistors 704-0, 704-1, 704-2, 704-3, and 704-4 arranged in a vertical stack can be coupled to digital lines above the SGD transistors 704-0, 704-1, 704-2, 704-3, and 704-4. The channel structure 710 can be vertically arranged in a stack of SGD transistors 704-0, 704-1, 704-2, 704-3, and 704-4, such that the channel structure 710 provides transistor channels for the SGD transistors 704-0, 704-1, 704-2, 704-3, and 704-4. An isolation region 725 separates each of the SGD transistors 704-0, 704-1, 704-2, 704-3, and 704-4 from its immediate neighbor. The channel structure 710 can be arranged to extend continuously in the vertical stack of SGD transistors 704-0, 704-1, 704-2, 704-3, and 704-4. Gate dielectric material 707 provides a gate dielectric for each of SGD transistors 704-0, 704-1, 704-2, 704-3, and 704-4. Gate dielectric material 707 may be arranged to extend continuously vertically in contact with isolation region 725 in a vertical stack of SGD transistors 704-0, 704-1, 704-2, 704-3, and 704-4. Alternatively, gate dielectric material 707 may be segmented vertically located between isolation regions 725. SGD transistors 704-0, 704-1, 704-2, 704-3, and 704-4 may respectively include gates 705-0, 705-1, 705-2, 705-3, and 705-4 separated from the channel structure 710 by gate dielectric material 707. SGD transistors 704-0, 704-1, 704-2, 704-3, and 704-4 can be structured to provide a Vt sequence configuration in a stack of SGD transistors 704-0, 704-1, 704-2, 704-3, and 704-4. The configuration can be a medium, high, or low Vt sequence.

[0040] Each gate of SGD transistors 704-0, 704-1, 704-2, 704-3, and 704-4 can be coupled to an SGD select line assigned to each of SGD transistors 704-0, 704-1, 704-2, 704-3, and 704-4. Selectors on the SGD select lines can be coupled together to provide the same voltage to the gate of the corresponding selected SGD transistor. Alternatively, the gates of the SGD transistors are not coupled together. Although... Figure 7 An arrangement 700 with five SGD transistors is shown, but arrangement 700 may have more or fewer than five SGD transistors.

[0041] Arrangement 700 may include SGD transistors 704-0, 704-1, 704-2, 704-3, and 704-4 formed around dielectric filler 720. In the manufacturing process, dielectric filler 720 may be formed after the SGD transistors are formed. Dielectric filler 720 may include dielectric pad 715 and dielectric region 722. Dielectric pad 715 may be a high-k dielectric pad and dielectric region 722 may be a non-high-k dielectric region. Dielectric pad 715 may extend from above SGD transistor 704-2 and below SGD transistor 704-1, SGD transistor 704-2 being the intermediate SGD transistor among a plurality of SGD transistors in arrangement 700, and SGD transistor 704-1 being the intermediate SGD transistor above the bottommost SGD transistor 704-0 in the stack. Dielectric pad 715 may be formed to have a thin thickness that fills dielectric filler 720 in the horizontal direction. Dielectric region 722 may be formed on and in contact with dielectric pad 715, and may also be formed below and in contact with dielectric pad 715. Dielectric region 722 may also be formed separately from SGD transistors 704-1 and 704-2 via dielectric pad 715. The Vt of SGD transistors 704-1 and 704-2 is tuned to a high Vt. The Vt of SGD transistors 704-3 and 704-4 may be tuned to a medium Vt via a tuning mechanism adjacent to the doped channel structure 710 of SGD transistors 704-3 and 704-4 or without using a high-k dielectric pad (e.g., dielectric pad 715). The Vt of the SGD transistor 704-0 can be tuned to a low Vt by means of a doped channel structure 710 adjacent to the SGD transistor 704-0 or by other tuning mechanisms that do not use a high-k dielectric pad (e.g., dielectric pad 715). Doping can be performed before the dielectric pad 715 is formed. Various Vt-tuning doping may include, but is not limited to, boron doping.

[0042] Figure 8The arrangement 800 in the memory device is described. The arrangement 800 has SGD transistors 804-0, 804-1, 804-2, 804-3, and 804-4 vertically positioned above and coupled to the memory cells, wherein the memory cells are arranged above one or more SGD transistors coupled to the source lines of the memory device. The SGD transistors 804-0, 804-1, 804-2, 804-3, and 804-4 arranged in a vertical stack can be coupled to digital lines above the SGD transistors 804-0, 804-1, 804-2, 804-3, and 804-4. The channel structure 810 can be vertically arranged in a stack of SGD transistors 804-0, 804-1, 804-2, 804-3, and 804-4, such that the channel structure 810 provides a transistor channel for the SGD transistors 804-0, 804-1, 804-2, 804-3, and 804-4. An isolation region 825 separates each of the SGD transistors 804-0, 804-1, 804-2, 804-3, and 804-4 from its immediate neighbor. The channel structure 810 can be arranged to extend continuously in the vertical stack of SGD transistors 804-0, 804-1, 804-2, 804-3, and 804-4. Gate dielectric material 807 provides a gate dielectric for each of SGD transistors 804-0, 804-1, 804-2, 804-3, and 804-4. Gate dielectric material 807 may be arranged to extend continuously in a vertical stack of SGD transistors 804-0, 804-1, 804-2, 804-3, and 804-4, vertically contacting isolation regions 825. Alternatively, gate dielectric material 807 may be segmented vertically located between isolation regions 825. SGD transistors 804-0, 804-1, 804-2, 804-3, and 804-4 may respectively include gates 805-0, 805-1, 805-2, 805-3, and 805-4 separated from the channel structure 810 by gate dielectric material 807. SGD transistors 804-0, 804-1, 804-2, 804-3, and 804-4 can be structured to provide a Vt sequence configuration in a stack of SGD transistors 804-0, 804-1, 804-2, 804-3, and 804-4. The configuration can be a medium, high, or low Vt sequence.

[0043] Each gate of SGD transistors 804-0, 804-1, 804-2, 804-3, and 804-4 can be coupled to an SGD select line assigned to each of SGD transistors 804-0, 804-1, 804-2, 804-3, and 804-4. Selectors on the SGD select lines can be coupled together to provide the same voltage to the gate of the corresponding selected SGD transistor. Alternatively, the gates of the SGD transistors are not coupled together. Although... Figure 8 An arrangement 800 with five SGD transistors is shown, but the arrangement 800 may have more or fewer than five SGD transistors.

[0044] Arrangement 800 may include SGD transistors 804-0, 804-1, 804-2, 804-3, and 804-4 formed around dielectric filler 820. In the manufacturing process, dielectric filler 820 may be formed after the SGD transistors are formed. Dielectric filler 820 may include dielectric pad 815 and dielectric region 822. Dielectric pad 815 may be a high-k dielectric pad and dielectric region 822 may be a non-high-k dielectric region. Dielectric pad 815 may extend from above SGD transistor 804-2 and below SGD transistor 804-1, SGD transistor 804-2 being the intermediate SGD transistor among a plurality of SGD transistors in arrangement 800, and SGD transistor 804-1 being the intermediate SGD transistor above the bottommost SGD transistor 804-0 in the stack. Dielectric pad 815 may be formed to have a thin thickness that fills dielectric filler 820 in the horizontal direction. Dielectric region 822 may be formed on and in contact with dielectric pad 815, and may also be formed below and in contact with dielectric pad 815. Dielectric region 822 may also be formed separately from SGD transistors 804-1 and 804-2 via dielectric pad 815. The Vt of SGD transistors 804-1 and 804-2 is tuned to high Vt. The Vt of SGD transistors 804-3 and 804-4 may be tuned to medium Vt via adjacent doped channel structures 810 of SGD transistors 804-3 and 804-4 or via other tuning mechanisms that do not use a high-k dielectric pad (e.g., dielectric pad 815). The Vt of the SGD transistor 804-0 can be tuned to a low Vt by means of a doped channel structure 810 adjacent to the SGD transistor 804-0 or by other tuning mechanisms that do not use a high-k dielectric pad (e.g., dielectric pad 815). Doping can be performed before the dielectric pad 815 is formed. Various Vt-tuning doping may include, but is not limited to, boron doping.

[0045] Figure 9This is a flowchart illustrating an embodiment of a method 900 for forming a memory device having one or more select-gate transistors with tuning threshold voltages therein. At 910, a plurality of select-gate transistors are formed in a stack of memory cell strings of the memory device, arranged vertically. At 920, a channel structure extending vertically in the stack is formed, wherein the channel structure is arranged as a transistor channel structure for each of the plurality of select-gate transistors. At 930, a dielectric pad is formed adjacent to and contacting the transistor channel structure of one or more of the plurality of select-gate transistors, wherein the dielectric pad is structured relative to the channel structure to provide a configuration of one or more of the plurality of select-gate transistors, including high threshold voltage select-gate transistors, medium threshold voltage select-gate transistors, or low threshold voltage select-gate transistors. The dielectric pad may be at least a portion of the dielectric filler formed around the channel structure. The dielectric pad may comprise a high-k dielectric material, wherein the dielectric pad has a thickness extending from the channel structure and a length along the channel structure.

[0046] Variations of method 900, or methods similar to method 900, may include several different embodiments depending on the application of such methods or the combination of architectures or process flows for integrated circuits implementing such methods. Such methods may include forming dielectric pads adjacent to each of a plurality of select-gate transistors; that is, dielectric pads may be formed adjacent to and contacting all of the plurality of select-gate transistors. In other arrangements, dielectric pads may be formed adjacent to and contacting selected groups of the plurality of select-gate transistors to achieve tuning of the plurality of select-gate transistors for a specific threshold voltage sequence.

[0047] Variations of method 900 or methods similar to method 900 may include forming a plurality of select-gate transistors having a memory cell structure. Alternatively, the plurality of select-gate transistors may be formed as MOSFET transistors. The channel structure may be structured around a dielectric filler, wherein the dielectric filler includes a dielectric pad and a dielectric region below the bottommost select-gate transistor of the plurality of select-gate transistors, wherein the dielectric region may be a non-high-k dielectric. An example of a non-high-k dielectric that may be formed is silicon oxide.

[0048] Figure 10This is a flowchart of an embodiment of a method 1000 for forming a memory device having a plurality of select-gate transistors having a selected threshold voltage sequence. At 1010, a plurality of select-gate transistors are formed in a stack of memory cell strings arranged vertically. At 1020, a channel structure extending vertically in the stack is formed, wherein the channel structure is arranged as a transistor channel structure for each of the plurality of select-gate transistors. At 1030, a dielectric pad is formed adjacent to and contacting the transistor channel structure of one or more of the plurality of select-gate transistors, wherein the dielectric pad comprises a high-k dielectric material and has a thickness from the beginning of the channel structure and a length along the channel structure to provide one or more threshold voltage values ​​for the plurality of select-gate transistors.

[0049] Variations of method 1000, or methods similar to method 1000, may include several different embodiments of the architecture or process flow combination for the application of such methods or for implementing such methods of integrated circuits. Such variations may include, but are not limited to, forming high-k dielectric materials by forming alumina. Other high-k dielectric materials may be used.

[0050] A variation of method 1000 may include a variation in the location of the dielectric pad. The variation may include forming a dielectric pad extending from above the topmost select-gate transistor of a plurality of select-gate transistors to below one or more select-gate transistors in a vertically arranged sequence directly below the topmost select-gate transistor, wherein another one or more select-gate transistors of the plurality of select-gate transistors are below the sequence. The gate of the topmost select-gate transistor and the gates of the one or more select-gate transistors in the sequence may be electrically coupled together. The channel structure may be structured around a dielectric filler, wherein the dielectric filler contains a dielectric pad, and the dielectric pad has a thickness in the horizontal direction equal to or less than one-thirteenth of the radius of the dielectric filler. Other thicknesses may be used. In another configuration, the channel structure may be structured around a dielectric filler, wherein the dielectric filler contains a dielectric pad, and the dielectric pad has a thickness in the horizontal direction greater than one-thirteenth and less than the radius of the dielectric filler. Other thickness ranges may be used. In another configuration, the channel structure may be structured around a dielectric filler containing a dielectric pad, wherein other materials in the dielectric filler do not extend from near the topmost select gate transistor among a plurality of select gate transistors below the select gate transistor sequence.

[0051] A variation of method 1000 may include forming a dielectric pad extending from above the topmost select gate transistor of the plurality of select gate transistors to below the bottommost select gate transistor of the plurality of select gate transistors. The channel structure may be structured around a dielectric filler containing the dielectric pad, wherein other material in the dielectric filler is not above a non-high-k dielectric region. In another configuration, the channel structure may be structured around a dielectric filler containing the dielectric pad, and the dielectric pad having a thickness in the horizontal direction equal to or less than one-thirteenth of the radius of the dielectric filler. Other thicknesses may be used.

[0052] A variation of method 1000 may include a dielectric pad formed in a vertical direction extending downward from below one of the select-gate transistors and above another of the select-gate transistors. The channel structure may be structured around a dielectric filler, wherein the dielectric filler contains the dielectric pad, and the dielectric pad has a thickness in the horizontal direction equal to or less than one-thirteenth of the radius of the dielectric filler. Other thicknesses may be used. In another configuration, the channel structure may be structured around a dielectric filler, wherein the dielectric filler contains the dielectric pad, and the dielectric pad has a thickness in the horizontal direction greater than one-thirteenth and less than the radius of the dielectric filler. Other thickness ranges may be used. In another configuration, the channel structure may be structured around a dielectric filler, wherein the dielectric filler contains the dielectric pad, a first dielectric region on and in contact with the dielectric pad, and a second dielectric region on which the dielectric pad is located. The dielectric pad may have a radius equal to that of the dielectric filler, wherein the first dielectric region and the second dielectric region are non-high-k dielectrics.

[0053] Can be used to form Figures 1 to 8 Various deposition techniques for arranging 100 to 800 components and related Figure 9 and 10The associated methods, techniques, and approaches are typical for the materials formed, the size of the materials formed, and the architecture of the materials formed. Processes used to form various materials may include, but are not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD). PVD may include, but is not limited to, sputtering, ion beam deposition, electron beam evaporation, pulsed laser deposition, and vacuum arc deposition, etc. CVD may include, but is not limited to, plasma chemical vapor deposition and laser chemical vapor deposition, etc. Selective etching and conventional masking techniques may be used to remove selected areas during processing. Selective etching is a process in which one or more materials are removed from a structure, while one or more other materials remain in the structure without being removed or are removed very little. Selective etching can depend on the material to be etched, the materials that will not be etched, the etchant used, and the etching method. Etching processes may include, but are not limited to, wet etching, dry etching, and atomic layer deposition, etc., each of these basic methods comprising several different etching processes.

[0054] Electronic devices (e.g., mobile electronic devices, such as smartphones, tablets, etc.), electronic devices for automotive applications (e.g., automotive sensors, control units, driver assistance systems, passenger safety or comfort systems, etc.), and Internet-connected electrical appliances or devices (e.g., Internet of Things (IoT) devices, etc.) have different storage requirements, depending particularly on the type of electronic device, the usage environment, and performance expectations. Electronic devices can be broken down into several main components: processors (e.g., central processing unit (CPU) or other main processors); memory (e.g., one or more volatile or non-volatile RAM memory devices, such as DRAM, mobile or low-power dual data rate synchronous DRAM (DDR SDRAM, etc.); and storage devices (e.g., non-volatile memory (NVM) devices, such as flash memory, ROM, SSD, MMC, or other memory card structures or assemblies, etc.). In some instances, electronic devices may include a user interface (e.g., a display, touchscreen, keyboard, one or more buttons, etc.), a graphics processing unit (GPU), power management circuitry, a baseband processor, or one or more transceiver circuits, etc.

[0055] Figure 11 A block diagram illustrating an example machine 1100 having one or more memory devices, the memory devices being structured with dielectric pads having channel structures adjacent to and contacting SGD transistors of a memory cell string, wherein the dielectric pads are implemented to tune the Vt of one or more SGD transistors. The machine 1100 having one or more such memory devices can operate as a standalone machine or can be connected (e.g., networked) to other machines.

[0056] In a networked deployment, machine 1100 can operate as a server machine, a client machine, or both in a server-client network environment. In an example, machine 1100 can act as a peer-to-peer (P2P) (or other distributed) network environment. Machine 1100 can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, networked appliance, IoT device, automotive system, or any machine capable of executing instructions (sequentially or otherwise) specifying actions to be taken by that machine. Furthermore, while only a single machine is described, the term "machine" should also be interpreted as encompassing any collection of machines that individually or jointly execute a set (or more) of instructions to perform any of the methodologies discussed herein (e.g., cloud computing, Software as a Service (SaaS), other computer cluster configurations). Example machine 1100 can be arranged to operate with one or more memory devices having pads for tuning the selection gate threshold voltage of one or more SGD transistors as taught herein.

[0057] Machine (e.g., computer system) 1100 may include a hardware processor 1150 (e.g., CPU, GPU, hardware processor core, or any combination thereof), main memory 1154, and static memory 1156, some or all of which may communicate with each other via an interconnect link (e.g., bus) 1158. Machine 1100 may further include a display device 1160, an alphanumeric input device 1162 (e.g., keyboard), and a user interface (UI) navigation device 1164 (e.g., mouse). In an example, the display device 1160, input device 1162, and UI navigation device 1164 may be a touchscreen display. Machine 1100 may additionally include a mass storage device (e.g., drive unit) 1151, a signal generation device 1168 (e.g., speaker), a network interface device 1153, and one or more sensors 1166, such as a Global Positioning System (GPS) sensor, a compass, an accelerometer, or other sensors. Machine 1100 may include output controller 1169, which may be serial (e.g., USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connected to communicate with or control one or more peripheral devices (e.g., printer, card reader, etc.).

[0058] Machine 1100 may include machine-readable media thereon storing one or more sets of data structures or instructions 1155 (e.g., software) embodying or used by machine 1100 to perform one or more technologies or functions (machine 1100 is designed for said technologies or functions). The machine-readable media may include main memory 1154, static memory 1156, or mass storage device 1151. Instructions 1155 may reside wholly or at least partially in main memory 1154, static memory 1156, mass storage device 1151, or hardware processor 1150 during execution by machine 1100.

[0059] Although each of the machine-readable media is described as a single medium, the term "machine-readable media" can include a single medium or multiple media (e.g., a centralized or distributed database, or associated cache and server) configured to store one or more instructions 1155. The term "machine-readable media" can include any medium capable of storing, encoding, or storing instructions for execution by machine 1100 and causing machine 1100 to perform any one or more technologies (machine 1100 is designed for said technologies), or any medium capable of storing, encoding, or storing data structures used by or associated with such instructions. Non-limiting examples of machine-readable media may include solid-state memory, optical and magnetic media, or other tangible structures. Examples of machine-readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., EPROM, EEPROM) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and compact optical disc-ROM (CD-ROM) and digital versatile optical disc read-only memory (DVD-ROM) disks.

[0060] Instructions 1155 (e.g., software, programs, operating systems (OS), etc.) or other data stored on mass storage device 1151 may be accessed by main memory 1154 for use by processor 1150. Main memory 1154 (e.g., DRAM) is typically fast but volatile, and is therefore a different type of storage device from mass storage device 1151 (e.g., SSD), which is suitable for long-term storage, including when in a "shutdown" state. Instructions 1155 or data used by user or machine 1100 are typically loaded into main memory 1154 for use by processor 1150. When main memory 1154 is full, virtual space from mass storage device 1151 can be allocated to supplement main memory 1154; however, because mass storage device 1151 is typically slower than main memory 1154, and its write speed is typically at least half that of its read speed, using virtual memory can significantly degrade the user experience (compared to main memory 1154, such as DRAM) due to storage device latency. Furthermore, using mass storage device 1151 for virtual memory can significantly reduce the available lifespan of mass storage device 1151.

[0061] Storage devices or mobile storage devices optimized for mobile electronic devices traditionally include MMC solid-state storage devices (e.g., microSD cards). TM (e.g., cards, etc.) MMC devices contain several parallel interfaces (e.g., 8-bit parallel interfaces) with the host device and are typically removable and separable components from the host device. In contrast, eMMC... TM The device, attached to a circuit board and considered a component of the host device, boasts read speeds comparable to SATA-based SSDs. However, the demand for mobile device performance continues to grow, for example, to fully enable virtual or augmented reality devices and leverage ever-increasing network speeds. In response to this demand, storage devices have transitioned from parallel communication interfaces to serial communication interfaces. UFS devices (including the controller and firmware) communicate with the host device using a Low Voltage Differential Signaling (LVDS) serial interface with dedicated read / write paths, further enhancing read / write speeds.

[0062] Several transmission protocols (e.g., Frame Relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.) can be used via network interface device 1153 to further transmit or receive instructions 1155 through communication network 1159 using transmission media. Example communication networks may include local area networks (LANs), wide area networks (WANs), packet data networks (e.g., the Internet), mobile phone networks (e.g., cellular networks), conventional telephone (POTS) networks, and wireless data networks (e.g., referred to as…). The Institute of Electrical and Electronics Engineers (IEEE) 802.11 family of standards, known as (e.g., IEEE 802.16 family of standards, IEEE 802.15.4 family of standards, peer-to-peer (P2P) networks, etc.). In an example, network interface device 1153 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas for connection to communication network 1159. In an example, network interface device 1153 may include multiple antennas for wireless communication using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technologies. The term "transmission medium" should be interpreted as including any tangible medium capable of carrying instructions to and executed by machine 1100, and including means for transmitting digital or analog communication signals to facilitate the communication of such instructions, which may be implemented by software.

[0063] The following are exemplary embodiments based on the apparatus and methods taught herein.

[0064] An example memory device 1 may include: a plurality of select-gate transistors vertically arranged in a stack to a string of memory cells; a channel structure extending vertically in the stack, the channel structure being arranged as a transistor channel structure for each of the plurality of select-gate transistors; and a dielectric pad adjacent to and contacting the transistor channel structure of one or more of the plurality of select-gate transistors, the dielectric pad being structured relative to the channel structure to provide a configuration of one or more of the plurality of select-gate transistors being high threshold voltage select-gate transistors, medium threshold voltage select-gate transistors, or low threshold voltage select-gate transistors.

[0065] Example memory device 2 may include the features described in example memory device 1 and may include the dielectric pad comprising a high-k dielectric material.

[0066] Example memory device 3 may include the features described in any of the aforementioned example memory devices and may include the channel structure structured around a dielectric filler, the dielectric filler including the dielectric pad and a dielectric region below the bottommost select gate transistor of the plurality of select gate transistors, the dielectric region being a non-high-k dielectric.

[0067] In instance memory device 4, any one of instance memory devices 1 to 3 may include components incorporated into an electronic device, the electronic device further including one or more host processors and a communication bus extending between the one or more host processors and the memory device.

[0068] In instance memory device 5, any of instance memory devices 1 to 4 may be modified to include any structure presented in another instance memory device among instance memory devices 1 to 4.

[0069] In instance memory device 6, any device associated with the memory devices in instance memory devices 1 to 5 may further include a machine-readable storage device configured to store instructions as a physical state, wherein the instructions may be used to perform one or more operations of the device.

[0070] In instance memory device 7, any one of instance memory devices 1 to 6 can be operated according to any one of the instance methods 1 to 17 below.

[0071] An example memory device 8 may include: a plurality of select-gate transistors vertically arranged in a stack to a string of memory cells; a channel structure extending vertically in the stack, the channel structure being arranged as a transistor channel structure for each of the plurality of select-gate transistors; and a dielectric pad adjacent to and contacting the transistor channel structure of one or more of the plurality of select-gate transistors, the dielectric pad comprising a high-k dielectric material, the dielectric pad having a thickness originating from the channel structure and a length along the channel structure to provide one or more threshold voltage values ​​for the plurality of select-gate transistors.

[0072] Example memory device 9 may include the features described in example memory device 8 and may include the high-k dielectric material comprising aluminum oxide.

[0073] Example memory device 10 may include the features described in any of the example memory devices 8 to 9 above and may include the dielectric pad extending from above the topmost select gate transistor of the plurality of select gate transistors to below one or more select gate transistors in a vertically arranged sequence of select gate transistors directly below the topmost select gate transistor, wherein another or more select gate transistors of the plurality of select gate transistors are below the sequence.

[0074] Instance memory device 11 may include the features described in any of the instance memory devices 8 to 10 described above and may include the gate of the topmost select gate transistor and the gates of the one or more select gate transistors in the sequence electrically coupled together.

[0075] Instance memory device 12 may include the features described in instance memory device 10 and any of the aforementioned instance memory devices 8 to 9 or 11, and may include the channel structure structured around a dielectric filler containing the dielectric pad, the dielectric pad having a thickness in the horizontal direction equal to or less than one-thirteenth of the radius of the dielectric filler.

[0076] Instance memory device 13 may include the features described in instance memory device 10 and any of the aforementioned instance memory devices 8 to 9 or 11 to 12, and may include the channel structure structured around a dielectric filler containing the dielectric pad, the dielectric pad having a thickness in the horizontal direction greater than one-thirteenth of the radius of the dielectric filler and less than the radius of the dielectric filler.

[0077] Instance memory device 14 may include the features described in instance memory device 10 and any of the aforementioned instance memory devices 8 to 9 or 11 to 13, and may include the channel structure structured around a dielectric filler containing the dielectric pad, wherein other materials in the dielectric filler do not extend from the vicinity of the topmost select gate transistor of the plurality of select gate transistors below the select gate transistor sequence.

[0078] Example memory device 15 may include the features described in any of the example memory devices 8 to 14 described above, and may include the dielectric pad extending from above the topmost select gate transistor of the plurality of select gate transistors below the bottommost select gate transistor of the plurality of select gate transistors.

[0079] Instance memory device 16 may include the features described in instance memory device 15 and any of the aforementioned instance memory devices 8 to 14, and may include the channel structure structured around a dielectric filler containing the dielectric pad, wherein other materials in the dielectric filler are not above a non-high-k dielectric region.

[0080] Instance memory device 17 may include features according to instance memory device 15 and any of the aforementioned instance memory devices 8 to 14 or instance memory device 16, and may include the channel structure structured around a dielectric filler containing the dielectric pad having a thickness in the horizontal direction equal to or less than one-thirteenth of the radius of the dielectric filler.

[0081] Example memory device 18 may include the features described in any of the example memory devices 8 to 17 described above, and may include the dielectric pad extending vertically from below one of the select gate transistors and above another of the select gate transistors.

[0082] Instance memory device 19 may include features according to instance memory device 18 and any of the aforementioned instance memory devices 8 to 17 and may include the channel structure structured around a dielectric filler containing the dielectric pad having a thickness in the horizontal direction equal to or less than one-thirteenth of the radius of the dielectric filler.

[0083] Instance memory device 20 may include the features described in instance memory device 19 and any of the aforementioned instance memory devices 8 to 18, and may include the channel structure structured around a dielectric filler containing the dielectric pad, the dielectric pad having a thickness in the horizontal direction greater than one-thirteenth of the radius of the dielectric filler and less than the radius of the dielectric filler.

[0084] Instance memory device 21 may include features according to instance memory device 20 and any of the aforementioned instance memory devices 8 to 19, and may include the channel structure structured around a dielectric filler, the dielectric filler including the dielectric pad, a first dielectric region on and in contact with the dielectric pad, and a second dielectric region on the dielectric pad, the dielectric pad having a radius equal to the radius of the dielectric filler, the first dielectric region and the second dielectric region being non-high-k dielectrics.

[0085] In instance memory device 22, any one of instance memory devices 8 to 21 may include a memory device incorporated in an electronic device, the electronic device further including a host processor or memory controller and a communication bus extending between the host processor / memory controller and the memory device.

[0086] In instance memory device 23, any of instance memory devices 8 to 22 may be modified to include the structure presented in another instance memory device among instance memory devices 1 to 7.

[0087] In instance memory device 24, any device associated with the memory devices in instance memory devices 8 to 23 may further include a machine-readable storage device configured to store instructions as physical state, wherein the instructions may be used to perform one or more operations of the device.

[0088] In instance memory device 25, any one of instance memory devices 8 to 24 can be operated according to any one of the instance methods 1 to 17 below.

[0089] An example method 1 may include: forming a plurality of select gate transistors vertically arranged in a stack to a string of memory cells; forming a channel structure extending vertically in the stack, the channel structure being arranged as a transistor channel structure for each of the plurality of select gate transistors; and forming a dielectric pad adjacent to and contacting the transistor channel structure of one or more of the plurality of select gate transistors, the dielectric pad being structured relative to the channel structure to provide a configuration of one or more of the plurality of select gate transistors being high threshold voltage select gate transistors, medium threshold voltage select gate transistors, or low threshold voltage select gate transistors.

[0090] Example method 2 may include the features described in example method 1 and may include the dielectric pad forming adjacent to each of the plurality of select gate transistors.

[0091] Example method 3 may include the features described in any of the foregoing example methods and may include the plurality of select gate transistors forming a memory cell structure.

[0092] In Example Method 4, any one of Example Methods 1 to 3 can be executed in an electronic device, which further includes a host processor and a communication bus extending between the host processor and the storage system.

[0093] In instance method 5, any of instance methods 1 through 4 may be modified to include the operations described in any of the other instance methods 1 through 4.

[0094] In instance method 6, any of instance methods 1 to 5 may be implemented at least in part by using instructions stored as physical state in one or more machine-readable storage devices.

[0095] Example method 7 may include the features described in any of the example methods 1 to 6 above and may include functions that perform any of the features described in the example memory devices 1 to 25.

[0096] An example method 8 may include: forming a plurality of select-gate transistors vertically arranged in a stack to a string of memory cells; forming a channel structure extending vertically in the stack, the channel structure being arranged as a transistor channel structure for each of the plurality of select-gate transistors; and forming a dielectric pad adjacent to and contacting the transistor channel structure of one or more of the plurality of select-gate transistors, the dielectric pad comprising a high-k dielectric material, the dielectric pad having a thickness from the start of the channel structure and a length along the channel structure to provide one or more values ​​of threshold voltage for the plurality of select-gate transistors.

[0097] Example method 9 may include the features described in example method 8 and may include forming the high-k dielectric material to include forming aluminum oxide.

[0098] Example method 10 may include the features described in any of the example methods 8 to 9 above and may include forming the dielectric pad extending from above the topmost select gate transistor of the plurality of select gate transistors to below one or more select gate transistors in a vertically arranged sequence of select gate transistors directly below the topmost select gate transistor, wherein another or more select gate transistors of the plurality of select gate transistors are below the sequence.

[0099] Example method 11 may include the features described in example method 10 and any of the preceding example methods 8 to 9, and may include electrically coupling the gate of the topmost select gate transistor and the gates of the one or more select gate transistors in the sequence together.

[0100] Example method 12 may include the features described in example method 10 and any of the preceding example methods 8 to 9 or 11, and may include structuring the channel structure around a dielectric filler, the dielectric filler containing the dielectric pad, the dielectric pad having a thickness in the horizontal direction equal to or less than one-thirteenth of the radius of the dielectric filler.

[0101] Example method 13 may include the features described in example method 10 and any of the preceding example methods 8 to 9 or 11 to 12, and may include structuring the channel structure around a dielectric filler, the dielectric filler containing the dielectric pad, the dielectric pad having a thickness in the horizontal direction greater than one-third of the radius of the dielectric filler and less than the radius of the dielectric filler.

[0102] Example method 14 may include the features described in example method 10 and any of the preceding example methods 8 to 9 or 11 to 13, and may include structuring the channel structure around a dielectric filler containing the dielectric pad, wherein other materials in the dielectric filler do not extend from the vicinity of the topmost select gate transistor of the plurality of select gate transistors below the select gate transistor sequence.

[0103] Example method 15 may include the features described in any of the example methods 8 to 14 above and may include forming the dielectric pad extending from above the topmost select gate transistor of the plurality of select gate transistors to below the bottommost select gate transistor of the plurality of select gate transistors.

[0104] Example method 16 may include the features described in example method 15 and any of the preceding example methods 8 to 14, and may include structuring the channel structure around a dielectric filler containing the dielectric pad, wherein other materials in the dielectric filler are not above a non-high-k dielectric region.

[0105] Example method 17 may include the features described in example method 15 and any of the preceding example methods 8 to 14 or 16, and may include structuring the channel structure around a dielectric filler, the dielectric filler containing the dielectric pad, the dielectric pad having a thickness in the horizontal direction equal to or less than one-thirteenth of the radius of the dielectric filler.

[0106] Example method 18 may include the features described in any of the example methods 8 to 17 above and may include the dielectric pad formed in a vertical direction extending downward from below one of the selection gate transistors and above another of the selection gate transistors.

[0107] Example method 19 may include the features described in example method 18 and any of the preceding example methods 8 to 17, and may include structuring the channel structure around a dielectric filler, the dielectric filler containing the dielectric pad having a thickness in the horizontal direction equal to or less than one-thirteenth of the radius of the dielectric filler.

[0108] Example method 20 may include the features described in example method 18 and any of the preceding example methods 8 to 17 or 19, and may include structuring the channel structure around a dielectric filler, the dielectric filler containing the dielectric pad, the dielectric pad having a thickness in the horizontal direction greater than one-thirteenth of the radius of the dielectric filler and less than the radius of the dielectric filler.

[0109] Example method 21 may include the features described in example method 18 and any of the preceding example methods 8 to 17 or 19 to 20, and may include structuring the channel structure around a dielectric filler, the dielectric filler including the dielectric pad, a first dielectric region on and in contact with the dielectric pad, and a second dielectric region on the dielectric pad, the dielectric pad having a radius equal to the radius of the dielectric filler, the first dielectric region and the second dielectric region being non-high-k dielectrics.

[0110] In example method 22, any of example methods 8 to 21 can be executed in an electronic device, the electronic device further including a host processor and a communication bus extending between the host processor and a memory system.

[0111] In instance method 23, any of the instance methods 8 through 22 may be modified to include the operations described in any of the other instance methods 8 through 22.

[0112] In instance method 24, any of instance methods 8 to 23 may be implemented at least in part by using instructions stored as physical state in one or more machine-readable storage devices.

[0113] Example method 25 may include the features described in any of the example methods 8 to 24 described above and may include functions that perform any of the features described in the example memory devices 1 to 25.

[0114] An example machine-readable storage device storing instructions that, when executed by one or more processors, cause a machine to perform operations, may include instructions for performing functions associated with any of the features described in example memory devices 1 to 25 or for performing methods associated with any of the features described in example methods 1 to 25.

[0115] Although specific embodiments have been described and illustrated herein, those skilled in the art will understand that any arrangement intended to achieve the same purpose may replace the specific embodiments shown. Various embodiments utilize arrangements and / or combinations of the embodiments described herein. The foregoing description is intended to be illustrative and not restrictive, and the terminology used herein is for descriptive purposes. Furthermore, it will be apparent from the foregoing detailed description that various features have been grouped together in a single embodiment for the purpose of simplifying this disclosure. Combinations of the foregoing embodiments with other embodiments will be readily apparent to those skilled in the art upon studying the foregoing description.

Claims

1. A memory device comprising: Multiple select gate transistors are vertically arranged in a stack to a memory cell string; A channel structure extending vertically in the stack, the channel structure being arranged as a transistor channel structure for each of the plurality of select-gate transistors; and A dielectric pad, adjacent to and contacting the transistor channel structure of one or more of the plurality of select gate transistors, the dielectric pad being structured relative to the channel structure to provide a configuration of one or more of the plurality of select gate transistors, a high threshold voltage select gate transistor, a medium threshold voltage select gate transistor, or a low threshold voltage select gate transistor.

2. The memory device of claim 1, wherein the dielectric pad comprises a high-k dielectric material.

3. The memory device of claim 1, wherein the channel structure is structured around a dielectric filler, the dielectric filler including the dielectric pad and a dielectric region below the bottommost select gate transistor of the plurality of select gate transistors, the dielectric region being a non-high-k dielectric.

4. A memory device comprising: Multiple select gate transistors are vertically arranged in a stack to a memory cell string; A channel structure extending vertically in the stack, the channel structure being arranged as a transistor channel structure for each of the plurality of select-gate transistors; and A dielectric pad, adjacent to and in contact with the transistor channel structure of one or more of the plurality of select-gate transistors, the dielectric pad comprising a high-k dielectric material, the dielectric pad having a thickness extending from the channel structure and a length along the channel structure to provide one or more threshold voltage values ​​for the plurality of select-gate transistors.

5. The memory device of claim 4, wherein the high-k dielectric material comprises aluminum oxide.

6. The memory device of claim 4, wherein the dielectric pad extends from above the topmost select gate transistor of the plurality of select gate transistors to below one or more select gate transistors in a vertically arranged sequence of select gate transistors directly below the topmost select gate transistor, wherein another or more select gate transistors of the plurality of select gate transistors are below the sequence.

7. The memory device of claim 6, wherein the gate of the topmost select gate transistor and the gates of the one or more select gate transistors in the sequence are electrically coupled together.

8. The memory device of claim 6, wherein the channel structure is structured around a dielectric filler, the dielectric filler including the dielectric pad, the dielectric pad having a thickness in the horizontal direction equal to or less than one-thirteenth of the radius of the dielectric filler.

9. The memory device of claim 6, wherein the channel structure is structured around a dielectric filler, the dielectric filler including the dielectric pad, the dielectric pad having a thickness in the horizontal direction greater than one-third the radius of the dielectric filler and less than the radius of the dielectric filler.

10. The memory device of claim 6, wherein the channel structure is structured around a dielectric filler containing the dielectric pad, and other materials in the dielectric filler do not extend from near the topmost select gate transistor of the plurality of select gate transistors below the select gate transistor sequence.

11. The memory device of claim 4, wherein the dielectric pad extends from above the topmost select gate transistor of the plurality of select gate transistors to below the bottommost select gate transistor of the plurality of select gate transistors.

12. The memory device of claim 11, wherein the channel structure is structured around a dielectric filler containing the dielectric pad, and other materials in the dielectric filler are not above a non-high-k dielectric region.

13. The memory device of claim 11, wherein the channel structure is structured around a dielectric filler, the dielectric filler including the dielectric pad, the dielectric pad having a thickness in the horizontal direction equal to or less than one-thirteenth of the radius of the dielectric filler.

14. The memory device of claim 4, wherein the dielectric pad extends vertically from below one of the select gate transistors and above another of the select gate transistors.

15. The memory device of claim 14, wherein the channel structure is structured around a dielectric filler, the dielectric filler including the dielectric pad, the dielectric pad having a thickness in the horizontal direction equal to or less than one-thirteenth of the radius of the dielectric filler.

16. The memory device of claim 14, wherein the channel structure is structured around a dielectric filler, the dielectric filler including the dielectric pad, the dielectric pad having a thickness in the horizontal direction greater than one-thirteenth the radius of the dielectric filler and less than the radius of the dielectric filler.

17. The memory device of claim 14, wherein the channel structure is structured around a dielectric filler, the dielectric filler comprising the dielectric pad, a first dielectric region on and in contact with the dielectric pad, and a second dielectric region on which the dielectric pad is located, the dielectric pad having a radius equal to the radius of the dielectric filler, the first dielectric region and the second dielectric region being non-high-k dielectrics.

18. A method comprising: Multiple selection gate transistors are formed in a stack and vertically arranged into a string of memory cells; A vertically extending channel structure is formed in the stack, the channel structure being arranged as the transistor channel structure of each of the plurality of select-gate transistors; and A dielectric pad is formed adjacent to and in contact with the transistor channel structure of one or more of the plurality of select gate transistors, the dielectric pad being structured relative to the channel structure to provide a configuration of one or more of the plurality of select gate transistors, including high threshold voltage select gate transistors, medium threshold voltage select gate transistors, or low threshold voltage select gate transistors.

19. The method of claim 18, wherein the method comprises forming the dielectric pad adjacent to each of the plurality of select gate transistors.

20. The method of claim 18, wherein the method comprises forming the plurality of select-gate transistors having a memory cell structure.

Images