Memory device, operating method thereof, and memory system

Abstract

The embodiment of the invention discloses a memory device, an operation method of the memory device and a memory system. The memory device comprises a memory cell array and a peripheral circuit coupled with the memory cell array. The memory cell array comprises at least one first memory block and a plurality of second memory blocks, and part of the plurality of second memory blocks are taken as sampling memory blocks; the peripheral circuit is configured to: perform an erase operation on the sampled memory block; and recording the number of erasure times of the sampling storage block in the first storage block.

Description

Technical Field

[0001] This disclosure relates to semiconductor technology, and specifically to, but is not limited to, a memory device and its operating method, and a memory system. Background Technology

[0002] Technological Breakthroughs and Innovations in Memory: With the rapid development of information technology, memory technology is also constantly breaking through and innovating. Memory is a crucial component of computer systems, responsible for storing and retrieving data, directly affecting computer performance and user experience. Over the past few decades, memory has undergone many significant technological breakthroughs and innovations. However, memory still faces numerous challenges, and how to continuously improve memory performance has become an urgent problem to be solved. Summary of the Invention

[0003] In view of the above, embodiments of the present disclosure provide a memory device and a method for operating the same, as well as a memory system.

[0004] In a first aspect, embodiments of this disclosure provide a memory device, the memory device including a memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array including at least one first memory block and a plurality of second memory blocks, wherein a portion of the plurality of second memory blocks serves as a sampling memory block; the peripheral circuitry is configured to: perform an erase operation on the sampling memory block; and record the number of erase operations of the sampling memory block in the at least one first memory block.

[0005] Secondly, embodiments of this disclosure also provide an operation method for a memory device, the method comprising: performing an erase operation on a sampled memory block; and recording the number of erases of the sampled memory block in at least one first memory block.

[0006] Thirdly, embodiments of this disclosure also provide a memory system, including: a memory device as described in any of the above embodiments; and a memory controller having a wear leveling function coupled to the memory device.

[0007] In this embodiment, a subset of second storage blocks can be selected as sample storage blocks from multiple second storage blocks using random sampling, systematic sampling, or other methods. The erase counts of these sample storage blocks are recorded in at least one first storage block. Therefore, by reading the erase counts recorded in the first storage block, the lifecycle stage of the memory device can be clearly determined. Subsequently, the reliability and performance of programming and erasing operations can be improved based on different wear levels. For example, if the memory device is at the end of its lifecycle, data that does not require frequent updates can be stored in it; if the memory device is in the early stage of its lifecycle, data that requires frequent updates can be stored in it. Furthermore, since this embodiment records the erase counts of the sample storage blocks internally within the memory device, even if the memory controller is damaged or fails, a new memory controller can be used to replace the faulty one. External devices can still obtain the erase counts of the sample storage blocks stored in the memory device through the new memory controller. This improves the overall effectiveness of the memory system. Attached Figure Description

[0008] In the accompanying drawings, similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0009] Figure 1A A schematic diagram of the structure of a memory system provided in an embodiment of this disclosure.

[0010] Figure 1B This is a schematic diagram of the structure of a memory card provided in an embodiment of this disclosure.

[0011] Figure 1C This is a schematic diagram of the structure of a solid state disk (SSD) provided in an embodiment of this disclosure.

[0012] Figure 1D and Figure 1E A schematic diagram of a memory device including a memory cell array and peripheral circuitry, provided for embodiments of this disclosure.

[0013] Figure 1F This is a schematic diagram of a storage cell array including a plurality of second storage blocks and at least one storage block, provided for embodiments of the present disclosure.

[0014] Figure 2 This is a schematic diagram of the structure of a storage cell array provided in an embodiment of this disclosure.

[0015] Figure 3 A comparison table of the total number of erasures and the preset number of erasures provided for embodiments of this disclosure.

[0016] Figure 4 A flowchart illustrating the operation method of the memory device provided in this embodiment of the present disclosure.

[0017] Figure 5 A flowchart illustrating the operation method of the memory device provided in the embodiments of this disclosure. Figure 2 .

[0018] Figure 6 A schematic diagram of the structure of a memory system provided in an embodiment of this disclosure. Detailed Implementation

[0019] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0021] like Figure 1A As shown in the illustration, this disclosure presents an exemplary system 10, which may include a host 20 and a memory system 30. The exemplary system 10 may include, but is not limited to, a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory 34 therein; the host 20 may be a processor of the electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)).

[0022] In one embodiment of this disclosure, the host 20 may be configured to send data to or receive data from the memory system 30. Here, the memory system 30 may include a memory controller 32 and one or more memory devices 34. The memory devices 34 may include, but are not limited to, NAND flash memory, vertical NAND flash memory, NOR flash memory, dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), phase change random access memory (PCRAM), resistive random access memory (RRAM), and nano random access memory (NRAM).

[0023] In one embodiment of this disclosure, a memory controller 32 may be coupled to the memory device 34 and the host 20 and is used to control the memory device 34. Exemplarily, the memory controller 32 may be designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a CompactFlash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones. In some embodiments, the memory controller 32 may also be designed to operate in a high duty cycle environment, such as an SSD or an embedded Multi-Media Card (eMMC), and the SSD or eMMC may be used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0024] Furthermore, the memory controller 32 can manage the data in the memory device 34 and communicate with the host. The memory controller 32 can be configured to control operations such as reading, erasing, and programming of the memory device 34; it can also be configured to manage various functions related to data stored or to be stored in the memory device 34, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.; and it can also be configured to process error checking and correction (ECC) codes for data read from or written to the memory device 34. In addition, the memory controller 32 can perform any other suitable functions, such as formatting the memory device 34, or communicating with external devices (e.g., according to a specific communication protocol) according to a specific communication protocol. Figure 1A Communication with the host (20). For example, the memory controller 32 can communicate with an external host via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Development Equipment (IDE), FireWire, etc.

[0025] In one embodiment of this disclosure, the memory controller 32 and one or more memory devices 34 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 30 can be implemented and packaged into different types of end electronic products. Figure 1BAs shown, the memory controller 32 and the individual memory device 34 can be integrated together to form a memory card 40. The memory card 40 may include PC cards (Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, Multimedia Cards (MMC, RS-MMC (Reduced-Size MMC), MMCmicro), SD cards (SD, miniSD, microSD, SDHC (Secure Digital High Capacity)), UFS, etc. The memory card 40 may also include a connector for connecting the memory card 40 to a host computer (e.g., Figure 1A The host 20) is coupled to the memory card connector 42. In such a way... Figure 1C In another embodiment shown, the memory controller 32 and a plurality of memory devices 34 may be integrated together to form an SSD 50. The SSD 50 may also include a connection between the SSD 50 and a host (e.g., Figure 1A The host 20 is coupled to the SSD connector 52. In some embodiments, the storage capacity and / or operating speed of the SSD 50 is greater than that of the memory card 40.

[0026] It should be noted that the memory involved in one embodiment of this disclosure can be a semiconductor memory, which is a solid-state electronic device for storing data information manufactured using semiconductor integrated circuit technology. For example, Figure 1D This is a schematic diagram of an optional memory device 34 according to an embodiment of this disclosure. Figure 1D As shown, the memory device 34 may include a memory cell array 62 and peripheral circuitry 64 coupled to the memory cell array 62. Here, the memory cell array may be a NAND flash memory cell array, wherein the memory cells are arranged in the form of an array of NAND memory strings 66, each NAND memory string 66 extending vertically above the substrate. In some embodiments, each NAND memory string 66 may include a plurality of memory cells coupled in series and stacked vertically. Each memory cell maintains a continuous analog value, such as voltage or charge, depending on the number of electrons trapped within the memory cell region. Additionally, the memory cells in the aforementioned memory cell array 62 may be floating-gate type memory cells including floating-gate transistors, or charge-trapping type memory cells including charge-trapping transistors.

[0027] In one embodiment of this disclosure, the aforementioned storage cell may be a single-level cell (SLC) having two possible storage states and thus capable of storing one bit of data. For example, a first storage state "0" may correspond to a first threshold voltage range, and a second storage state "1" may correspond to a second threshold voltage range. In other embodiments, each storage cell may be a multi-level cell (MLC) capable of storing more than a single bit of data. For example, an MLC may store two bits per cell. Each storage cell may also be a triple-level cell (TLC), or each storage cell may also be a quad-level cell (QLC). Each MLC may be programmed to a range of possible nominal storage values. Exemplarily, if each MLC stores two bits of data, the MLC may be programmed to change from an erase state to one of three possible programmed states by writing one of three possible nominal storage values ​​into that storage cell. The fourth nominal storage value may be used to correspond to the erase state.

[0028] In this embodiment of the disclosure, the peripheral circuit 64 described above can be coupled to the memory cell array via bit lines (BL), word lines (WL), source lines, source select gates (SSG), and drain select gates (DSG). Here, the peripheral circuit 64 can include any suitable analog, digital, and mixed-signal circuitry to facilitate related operations of the memory cell array by applying voltage and / or current signals to each target memory cell via bit lines, word lines, source lines, SSG, or DSG, and by sensing voltage and / or current signals from each target memory cell. Furthermore, the peripheral circuit 64 can also include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, as... Figure 1E As shown. The peripheral circuitry 64 may include a page buffer (PB) / sensor amplifier 71, a column decoder / bit line driver 72, a row decoder / word line driver 73, a voltage generator 74, a control logic unit 75, a register 76, an interface 77, and a data bus 78. In other embodiments, the peripheral circuitry 64 may also include... Figure 1E Additional peripheral circuitry not shown.

[0029] In some embodiments, the memory controller may record the number of times multiple memory blocks in the connected memory device are erased, with the number of erases used to reflect the degree of wear.

[0030] Internally, the memory device does not record the wear and tear of each memory block, causing the device to be unaware of its current stage in its lifecycle. In particular, when the memory controller fails or malfunctions, the recorded erase counts for multiple memory blocks are lost. At this point, the memory device is completely unaware of its current stage in its lifecycle.

[0031] In addition, memory devices need to know which stage of their lifecycle they are in in order to improve the reliability and performance of programming and erasing operations.

[0032] In some embodiments, the number of erases for each memory block can be recorded inside the memory device. However, if the number of erases for each memory block is recorded, not only will a large storage capacity be required, but the performance of the device itself will also be affected.

[0033] To address the aforementioned problems, embodiments of this disclosure provide a memory device, the memory device including a memory cell array and peripheral circuitry coupled to the memory cell array; such as Figure 1F As shown, the storage cell array 62 includes at least one first storage block 201 and a plurality of second storage blocks 202, wherein a portion of the plurality of second storage blocks 202 serve as sampling storage blocks; the peripheral circuitry is configured as follows:

[0034] An erase operation is performed on the sampled storage block.

[0035] The number of times the sampling storage block is erased is recorded in the at least one first storage block 201.

[0036] The memory devices shown in the embodiments of this disclosure include, but are not limited to, NAND flash memory, vertical NAND flash memory, NOR flash memory, dynamic random access memory, ferroelectric random access memory, magnetic random access memory, phase change random access memory, resistive random access memory, and nano random access memory.

[0037] In this embodiment of the disclosure, the user can perform corresponding read, write, and erase operations on the second storage block 202. However, for the first storage block 201, the user cannot perform write or erase operations on it, but can only perform read operations on it, so that the user can obtain the number of erases of the sampled storage block.

[0038] In practical use, the memory device needs to be coupled with a memory controller to form a memory system. The memory controller typically has a wear leveling function, which evenly distributes the usage of multiple second memory blocks 202 in the memory device to prevent some second memory blocks 202 from becoming bad blocks due to overuse. Thus, the number of erases experienced by the multiple second memory blocks 202 in the memory device is roughly balanced. Therefore, a subset of memory blocks 202 can be selected as sample memory blocks to represent all second memory blocks 202. This embodiment of the present disclosure saves space by recording the erase counts of the sample memory blocks, rather than recording the erase counts of all second memory blocks 202, thereby saving the number of first memory blocks 201 and the recording time.

[0039] In this embodiment of the disclosure, a portion of the second storage blocks 202 can be selected as sampling storage blocks from a plurality of second storage blocks 202 by means of random sampling, systematic sampling, etc.

[0040] In some embodiments, the storage cell array includes multiple storage planes, each storage plane including the multiple second storage blocks, and all of the sampled storage blocks belong to the same storage plane.

[0041] In this embodiment of the disclosure, the storage cell array includes multiple storage surfaces, which can be sequentially numbered starting from 0 (e.g., Plane0, Plane1, Plane2...). Different storage surfaces contain the same number of second storage blocks, which can be sequentially numbered starting from 1 (e.g., Block1, Block2, Block3...). Figure 2 An example of a memory cell array comprising four memory planes, each containing 200 second memory blocks, is shown. It should be understood that the number of memory planes and the number of second memory blocks described above are merely examples, and this disclosure does not impose any limitations on them. Second memory blocks with the same number in each memory plane constitute a virtual block (VB). Figure 2 As shown, multiple Block1s (the first second storage blocks) in Plane0 to Plane3 constitute virtual storage block 1, multiple Block2s (the second second storage blocks) in Plane0 to Plane3 constitute virtual storage block 2, and so on.

[0042] In some embodiments, P / E (Program / Erase) operations can be performed on multiple planes in units of virtual memory blocks, which can reduce the complexity of memory block management. P / E cycles represent the number of times a program can be written and erased; one P / E cycle is counted for each programming (i.e., writing) / erase operation.

[0043] Therefore, for a virtual storage block, any second storage block within it can represent the number of erases for all second storage blocks in that virtual storage block.

[0044] In some embodiments, each sampled storage block belongs to a different virtual storage block.

[0045] In some embodiments, all of the sampling storage blocks may belong to the same storage plane.

[0046] For example, a portion of the second storage blocks in Plane0 can be selected as all the sampled storage blocks, or a portion of the second storage blocks in Plane1 can be selected as all the sampled storage blocks.

[0047] In some embodiments, all of the sampling storage blocks may belong to different storage planes.

[0048] For example, a portion of the second storage block can be selected from Plane0 as part of the entire sampled storage block, and a portion of the second storage block can be selected from Plane1 as another part of the entire sampled storage block.

[0049] In some embodiments, the plurality of second storage blocks in the storage plane are numbered sequentially, and adjacent sampling storage blocks have the same numbering difference.

[0050] In some embodiments, such as Figure 2 As shown, each storage plane includes 200 second storage blocks numbered from 1 to 200. Ten second storage blocks can be selected from the same storage plane as sampling storage blocks. That is, one second storage block is selected from 20 second storage blocks as sampling storage blocks. For example, second storage blocks numbered 20, 40, 60, 80…200 can be selected as sampling storage blocks. For example, second storage blocks numbered 20, 40, 60, 80…200 in Plane0.

[0051] Alternatively, the second storage blocks numbered 20, 40, 60, 80...200 can be selected from different storage planes as sampling storage blocks. For example, the second storage blocks numbered 20, 40, 60, 80 and 100 in Plane0, and the second storage blocks numbered 120, 140, 160, 180 and 200 in Plane1.

[0052] In this embodiment of the disclosure, there is no restriction on the selection method of the sampling storage block. The sampling storage block can be selected from a portion of the second storage block in a uniform and dispersed manner from the storage cell array, including but not limited to system sampling.

[0053] In this embodiment, a subset of second storage blocks can be selected as sample storage blocks from multiple second storage blocks using random sampling, systematic sampling, or other methods. The erase counts of these sample storage blocks are recorded in at least one first storage block. Therefore, by reading the erase counts recorded in the first storage block, the lifecycle stage of the memory device can be clearly determined. Subsequently, the reliability and performance of programming and erasing operations can be improved based on different wear levels. For example, if the memory device is at the end of its lifecycle, data that does not require frequent updates can be stored in it; if the memory device is in the early stage of its lifecycle, data that requires frequent updates can be stored in it. Furthermore, since this embodiment records the erase counts of the sample storage blocks internally within the memory device, even if the memory controller is damaged or fails, a new memory controller can be used to replace the faulty one. External devices can still obtain the erase counts of the sample storage blocks stored in the memory device through the new memory controller. This improves the overall effectiveness of the memory system.

[0054] In some embodiments, the peripheral circuitry is configured to perform an erase operation on the selected second memory block.

[0055] Based on the fact that the selected second storage block belongs to the sampling storage block, the number of erases of the selected second storage block is recorded in the first storage block.

[0056] Since the selected second storage block is a non-sampled storage block, the number of erases for the selected second storage block is not recorded.

[0057] In this embodiment of the disclosure, an erase operation can be performed on any second storage block, but only the number of erases for the second storage block that belongs to the sampling storage block is recorded. Therefore, after the erase operation is performed on the selected second storage block, the address information of the selected second storage block can be compared with the address information of the sampling storage block, and the selection of the second storage block can be determined based on the comparison result.

[0058] In some embodiments, the at least one first memory block includes a plurality of physical page groups, each physical page group corresponding to storing a plurality of erase counts for one of the sampled memory blocks. The memory device includes registers. The peripheral circuitry is configured to:

[0059] In response to the erase operation performed on the sampled memory block being the first erase operation in the current power supply cycle of the memory device, the physical page corresponding to the sampled memory block is searched for the physical page with the maximum number of erases among a plurality of erase counts recorded for the sampled memory block.

[0060] The address information of the physical page with the maximum number of erases among multiple erase counts of the sampled storage block is stored in the first area of ​​the register.

[0061] The number of times a memory cell can be erased and rewritten varies. Generally speaking, the number of times SLC can be erased and rewritten is greater than that of MLC, MLC is greater than that of TLC, and TLC is greater than that of QLC.

[0062] In some embodiments, multiple counters can be used to count the number of erases to each sampled memory block during a power supply cycle. One timer can be used to count one sampled memory block. At the end of the power supply cycle (i.e., when power is lost), the multiple counters are reset to their initial value of 0.

[0063] The memory device provided in this embodiment includes a register. A first region of the register is used to store address information of the physical page with the maximum number of erases among a plurality of erase counts of the sampled memory block. The information stored in the register is volatile. That is, the address information stored in the register is reset after the end of the previous power-on cycle. Therefore, after performing an erase operation on the sampled memory block, it is necessary to determine whether the erase operation performed on the sampled memory block is the first erase operation in the current power-on cycle.

[0064] The register in this embodiment may be register 76 in Figure IE, or it may be an additional register set in the peripheral circuit.

[0065] In some embodiments, the size of the first region of the register is equal to the number of sampled memory blocks multiplied by the size of the address information of each physical page. For example, the size of the address information of each physical page can be 11 bits. The first region can be divided into multiple first sub-regions, the number of which is equal to the number of sampled memory blocks, and the size of each first sub-region is equal to the size of the address information of each physical page. Each first sub-region is used to store the corresponding address information. It should be understood that the size of the address information described above is merely an example, and this disclosure is not limited thereto.

[0066] In some embodiments, the peripheral circuit is configured as follows:

[0067] Based on the identifier information stored in the second region of the register, it is determined whether the erase operation performed on the sampled storage block is the first erase operation in the current power supply cycle.

[0068] In this embodiment of the present disclosure, a second region of the memory stores identifier information indicating whether it is the first erase operation in the current power-on cycle. In some embodiments, the size of the identifier information can be 1 bit. The value of one bit can be "0" or "1". For example, an identifier information of "1" indicates that it is not the first erase operation in the current power-on cycle, and an identifier information of "0" indicates that it is the first erase operation in the current power-on cycle.

[0069] The identifier information is reset to "0" after the end of the previous power cycle. After it is determined to be the first erase operation of the current power cycle, the identifier information is set to "1". And, the identifier information will remain "1" until the end of the current power cycle.

[0070] The identifier information being "0" indicates that this is the first erase operation of the current power supply cycle. Since the address information in the first area of ​​the register is reset at this time, it is necessary to search for the physical page in the physical page group corresponding to the sampling memory block that records the maximum number of erases among the multiple erase counts of the sampling memory block. Subsequently, the total number of erases of the sampling memory block can be recorded in the physical page that records the maximum number of erases among the multiple erase counts of the sampling memory block or in the physical pages thereafter.

[0071] In some embodiments, the at least one first memory block includes a plurality of physical page groups, each physical page group corresponding to storing a plurality of erase counts for one of the sampled memory blocks. The memory device includes registers. The peripheral circuitry is configured to:

[0072] In response to the erase operation performed on the sampled memory block being the Nth erase operation in the current power-on cycle of the memory device, the address information of the physical page containing the maximum erase count among multiple erase counts of the sampled memory block, stored in the first region of the register, is read. Here, N is an integer greater than or equal to 2.

[0073] The identifier "1" indicates that this is the Nth erase operation in the current power supply cycle, not the first erase operation. The address information of the physical page storing the maximum erase count among multiple erase counts of the sampled memory block in the first region of the register is read. The total erase count of the sampled memory block can continue to be recorded in the physical page storing the maximum erase count among multiple erase counts of the sampled memory block or in subsequent physical pages.

[0074] Total erase count refers to the total number of erases performed on the sampling memory block during the current power cycle and before the current power cycle.

[0075] The maximum number of erases refers to the maximum number of erases among multiple erase counts. These multiple erase counts all refer to the total number of erases.

[0076] In some implementations, if the physical page recording the maximum number of erases among the multiple erase counts of the sampled storage block is not full, the total number of erases of the sampled storage block can continue to be recorded in that physical page.

[0077] In some implementations, if the physical page recording the maximum number of erases among the multiple erase counts of the sampled storage block is full, the total number of erases of the sampled storage block can continue to be recorded in the physical pages following that physical page.

[0078] In some embodiments, the peripheral circuit is configured to use a binary search method to find the physical page in the physical page group corresponding to the sampling storage block that records the maximum number of erases among multiple erase counts of the sampling storage block.

[0079] In this embodiment, by employing a binary search method to find the physical page with the maximum number of erases among multiple erase counts recorded for the sampled storage block in the physical page group corresponding to the sampled storage block, the search efficiency can be effectively improved. If the physical page group corresponding to the sampled storage block is M pages, the maximum search count using the binary search method is [log2(M)]+1. For example, if M is 230, the maximum search count using the binary search method is [log2(M)]+1=11. Here, [] represents the floor function.

[0080] In some embodiments, the peripheral circuit is configured to: use a sequential search method to search for the physical page in the physical page group corresponding to the sampling storage block that records the maximum number of erases among multiple erase counts of the sampling storage block.

[0081] In some embodiments, the physical page group corresponding to the sampling storage block comprises K+1 physical pages consecutively numbered from M to M+K. Wherein, M and K are positive integers. The peripheral circuitry is configured as follows:

[0082] Based on the address information of the physical page with the maximum erase count among the multiple erase counts of the sampled storage block recorded in the first area of ​​the register, it is determined whether the physical page with the maximum erase count among the multiple erase counts of the sampled storage block is the last physical page in the physical page group corresponding to the sampled storage block.

[0083] If the address information indicates that the physical page with the maximum number of erases among the multiple erase counts of the sampled storage block is the physical page numbered M+K, then the total number of erases of the sampled storage block in the current power supply cycle and before the current power supply cycle will not be recorded.

[0084] If the address information indicates that the physical page with the maximum number of erases among the multiple erase counts of the sampled storage block is any physical page numbered from M to M+K-1, then the number of erases of the sampled storage block in the current power supply cycle is recorded.

[0085] In this embodiment, a preset number of erasable / write cycles (i.e., a preset total number of erase cycles) is set, allowing only the erase cycles within this preset number of cycles to be recorded. This is because if the actual number of erasable / write cycles of a sampled storage block exceeds the preset number of cycles, the sampled storage block has reached the end of its lifecycle, and continuing to record its erase cycles is not very meaningful. This embodiment provides K+1 physical pages, consecutively numbered from M to M+K, for each sampled storage block to record the preset number of erasable / write cycles. In other words, these K+1 physical pages can record exactly all the preset number of erasable / write cycles without any waste of physical pages.

[0086] Therefore, in this embodiment, after reading the address information of the physical page with the maximum erase count among the multiple erase counts of the sampled storage block recorded in the first area of ​​the register, it is necessary to further determine whether the physical page with the maximum erase count among the multiple erase counts of the sampled storage block is the last physical page in the physical page group corresponding to the sampled storage block. That is, it is used to determine whether the physical page group is full. If it is full, that is, the preset number of erase / write operations has been reached, even if subsequent erase operations are performed on the sampled storage block, the erase count of the sampled storage block will no longer be recorded. If it is not full, a counter is used to record the number of erases of the sampled storage block in the current power supply cycle. It should be noted that the recording here refers to temporary recording in the counter, and may not necessarily be synchronously recorded in the physical page group corresponding to the sampled storage block. In some embodiments, the value recorded in the counter will be synchronously recorded in the physical page group corresponding to the sampled storage block only when the value recorded in the counter reaches certain conditions.

[0087] In this embodiment, the number of erases in the current power supply cycle is independent of the number of erases in previous power supply cycles. The sum of the number of erases before the current power supply cycle and the number of erases in the current power supply cycle equals the total number of erases.

[0088] In some embodiments, the peripheral circuit is configured as follows:

[0089] Whenever the number of erases of the sampling storage block in the current power supply cycle reaches a multiple of the preset number of erases, the total number of erases of the sampling storage block after the erase operation is performed on the sampling storage block in the current power supply cycle is recorded in the first storage block.

[0090] The address information of the physical page that records the total number of erases of the sampled storage block is written into the first area of ​​the register.

[0091] In some embodiments, the preset number of erases can be a fixed value, such as an integer greater than or equal to 1. The following explanation uses a preset number of erases fixed at 3 as an example.

[0092] When the number of erases recorded in the counter for the sampled storage block in the current power supply cycle reaches a multiple of the preset number of erases, for example, 3, 6, 9..., then the total number of erases for the sampled storage block after the erase operation is performed on the sampled storage block in the current power supply cycle is recorded in the first storage block. The address information of the physical page recording the total number of erases for the sampled storage block is then written into the first area of ​​the register.

[0093] In this embodiment of the disclosure, by reading the address information in the first region of the register, the total number of erases of the sampling memory can be found, thereby determining which stage of the life cycle the memory device is in.

[0094] In some embodiments, the preset number of erases can be a non-fixed value.

[0095] In some embodiments, if the total number of erases of the sampling storage block is less than a first preset value, the preset number of erases is the first value.

[0096] If the total number of erases of the sampling storage block is greater than or equal to the first preset value and less than the second preset value, the preset number of erases is the second value.

[0097] If the total number of erases of the sampling storage block is greater than or equal to the second preset value and less than the third preset value, the preset number of erases is the third value.

[0098] In some embodiments, the third value is greater than the second value, and the second value is greater than the first value.

[0099] Setting the preset erase count too high will result in inaccurate erase count recording, while setting it too low will lead to overly frequent erase count recording, consuming too many programming operations. Here, programming refers to recording the erase count in the first storage block.

[0100] In this embodiment of the disclosure, during the early stages of the memory device's lifecycle, the erase count can be recorded with greater precision, so the first value can be smaller. During the middle stages of the memory device's lifecycle, the erase count can be recorded with slightly less precision, so the second value can be greater than the first value. During the late stages of the memory device's lifecycle, the erase count can be recorded with less precision, so the third value can be greater than the second value.

[0101] In this embodiment of the disclosure, the storage cell in the second storage block is a TLC and the preset number of erase / write cycles is 2996.

[0102] like Figure 3 As shown, when the total number of erases of the sampling storage block is between 1 and 1000, the preset number of erases is the first value, and the first value is equal to 2. That is, the 2nd erase, the 4th erase, and so on are recorded. When the 1000th erase is recorded, a total of 500 erases have been recorded.

[0103] When the total number of erases of the sampling storage block is between 1000 and 2000, the preset number of erases is the second value, and the second value is equal to 4. That is, the 1004th erase, the 1008th erase, and so on are recorded. When the 2000th erase is recorded, a total of 250 erases have been recorded.

[0104] When the total number of erases of the sampling storage block is between 2000 and 3000, the preset number of erases is the third value, and the third value is equal to 6. That is, the 2006th erase, the 2012th erase, and so on are recorded. When the 2996th erase is recorded, a total of 166 erases have been recorded.

[0105] In summary, a total of 500 + 250 + 166 = 916 erase counts were recorded. If the second storage unit is SLC and its NOP = 4, then recording 916 erase counts requires 229 physical pages, meaning one physical page group consists of 229 physical pages.

[0106] If 10 of the multiple second storage blocks are used as sampling storage blocks, these 10 sampling storage blocks require a total of 2290 physical pages to record the erase counts. If the first storage block has 2290 or more physical pages, then one first storage block can be provided to record all the erase counts of the 10 sampling storage blocks. If the first storage block has more than 1145 physical pages but less than 2290 physical pages, then two first storage blocks can be provided to record all the erase counts of the 10 sampling storage blocks. In this embodiment, the number of first storage blocks can be determined based on the number of physical pages required by all sampling storage blocks and the number of physical pages in each first storage block.

[0107] In some embodiments, the preset number of erase cycles can be determined based on the number of first storage blocks and the number of physical pages in the first storage blocks to ensure that all preset erase and write cycles can be recorded.

[0108] It is important to note that, for example, when the total number of erases on the sampling memory block is between 1 and 1000, if power is lost after erasing the sampling memory block once during the current power cycle, the total number of erases on the sampling memory block will not increase. Therefore, the recorded total number of erases on the sampling memory block differs from the actual total number of erases experienced by the sampling memory block, and the recorded total number of erases on the sampling memory block is less than the actual total number of erases experienced by the sampling memory block.

[0109] It should be understood that the values ​​of the first, second, and third values ​​mentioned above are merely examples, and this disclosure is not limited thereto; the values ​​can be selected according to the user's actual needs.

[0110] In some embodiments, the second storage block includes a plurality of first storage cells, each capable of storing at least one bit of data. The first storage block includes a plurality of second storage cells, each capable of storing one bit of data.

[0111] In some embodiments, the memory device can operate in a single mode, such as SLC mode. That is, both the first and second memory cells are SLC. SLC mode is characterized by faster read / write performance and stricter reliability requirements.

[0112] In some embodiments, the memory device can also be in a hybrid mode: "XLC mode + SLC mode". XLC includes, but is not limited to, MLC, TLC, and QLC, etc. These two modes can be used in combination under the control of the controller, which can not only give full play to the high read and write performance advantage of SLC mode, but also obtain the high storage capacity of X mode, which is several times the storage capacity of SLC mode.

[0113] From SLC mode to MLC mode to TLC mode and then to QLC mode, the storage capacity increases, but the reliability quality such as lifespan and data retention capability decreases accordingly.

[0114] The reason why the second storage unit can be SLC is that SLC has a higher Number of Programs (NOP), which can save the number of blocks used in the first storage unit. Here, the number of programs represents the maximum number of partial programs that can be written to each physical page. For example, NOP = 4 means that each physical page can be written to a maximum of four more times. Generally, SLC has 4 to 8 NOPs, while MLC and TLC have 1 NOP.

[0115] This disclosure also provides an operation method for a memory device, such as... Figure 4 As shown: The method includes:

[0116] Step S1001: Perform an erase operation on the sampling storage block.

[0117] Step S1002: Record the number of erases of the sampling storage block in at least one first storage block.

[0118] In this embodiment, a subset of second storage blocks can be selected as sample storage blocks from multiple second storage blocks using random sampling, systematic sampling, or other methods. The erase counts of these sample storage blocks are recorded in at least one first storage block. Therefore, by reading the erase counts recorded in the first storage block, the lifecycle stage of the memory device can be clearly determined. Subsequently, the reliability and performance of programming and erasing operations can be improved based on different wear levels. For example, if the memory device is at the end of its lifecycle, data that does not require frequent updates can be stored in it; if the memory device is in the early stage of its lifecycle, data that requires frequent updates can be stored in it. Furthermore, since this embodiment records the erase counts of the sample storage blocks internally within the memory device, even if the memory controller is damaged or fails, a new memory controller can be used to replace the faulty one. External devices can still obtain the erase counts of the sample storage blocks stored in the memory device through the new memory controller. This improves the overall effectiveness of the memory system.

[0119] In some embodiments, the method further includes:

[0120] Perform an erase operation on the selected second storage block.

[0121] Based on the fact that the selected second storage block belongs to the sampling storage block, the number of erases of the selected second storage block is recorded in the first storage block.

[0122] Since the selected second storage block does not belong to the sampled storage block, the number of erases for the selected second storage block is not recorded.

[0123] In some embodiments, the method further includes:

[0124] In response to the erase operation performed on the sampled memory block being the first erase operation in the current power supply cycle of the memory device, the physical page corresponding to the sampled memory block is searched for the physical page with the maximum number of erases among a plurality of erase counts recorded for the sampled memory block.

[0125] The address information of the physical page with the maximum number of erases among multiple erase counts of the sampled storage block is stored in the first area of ​​the register.

[0126] In some embodiments, searching for the physical page in the physical page group corresponding to the sampled storage block that records the maximum number of erases for the sampled storage block includes:

[0127] The binary search method is used to find the physical page in the physical page group corresponding to the sampling storage block that has the maximum number of erases among the multiple erase counts of the sampling storage block.

[0128] In some embodiments, the method further includes:

[0129] In response to the erase operation performed on the sampled memory block being the Nth erase operation in the current power-on cycle of the memory device, the address information of the physical page with the maximum erase count among multiple erase counts of the sampled memory block, stored in the first region of the register, is read. Here, N is an integer greater than or equal to 2.

[0130] In some embodiments, the method further includes:

[0131] Based on the identifier information stored in the second region of the register, it is determined whether the erase operation performed on the sampled storage block is the first erase operation in the current power supply cycle.

[0132] In some embodiments, the physical page group corresponding to the sampling storage block comprises K+1 physical pages consecutively numbered from M to M+K. Wherein, M and K are positive integers. The method further includes:

[0133] Based on the address information of the physical page with the maximum erase count among the multiple erase counts of the sampled storage block recorded in the first area of ​​the register, it is determined whether the physical page with the maximum erase count among the multiple erase counts of the sampled storage block is the last physical page in the physical page group corresponding to the sampled storage block.

[0134] If the address information indicates that the physical page with the largest number of erases among the multiple erase counts of the sampled storage block is the physical page numbered M+K, then the number of erases of the sampled storage block in the current power supply cycle is not recorded.

[0135] If the address information indicates that the physical page with the maximum number of erases among the multiple erase counts of the sampled storage block is any physical page numbered from M to M+K-1, then the number of erases of the sampled storage block in the current power supply cycle is recorded.

[0136] In some embodiments, the method further includes:

[0137] Whenever the number of erases of the sampling storage block in the current power supply cycle reaches a multiple of the preset number of erases, the total number of erases of the sampling storage block after the erase operation is performed on the sampling storage block in the current power supply cycle is recorded in the first storage block.

[0138] The address information of the physical page that records the total number of erases of the sampled storage block is written into the first area of ​​the register.

[0139] In some embodiments, if the total number of erases of the sampling storage block is less than a first preset value, the preset number of erases is the first value.

[0140] If the total number of erases of the sampling storage block is greater than or equal to the first preset value and less than the second preset value, the preset number of erases is the second value.

[0141] If the total number of erases of the sampling storage block is greater than or equal to the second preset value and less than the third preset value, the preset number of erases is the third value.

[0142] In some embodiments, the third value is greater than the second value, and the second value is greater than the first value.

[0143] In some embodiments, the storage cell array includes multiple storage surfaces, each storage surface including multiple second storage blocks, and all of the sampled storage blocks belong to the same storage surface.

[0144] In some embodiments, a plurality of the second storage blocks in the storage plane are sequentially numbered, and adjacent sampled storage blocks have the same numbering difference.

[0145] In some embodiments, the second storage block includes a plurality of first storage cells, each capable of storing at least one bit of data. The first storage block includes a plurality of second storage cells, each capable of storing one bit of data.

[0146] The specific implementation methods of the methods in the above embodiments have been described in detail in the embodiments of the products corresponding to the methods, and will not be elaborated here.

[0147] This disclosure also provides the following embodiments, such as Figure 5 As shown:

[0148] First, step S1 is executed to perform an erase operation on the selected second storage block.

[0149] Then, step S2 is executed to determine whether the selected second storage block belongs to the sampled storage block. If the selected second storage block belongs to the non-sampled storage block, the number of erases of the selected second storage block is not recorded, and the process ends.

[0150] If the selected second storage block is a sampling storage block, continue to execute step S3, read the identifier stored in the second area of ​​the register, and determine whether the erase operation performed on the sampling storage block is the first erase operation in the current power supply cycle.

[0151] If the erase operation performed on the sampling memory block is the first erase operation in the current power supply cycle, continue to execute step S4, use the binary search method to find the physical page in the physical page group corresponding to the sampling memory block that records the maximum number of erases among the multiple erase counts of the sampling memory block, and store the address information of the physical page that records the maximum number of erases among the multiple erase counts of the sampling memory block in the first area of ​​the register.

[0152] If the erase operation performed on the sampled storage block is not the first erase operation in the current power supply cycle, continue to step S5 and read the address information of the physical page that records the maximum number of erases among the multiple erase counts of the sampled storage block stored in the first area of ​​the register.

[0153] Continue with step S6 to determine whether the physical page with the maximum number of erases among the multiple erase counts recorded for the sampled storage block is the last physical page in the physical page group corresponding to the sampled storage block.

[0154] If the physical page with the highest erase count among the multiple erase counts recorded for the sampled storage block is the last physical page in the physical page group corresponding to the sampled storage block, the total erase count of the sampled storage block in the current power supply cycle and before the current power supply cycle is not recorded, and the current process ends.

[0155] If the physical page with the largest number of erases among the multiple erase counts recorded for the sampled storage block is not the last physical page in the physical page group corresponding to the sampled storage block, then continue to execute step S7 to record the number of erases of the sampled storage block in the current power supply cycle.

[0156] Continue with step S8. If the total number of erases on the sampling memory block is between 1 and 1000, and whenever the number of erases on the sampling memory block in the current power supply cycle reaches a multiple of 2, record the total number of erases on the sampling memory block after the erase operation is performed on the sampling memory block in the first memory block during the current power supply cycle. Then update the address information recording the total number of erases in the register.

[0157] Alternatively, continue with step S9. If the total number of erases on the sampling memory block is between 1001 and 2000, and whenever the number of erases on the sampling memory block in the current power supply cycle reaches a multiple of 4, record in the first memory block the total number of erases on the sampling memory block after the erase operation is performed on the sampling memory block in the current power supply cycle. Then update the address information recording the total number of erases in the register.

[0158] Alternatively, continue with step S10. If the total number of erases on the sampling memory block is between 2001 and 2996, and whenever the number of erases on the sampling memory block in the current power supply cycle reaches a multiple of 6, record in the first memory block the total number of erases on the sampling memory block after the erase operation is performed on the sampling memory block in the current power supply cycle. Then update the address information recording the total number of erases in the register.

[0159] Finally, this process concludes.

[0160] This disclosure also provides a memory system, including: a memory device as described in any of the foregoing embodiments; and a memory controller coupled to the memory device and having a wear leveling function.

[0161] Figure 6 This is a schematic diagram of a memory system 101, which includes a memory controller 102 and a memory device 103. The memory controller 102 controls the memory device 103 to perform read and write operations. The memory controller 102 and the memory device 103 can be coupled in any suitable manner. The memory controller 102 includes a control unit (CPU) 108, a cache 109, a host interface 105, a memory interface 107, and a wear leveling module 111. In this embodiment, the memory device 103 can be a non-volatile semiconductor memory, such as a NAND flash memory. The memory system 101 is connected to a host 104. The host interface 105 outputs commands and valid data (write data) received from the host 104 to the internal bus 110, and sends valid data read from the memory device 103 (read data) and responses from the control unit 108 back to the host 104.

[0162] The memory interface 107 controls the processes of writing data to and reading data from the memory device 103 based on instructions from the control unit 108. The control unit 108 controls the memory system 101 as a whole; the control unit 108 may be, for example, a central processing unit (CPU) or a microprocessor (MPU). The control unit 108 performs control based on commands received from the host 104 via the host interface 105. For example, the control unit 108 instructs the memory interface 107 to write data to the memory device 103 based on a command from the host 104. Furthermore, the control unit 108 instructs the memory interface 107 to read data from the memory device 103 based on a command from the host 104.

[0163] The buffer 109 temporarily stores the data received from the host 104 before storing it in the memory device 103, and temporarily stores the data read from the memory device 103 before sending it to the host 104.

[0164] Flash memory has a limited lifespan, meaning that each flash memory block has a limited number of erase / write cycles. If a block's erase / write cycles exceed a certain value, it becomes less reliable and may even become a bad block, rendering it unusable. The wear leveling module 111 can prevent some blocks from being frequently erased and written, keeping the erase / write values ​​of each block relatively balanced, thereby extending the overall lifespan of the flash memory.

[0165] In some embodiments, the memory system includes, but is not limited to, memory cards and solid-state drives.

[0166] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0167] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0168] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A memory device, characterized in that, The memory device includes a memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array includes at least one first memory block and a plurality of second memory blocks, wherein a portion of the plurality of second memory blocks serves as a sampling memory block; the peripheral circuitry is configured to: Perform an erase operation on the sampled storage block; The number of times the sampled storage block is erased is recorded in the at least one first storage block.

2. The memory device according to claim 1, characterized in that, The peripheral circuit is configured as follows: Perform an erase operation on the selected second storage block; Based on the fact that the selected second storage block belongs to the sampled storage block, the number of erases of the selected second storage block is recorded in the at least one first storage block.

3. The memory device according to claim 1, characterized in that, The at least one first storage block includes multiple physical page groups, each physical page group corresponding to storing multiple erase counts of one of the sampled storage blocks; the memory device includes registers; the peripheral circuitry is configured as follows: In response to the erase operation performed on the sampled storage block being the first erase operation in the current power supply cycle of the memory device, the physical page corresponding to the sampled storage block is searched for the physical page with the maximum number of erases among multiple erase counts recorded for the sampled storage block; The address information of the physical page with the maximum number of erases among multiple erase counts of the sampled storage block is stored in the first area of ​​the register.

4. The memory device according to claim 3, characterized in that, The peripheral circuit is configured to use a binary search method to find the physical page in the physical page group corresponding to the sampling storage block that records the maximum number of erases among multiple erase counts of the sampling storage block.

5. The memory device according to claim 1, characterized in that, The at least one first storage block includes multiple physical page groups, each physical page group corresponding to storing multiple erase counts of one of the sampled storage blocks; the memory device includes registers; the peripheral circuitry is configured as follows: In response to the erase operation performed on the sampled memory block being the Nth erase operation in the current power supply cycle of the memory device, the address information of the physical page containing the maximum erase count among multiple erase counts of the sampled memory block, stored in the first region of the register, is read; where N is an integer greater than or equal to 2.

6. The memory device according to claim 3 or 5, characterized in that, The peripheral circuit is configured as follows: Based on the identifier information stored in the second region of the register, it is determined whether the erase operation performed on the sampled storage block is the first erase operation in the current power supply cycle.

7. The memory device according to claim 3 or 5, characterized in that, The physical page group corresponding to the sampling storage block includes K+1 physical pages numbered consecutively from M to M+K; wherein M and K are positive integers; the peripheral circuit is configured as follows: Based on the address information of the physical page with the maximum number of erases among the multiple erase counts of the sampled storage block recorded in the first area of ​​the register, it is determined whether the physical page with the maximum number of erases among the multiple erase counts of the sampled storage block is the last physical page in the physical page group corresponding to the sampled storage block; If the address information indicates that the physical page with the maximum number of erases among the multiple erase counts of the sampled storage block is the physical page numbered M+K, then the total number of erases of the sampled storage block in the current power supply cycle and before the current power supply cycle will not be recorded. If the address information indicates that the physical page with the maximum number of erases among the multiple erase counts of the sampled storage block is any physical page numbered from M to M+K-1, then the number of erases of the sampled storage block in the current power supply cycle is recorded.

8. The memory device according to claim 7, characterized in that, The peripheral circuit is configured as follows: Whenever the number of erases of the sampling storage block in the current power supply cycle reaches a multiple of the preset number of erases, the total number of erases of the sampling storage block after the erase operation is performed on the sampling storage block in the current power supply cycle is recorded in the first storage block; The address information of the physical page that records the total number of erases of the sampled storage block is written into the first area of ​​the register.

9. The memory device according to claim 8, characterized in that, If the total number of erases of the sampling storage block is less than a first preset value, the preset number of erases is the first value; If the total number of erases of the sampling storage block is greater than or equal to the first preset value and less than the second preset value, the preset number of erases is the second value; If the total number of erases of the sampling storage block is greater than or equal to the second preset value and less than the third preset value, the preset number of erases is the third value.

10. The memory device according to claim 9, characterized in that, The third value is greater than the second value, and the second value is greater than the first value.

11. The memory device according to claim 1, characterized in that, The storage cell array includes multiple storage surfaces, each storage surface includes multiple second storage blocks, and all of the sampling storage blocks belong to the same storage surface.

12. The memory device according to claim 11, characterized in that, The plurality of second storage blocks in the storage plane are numbered sequentially, and adjacent sampling storage blocks have the same numbering difference.

13. The memory device according to claim 1, characterized in that, The second storage block includes a plurality of first storage units, each of which can store at least one bit of data; the first storage block includes a plurality of second storage units, each of which can store one bit of data.

14. A method of operating a memory device, characterized in that, The method includes: Perform an erase operation on the sampled storage block; The number of times the sampled storage block is erased is recorded in at least one first storage block.

15. The operating method according to claim 14, characterized in that, The method further includes: Perform an erase operation on the selected second storage block; Based on the fact that the selected second storage block belongs to the sampled storage block, the number of erases of the selected second storage block is recorded in the at least one first storage block.

16. The operating method according to claim 14, characterized in that, The method further includes: In response to the erase operation performed on the sampled storage block being the first erase operation in the current power supply cycle of the memory device, the physical page corresponding to the sampled storage block is searched for the physical page with the maximum number of erases among multiple erase counts recorded for the sampled storage block; The address information of the physical page with the maximum number of erases among multiple erase counts of the sampled storage block is stored in the first area of ​​the register.

17. The operating method according to claim 16, characterized in that, The step of searching for the physical page in the physical page group corresponding to the sampling storage block that records the maximum number of erases for the sampling storage block includes: The binary search method is used to find the physical page in the physical page group corresponding to the sampling storage block that has the maximum number of erases among the multiple erase counts of the sampling storage block.

18. The operating method according to claim 14, characterized in that, The method further includes: In response to the erase operation performed on the sampled memory block being the Nth erase operation in the current power supply cycle of the memory device, the address information of the physical page with the maximum erase count among the multiple erase counts of the sampled memory block, which is stored in the first region of the register, is read; where N is an integer greater than or equal to 2.

19. The operating method according to claim 16 or 18, characterized in that, The method further includes: Based on the identifier information stored in the second region of the register, it is determined whether the erase operation performed on the sampled storage block is the first erase operation in the current power supply cycle.

20. The operating method according to claim 16 or 18, characterized in that, The physical page group corresponding to the sampling storage block includes K+1 physical pages consecutively numbered from M to M+K; wherein M and K are positive integers; the method further includes: Based on the address information of the physical page with the maximum number of erases among the multiple erase counts of the sampled storage block recorded in the first area of ​​the register, it is determined whether the physical page with the maximum number of erases among the multiple erase counts of the sampled storage block is the last physical page in the physical page group corresponding to the sampled storage block; If the address information indicates that the physical page with the maximum number of erases among the multiple erase counts of the sampled storage block is the physical page numbered M+K, then the number of erases of the sampled storage block in the current power supply cycle is not recorded. If the address information indicates that the physical page with the maximum number of erases among the multiple erase counts of the sampled storage block is any physical page numbered from M to M+K-1, then the number of erases of the sampled storage block in the current power supply cycle is recorded.

21. The operating method according to claim 20, characterized in that, The method further includes: Whenever the number of erases of the sampling storage block in the current power supply cycle reaches a multiple of the preset number of erases, the total number of erases of the sampling storage block after the erase operation is performed on the sampling storage block in the current power supply cycle is recorded in the first storage block; The address information of the physical page that records the total number of erases of the sampled storage block is written into the first area of ​​the register.

22. The operating method according to claim 21, characterized in that, If the total number of erases of the sampling storage block is less than a first preset value, the preset number of erases is the first value; If the total number of erases of the sampling storage block is greater than or equal to the first preset value and less than the second preset value, the preset number of erases is the second value; If the total number of erases of the sampling storage block is greater than or equal to the second preset value and less than the third preset value, the preset number of erases is the third value.

23. The operating method according to claim 22, characterized in that, The third value is greater than the second value, and the second value is greater than the first value.

24. The operating method according to claim 15, characterized in that, The storage cell array includes multiple storage surfaces, each storage surface includes multiple second storage blocks, and all of the sampled storage blocks belong to the same storage surface.

25. The operating method according to claim 24, characterized in that, The multiple second storage blocks in the storage plane are numbered sequentially, and adjacent sampling storage blocks have the same numbering difference.

26. The operating method according to claim 15, characterized in that, The second storage block includes a plurality of first storage units, each of which can store at least one bit of data; the first storage block includes a plurality of second storage units, each of which can store one bit of data.

27. A memory system, characterized in that, include: The memory device as claimed in any one of claims 1 to 13; as well as, A memory controller with wear leveling function coupled to the memory device.

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