Technological method applied to preparation process of semiconductor device
By covering the surface of semiconductor devices with a protective thin film and forming a stress film layer using ALD and PE CVD processes, the problem of NBTI performance degradation caused by hydrogen diffusion was solved, thus improving the reliability of the devices.
Patent Information
- Application Number
- CN202511055372.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-29
- Publication Date
- 2025-11-11
AI Technical Summary
In existing SMT processes, hydrogen in the silicon nitride stress film layer causes boron diffusion, which deteriorates the negative bias temperature stability of semiconductor devices.
After covering the substrate surface with a protective thin film layer, a dense stress film layer is formed by ALD and PE CVD processes. Subsequently, heat treatment is performed to remove unnecessary film layers and reduce hydrogen diffusion.
It effectively reduces hydrogen diffusion, improves the NBTI performance of semiconductor devices, and reduces interface defects in the gate dielectric layer.
Smart Images
Figure CN120933152A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor devices and integrated circuit technology, and in particular to a process method applied in the fabrication of semiconductor devices. Background Technology
[0002] Stress memorization technique (SMT) is a process in semiconductor integrated circuit manufacturing where a stress film layer is deposited on the surface of a semiconductor device, followed by annealing (e.g., rapid thermal annealing) to remove the stress film layer. Although the stress film layer is removed, the stress is memorized through annealing, so that the channel retains stress even after the stress film layer is removed.
[0003] In related technologies, the SMT process uses silicon nitride (Si3N4) as a stress film layer. The stress of silicon nitride is tensile stress and its hydrogen (H) content is high. During the annealing process, the hydrogen element in the silicon nitride film will affect the defect density, leading to the diffusion of boron (B) element, which will deteriorate the negative bias temperature instability (NBTI) performance and thus reduce the reliability of the device. Summary of the Invention
[0004] This application provides a process method applied in the fabrication of semiconductor devices, which can solve the problem in related technologies where hydrogen elements in the stress film formed in the SMT process easily lead to the diffusion of boron elements in the semiconductor device, resulting in deterioration of NBTI performance. The method includes:
[0005] A protective thin film layer is deposited on the front side of the substrate, the protective thin film layer covering the semiconductor device formed on the substrate, and a back nitride layer is formed on the back side of the substrate;
[0006] A first stress film layer is formed on the protective film layer by the ALD process;
[0007] A second stress film layer is formed on the first stress film layer by a PE CVD process. The first stress film layer and the second stress film layer are made of the same material. The first stress film layer and the second stress film layer are used to transfer tensile stress to the semiconductor device.
[0008] The back side of the substrate is heat-treated using an RTA process;
[0009] Remove the back nitride layer, the first stress film layer, and the second stress film layer;
[0010] Remove the protective film layer;
[0011] The substrate is heat-treated using the LSA process.
[0012] In some embodiments, the first stress film layer and the second stress film layer comprise silicon nitride layers.
[0013] In some embodiments, the thickness of the first stress film layer is 10 to 30 angstroms.
[0014] In some embodiments, the thickness of the second stress film layer is 250 angstroms to 350 angstroms.
[0015] In some embodiments, the protective film layer comprises a silicon dioxide layer.
[0016] In some embodiments, removing the back nitride layer, the first stress film layer, and the second stress film layer includes:
[0017] The back nitride layer, the first stress film layer, and the second stress film layer are removed by a wet etching process.
[0018] The technical solution of this application has at least the following advantages:
[0019] After covering the surface of a semiconductor device with a protective thin film layer, a stress film layer is formed by sequentially depositing ALD and PE CVD processes. Since the stress film layer formed by the ALD process is dense and has a low hydrogen content, it can effectively reduce the diffusion of hydrogen elements, reduce the interface defects of the gate dielectric layer of the semiconductor device, and improve its NBTI performance. Attached Figure Description
[0020] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0021] Figure 1 This is a flowchart of a process method applied in the fabrication of semiconductor devices provided in an exemplary embodiment of this application;
[0022] Figures 2 to 6 This is a schematic diagram of the preparation process of a process method provided in an exemplary embodiment of this application. Detailed Implementation
[0023] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0024] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0025] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0026] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0027] refer to Figure 1 It illustrates a flowchart of a process method applied in the fabrication of semiconductor devices according to an exemplary embodiment of this application, such as... Figure 1 As shown, the method includes:
[0028] Step S1: A protective thin film layer is deposited on the front side of the substrate, which covers the semiconductor device formed on the substrate, and a back nitride layer is formed on the back side of the substrate.
[0029] refer to Figure 2 This illustrates a cross-sectional view after a protective thin film layer has been deposited on the front side of a substrate. For example, such as... Figure 2As shown, a semiconductor device is formed on the substrate 210. A back nitride layer 270 is formed on the back side of the substrate 210, and a silicon dioxide (SiO2) layer can be deposited to form a protective thin film 250 by chemical vapor deposition (CVD). It should be noted that in this embodiment, a complementary metal oxide semiconductor (CMOS) device is formed on the substrate 210 as an example. In practical applications, any semiconductor fabrication process that requires SMT (Surface Mount Technology) can implement the embodiments of this application.
[0030] like Figure 2 As shown, the regions on substrate 210 used for forming semiconductor devices include a first region 201 and a second region 202. A shallow trench isolation (STI) structure 211 is formed in substrate 210 to isolate the active areas (AA) of each semiconductor device. The first region 201 is used to form an N-type metal-oxide-semiconductor field-effect transistor (NMOS) device, and the second region 202 is used to form a P-type (positive-type metal-oxide-semiconductor field-effect transistor, PMOS) device. Wherein:
[0031] The NMOS device includes a first gate 231, a first heavily doped region 2012 and a second heavily doped region 2013 formed in the substrates 210 on both sides of the first gate 231, and a first gate dielectric layer 221 formed between the first gate 231 and the substrates 210. A P-type well region 2011 is formed in the active region of the NMOS device, and the first heavily doped region 2012 and the second heavily doped region 2013 are formed in the P-type well region 2011. The periphery of the first gate 231 includes a first sidewall 2411, a second sidewall 2412 and a third sidewall 2413 from the inside to the outside.
[0032] Furthermore, a first lightly doped drain (LDD) region 2014 and a first Halo implantation region 2015 are formed in the substrate on both sides of the first gate 231. Laterally, the heavily doped region (first heavily doped region 2012 or second heavily doped region 2013) is furthest from the first gate 231, the first LDD region 2014 is located between the heavily doped region and the first Halo implantation region 2015, and the first Halo implantation region 2015 is closest to the first gate 231. The impurity concentration in the first heavily doped region 2012 and the second heavily doped region 2013 is greater than the impurity concentration in the first LDD region 2014 and the first Halo implantation region 2015. The impurities doped in the first heavily doped region 2012, the second heavily doped region 2013, and the first LDD region 2014 are N-type impurities, while the impurities doped in the first well region 2011 and the first Halo implantation region 2015 are P-type impurities.
[0033] The PMOS device includes a second gate 232, a third heavily doped region 2022 and a second heavily doped region 2023 formed in the substrates 210 on both sides of the second gate 232, and a second gate dielectric layer 222 formed between the second gate 232 and the substrates 210. An N-type well region 2021 is formed in the active region of the PMOS device, and the third heavily doped region 2022 and the fourth heavily doped region 2023 are formed in the N-type well region 2021. The periphery of the second gate 232 includes, from the inside out, a fourth sidewall 2421, a fifth sidewall 2422, and a sixth sidewall 2423.
[0034] Furthermore, a second LDD region 2024 and a second Halo implantation region 2025 are formed in the substrate on both sides of the second gate 2321. Laterally, the heavily doped region (the third heavily doped region 2022 or the fourth heavily doped region 2023) is furthest from the second gate 232, the second LDD region 2024 is located between the heavily doped region and the second Halo implantation region 2025, and the second Halo implantation region 2025 is closest to the second gate 232. The impurity concentration in the third heavily doped region 2022 and the fourth heavily doped region 2023 is greater than the impurity concentration in the second LDD region 2024 and the second Halo implantation region 2025. The impurities doped in the third heavily doped region 2022, the fourth heavily doped region 2023, and the second LDD region 2024 are P-type impurities, while the impurities doped in the second well region 2021 and the second Halo implantation region 2025 are N-type impurities.
[0035] Step S2: A first stress film layer is formed on the protective film layer using the ALD process.
[0036] Step S3: A second stress film layer is formed on the first stress film layer by a PE CVD process. The first stress film layer and the second stress film layer are made of the same material. The first stress film layer and the second stress film layer are used to transfer tensile stress to the semiconductor device.
[0037] refer to Figure 3 It shows a schematic cross-sectional view after the formation of the first stress film layer and the second stress film layer. For example, as shown... Figure 3 As shown, a first stress film layer formed by atomic layer deposition (ALD) and a second stress film layer formed by plasma enhanced chemical vapor deposition (PE CVD) constitute a stress film layer 260, which is used to transfer tensile stress to semiconductor devices (NMOS devices and PMOS devices). The stress film layer 260 (the first stress film layer and the second stress film layer) includes a silicon nitride layer. The first stress film layer acts as a barrier layer to block free hydrogen elements, and due to the low content of free hydrogen elements, it significantly reduces the probability of defect formation. The thickness of the first stress film layer is 10 angstroms. The thickness of the second stress film layer is 250 to 350 angstroms, up to 30 angstroms.
[0038] Step S4: Perform heat treatment on the back side of the substrate using the RTA process.
[0039] refer to Figure 4 This diagram shows a cross-sectional view of the back side of a substrate being heat-treated using a rapid thermal annealing (RTA) process. The RTA process is performed at temperatures ranging from 1010°C to 1060°C.
[0040] Step S5: Remove the back nitride layer, the first stress film layer, and the second stress film layer.
[0041] refer to Figure 5 It shows a schematic cross-sectional view after removing the back nitride layer, the first stress film layer, and the second stress film layer. For example, as shown... Figure 5 As shown, the back nitride layer 270 and the stress film layer 260 (first stress film layer and second stress film layer) can be removed by a wet etching process (the reagents used may include SPM solution (which typically includes sulfuric acid (H2SO4) and hydrogen peroxide (H2O2)), hydrofluoric acid and SCI solution (which typically includes ammonia (NH3·H2O), hydrogen peroxide and water).
[0042] Step S6: Remove the protective film layer.
[0043] Step S7: Perform heat treatment on the substrate using the LSA process.
[0044] refer to Figure 6 This illustrates a cross-sectional schematic diagram of a substrate subjected to heat treatment via laser spike annealing (LSA) after the protective thin film layer has been removed. For example, such as... Figure 6 As shown, the temperature for heat treatment via the LSA process is 1010°C to 1070°C.
[0045] In summary, in this embodiment of the application, after covering the surface of the semiconductor device with a protective thin film layer, a stress thin film layer is formed by sequentially depositing ALD and PE CVD processes. Since the stress thin film layer formed by the ALD process is dense and has a low hydrogen content, it can effectively reduce the diffusion of hydrogen elements, reduce the interface defects of the gate dielectric layer of the semiconductor device, and improve its NBTI performance.
[0046] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A process method applied in the fabrication of semiconductor devices, characterized in that, include: A protective thin film layer is deposited on the front side of the substrate, the protective thin film layer covering the semiconductor device formed on the substrate, and a back nitride layer is formed on the back side of the substrate; A first stress film layer is formed on the protective film layer by the ALD process; A second stress film layer is formed on the first stress film layer by a PE CVD process. The first stress film layer and the second stress film layer are made of the same material. The first stress film layer and the second stress film layer are used to transfer tensile stress to the semiconductor device. The back side of the substrate is heat-treated using an RTA process; Remove the back nitride layer, the first stress film layer, and the second stress film layer; Remove the protective film layer; The substrate is heat-treated using the LSA process.
2. The method according to claim 1, characterized in that, The first stress film layer and the second stress film layer include silicon nitride layers.
3. The method according to claim 2, characterized in that, The thickness of the first stress film layer is 10 to 30 angstroms.
4. The method according to claim 3, characterized in that, The thickness of the second stress film layer is 250 angstroms to 350 angstroms.
5. The method according to any one of claims 2 to 4, characterized in that, The protective film layer includes a silicon dioxide layer.
6. The method according to claim 5, characterized in that, The removal of the back nitride layer, the first stress film layer, and the second stress film layer includes: The back nitride layer, the first stress film layer, and the second stress film layer are removed by a wet etching process.