Formation method of semiconductor device
By adding He gas to the etching gas to optimize the etching process, the problem of controlling the morphology of deep trenches was solved, and full filling and online monitoring of polycrystalline silicon layers were achieved, which improved the yield of finished products and saved resources.
Patent Information
- Application Number
- CN202511074441.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-31
- Publication Date
- 2025-11-11
AI Technical Summary
Under small-size conditions, the morphology of deep trenches is difficult to control, resulting in insufficient etching stop or a bowl-shaped bottom of the trench, which affects polysilicon filling, reduces product yield and reliability, and the existing monitoring methods waste manpower and resources.
He gas was added to the etching gases SF6 and O2 to optimize the etching process parameters. By adjusting the gas ratio and flow rate, the loading effect was reduced, ensuring that the trench morphology met the requirements. A test groove without silica grass was formed in the dicing area to achieve online monitoring of the trench depth.
It achieves full filling of polycrystalline silicon layers at small critical dimensions, avoids voids, simplifies the depth monitoring process, and saves manpower and resources.
Smart Images
Figure CN120933157A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit manufacturing technology, and specifically relates to a method for forming a semiconductor device. Background Technology
[0002] With the development of power devices, the demand for reduced power consumption is constantly increasing. Device spacing is becoming smaller, and the critical dimensions of deep trenches in the device substrate are also decreasing. This reduction in critical dimensions makes it difficult to control the morphology of the deep trenches, easily leading to issues such as… Figure 1 The etching stop indicated by the red circle, or as shown in the image, indicates a stop in the etching process. Figure 2 The bottom of the trench shown is bowl-shaped (B). Stopping etching will result in the etching depth not meeting the process requirements; the bowl-shaped bottom of the trench (B) will cause insufficient filling of the subsequent polysilicon, forming gaps (voids), affecting the etching of subsequent polysilicon, and thus affecting the yield and reliability of the finished product.
[0003] The depth of the trenches in the functional areas of power devices fluctuates due to factors such as preventative maintenance checks on the equipment and the inspection of critical dimensions after hard mask etching of the trenches. Currently, factories mainly monitor the depth of the test grooves in the dicing area of power devices through process control and dynamically adjust the process time to meet the depth requirements. However, as the size gradually decreases, while meeting the morphology requirements of the functional areas, such as... Figure 3 As shown, dense, grass-like strips of silicon (silicon grass) form in the test grooves of the substrate's dicing area, leading to inaccurate depth measurements of the test grooves during process control monitoring. The only way to monitor depth is to shift from measuring the product to periodically slicing experimental wafers, resulting in significant waste of manpower and resources. Summary of the Invention
[0004] The purpose of this invention is to provide a method for forming semiconductor devices. By adding He gas to the etching gases SF6 and O2, the loading effect is changed, and the morphology of the trench etching in the substrate meets the requirements under the condition of smaller critical dimensions. The trench can be fully filled with polycrystalline silicon without voids. By adjusting and controlling the etching gas, there is no silicon straw in the test groove. The trench depth can be monitored online by measuring the depth of the test groove, eliminating the need for periodic wafer slicing, thus saving manpower and resources.
[0005] This invention provides a method for forming a semiconductor device, comprising:
[0006] A substrate is provided, the substrate including functional regions and dicing regions, and a patterned hard mask layer is formed on the substrate;
[0007] Using the hard mask layer as a mask, the substrate is etched to form a plurality of spaced trenches in the functional area of the substrate. The etching gas includes SF6, O2 and He. At the same time, a test groove is formed in the dicing area of the substrate. The test groove is free of silica.
[0008] A polycrystalline silicon layer is formed, which fills the trench.
[0009] Furthermore, the hard mask layer includes a pad oxide layer, a silicon nitride layer, and a TEOS layer sequentially located on the substrate.
[0010] Furthermore, in a cross-section perpendicular to the substrate, the cross-sectional width of the test groove is 50 to 60 times the cross-sectional width of the trench.
[0011] Furthermore, viewed from above, the test groove is rectangular or square.
[0012] Furthermore, in the same step of etching the substrate, due to the load effect, the trenches and test grooves with different cross-sectional widths are etched to different depths, and the depth of the test groove corresponds to the depth of the trench. The depth of the trench is monitored by measuring the depth of the test groove.
[0013] Furthermore, in the etching process of the substrate, the pressure is 10 mTorr to 100 mTorr; the source power is 500 W to 2000 W; the bias power is 50 W to 300 W; and the gas ratio of SF6, O2 and He is 1:0.1 to 0.3:1 to 5.
[0014] Furthermore, in the etching process of the substrate, the temperature is from -20°C to +90°C.
[0015] Furthermore, the polysilicon layer in the trench serves as the source of the transistor.
[0016] Furthermore, the polycrystalline silicon layer is formed using low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition processes.
[0017] Furthermore, in a cross-section perpendicular to the substrate, the trench has a rectangular upper section combined with a semi-circular lower section.
[0018] Compared with the prior art, the present invention has the following beneficial effects:
[0019] This invention provides a method for forming a semiconductor device, comprising: providing a substrate, the substrate including functional regions and dicing regions; forming a patterned hard mask layer on the substrate; using the hard mask layer as a mask, etching the substrate to form a plurality of spaced trenches in the functional regions of the substrate; the etching gas including SF6, O2, and He; simultaneously forming test grooves in the dicing regions of the substrate, the test grooves being free of silica spores; and forming a polysilicon layer filling the trenches. This invention adds He gas to the SF6 and O2 etching gases to change the loading effect, achieving the desired trench morphology under relatively small critical dimensions, and ensuring sufficient filling of the polysilicon layer without voids in the trenches; by adjusting and controlling the etching gas, the test grooves are free of silica spores, and the trench depth can be monitored online by measuring the depth of the test grooves, eliminating the need for periodic wafer slicing, thus saving manpower and resources. Attached Figure Description
[0020] Figure 1 This is a schematic diagram of the etching stop of a semiconductor device.
[0021] Figure 2 This is a schematic diagram of a bowl-shaped morphology formed by etching a semiconductor device.
[0022] Figure 3 This is a schematic diagram of silicon grass being formed in a test groove for a semiconductor device.
[0023] Figure 4 This is a schematic flowchart of a method for forming a semiconductor device according to an embodiment of the present invention.
[0024] Figure 5 This is a schematic diagram of forming a patterned hard mask layer for a semiconductor device according to an embodiment of the present invention.
[0025] Figure 6 This is a schematic diagram of a semiconductor device according to an embodiment of the present invention, showing trenches formed in the functional area and test grooves formed in the dicing area.
[0026] Figure 7 This is a schematic diagram illustrating the reverse side of a semiconductor device with silicon slag formed in a test recess, before improvement.
[0027] Figure 8 This is a schematic diagram illustrating an example of filling a trench with a polysilicon layer to form a void in a semiconductor device before improvement.
[0028] Figure 9 This is a schematic diagram of the front side of the semiconductor device of the present invention, showing a void-free polysilicon layer filled in the trench.
[0029] The accompanying figure is labeled as follows:
[0030] 10-Substrate; 11-Silica; 21-Pad oxide layer; 22-Silicon nitride layer; 23-TEOS layer; 30-Photoresist layer; 40-Polysilicon layer; P-Void (gap); V-Trench; C-Test groove; I-Functional area; II-Scribble area. Detailed Implementation
[0031] As described in the background section, with increasingly smaller device pitches, controlling the morphology of deep trenches becomes increasingly difficult. Further research has revealed that deep trenches under small pitch and small critical size conditions pose a significant challenge to process gases SF6 and O2. Figure 1 As shown, when SF6:O2 < 1, the excessive amount of polymer P generated due to the higher O2 content leads to the cessation of deep trench etching (within the red circle), resulting in the depth not meeting the requirements. Figure 2 As shown, when SF6:O2≥1, the sidewalls of the trenches are less likely to form polymers due to the higher SF6 content, resulting in a loss of protection for the sidewalls. Simultaneously, SF6 exhibits high selectivity for the ONO (oxide-nitride-oxide) hard mask, resulting in a bowl-shaped morphology B with a small top critical dimension and a large bottom critical dimension in the formed deep trenches.
[0032] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0033] For ease of description, some embodiments of this application may use spatially relative terms such as “above,” “below,” “top,” and “under” to describe the relationship between one element or component and another (or more) elements or components as shown in the accompanying drawings. It should be understood that, in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device during use or operation. For example, if the device in the drawings is flipped, it is described as an element or component “below” or “under” other elements or components, and will subsequently be positioned “above” or “on” other elements or components. The terms “first,” “second,” etc., used below are used to distinguish between similar elements and are not necessarily used to describe a particular order or temporal sequence. It should be understood that these terms, as used, may be replaced where appropriate.
[0034] This invention provides a method for forming a semiconductor device, such as... Figure 4 As shown, it includes:
[0035] Step S1: Provide a substrate, which includes functional regions and dicing regions, and form a patterned hard mask layer on the substrate;
[0036] Step S2: Using a hard mask layer as a mask, etch the substrate to form several spaced trenches in the functional areas of the substrate. The etching gases include SF6, O2 and He. At the same time, test grooves are formed in the dicing area of the substrate. There is no silica in the test grooves.
[0037] Step S3: Form a polycrystalline silicon layer and fill the trench with the polycrystalline silicon layer.
[0038] The steps of the method for forming a semiconductor device according to an embodiment of the present invention will be described in detail below with reference to the accompanying drawings.
[0039] Step S1, as follows Figure 5 As shown, a substrate 10 is provided, which includes functional regions and dicing regions. A patterned hard mask layer is formed on the substrate 10. The hard mask layer includes a pad oxide layer 21, a silicon nitride layer 22, and a TEOS (tetraethyl orthosilicate) layer 23 sequentially located on the substrate. A photoresist layer 30 is formed on the hard mask layer, which defines the opening regions of the patterned hard mask layer.
[0040] Step S2, as follows Figure 6 As shown, a hard mask layer is used as a mask to etch the substrate 10, forming several spaced trenches V in the functional region I of the substrate 10. The etching gases include SF6, O2 and He. At the same time, a test groove C is formed in the dicing region II of the substrate 10. There is no silica in the test groove C.
[0041] Figure 6 This is a schematic diagram of a semiconductor device according to an embodiment of the present invention, in which a trench V is formed in functional region I and a test groove C is formed in dicing region II. Figure 7 A schematic diagram illustrating the reverse side of the semiconductor device formed in the test recess C to improve upon previous semiconductor device design.
[0042] like Figure 6 As shown, in a cross-section perpendicular to the substrate 10, the cross-sectional width of the test groove C is 50 to 60 times the cross-sectional width of the trench V. Viewed from above, the test groove C is rectangular or square; for example, the test groove C is a 50μm*50μm square or a 60μm*60μm square. These are just examples; the size of the test groove C is not limited and can be set according to actual needs.
[0043] In the same etching substrate 10 step, due to the loading effect, the trenches V and test grooves C with different cross-sectional widths are etched to different depths, and the depth of the test groove C corresponds to the depth of the trench V. The depth of the trench V is monitored by measuring the depth of the test groove C. The depth of the test groove C is greater than the depth of the trench V.
[0044] In the etching process of substrate 10, the process parameters include: pressure: 10 mTorr to 100 mTorr; source power: 500 W to 2000 W, affecting plasma density; bias power: 50 W to 300 W, affecting ion bombardment energy; the gas ratio of SF6, O2, and He is in the range of 1:0.1 to 0.3:1 to 5, which affects the etching rate and etching selectivity; temperature: -20℃ to +90℃, affecting the sidewall passivation effect. SF6 etching and C4F6 passivation can be performed alternately to achieve high aspect ratio structure etching. Profile control: O2 content affects sidewall angle, and high He flow rate improves etching uniformity.
[0045] SF6 is the primary etching agent, which decomposes in plasma to generate fluorine radicals. O2 reacts with the decomposition products of SF6 to form SOF. x Substances such as O2 promote the formation of a sidewall passivation film (SiOxFy) and regulate etching anisotropy; increasing the proportion of O2 will decrease the etching rate but improve anisotropy. Helium's main functions are: a plasma stabilizer to improve discharge uniformity; a thermal conductivity medium to help dissipate heat; and process pressure regulation to improve etching profile uniformity and reduce micro-load effects.
[0046] In semiconductor manufacturing and micro / nano fabrication, etching is a crucial process for transferring mask patterns to material surfaces. The loading effect during etching manifests as variations in etching rate, uniformity, or selectivity, primarily due to differences in the area, distribution, or material properties of the etched region (load). The etching rate varies with the area of the etched pattern (load area).
[0047] In a cross-section perpendicular to the substrate 10, the cross-sectional width of the test groove C is 50 to 60 times that of the trench V. Trench V has a small opening and low load (small area etching), with sufficient reactive gas and a high etching rate. Test groove C has a large opening and high load (large area etching), resulting in rapid consumption of reactive gas and a decreased etching rate. The large opening of test groove C makes it prone to incomplete reaction between the etching gas and the substrate 10, leading to the formation of byproducts such as silicon oxide during the reaction. These byproducts hinder further etching of the substrate 10 by the etching gas, forming… Figure 7 The silica grass 11.
[0048] The etching gas of this invention includes SF6, O2, and He. Adding He gas to the SF6 and O2 etching gas alters the loading effect, allowing small-aperture trenches (V) to be etched. For large-aperture test grooves (C), by setting an appropriate gas ratio, for example, the ratio of SF6, O2, and He in the range of 1:0.1–0.3:1–5, this invention optimizes etching process parameters, adjusts gas flow rates, and increases the amount of reactive gas, such as SF6, to compensate for the consumption in high-load areas, thereby increasing the reaction amount in the test groove C area. He is an inert gas; its addition dilutes SF6 and O2, slowing down the reaction rate. This makes adjusting the SF6 and O2 ratio easier, ensuring a suitable ratio. He significantly reduces the reaction between O2 and silicon to form silica precipitates, thus eliminating silica precipitates in the test groove C while maintaining the morphology of trench V, facilitating online measurement. Figure 6 As shown, in the semiconductor device of this embodiment, a trench V is formed in functional region I, and a test groove C is formed in dicing region II. There is no silicon grass in the test groove C.
[0049] Figure 8 This is a schematic diagram of the reverse side of a semiconductor device before improvement, showing the formation of voids P by filling a polysilicon layer 40 in the trench V. The bowl-shaped morphology with a large bottom critical dimension before improvement results in insufficient filling of the subsequent polysilicon, forming gaps (voids P), which affect the subsequent etching of polysilicon, and consequently impact the yield and reliability of the finished product.
[0050] Figure 9 This is a schematic diagram illustrating the front side of the semiconductor device of the present invention with a void-free polysilicon layer 40 filled in the trench. Step S3, as follows: Figure 9 As shown, a polysilicon layer 40 is formed, which fills a trench V. The polysilicon layer 40 in the trench V serves as the source of a transistor. This invention uses an etching gas process to control the formation of trenches V with a regular morphology. The bottom of the trench V does not have an enlarged bowl-shaped morphology, and the trench can be sufficiently filled with a polysilicon layer without voids.
[0051] In summary, this invention provides a method for forming a semiconductor device, comprising: providing a substrate, the substrate including functional regions and dicing regions; forming a patterned hard mask layer on the substrate; using the hard mask layer as a mask, etching the substrate to form a plurality of spaced trenches in the functional regions of the substrate; the etching gas including SF6, O2, and He; simultaneously forming test grooves in the dicing regions of the substrate, the test grooves being free of silica spores; and forming a polysilicon layer filling the trenches. This invention adds He gas to the SF6 and O2 etching gases to change the loading effect, achieving the desired trench morphology under relatively small critical dimensions, and ensuring sufficient filling of the polysilicon layer without voids in the trenches; by adjusting and controlling the etching gas, the test grooves are free of silica spores, and the trench depth can be monitored online by measuring the depth of the test grooves, eliminating the need for periodic wafer slicing, thus saving manpower and resources.
[0052] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The methods disclosed in the embodiments are described simply because they correspond to the devices disclosed in the embodiments; relevant details can be found in the method section.
[0053] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.
Claims
1. A method for forming a semiconductor device, characterized in that, include: A substrate is provided, the substrate including functional regions and dicing regions, and a patterned hard mask layer is formed on the substrate; Using the hard mask layer as a mask, the substrate is etched to form a plurality of spaced trenches in the functional area of the substrate. The etching gas includes SF6, O2 and He. At the same time, a test groove is formed in the dicing area of the substrate. The test groove is free of silica. A polycrystalline silicon layer is formed, which fills the trench.
2. The method for forming a semiconductor device as described in claim 1, characterized in that, The hard mask layer includes a pad oxide layer, a silicon nitride layer, and a TEOS layer, which are sequentially located on the substrate.
3. The method for forming a semiconductor device as described in claim 1, characterized in that, In a cross-section perpendicular to the substrate, the cross-sectional width of the test groove is 50 to 60 times the cross-sectional width of the trench.
4. The method for forming a semiconductor device as described in claim 3, characterized in that, Viewed from above, the test groove is rectangular or square.
5. The method for forming a semiconductor device as described in claim 3, characterized in that, In the same etching step of the substrate, due to the load effect, the trenches and test grooves with different cross-sectional widths are etched to different depths, and the depth of the test groove is related to the depth of the trench. The depth of the trench is monitored by measuring the depth of the test groove.
6. The method for forming a semiconductor device as described in claim 1, characterized in that, In the etching process of the substrate, the pressure is 10 mTorr to 100 mTorr; Source power: 500W~2000W; bias power: 50W~300W; the gas ratio range of SF6, O2 and He is 1:0.1~0.3:1~5.
7. The method for forming a semiconductor device as described in claim 6, characterized in that, In the etching process of the substrate, the temperature is -20°C to +90°C.
8. The method for forming a semiconductor device as described in claim 1, characterized in that, The polysilicon layer in the trench serves as the source of the transistor.
9. The method for forming a semiconductor device as claimed in claim 1, characterized in that, The polycrystalline silicon layer is formed using low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition processes.
10. The method for forming a semiconductor device as claimed in claim 1, characterized in that, In a cross-section perpendicular to the substrate, the trench has a rectangular upper section combined with a semi-circular lower section.