Semiconductor structure and forming method thereof
By employing processes such as ring implantation, lightly doped drain implantation, and source/drain implantation in semiconductor structures, combined with etching and annealing, the problem of substrate depressions affecting doping distribution and depth is solved, achieving uniformity and performance stability of the doped region, and reducing hot carrier effect and breakthrough effect.
Patent Information
- Application Number
- CN202511090494.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2025-03-04
- Filing Date
- 2025-08-05
- Publication Date
- 2025-11-11
AI Technical Summary
In semiconductor structures, tiny depressions on the substrate affect the distribution and depth of implantation, leading to unstable performance. Existing technologies struggle to achieve uniform doping distribution and depth.
After forming the gate structure on the substrate, a dielectric material is conformally deposited, and processes such as ring implantation, lightly doped drain implantation, and source/drain implantation are performed. Combined with etching and annealing processes, a uniform doped region is formed to ensure the flatness of the substrate surface and the uniformity of the doping distribution.
It achieves uniform distribution and depth control of doped regions in semiconductor structures, reduces hot carrier effects and breakdown effects, and improves the stability of drain-source current and the uniformity of doped regions.
Smart Images
Figure CN120933227A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor structure and a method for forming the same. Background Technology
[0002] Due to the reduction in the length of semiconductor structures, implantation processes are used to reduce the hot carrier effect and punch-through effect. However, even tiny depressions on the substrate can affect the distribution and depth of implantation, thereby affecting the performance stability of the semiconductor structure.
[0003] Therefore, a method capable of achieving a uniform distribution and depth of implantation is of importance in this field. Summary of the Invention
[0004] This invention provides a method for forming a semiconductor structure, including forming a gate structure on a substrate, conformally depositing a first dielectric material on the gate structure and the substrate, performing a first implantation process to implant a first dopant into the substrate to form a first doped region in the substrate, wherein the top surface of the substrate is uniform. The method further includes performing a second implantation process to implant a second dopant into the substrate to form a second doped region in the substrate, the second dopant being the opposite of the first dopant, wherein the top surface of the substrate is uniform. The method further includes depositing a second dielectric material on the first dielectric material, etching portions of the first dielectric material, the second dielectric material, and the substrate to form a recess in the substrate, performing a third implantation process to implant a third dopant into the recess in the substrate to form a third doped region in the substrate, wherein the third dopant is the same as the second dopant, and performing an annealing process on the substrate.
[0005] In some embodiments, the first implantation process includes HALO implantation with an angle, and the second implantation process includes light doped drain (LDD).
[0006] In some embodiments, angle implantation is performed at an angle to the sidewall of the gate structure, and the angle is between 12° and 22°.
[0007] In some embodiments, the first doped region extends into the region beneath the gate structure.
[0008] In some embodiments, the doping concentration of the first dopant species in the first doped region is from 1.0E14 to 8.0E14 cm⁻¹. 2 Within the range.
[0009] In some embodiments, the doping concentration of the second doping species in the second doped region is from 1.0E15 to 6.0E15 cm⁻¹.2 Within the range.
[0010] In some embodiments, the doping concentration of the third dopant species in the third doped region is from 2.0E15 to 9.0E15 cm⁻¹. 2 Within the range.
[0011] In some embodiments, the third implantation process includes source / drain implantation.
[0012] In some embodiments, etching portions of the first dielectric material, the second dielectric material, and the substrate to form a recess in the substrate includes removing horizontal portions of the first and second dielectric materials above the top surface of the gate structure, and partially removing another horizontal portion of the first and second dielectric materials on the substrate, thereby exposing the top surface of the gate structure.
[0013] In some embodiments, etching portions of the first dielectric material, the second dielectric material, and the substrate to form a recess in the substrate further includes removing portions of the second doped region.
[0014] This invention provides a semiconductor structure including a gate structure, spacers, a second dielectric layer, a recess, a first doped region, a second doped region, and a third doped region. The gate structure is on a substrate. Each spacer includes a first portion along a sidewall of the gate structure and a second portion on the substrate connecting the endpoints of the first portion. The second dielectric layer is on the spacers and adjacent to the first and second portions. The recess is exposed on the top of the substrate and laterally surrounds the gate structure, spacers, and second dielectric layer. The first doped region is in the substrate and has a first doping class, including a width between the top and bottom surfaces of the first doped region ranging from 18.2 nm to 33.8 nm, a distance between the top surface of the first doped region and the top surface of the substrate ranging from 16.1 nm to 23.9 nm, a distance between the bottom surface of the first doped region and the top surface of the substrate ranging from 42.1 nm to 49.9 nm, and a maximum doping concentration at a depth below the top surface of the substrate ranging from 30 nm to 36 nm. The second doped region is located in the substrate below the second portion and has a second doping type opposite to the first doping type. It includes a width between the top and bottom surfaces of the second doped region ranging from 1.6 nm to 2.8 nm, a distance between the top surface of the second doped region and the top surface of the substrate ranging from 1.6 nm to 2.2 nm, a distance between the bottom surface of the second doped region and the top surface of the substrate ranging from 3.8 nm to 4.4 nm, and a maximum doping concentration at a depth below the top surface of the substrate ranging from 2.75 nm to 3.25 nm. A third doped region is located in the substrate below the recess and has a third doping type, wherein the third doped region partially overlaps with the first doped region.
[0015] In some embodiments, the doping concentration of the first doped region gradually decreases from the depth to the top surface of the first doped region; and wherein the doping concentration of the first doped region gradually decreases from the depth to the bottom surface of the first doped region.
[0016] In some embodiments, the recess is located in the range of 6 nm to 10 nm from the top surface of the substrate.
[0017] In some embodiments, the third doped region includes a width between the top and bottom surfaces of the third doped region, the width being in the range of 8 nm to 24 nm; a distance between the top surface of the third doped region and the top surface of the substrate, the distance being in the range of 7.5 nm to 15.5 nm; a distance between the bottom surface of the third doped region and the top surface of the substrate, the distance being in the range of 23.5 nm to 31.5 nm; and a maximum doping concentration at a depth below the top surface of the substrate, the depth being in the range of 16 nm to 20 nm.
[0018] In some embodiments, the first part and the second part are L-shaped.
[0019] In some embodiments, the semiconductor structure includes an NMOS transistor, the first doping type includes p-type doping, the second doping type includes n-type doping, and the third doping type includes n-type doping.
[0020] It should be understood that the foregoing general description and the following detailed description are by way of example and are intended to provide further explanation of the claimed disclosure. Attached Figure Description
[0021] A more complete understanding of the present invention can be obtained by reading the following embodiments and the detailed description in conjunction with the accompanying drawings:
[0022] Figures 1 to 7 This is a cross-sectional view of a method for forming a semiconductor device at various stages according to some embodiments of the present invention. Detailed Implementation
[0023] Embodiments of the present invention will now be described in detail, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.
[0024] See Figure 1The method begins at step S10. A substrate 100 is provided. A gate structure 102 is formed on the substrate 100. The gate structure 102 includes a conductive stack 104 and a capping layer 106 on the conductive stack 104. The conductive stack 104 may be a single layer, a double layer, or a multilayer, and the material of the conductive stack 104 may be polysilicon, copper (Cu), tungsten (W), titanium (Ti), etc. In some embodiments, the conductive stack 104 may include polysilicon and a metal layer on the polysilicon. In some embodiments, the gate structure 102 is a high-k metal gate, and an additional high-k dielectric layer (not shown), such as HfO2, may be formed between the substrate 100 and the conductive stack 104 of the gate structure 102. In some embodiments, the material of the capping layer 106 may include silicon nitride.
[0025] After the gate structure 102 is formed, a first dielectric material 108 is conformally deposited on the substrate 100 and the gate structure 102. The first dielectric material 108 may extend along the top surface and sidewalls of the gate structure 102 and the top surface of the substrate 100. The first dielectric material 108 may be formed by any suitable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc. In some embodiments, the material of the first dielectric material 108 may include silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, low dielectric constant dielectric materials and / or any suitable insulating material to protect the gate structure 102.
[0026] See Figure 2 The method proceeds to step S20. A first implantation process, such as a HALO implantation process, is performed to implant a first dopant species into the substrate 100 through the first dielectric material 108, and a first doped region 110 is formed in the substrate 100. In some embodiments, a photoresist layer or hard masking layer (not shown) may be formed on the gate structure 102 and prevent the gate structure 102 from being implanted during the first implantation process. The HALO implantation process with angled implantation results in the formed first doped region 110 extending laterally in the substrate 100 below the gate structure 102. A HALO implantation process with an angle θ to the sidewalls of the gate structure 102 may be performed, and the angle θ is from 12° to 22°. In some embodiments, the doping concentration of the first dopant species in the first doped region 110 may be from 1.0E14 cm⁻¹. 2 up to 8.0E14 cm 2 Within the range.
[0027] It should be noted that the top surface of the substrate 100 remains flat and / or uniform without additional etching processes, and the distribution and depth of the first doped regions 110 can be uniform. Furthermore, the first dielectric material 108 along the sidewalls of the gate structure 102 and the top surface of the substrate 100 can be L-shaped rather than irregularly angled, resulting in a uniform distribution of the first doped regions 110. In some embodiments, the semiconductor structure has an n-type metal-oxide-semiconductor field-effect transistor (NMOSFET), and the first doping type may include p-type doping, such as boron (B). In some embodiments, the semiconductor structure has a p-type metal-oxide-semiconductor field-effect transistor (PMOSFET), and the first doping type may include n-type doping, such as phosphorus (P).
[0028] See Figure 3 The method proceeds to step S30. A second implantation process, such as a light-doped drain implantation process, is performed to implant a second dopant species into the substrate 100 through the first dielectric material 108, and a second doped region 112 is formed in the substrate 100, the second dopant species being the opposite of the first dopant species. The second doped region 112 in the substrate 100 includes an implantation distribution and dopant species different from the first doped region 110. In some embodiments, a photoresist layer or hard mask layer (not shown) may be formed on the gate structure 102 and prevent the gate structure 102 from being implanted during the second implantation process. The light-doped drain implantation process may be performed perpendicular to the substrate 100. The gate structure 102 may act as a mask such that the second doped region 112 is not located below the gate structure 102. Therefore, the second doped region 112 may be distributed near the top surface of the substrate 100 and around the gate structure 102. In some embodiments, the doping concentration of the second dopant species in the second doped region 112 may be from 1.0E15 cm⁻¹. 2 Up to 6.0E15 cm 2 Within the range.
[0029] It should be noted that the top surface of substrate 100 remains flat and / or uniform without additional etching processes, which reduces the risk of lateral scattering during lightly doped drain implantation processes, thereby achieving a shallow junction without lateral scattering. In some embodiments, the semiconductor structure has an n-type metal-oxide-semiconductor field-effect transistor (NMOSFET), and the second doping type may include n-type doping, such as phosphorus (P). In some embodiments, the semiconductor structure has a p-type metal-oxide-semiconductor field-effect transistor (PMOSFET), and the second doping type may include p-type doping, such as boron (B).
[0030] A ring implantation process and a lightly doped drain implantation process are used to prevent the hot carrier effect and the punch-through effect. (As described in this invention...) Figure 2 and Figure 3 During the operation of the ring implantation process and the lightly doped drain implantation process described herein, the top surface of the substrate 100 is flat and / or uniform without additional etching processes, resulting in a uniform distribution and depth of doping, further improving the stability of the drain-source currents (IDs). Furthermore, performing the lightly doped drain implantation process on such a flat and / or uniform surface of the substrate 100 allows for shallow junctions without lateral scattering.
[0031] See Figure 4 The method proceeds to step S40. A second dielectric material 114 is conformally deposited on the first dielectric material 108. The second dielectric material 114 may cover the first dielectric material 108 and the gate structure 102. The second dielectric material 114 can be used to define the distance outward from the sidewall of the gate structure 102 for subsequent source / drain implantation. This distance for subsequent source / drain implantation may vary according to process requirements. The second dielectric material 114 may be formed by any suitable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc. In some embodiments, the second dielectric material 114 may include silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), high dielectric constant dielectric materials, and / or any suitable dielectric material.
[0032] See Figure 5 The method proceeds to step S50. An etching process is performed to remove the first dielectric material 108 (e.g., ...). Figure 4 (as shown), second dielectric material 114 (as shown) Figure 4The recess 124 is formed by removing portions of the first dielectric material 108 and the second dielectric material 114 above the gate structure 102 to expose the top surface of the gate structure 102, and partially removing other lateral portions of the first dielectric material 108 and the second dielectric material 114 above the substrate 100 to expose portions of the top surface of the substrate 100, thereby forming the recess 124 in the substrate 100 with the exposed top surface. The etching process can be performed by any suitable process, such as dry etching and / or wet etching. In some embodiments, the top surface of the gate structure 102 is coplanar with the top surface of the retained first dielectric material 108. In some embodiments, the recess 124 may have a depth d1 from the top surface S0 of the substrate 100, and the depth d1 is in the range of 6 nm to 10 nm.
[0033] The retained first dielectric material 108 may serve as spacers 116. Each spacer 116 includes a first portion 118 along the sidewall of the gate structure 102 and a second portion 120 along the top surface S0 of the substrate 100 and connecting the endpoints of the first portion 118. In some embodiments, the first portion 118 and the second portion 120 are L-shaped. The retained second dielectric material 114 may serve as a second dielectric layer 122. The second dielectric layer 122 is on the spacers 116 and adjacent to the first portion 118 and the second portion 120 of the spacers 116. The second dielectric layer 122 may also laterally surround the gate structure 102 and the first portion 118 of the spacers 116.
[0034] After the etching process is performed, the recess 124 in the top of the substrate 100 may laterally surround the gate structure 102, the spacer 116, and the second dielectric layer 122. Since the second doped region 112 is located near the top surface S0 of the substrate 100, the formation of the recess 124 may further remove a portion of the second doped region 112, such that the remaining second doped region 112 may be located below the second portion 120 of the spacer 116.
[0035] See Figure 6The method proceeds to step S60. A third implantation process, such as source / drain implantation, is performed to implant a third dopant into the recess 124 in the substrate 100, and a third doped region 126 is formed in the substrate 100. The third dopant is the same as the second dopant. The second dielectric layer 122 and the gate structure 102 can serve as protective layers to prevent the region below the second dielectric layer 122 and the gate structure 102 from being implanted during source / drain implantation. The second dielectric layer 122 can further define a distance D1 to determine the lateral distance between the sidewall of the gate structure 102 and the third doped region 126. The distance D1 can vary according to process requirements. The third doped region 126 can be distributed in the substrate 100 below the recess 124 and laterally surrounds the gate structure 102, the spacer 116, and the second dielectric layer 122. In some embodiments, the doping concentration of the third dopant in the third doped region 126 can be from 2.0E15 cm⁻¹. 2 Up to 9.0E15 cm 2 Within the range.
[0036] It should be noted that after one etching process (such as...) Figure 5 The substrate 100 (described herein) may include a recess 124 having a slightly uniform bottom surface, which is beneficial for the depth of the source / drain implantation process. In some embodiments, the semiconductor structure has an n-type metal-oxide-semiconductor field-effect transistor (NMOSFET), and the third doping type may include an n-type dopant, such as phosphorus (P). In some embodiments, the semiconductor structure has a p-type metal-oxide-semiconductor field-effect transistor (PMOSFET), and the third doping type may include a p-type dopant, such as boron (B).
[0037] See Figure 7The method proceeds to step S70. An annealing process is performed. After the annealing process, the first doped region 110 may have a top surface S1 and a bottom surface S2, and a width W1 is between the top surface S1 and the bottom surface S2 of the first doped region 110. In some embodiments, for example, the width W1 is in the range of 18.2 nm to 33.8 nm. The first doped region 110 has a distance D3 between the top surface S1 of the first doped region 110 and the top surface S0 of the substrate 100, and the distance D3 is in the range of 16.1 nm to 23.9 nm. The first doped region 110 has a distance D4 between the bottom surface S2 of the first doped region 110 and the top surface S0 of the substrate 100, and the distance D4 is in the range of 42.1 nm to 49.9 nm. Each first doped region 110 has the highest doping concentration at a depth d2 below the top surface S0 of the substrate 100, and the depth d2 is in the range of 30 nm to 36 nm. The doping concentration of the first doped region 110 gradually decreases from depth d2 to the top surface S1 of the first doped region 110, and also gradually decreases from depth d2 to the bottom surface S2 of the first doped region 110. In some embodiments, for example, the highest doping concentration of the first doped region 110 is at a depth d2 of 33 nm from the top surface S0 of the substrate 100, and the doping distribution of the first doped region 110 may be distributed at a depth within a range of 33 ± 13 nm from the top surface S0 of the substrate 100. In other words, the distance D3 between the top surface S1 of the first doped region 110 and the top surface S0 of the substrate 100 is approximately 20 nm, and the distance D4 between the bottom surface S2 of the first doped region 110 and the top surface S0 of the substrate 100 is approximately 46 nm. The doping concentration of the first doped region 110 gradually decreases from a depth d2 of 33 nm from the top surface S0 of the substrate 100 to the top surface S1 of the first doped region 110 (e.g., at a distance D3 of 20 nm from the top surface S0 of the substrate 100), and the doping concentration of the first doped region 110 gradually decreases from a depth d2 of 33 nm from the top surface S0 of the substrate 100 to the bottom surface S2 of the first doped region 110 (e.g., at a distance D4 of 46 nm from the top surface S0 of the substrate 100). Due to the angular implantation of the ring implantation process, the first doped region 110 extends further by a distance D2 to the region below the gate structure 102. For example, the distance D2 is in the range of 4.3 nm to 18.6 nm from the sidewall of the first portion 118 of the spacer 116.
[0038] After the annealing process, the second doped region 112 may have a top surface S3 and a bottom surface S4, and a width W2 is between the top surface S3 and the bottom surface S4 of the second doped region 112. In some embodiments, for example, the width W2 is in the range of 1.6 nm to 2.8 nm. The second doped region 112 has a distance D5 between the top surface S3 of the second doped region 112 and the top surface S0 of the substrate 100, and the distance D5 is in the range of 1.6 nm to 2.2 nm. The second doped region 112 has a distance D6 between the bottom surface S4 of the second doped region 112 and the top surface S0 of the substrate 100, and the distance D6 is in the range of 3.8 nm to 4.4 nm. Each second doped region 112 has the highest doping concentration at a depth d3 below the top surface S0 of the substrate 100, and the depth d3 is in the range of 2.75 nm to 3.25 nm. The doping concentration of the second doped region 112 gradually decreases from depth d3 to the top surface S3 of the second doped region 112, and also gradually decreases from depth d3 to the bottom surface S4 of the second doped region 112. In some embodiments, for example, the highest doping concentration of the second doped region 112 is at a depth d3 of 3 nm from the top surface S0 of the substrate 100, and the doping distribution of the second doped region 112 can be distributed at a depth ranging from 3 ± 1.1 nm from the top surface S0 of the substrate 100. In other words, the distance D5 between the top surface S3 of the second doped region 112 and the top surface S0 of the substrate 100 is approximately 1.9 nm, and the distance D6 between the bottom surface S4 of the second doped region 112 and the top surface S0 of the substrate 100 is approximately 4.1 nm. The doping concentration of the second doped region 112 gradually decreases from a depth d3 of 3 nm from the top surface S0 of the substrate 100 to the top surface S3 of the second doped region 112 (e.g., at a distance D5 of 1.9 nm from the top surface S0 of the substrate 100), and the doping concentration of the second doped region 112 gradually decreases from a depth d3 of 3 nm from the top surface S0 of the substrate 100 to the bottom surface S4 of the second doped region 112 (e.g., at a distance D6 of 4.1 nm from the top surface S0 of the substrate 100).
[0039] After the annealing process, the third doped region 126 may have a top surface S5 and a bottom surface S6, and a width W3 is between the top surface S5 and the bottom surface S6 of the third doped region 126. In some embodiments, for example, the width W3 is in the range of 8 nm to 24 nm. The third doped region 126 has a distance D7 between the top surface S5 of the third doped region 126 and the top surface S0 of the substrate 100, and the distance D7 is in the range of 7.5 nm to 15.5 nm. The third doped region 126 has a distance D8 between the bottom surface S6 of the third doped region 126 and the top surface S0 of the substrate 100, and the distance D8 is in the range of 23.5 nm to 31.5 nm. Each third doped region 126 has the highest doping concentration at a depth d4 below the top surface S0 of the substrate 100, and the depth d4 is in the range of 16 nm to 20 nm. The doping concentration of the third doped region 126 gradually decreases from depth d4 to the top surface S5 of the third doped region 126, and also gradually decreases from depth d4 to the bottom surface S6 of the third doped region 126. In some embodiments, for example, the highest doping concentration of the third doped region 126 is at a depth d4 of 18 nm from the top surface S0 of the substrate 100, and the doping distribution of the third doped region 126 may be distributed at a depth ranging from 18 ± 8 nm from the top surface S0 of the substrate 100. In other words, the distance D7 between the top surface S5 of the third doped region 126 and the top surface S0 of the substrate 100 is approximately 10 nm, and the distance D8 between the bottom surface S6 of the third doped region 126 and the top surface S0 of the substrate 100 is approximately 26 nm. The doping concentration of the third doped region 126 gradually decreases from a depth d4 of 18 nm from the top surface S0 of the substrate 100 to the top surface S5 of the third doped region 126 (e.g., at a distance D7 of 10 nm from the top surface S0 of the substrate 100), and the doping concentration of the third doped region 126 gradually decreases from a depth d4 of 18 nm from the top surface S0 of the substrate 100 to the bottom surface S6 of the third doped region 126 (e.g., at a distance D8 of 26 nm from the top surface S0 of the substrate 100). The first doped region 110 and the third doped region 126 partially overlap.
[0040] The first doped region 110 includes a first doping type, the second doped region 112 includes a second doping type, the second doping type being the opposite of the first doping type, and the third doped region 126 includes a third doping type, the third doping type being the same as the second doping type. In some embodiments, the semiconductor structure has an n-type metal-oxide-semiconductor field-effect transistor (NMOSFET), and the first doped region 110, the second doped region 112, and the third doped region 126 may respectively include p-type doping, n-type doping, and n-type doping. On the other hand, the semiconductor structure has a p-type metal-oxide-semiconductor field-effect transistor (PMOSFET), and the first doped region 110, the second doped region 112, and the third doped region 126 may respectively include n-type doping, p-type doping, and p-type doping.
[0041] Although the invention has been described in considerable detail with reference to certain embodiments, other embodiments may also be possible. Therefore, the spirit and scope of the appended claims should not be limited to the embodiments described herein.
[0042] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of this invention without departing from the scope or spirit of the invention. In view of the foregoing, this invention is intended to cover modifications and variations falling within the scope of the appended claims.
[0043] [Symbol Explanation]
[0044] 100:Substrate
[0045] 102: Gate Structure
[0046] 104: Conductive Stack
[0047] 106: Cap layer
[0048] 108: First Dielectric Material
[0049] 110: First doped region
[0050] 112: Second doped region
[0051] 114: Second dielectric material
[0052] 116: Spacer
[0053] 118: Part One
[0054] 120: Part Two
[0055] 122: Second dielectric layer
[0056] 124: Depression
[0057] 126: Third doped region
[0058] d1: Depth
[0059] d2: Depth
[0060] d3: Depth
[0061] d4: Depth
[0062] D1: Distance
[0063] D2: Distance
[0064] D3: Distance
[0065] D4: Distance
[0066] D5: Distance
[0067] D6: Distance
[0068] D7: Distance
[0069] D8: Distance
[0070] W1: Width
[0071] W2: Width
[0072] W3: Width
[0073] S0: Top surface
[0074] S1: Top surface
[0075] S2: Bottom surface
[0076] S3: Top surface
[0077] S4: Bottom surface
[0078] S5: Top surface
[0079] S6: Bottom surface
[0080] S10: Steps
[0081] S20: Steps
[0082] S30: Steps
[0083] S40: Steps
[0084] S50: Steps
[0085] S60: Steps
[0086] S70: Steps.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A gate structure is formed on the substrate; A first dielectric material is conformally deposited on the gate structure and the substrate; A first implantation process is performed to implant a first dopant into the substrate to form a first doped region in the substrate, wherein the top surface of the substrate is uniform. A second implantation process is performed to implant a second dopant into the substrate to form a second doped region in the substrate, the second dopant being the opposite of the first dopant, wherein the top surface of the substrate is uniform. Deposit a second dielectric material on the first dielectric material; Etch the first dielectric material, the second dielectric material, and a portion of the substrate to form a plurality of recesses in the substrate; A third implantation process is performed to implant a third doping type into the plurality of recesses in the substrate to form a third doped region in the substrate, wherein the third doping type is the same as the second doping type. as well as An annealing process is performed on the substrate.
2. The method according to claim 1, wherein the first implantation process includes annular implantation with an angle, and the second implantation process includes lightly doped drain implantation.
3. The method of claim 2, wherein the angle implantation is performed at an angle to the sidewall of the gate structure, and the angle is between 12° and 22°.
4. The method of claim 3, wherein the first doped region extends into the region beneath the gate structure.
5. The method of claim 1, wherein the doping concentration of the first dopant species in the first doped region is from 1.0E14 to 8.0E14 cm⁻¹. 2 Within the range.
6. The method of claim 1, wherein the doping concentration of the second dopant species in the second doped region is from 1.0E15 to 6.0E15 cm⁻¹. 2 Within the range.
7. The method of claim 1, wherein the doping concentration of the third dopant species in the third doped region is from 2.0E15 to 9.0E15 cm⁻¹. 2 Within the range.
8. The method of claim 1, wherein the third implantation process includes source / drain implantation.
9. The method of claim 1, wherein etching the portions of the first dielectric material, the second dielectric material, and the substrate to form the plurality of recesses in the substrate comprises: Remove a horizontal portion of the first dielectric material and the second dielectric material above the top surface of the gate structure, and partially remove another horizontal portion of the first dielectric material and the second dielectric material on the substrate, thereby exposing the top surface of the gate structure.
10. The method of claim 1, wherein etching the portions of the first dielectric material, the second dielectric material, and the substrate to form the plurality of recesses in the substrate further comprises removing a portion of the second doped region.
11. A semiconductor structure, characterized in that, include: The gate structure is on the substrate; Multiple spacers, each spacer comprising: The first portion, along the sidewall of the gate structure; and The second part is on the substrate and connects to the endpoint of the first part; A second dielectric layer is disposed on the plurality of spacers and adjacent to the plurality of first portions and the plurality of second portions; Multiple recesses are exposed on the top of the substrate and laterally surround the gate structure, the multiple spacers, and the second dielectric layer; The first doped region, located in the substrate and having a first doping type, includes: The width between the top and bottom surfaces of the first doped region, wherein the width is in the range of 18.2 nm to 33.8 nm; The distance between the top surface of the first doped region and the top surface of the substrate is in the range of 16.1 nm to 23.9 nm; The distance between the bottom surface of the first doped region and the top surface of the substrate, the distance being in the range of 42.1 nm to 49.9 nm; and The highest doping concentration at a depth below the top surface of the substrate, the depth being in the range of 30 nm to 36 nm; The second doped region, located in the substrate below the second portion and having a second doped type opposite to the first doped type, includes: The width between the top and bottom surfaces of the second doped region, wherein the width is in the range of 1.6 nm to 2.8 nm; The distance between the top surface of the second doped region and the top surface of the substrate is in the range of 1.6 nm to 2.2 nm; The distance between the bottom surface of the second doped region and the top surface of the substrate, the distance being in the range of 3.8 nm to 4.4 nm; and The highest doping concentration at a depth below the top surface of the substrate, the depth being in the range of 2.75 nm to 3.25 nm; and A third doped region is located in the substrate beneath the plurality of recesses and has a third doping type, wherein the third doped region partially overlaps with the first doped region.
12. The semiconductor structure of claim 11, wherein the doping concentration of the first doped region gradually decreases from the depth to the top surface of the first doped region; and wherein the doping concentration of the first doped region gradually decreases from the depth to the bottom surface of the first doped region.
13. The semiconductor structure of claim 11, wherein the plurality of recesses are located in the range of 6 nm to 10 nm from the top surface of the substrate.
14. The semiconductor structure of claim 11, wherein the third doped region comprises: The width between the top and bottom surfaces of the third doped region, wherein the width is in the range of 8 nm to 24 nm; The distance between the top surface of the third doped region and the top surface of the substrate is in the range of 7.5 nm to 15.5 nm; The distance between the bottom surface of the third doped region and the top surface of the substrate is in the range of 23.5 nm to 31.5 nm; as well as The highest doping concentration at a depth below the top surface of the substrate, the depth being in the range of 16 nm to 20 nm.
15. The semiconductor structure of claim 11, wherein the first portion and the second portion are L-shaped.
16. The semiconductor structure of claim 11, wherein the semiconductor structure comprises an NMOS transistor, the first doping type comprises p-type doping, the second doping type comprises n-type doping, and the third doping type comprises n-type doping.