Semiconductor structure and forming method thereof
By forming deep trenches between active regions using a self-aligned process, and employing high etching selectivity dielectric and sacrificial layer etching techniques, the problems of deep trench position misalignment and dimensional inaccuracy are solved, thereby improving device reliability.
Patent Information
- Application Number
- CN202410565215.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-08
- Publication Date
- 2025-11-11
AI Technical Summary
In advanced technology nodes, the increased density of metal interconnects leads to limitations in the wiring size on the front side of the wafer. Existing processes are prone to positional shifts or dimensional inaccuracies when etching deep trenches, which can damage the structure of adjacent active regions and affect device reliability.
A self-aligned process is used to define the first trench by depositing a sacrificial layer. The high etch selectivity of the dielectric layer and the sacrificial layer ensures etching accuracy and forms a second trench aligned with the first trench, protecting the active region from damage.
This improves the process window for forming deep trenches between active regions, avoids damage to the active region structure, and enhances device reliability.
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Figure CN120933232A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology
[0002] Metal interconnects are a crucial part of semiconductor manufacturing processes. In advanced technology nodes, the size of front-side wiring is severely limited due to increased metal interconnect density. Back-side Power Deliverable Network (BSPDN) technology places signal lines on the front side of the wafer and power lines on the back side to save wiring space and reduce power line resistance and signal line coupling noise.
[0003] When arranging signal lines on the front side, deep trenches need to be etched between the active areas to form a metal interconnect structure. In current processes, the process window for etching deep trenches is very small, which can easily lead to trench misalignment or excessive or insufficient size, thereby damaging the adjacent active area structure.
[0004] Therefore, it is necessary to provide a more effective and reliable technical solution to improve the process window for forming deep trenches, avoid damage to the active region structure, and improve device reliability. Summary of the Invention
[0005] This application provides a semiconductor structure and a method for forming the same, which can improve the process window for forming deep trenches between active regions, avoid damage to the active region structure, and improve device reliability.
[0006] One aspect of this application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, the semiconductor substrate including a plurality of alternately distributed first regions and second regions, the surface of the semiconductor substrate in the first regions including active regions, the surface of the semiconductor substrate in the second regions having a first dielectric layer formed thereon, the top surface of the first dielectric layer being lower than the top surface of the active regions; forming a sacrificial layer on the sidewalls and top surface of the active regions above the top surface of the first dielectric layer, the sacrificial layer defining a first trench between adjacent active regions; forming a patterned photoresist layer on the semiconductor substrate, the patterned photoresist layer covering the first dielectric layer and the sacrificial layer and exposing a portion of the first trench; etching the first dielectric layer at the bottom of the exposed portion of the first trench into the semiconductor substrate to form a second trench, wherein the etching rate of the first dielectric layer is greater than the etching rate of the sacrificial layer; and removing the patterned photoresist layer.
[0007] In some embodiments of this application, the material of the first dielectric layer is silicon oxide, the material of the sacrificial layer is silicon nitride, and the etchant used in the etching process for etching the exposed portion of the first dielectric layer at the bottom of the first trench to form a second trench in the semiconductor substrate includes any one or more of CF4, HBr, O2, Cl2, and CH2F2.
[0008] In some embodiments of this application, a protective layer is also formed on the sidewalls and top surface of the active region, and the sacrificial layer is located on the surface of the protective layer.
[0009] In some embodiments of this application, when the first dielectric layer at the bottom of the exposed portion of the first trench is etched into the semiconductor substrate to form a second trench, the projection of the second trench onto the first trench in the vertical direction coincides.
[0010] In some embodiments of this application, the method for forming the semiconductor structure further includes: forming a metal interconnect structure in the second trench.
[0011] In some embodiments of this application, after forming a metal interconnect structure in the second trench, the method for forming the semiconductor structure further includes removing the sacrificial layer.
[0012] Another aspect of this application provides a semiconductor structure formed by the semiconductor structure formation method described above, comprising: a semiconductor substrate, the semiconductor substrate including a plurality of alternately distributed first regions and second regions, the surface of the semiconductor substrate in the first region including an active region, the surface of the semiconductor substrate in the second region having a first dielectric layer formed thereon, the top surface of the first dielectric layer being lower than the top surface of the active region; and a second trench penetrating a portion of the first dielectric layer in the second region and extending into the semiconductor substrate.
[0013] In some embodiments of this application, the material of the first dielectric layer is silicon oxide.
[0014] In some embodiments of this application, a protective layer is also formed on the sidewalls and top surface of the active region, and the sacrificial layer is located on the surface of the protective layer.
[0015] In some embodiments of this application, a metal connection structure is formed in the second trench.
[0016] This application provides a semiconductor structure and a method for forming the same, which can improve the process window for forming deep trenches between active regions, avoid damage to the active region structure, and improve device reliability. Attached Figure Description
[0017] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale.
[0018] in:
[0019] Figures 1 to 7 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to some embodiments of this application. Detailed Implementation
[0020] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.
[0021] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.
[0022] Figures 1 to 7 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to some embodiments of this application. The method for forming a semiconductor structure according to some embodiments of this application will be described in detail below with reference to the accompanying drawings.
[0023] refer to Figure 1 As shown, a semiconductor substrate 100 is provided, the semiconductor substrate 100 including a plurality of alternately distributed first regions 101 and second regions 102, the surface of the semiconductor substrate 100 in the first region 101 includes an active region 110, and the surface of the semiconductor substrate 100 in the second region 102 is formed with a first dielectric layer 120, the top surface of the first dielectric layer 120 being lower than the top surface of the active region 110.
[0024] In some embodiments of this application, the material of the semiconductor substrate 100 includes (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) combinations thereof.
[0025] In some embodiments of this application, the active region 110 is used to form an active device, such as a MOSFET or a FinFET. (See reference...) Figure 1 As shown, since the active region 110 can be used to form any transistor structure, the detailed structure of the active region 110 is omitted for simplicity, and is only illustrated in blocks. However, those skilled in the art, based on common knowledge, should be able to understand the detailed structure of the corresponding active region 110 and subsequent fabrication processes once the type of active device in the active region 110 is determined. For example, if the active region 110 is used for a MOSFET, the corresponding active region 110 can form structures such as gate, source, and drain. If the active region 110 is used to form a FIFET, the corresponding active region 110 may include a fin structure, with the gate and source / drain subsequently formed.
[0026] In some embodiments of this application, the material of the first dielectric layer 120 includes silicon oxide. The first dielectric layer 120 is used to isolate adjacent active regions 110.
[0027] In some embodiments of this application, the sidewalls and top surface of the active region 110 are further provided with a protective layer 111 for protecting the active region 110 in subsequent processes.
[0028] refer to Figure 2 As shown, a sacrificial layer 130 is formed on the sidewalls and top surface (e.g., the surface of the protective layer 111) of the active region 110 above the top surface of the first dielectric layer 120, and the sacrificial layer 130 defines a first trench 131 between adjacent active regions 110.
[0029] In some embodiments of this application, the sacrificial layer 130 is made of silicon nitride. Methods for forming the sacrificial layer 130 include deposition processes with strong conformal properties and high film density, such as atomic layer deposition (ALD).
[0030] In some embodiments of this application, the width of the first trench 131 can be set according to design requirements. The width of the first trench 131 can be controlled by the thickness of the sacrificial layer 130.
[0031] In conventional processes, defining the position and size of the first trench solely through photoresist layer exposure and development in photolithography can easily lead to trench misalignment or excessively large or small dimensions, thereby damaging adjacent active area structures during subsequent etching. In the technical solution of this application, a self-aligned approach is adopted, using a sacrificial layer 130 to define the first trench 131 in a self-aligned manner. This ensures the precise position and size of the first trench 131, and the sacrificial layer 130 also protects the active area 110 from damage during subsequent etching, improving device reliability.
[0032] refer to Figure 3 As shown, a patterned photoresist layer 140 is formed on the semiconductor substrate 100. The patterned photoresist layer 140 covers the first dielectric layer 120 and the sacrificial layer 130 and exposes a portion of the first trench 131. The location of the exposed portion of the first trench 131 is determined according to design requirements and is not limited in this application. Since the first trench 131 is defined by the sacrificial layer 130, the process window of the patterned photoresist layer 140 can be increased.
[0033] refer to Figure 4 As shown, the first dielectric layer 120 at the bottom of the exposed portion of the first trench 131 is etched into the semiconductor substrate 100 to form a second trench 132, wherein the etching rate of the first dielectric layer 120 is greater than the etching rate of the sacrificial layer 130. Specifically, the etch selectivity ratio of the first dielectric layer 120 to the sacrificial layer 130 is greater than 50. A high etch selectivity ratio ensures that the sacrificial layer 130 is almost not etched away, allowing the sacrificial layer 130 to function as a self-aligned structure and expand the photoresist exposure process window.
[0034] In some embodiments of this application, the etchant used in the etching process for etching the exposed portion of the first dielectric layer 120 at the bottom of the first trench 131 to form the second trench 132 in the semiconductor substrate 100 includes any one or more of CF4, HBr, O2, Cl2 and CH2F2.
[0035] In some embodiments of this application, when the first dielectric layer 120 at the bottom of the exposed portion of the first trench 131 is etched into the semiconductor substrate 100 to form a second trench 132, the projection of the second trench 132 onto the first trench 131 in the vertical direction coincides.
[0036] In the technical solution of this application, when etching the exposed portion of the first dielectric layer 120 at the bottom of the first trench 131 into the semiconductor substrate 100 to form the second trench 132, since the etching selectivity of the first dielectric layer 120 and the sacrificial layer 130 is relatively large, the sacrificial layer 130 is almost undamaged, allowing the second trench 132 to be completely aligned with the first trench 131, achieving self-aligned etching of the deep trench. Furthermore, the sacrificial layer 130 can also protect the active region 110 from damage.
[0037] refer to Figure 5 As shown, the patterned photoresist layer 140 is removed.
[0038] refer to Figure 6 As shown, in some embodiments of this application, the method for forming the semiconductor structure further includes: forming a metal interconnect structure 150 in the second trench 132.
[0039] In some embodiments of this application, the metal connection structure 150 includes: an oxide layer (not shown) insulating the sidewalls and bottom of the metal connection structure 150; a first metal layer (not shown) on a portion of the oxide layer surface near the bottom of the metal connection structure 150; and a second metal layer located on the surfaces of the first metal layer and the oxide layer. The first metal layer is, for example, tungsten, and the second metal layer is, for example, copper or aluminum.
[0040] In some embodiments of this application, a second dielectric layer (not shown in the figure) may also be formed on the metal connection structure 150 to cover and protect the metal connection structure 150.
[0041] In some embodiments of this application, the top surface of the metal connection structure 150 is lower than or flush with the top surface of the first dielectric layer 120.
[0042] refer to Figure 7 As shown, in some embodiments of this application, after forming the metal connection structure 150 in the second trench 132, the method for forming the semiconductor structure further includes: removing the sacrificial layer 130.
[0043] This application provides a method for forming a semiconductor structure, which can improve the process window for forming deep trenches between active regions, avoid damage to the active region structure, and improve device reliability.
[0044] Another aspect of this application provides a semiconductor structure formed by the semiconductor structure formation method described above, referenced... Figure 7 As shown, it includes: a semiconductor substrate 100, the semiconductor substrate 100 including a plurality of alternately distributed first regions 101 and second regions 102, the surface of the semiconductor substrate 100 in the first region 101 including an active region 110, the surface of the semiconductor substrate 100 in the second region 102 having a first dielectric layer 120 formed thereon, the top surface of the first dielectric layer 120 being lower than the top surface of the active region 110; and a second trench 132, penetrating a portion of the first dielectric layer 120 in the second region 102 and extending into the semiconductor substrate 100.
[0045] In some embodiments of this application, the material of the semiconductor substrate 100 includes (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) combinations thereof.
[0046] In some embodiments of this application, the active region 110 can be formed into any active device, such as a MOSFET or a FIFET. (See reference...) Figure 1 As shown, since the active region 110 can be used to form any transistor structure, the detailed structure of the active region 110 is omitted for the sake of simplicity, and is only illustrated with blocks. However, those skilled in the art, based on common knowledge, should be able to know the detailed structure of the corresponding active region 110 and subsequent fabrication processes once the type of active device in the active region 110 is determined. For example, if the active device in the active region 110 is a MOSFET, the corresponding active region 110 can form structures such as gate, source, and drain. If the active region 110 is used to form a FIFET, the corresponding active region 110 may include a fin structure, with the gate and source / drain subsequently formed.
[0047] In some embodiments of this application, the material of the first dielectric layer 120 includes silicon oxide. The first dielectric layer 120 is used to isolate adjacent active regions 110.
[0048] In some embodiments of this application, a protective layer 111 is also formed on the sidewalls and top surface of the active region 110 to protect the active region 110.
[0049] Continue to refer to Figure 7 As shown, in some embodiments of this application, a metal connection structure 150 is formed in the second trench 132.
[0050] In some embodiments of this application, the metal connection structure 150 includes: an oxide layer (not shown) insulating the sidewalls and bottom of the metal connection structure 150; a first metal layer (not shown) on a portion of the oxide layer surface near the bottom of the metal connection structure 150; and a second metal layer located on the surfaces of the first metal layer and the oxide layer. The first metal layer is, for example, tungsten, and the second metal layer is, for example, copper or aluminum.
[0051] In some embodiments of this application, a second dielectric layer (not shown in the figure) is also formed on the metal connection structure 150 to cover and protect the metal connection structure 150.
[0052] In some embodiments of this application, the top surface of the metal connection structure 150 is lower than or flush with the top surface of the first dielectric layer 120.
[0053] This application provides a semiconductor structure and a method for forming the same, which can improve the process window for forming deep trenches between active regions, avoid damage to the active region structure, and improve device reliability.
[0054] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.
[0055] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.
[0056] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.
[0057] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.
[0058] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate including a plurality of alternately distributed first regions and second regions, the surface of the semiconductor substrate in the first region including an active region, the surface of the semiconductor substrate in the second region having a first dielectric layer formed thereon, the top surface of the first dielectric layer being lower than the top surface of the active region; A sacrificial layer is formed on the sidewall and top surface of the active region above the top surface of the first dielectric layer, and the sacrificial layer defines a first trench between adjacent active regions; A patterned photoresist layer is formed on the semiconductor substrate, the patterned photoresist layer covering the first dielectric layer and the sacrificial layer and exposing a portion of the first trench; The first dielectric layer at the bottom of the exposed portion of the first trench is etched into the semiconductor substrate to form a second trench, wherein the etching rate of the first dielectric layer is greater than the etching rate of the sacrificial layer; Remove the patterned photoresist layer.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first dielectric layer is silicon oxide, the material of the sacrificial layer is silicon nitride, and the etchant used in the etching process of etching the exposed portion of the first dielectric layer at the bottom of the first trench into the semiconductor substrate to form a second trench includes any one or more of CF4, HBr, O2, Cl2 and CH2F2.
3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The active region is further provided with a protective layer on its sidewalls and top surface, and the sacrificial layer is located on the surface of the protective layer.
4. The method for forming a semiconductor structure as described in claim 1, characterized in that, When the first dielectric layer at the bottom of the exposed portion of the first trench is etched into the semiconductor substrate to form a second trench, the projection of the second trench onto the first trench in the vertical direction coincides.
5. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: A metal connection structure is formed in the second trench.
6. The method for forming a semiconductor structure as described in claim 5, characterized in that, After forming the metal connection structure in the second trench, the process further includes removing the sacrificial layer.
7. A semiconductor structure formed by the method of forming a semiconductor structure according to any one of claims 1-6, characterized in that, include: A semiconductor substrate includes a plurality of alternately distributed first regions and second regions. The surface of the semiconductor substrate in the first region includes an active region, and the surface of the semiconductor substrate in the second region has a first dielectric layer formed thereon. The top surface of the first dielectric layer is lower than the top surface of the active region. The second trench penetrates a portion of the first dielectric layer in the second region and extends into the semiconductor substrate.
8. The semiconductor structure as described in claim 7, characterized in that, The material of the first dielectric layer is silicon oxide.
9. The semiconductor structure as described in claim 7, characterized in that, The active region is further provided with a protective layer on its sidewalls and top surface, and the sacrificial layer is located on the surface of the protective layer.
10. The semiconductor structure as claimed in claim 7, characterized in that, A metal connection structure is formed in the second trench.