Microelectronic assembly with dual liners in through glass vias

Abstract

A microelectronic assembly according to an embodiment of the present disclosure may include a glass core (e.g., a glass layer or glass structure) having a first face and a second face opposite the first face; a through glass via (TGV) in the glass layer, the TGV extending from the first face toward the second face and including an electrically conductive material; a first liner in the TGV between the conductive material and the glass layer; and a second pad in the TGV between the conductive material and the glass layer, where the first pad is between the glass layer and the second pad, and where the first pad has a modulus higher than that of the second pad.

Description

Background Technology

[0001] For decades, the scaling of features in integrated circuits (ICs) has been a driving force behind the ever-growing semiconductor industry and emerging applications in fields such as big data, artificial intelligence, mobile communications, and autonomous driving. Scaling to increasingly smaller features enables increased density of functional units on the finite substrate surface of semiconductor chips. For example, smaller transistor sizes allow for the integration of a greater number of memory or logic devices on a single chip, resulting in the manufacture of products with larger capacities. However, this drive for ever-increasing capacity is not without its challenges. The need to optimize the manufacturing and performance of each component (e.g., each transistor) has become increasingly important.

[0002] Alongside transistor-level optimization, the landscape of advanced IC packaging is rapidly evolving to accommodate performance expectations and requirements for shrinking transistor sizes. Currently, multiple IC dies are typically coupled together in multi-die IC packages to integrate features or functionality and facilitate connectivity to other components, such as the package substrate. For example, an IC package may include an embedded multi-die interconnect bridge (EMIB) for coupling two or more IC dies.

[0003] Integrating multiple dies within a single IC package offers significant benefits, but it also adds additional complexity by placing materials with different material properties close to each other. As the IC package undergoes multiple processing steps involving varying temperature and pressure loads, the individual materials within the package may behave differently, leading to out-of-plane deformation of the layers, a phenomenon known as "package warpage." One approach to address package warpage is to use a stiffer core to which the different IC dies are attached. Recently, glass cores have been developed as an alternative to resin-based cores (e.g., cores based on Ajinomoto Accumulated Film (ABF)). Glass is considered harder than resin-based materials and offers several advantages, such as excellent thermal properties, a low coefficient of thermal expansion (CTE), high electrical insulation, chemical resistance, optical transparency, and compatibility with advanced semiconductor properties. However, a major challenge to the widespread adoption of glass cores is the fact that glass is highly susceptible to damage from mechanical and / or thermal stresses, such as stress caused by metal-filled through-glass vias (TGVs). Attached Figure Description

[0004] The embodiments will be readily understood from the following detailed description taken in conjunction with the accompanying drawings. For ease of description, similar reference numerals denote similar structural elements. In the accompanying figures, the embodiments are shown by way of example rather than limitation.

[0005] Figure 1 This is a schematic side cross-sectional view of an example microelectronic assembly according to some embodiments of the present disclosure.

[0006] Figure 2 This is a schematic side cross-sectional view of another example microelectronic assembly according to some embodiments of the present disclosure.

[0007] Figure 3 The surface of a glass core, from which TGV stress may originate, is shown in some embodiments of this disclosure.

[0008] Figure 4 This is a flowchart of a method for manufacturing a glass core with double pads in one or more TGVs according to some embodiments.

[0009] Figures 5A-5D Provided according to some embodiments Figure 4 The method is used to manufacture cross-sectional side views of various stages of an example glass core.

[0010] Figure 6 This is a top view of a wafer and die that may be included in a microelectronic assembly with a glass core according to some embodiments of this disclosure, as disclosed herein.

[0011] Figure 7 This is a side cross-sectional view of an IC device that may be included in a microelectronic assembly with a glass core according to some embodiments of the present disclosure, in any embodiment of the present disclosure.

[0012] Figure 8 This is a side cross-sectional view of an IC device assembly that may include a glass core according to any embodiment of the present disclosure, based on some embodiments thereof.

[0013] Figure 9 This is a block diagram of an example communication device that may include a microelectronic assembly with a glass core, which may be included according to any embodiment of the present disclosure, based on some embodiments of the present disclosure. Detailed Implementation

[0014] As mentioned above, glass possesses properties that make it promising for integration into advanced IC packages. When a glass core is included in a microelectronic assembly, it may be desirable to route electrical signals within and / or through the glass core. For this purpose, conductive vias (TGVs) can be provided in the glass core. TGVs can also support effective thermal management by providing a heat dissipation path from active components to the external environment of the package. In some implementations, the TGV may extend between the top and bottom surfaces of the glass core, for example, to provide electrical connections between electronic components such as dies and / or package substrates coupled to the top and bottom surfaces of the glass core. In other implementations, the TGV may be a blind via that extends from the top / bottom surface of the glass core toward the opposite surface but does not reach the opposite surface, for example, to provide electrical connectivity from the surface of the glass core to conductive traces or IC components embedded in the glass core.

[0015] Providing TGVs within a glass core enables more compact and efficient designs for microelectronic assemblies. However, integrating TGVs within a glass core is not straightforward. Conventionally, TGV fabrication involves forming openings for the future TGV, lining the openings with a seed material, and then depositing a conductive filler material into the lining openings. Seed materials typically include low-resistivity metals, such as copper, which can be deposited in a thin layer on the substantially non-conductive surfaces (e.g., sidewalls) of the openings within the glass core. The seed material is intended to provide a conductive surface for the uniform and controlled deposition of the conductive filler material in subsequent deposition steps, for example, when the conductive filler material is deposited in the lining openings using processes such as electroplating. One challenge associated with integrating TGVs within a glass core stems from the CTE difference (sometimes referred to as the "CTE mismatch") between the materials available for the glass core and the metals of the seed material and conductive filler material deposited in the TGV. CTE is a method of measuring how a material expands or contracts with temperature changes. CTE is typically defined as the fraction of length increase per unit temperature rise, measured, for example, in parts per million (ppm) or ppm / K. Glass materials used for glass cores and metals have significantly different CTEs. Metals have relatively high CTEs, meaning they can expand and contract significantly with temperature changes. Glass materials, on the other hand, have much lower CTEs and respond less to temperature changes. For example, the CTE of glass materials can be on the order of approximately 3.5 ppm / K, while the CTE of metals such as copper can be on the order of approximately 15–17 ppm / K. When a metal is in close contact with a glass (e.g., a seed material or conductive filler within a TGV in a glass structure) and the assembly is exposed to temperature changes such as heating or cooling, the metal will heat or cool faster and to a greater extent than the glass. This results in significant stresses being generated at the interface between the two materials. For example, an expanding metal may generate compressive stress, while a contracting metal may generate tensile stress. Sufficiently high stresses may exceed the strength of the glass, leading to crack formation, which can then propagate and jeopardize the structural integrity of the glass. Even if cracks do not form immediately, repeated thermal cycling can gradually weaken the glass, potentially leading to the development of surface defects or microcracks. Prolonged exposure to stress caused by CTE mismatch can cause gradual degradation of the glass, making it more susceptible to failure over time.

[0016] Embodiments of this disclosure relate to techniques, apparatus, and methods for mitigating (e.g., reducing or decreasing) stress caused by CTE mismatch due to proximity between the conductive material of a TGV and the glass material of a glass structure (e.g., a glass core). Such stress is referred to herein as “TGV stress.” Embodiments of this disclosure are based on the understanding that including a double liner on the sidewalls of the TGV, which acts as a buffer layer between the glass core and (one or more) conductive materials in the TGV, can help reduce TGV stress because the double liner separates the glass from the metal of the seed material and conductive filler material deposited in the TGV. Specifically, the double liner may comprise a first liner of material having a first modulus (e.g., having a Young's modulus of at least about 30 gigapascals (GPa)) deposited on the sidewalls of the TGV, followed by a second liner of material having a second modulus (e.g., having a Young's modulus of less than 30 GPa) deposited on top of the first liner on the sidewalls of the TGV. Implementing a gasket with a higher modulus that is in direct contact with the glass (i.e., the first gasket) can help reduce tensile stress caused by, for example, the shrinkage of the metal subsequently filled into the TGV. In some embodiments, the first gasket may have a relatively low CTE (e.g., between about 3 ppm / K and about 10-12 ppm / K), which may be particularly advantageous in reducing stress caused by CTE mismatch. Furthermore, placing the first gasket directly along the sidewalls of the TGV can help smooth the glass surface at the sidewalls. Implementing a gasket with a lower modulus that is closer to the metal subsequently filled into the TGV than a higher modulus gasket (i.e., the second gasket) can help reduce compressive stress caused by, for example, the expansion of the metal subsequently filled into the TGV. The second gasket can act as a stress-absorbing layer. In some embodiments, the second gasket may have a higher CTE (e.g., above about 15 ppm / K), although in other embodiments, the second gasket may have a lower CTE. In some embodiments, the first liner may comprise an inorganic material, such as silicon oxide or silicon nitride, while the second liner may comprise an organic material, such as parylene, wherein the name “parylene” refers to a group of polymers called parylene.

[0017] In one aspect, a microelectronic assembly according to embodiments of the present disclosure may include a glass core (e.g., a glass layer or glass structure) having a first side and a second side opposite to the first side; a TGV in the glass layer extending from the first side toward the second side and comprising a conductive material; a first pad in the TGV between the conductive material and the glass layer; and a second pad in the TGV between the conductive material and the glass layer, wherein the first pad is between the glass layer and the second pad, and wherein the modulus of the first pad is higher than that of the second pad.

[0018] Integrating different material layers (e.g., multiple dies, redistribution layers, packaging substrates) within a single IC package or microelectronic assembly is challenging due to factors such as package warpage. As described herein, providing IC packages or microelectronic assemblies with dual pads in the TGV can be helpful. Various embodiments disclosed herein can facilitate reliable integration of multiple layers of different materials within a single microelectronic assembly with lower cost and / or greater design flexibility compared to conventional approaches. The various microelectronic assemblies disclosed herein can exhibit reduced warpage compared to microelectronic assemblies without a glass core. The microelectronic assemblies disclosed herein may be particularly advantageous for small and low-profile applications in computers, tablets, industrial robots, and consumer electronics devices (e.g., wearable devices).

[0019] In the following detailed description, reference is made to the accompanying drawings, which form a part of this description, wherein similar numerals denote similar parts throughout the drawings, and implementable embodiments are illustrated by way of illustration. It should be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of this disclosure. Therefore, the following detailed description is not intended to be limiting.

[0020] Any feature discussed herein with reference to any of the accompanying drawings may be combined with any other feature to form microelectronic assembly 100, glass core 110, IC device 1600, IC device assembly 1700, or communication device 1800, as appropriate. For convenience, the phrase "die 114" may be used to refer to a collection of dies 114-1, 114-2, etc. Many elements having the same reference numerals in the drawings may be shared between different drawings; for ease of discussion, descriptions of these elements provided in one of the drawings will not be repeated in other drawings, and these elements may take the form of any embodiment disclosed herein. To avoid confusion in the drawings, if multiple instances of certain elements are shown, only some of the elements may be labeled with reference numerals (e.g., Figure 1 Multiple conductive contacts 122 are shown, but only one of them is labeled with reference numerals. Similarly, to avoid confusion, not all reference numerals shown in one of the accompanying drawings are shown in other similar drawings.

[0021] The accompanying figures are not necessarily drawn to scale. While many figures illustrate straight structures with flat walls and right-angled corners, this is merely for illustrative purposes and may not reflect real-world process constraints that can cause various features to appear less “ideal” when examined using, for example, scanning electron microscopy (SEM) or transmission electron microscopy (TEM) images. Possible processing defects may also be visible in such images of real structures, such as imperfectly straight edges of material, tapered vias or other openings, unintentional chamfers, or variations in the thickness of different material layers. Other defects not listed here but common in the field of semiconductor device fabrication and packaging may also exist. Examining layout and mask data using, for example, optical microscopy, TEM, or SEM, and reverse engineering portions of the device to reconstruct the circuitry, and / or examining cross-sections of the device using, for example, physical failure analysis (PFA) to detect the shape and location of the various device elements described herein, will allow the determination of the presence of double pads in TGVs as described herein.

[0022] For the purposes of this disclosure, the phrase "A and / or B" refers to (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). When used to describe a range of dimensions, the phrase "between X and Y" indicates a range including both X and Y. When used to describe the location of an element, the phrase "between X and Y" indicates a region spatially located between element X and element Y. The terms "substantially," "close to," "approximately," "near," and "about" generally refer to a target value within + / -20% of the context of a particular value as described herein or as known in the art, for example, within + / -5% or within + / -2%. Similarly, terms referring only to the orientation of various elements (e.g., "coplanar," "perpendicular," "orthogonal," "parallel," or any other angle between elements) generally refer to a precise orientation within + / -10%, for example, within + / -5% or within + / -2%.

[0023] This description uses the phrases "in one embodiment" or "in an embodiment," each of which can refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used with respect to embodiments of this disclosure are synonymous. As used herein, the terms "package" and "IC package" are synonymous, as are the terms "die" and "IC die." Additionally, the terms "chip," "chiplet," "die," and "IC die" are used interchangeably herein.

[0024] Although certain elements may be referred to in the singular herein, such elements may include multiple sub-elements. For example, "dielectric material" may include one or more dielectric materials, or "insulating material" may include one or more insulating materials. The terms "oxide," "carbide," "nitride," etc., refer to compounds containing oxygen, carbon, nitrogen, etc., respectively. The term "high-k dielectric" refers to a material having a dielectric constant compared to silicon oxide, while the term "low-k dielectric" refers to a material having a dielectric constant compared to silicon oxide. The term "insulating" and its variations (e.g., "insulating" or "insulator") mean "electrically insulating," and the term "conductive" and its variations (e.g., "conductive" or "conductor") mean "conductive," unless otherwise stated. Regarding optical signals and / or devices, components, and elements that operate on or use optical signals, the term "conductive" may also mean "optically conductive." When two materials or layers are described as "contacting," this may mean that the two materials or layers are in physical contact, such as direct physical contact, or possibly in contact with an interface layer formed as a result of said contact. The term "insulating material" refers to a solid material that is substantially non-conductive (and / or a liquid material that solidifies upon processing as described herein). By way of example and not limitation, they may include organic polymers and plastics, as well as inorganic materials such as ionic crystals, ceramics, glasses, silicon, and alumina, or combinations thereof. They may include dielectric materials, highly polarizable materials, and / or piezoelectric materials. They may be transparent or opaque without departing from the scope of this disclosure. Further examples of insulating materials are underfill and molding or mold-like materials used in encapsulation applications, including, for example, materials used for organic inserts, encapsulation supports, and other such components.

[0025] Figure 1This is a schematic side cross-sectional view of an example microelectronic assembly 100 according to some embodiments of the present disclosure, wherein a glass core having one or more TGVs with dual pads can be implemented as described herein. The microelectronic assembly 100 may include a substrate 107 having a dual-sided bridging die 114-1 in a cavity 119 of the substrate 107, the die 114-1 being electrically coupled to a conductive path, such as conductive trace 108A or conductive via 108B, in a metal layer N-1 of the substrate 107 below the bottom of the cavity 119. The substrate 107 may include a dielectric material 112 (e.g., a first dielectric material layer 112A and a second dielectric material layer 112B, collectively referred to as "one or more dielectric materials 112") and conductive material 108 disposed in the one or more dielectric materials 112 to provide conductive paths (e.g., conductive trace 108A and conductive via 108B) through the substrate 107, and to provide conductive pads and contacts. Substrate 107 may include a first surface 120-1 and an opposing second surface 120-2. Die 114-1 may be surrounded by a dielectric material 112 of substrate 107. Die 114-1 may include a bottom surface (e.g., the surface facing the first surface 120-1) having first conductive contacts 122, an opposing top surface (e.g., the surface facing the second surface 120-2) having second conductive contacts 124, and through-silicon vias (TSVs) 125 coupling the respective first and second conductive contacts 122, 124. In some embodiments, the spacing of the first conductive contacts 122 on the first die 114-1 may be between 25 micrometers and 250 micrometers. As used herein, the spacing is measured center-to-center (e.g., from the center of a conductive contact to the center of an adjacent conductive contact). In some embodiments, the spacing of the second conductive contacts 124 on the first die 114-1 may be between 25 micrometers and 100 micrometers. Dies 114-2 and 114-3 may include a set of conductive contacts 122 on the bottom surface of the die (e.g., the surface facing the first surface 120-1). Die 114 may include other conductive paths (e.g., wires and vias) coupled to corresponding conductive contacts (e.g., conductive contacts 122, 124) on the surface of die 114 and / or to other circuit modules (not shown). As used herein, the terms “die,” “microelectronic component,” and similar variations are used interchangeably. As used herein, the terms “interconnect component,” “bridging die,” and similar variations are used interchangeably. Bridging die 114-1 may be electrically coupled to dies 114-2 and 114-3 via a die-to-die (DTD) interconnect 130 at the second surface 120-2. Specifically, the conductive contact 124 on the top surface of die 114-1 can be coupled to the conductive contact 122 on the bottom surface of dies 114-2 and 114-3 through the conductive via 108B passing through the second dielectric material layer 112B.

[0026] As used herein, "conductive contact" refers to a portion of an electrical material (such as a metal) that serves as an electrical interface between different components (e.g., part of a conductive interconnect); a conductive contact may be recessed, flush with, or extend from the surface of a component (e.g., having a columnar shape) and may take any suitable form (e.g., a conductive pad or socket, or part of a conductive wire or through-hole). In a general sense, "interconnect" refers to any element that provides a physical connection between two other elements. For example, an electrical interconnect provides an electrical connection between two electrical components, facilitating the transmission of electrical signals between them; an optical interconnect provides an optical connection between two optical components, facilitating the transmission of optical signals between them. As used herein, the term "interconnect" includes both electrical interconnects and optical interconnects. The nature of the interconnects described herein will be understood with reference to the signal medium associated with them. Thus, when used with reference to electronic devices (e.g., ICs that operate using electrical signals), the term "interconnect" describes any element formed of a conductive material that provides an electrical connection between one or more elements associated with the IC and / or various such elements. In such cases, the term "interconnect" can refer to electrical traces (sometimes also called "metallic traces," "lines," "metallic wires," "conductors," "metallic conductors," "grooves," or "metallic trenches") and conductive vias (sometimes also called "vias" or "metallic vias"). Sometimes, conductive traces and vias can be referred to as "metallic traces" and "metallic vias," respectively, to emphasize the fact that these elements comprise conductive materials such as metals. Similarly, when also used with reference to devices such as photonic ICs (PICs) that operate on optical signals, "interconnect" can also describe any element formed of an optically conductive material used to provide an optical connection to one or more elements associated with the PIC. In such cases, the term "interconnect" can refer to optical waveguides (e.g., structures that guide and confine light waves), including optical fibers, beam splitters, optical combiners, optical couplers, and optical vias.

[0027] The die 114 disclosed herein may include an insulating material (e.g., a multilayer dielectric material as known in the art) and multiple conductive paths formed through the insulating material. In some embodiments, the insulating material of the die 114 may include a dielectric material, such as silicon dioxide, silicon nitride, oxide nitride, polyimide material, glass-reinforced epoxy matrix material, or low-k or ultra-low-k dielectric (e.g., carbon-doped dielectric, fluorine-doped dielectric, porous dielectric, organic polymer dielectric, photo-imaging dielectric, and / or benzocyclobutene-based polymer). In some embodiments, the insulating material of the die 114 may include a semiconductor material, such as silicon, germanium, or a III-V group material (e.g., gallium nitride), and one or more additional materials. For example, the insulating material may include silicon oxide or silicon nitride. The conductive paths in the die 114 may include conductive traces and / or conductive vias, and may connect any conductive contacts in the die 114 in any suitable manner (e.g., connecting multiple conductive contacts on the same or different surfaces of the die 114). The following discussion, with reference to IC device 1600, discusses example structures that may be included in the die 114 disclosed herein. Conductive paths in die 114 may be bounded by padding materials (e.g., suitable adhesive pads and / or barrier pads). In some embodiments, die 114 is a wafer. In some embodiments, die 114 is a monolithic silicon, fan-out or fan-in package die, or die stack (e.g., wafer stack, die stack, or multilayer die stack).

[0028] In some embodiments, chip 114 may include conductive paths for routing power, ground, and / or signals to or from other dies 114 in the microelectronic assembly 100. For example, die 114-1 may include a TSV 125, which includes a conductive via (e.g., a metal via) isolated from surrounding silicon or other semiconductor material by blocking oxides, or other conductive pathways through which power, ground, and / or signals can be transmitted on one or more dies 114 on the “top” of the package substrate 102 and die 114-1 (e.g., in…). Figure 1In some embodiments, power is transmitted between dies 114-2 and / or 114-3. In some embodiments, die 114-1 may not route power and / or ground to dies 114-2 and 114-3; instead, dies 114-2 and 114-3 may be directly coupled to power lines and / or ground lines in package substrate 102 via substrate-to-package substrate (STPS) interconnect 150, conductive paths provided by conductive material 108 in substrate 107, and die-to-substrate (DTS) interconnect 140. In some embodiments, die 114-1 may be thicker than dies 114-2 and 114-3. In some embodiments, die 114-1 may be a memory device or a high-frequency serializer and deserializer (SerDes), such as a Fast Peripheral Component Interconnect (PCI). In some embodiments, die 114-1 may be a processing die, an RF chip, a power converter, a network processor, a workload accelerator, a voltage regulator die, or a security cipher. In some embodiments, die 114-2 and / or die 114-3 may be a processing die, an RF chip, a power converter, a network processor, a workload accelerator, a voltage regulator die, or a security cipher. In some embodiments, die 114 may be referenced as follows. Figure 6 As described in the 1502 die.

[0029] The dielectric material 112 of the substrate 107 may be formed in layers (e.g., at least a first dielectric material layer 112A and a second dielectric material layer 112B). In some embodiments, the dielectric material 112 may include an organic material, such as an organic accumulation film. In some embodiments, for example, the dielectric material 112 may include ceramics, epoxy resin films having filler particles, glass, inorganic materials, or a combination of organic and inorganic materials. In some embodiments, the conductive material 108 may include a metal (e.g., copper). In some embodiments, the substrate 107 may include layers of dielectric material 112 / conductive material 108, wherein lines / traces / pads / contacts (e.g., conductive trace 108A) of the conductive material 108 in one layer are electrically coupled to lines / traces / pads / contacts (e.g., conductive trace 108A) of the conductive material 108 in an adjacent layer through vias (e.g., 108B) extending through the conductive material 108 in the dielectric material 112. The conductive trace 108A may be referred to herein as a “conductive line,” “conductive element,” “conductive pad,” or “conductive contact.” For example, printed circuit board (PCB) manufacturing technology can be used to form a substrate 107 that includes such a layer.

[0030] Individual layer dielectric material 112 (e.g., first dielectric material layer 112A) may include a cavity 119, and a bridging pipe core 114-1 may be at least partially nested within the cavity 119. The bridging pipe core 114-1 may be surrounded (e.g., embedded therein) by a next individual layer dielectric material 112 (e.g., second dielectric material layer 112B). In some embodiments, the cavity 119 is tapered, narrowing towards its bottom surface (e.g., the surface facing the first surface 120-1 of the substrate 107). The cavity 119 may be indicated by a seam between dielectric materials 112A and 112B. Figure 1 As shown, when the bridging core 114-1 is partially nested in the cavity 119, the top surface of the bridging core 114-1 can extend above the top surface of the dielectric material 112A. When the bridging core 114-1 is completely nested in the cavity 119 (not shown), the top surface of the bridging core 114-1 can be on the same plane as the top surface of the dielectric material 112A or below the top surface of the dielectric material 112A.

[0031] The substrate 107 may include N layers of conductive material 108, where N is an integer greater than or equal to 1. Figure 1 In this context, the layers are labeled in descending order from the second surface 120-2 (e.g., the top surface) of the substrate 107 (e.g., layer N, layer N-1, layer N-2, etc.). Specifically, as... Figure 1 As shown, substrate 107 may include four metal layers (e.g., N, N-1, N-2, and N-3). The N metal layer may include conductive contacts 121 at the second surface 120-2 of substrate 107, coupled via DTS interconnects 140 to conductive contacts 122 at the bottom surfaces of dies 114-2 and 114-3. The N-2 metal layer may include a conductive trace 108A having a top surface (e.g., a surface facing the second surface 120-2 of substrate 107), an opposing bottom surface (e.g., a surface facing the first surface 120-1 of substrate 107), and a lateral surface extending between the top and bottom surfaces of the conductive trace 108A. Substrate 107 may further include an N-1 metal layer above the N-2 metal layer and below the N metal layer, wherein a portion of the N-1 metal layer includes a metal ring 118 exposed at the bottom periphery of cavity 119. As shown, the metal ring 118 can be coplanar with the conductive trace 108A of the N-1 metal layer and can be close to the edge of the cavity 119.

[0032] Although specific numbers and arrangements of dielectric material 112 / conductive material 108 layers are shown in the various figures in the accompanying drawings, these specific numbers and arrangements are for illustrative purposes only, and any desired number and arrangement of dielectric material 112 / conductive material 108 can be used. Furthermore, although a specific number of layers (e.g., four layers) are shown in the substrate 107, these layers may represent only a portion of the substrate 107; for example, additional layers (e.g., layers N-4, N-5, N-6, etc.) may be present.

[0033] like Figure 1As shown, substrate 107 may further include a glass core 110 having a TGV 115, and an additional layer 111 may exist beneath the glass core 110 and be coupled to the encapsulation substrate 102 via interconnect 150. As described herein, any TGV 115 may be a conductive via with dual pads. As used herein, the term "glass core" refers to any layer (e.g., a glass layer) or structure (e.g., a portion of a glass layer) of glass material, such as quartz, silica, fused silica, silicate glass (e.g., borosilicate, aluminosilicate, aluminoborosilicate), soda-lime glass, soda-lime silica, borosilicate float glass, lead borate glass, photosensitive glass, non-photosensitive glass, or ceramic glass. In particular, glass core 110 may be a bulk glass or a solid volume / glass layer, as opposed to materials that may include, for example, glass particles, such as glass fiber reinforced polymers (e.g., a substrate / plate composed of glass fibers and epoxy adhesive). Such glass materials are typically amorphous and generally transparent amorphous solids. In some embodiments, the glass core 110 may be an amorphous solid glass layer. In some embodiments, the glass core 110 may include a material comprising silicon and oxygen, and any one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc. In some embodiments, the glass core 110 may include a material, such as any of the above-mentioned materials, wherein the weight percentage of silicon is at least about 0.5%, for example, between about 0.5% and 50%, between about 1% and 48%, or at least about 23%. For example, if the glass core 110 is fused silica, the weight percentage of silicon may be about 47%. In some embodiments, the glass core 110 may include a material having at least 23% silicon and / or at least 26% oxygen by weight, and in some further embodiments, the glass core 110 may further include at least 5% aluminum by weight. In some embodiments, the glass core 110 may comprise any of the materials described above, and may further comprise one or more additives, such as Al2O3, B2O3, MgO, CaO, SrO, BaO, SnO2, Na2O, K2O, SrO, P2O3, ZrO2, Li2O, Ti, and Zn. In some embodiments, the glass core 110 may be a glass layer that does not include organic binders or organic materials. The glass core 110 may be distinguished from, for example, a “prepreg” or “RF4” core of a PCB substrate, which typically comprises glass fibers embedded in a resinous organic material such as epoxy resin. In such conventional cores / substrates comprising glass fibers and epoxy resin, the diameter of the glass fibers is typically in the range of 5 micrometers to 200 micrometers. In contrast, the glass core 110 may be a glass layer with a side length of about 10 millimeters to about 250 millimeters (e.g., 10 mm × 10 mm to 250 mm × 250 mm).In some embodiments, the cross-section in the xy-plane may be substantially rectangular (the axes shown in subsequent figures refer to the axes of coordinate system 105), although in some further embodiments, the glass core 110 may have rounded or beveled edges / sides / sidewalls. In some embodiments, in a top view of the glass core 110 (e.g., in the xy-plane of coordinate system 105), the glass core 110 may have a first length in the range of 10 mm to 250 mm, and a second length in the range of 10 mm to 250 mm, the first length being perpendicular to the second length. The thickness of the glass core 110 (e.g., a dimension measured along the z-axis of coordinate system 105) may be in the range of approximately 50 micrometers to 1.4 mm. In some embodiments, the glass core 110 may be a glass core substrate having a thickness in the range of approximately 50 micrometers to 1.4 mm. In some embodiments, the glass core 110 may be a glass layer comprising rectangular prisms, possibly having rounded or beveled edges / sides / sidewalls. In some such embodiments, the rectangular prism may have a first side and a second side perpendicular to the first side, the first side having a length in the range of 10 mm to 250 mm, and the second side having a length in the range of 10 mm to 250 mm. In some embodiments, the glass core 110 may be a rectangular prism in which a portion (e.g., a through-hole) is removed and filled with other materials (e.g., metal), such as TGV 115. In some embodiments, the glass core 110 may be a glass layer having a thickness in the range of 50 micrometers to 1.4 mm, a first length in the range of 10 mm to 250 mm, and a second length in the range of 10 mm to 250 mm, the first length being perpendicular to the second length.

[0034] In some implementations, the substrate 107, including the glass core 110, and the die 114 may be collectively referred to as the "multilayer die subassembly 104". The glass core 110 can provide mechanical stability for the multilayer die subassembly 104, the substrate 107, and / or the microelectronic assembly 100. The glass core 110 can reduce warpage and can provide a more robust surface for the multilayer die subassembly 104 to attach to the packaging substrate 102 or other substrates (e.g., inserters or circuit boards).

[0035] In some implementations, the dielectric material 112 and glass core 110 of substrate 107 may be collectively referred to as a "multilayer glass substrate." In some such embodiments, the multilayer glass substrate may be a coreless substrate. In some such embodiments, the glass core 110 may be a glass layer having a thickness in the range of approximately 25 micrometers to 50 micrometers. In some embodiments, an additional layer 111 may also be part of the multilayer glass substrate.

[0036] TGV 115 may be a through-hole extending between a first and a second side of glass core 110 (e.g., between the bottom and top surfaces of glass core 110), the through-hole comprising any suitable conductive material, such as a metal, such as copper, silver, nickel, gold, aluminum, or other metals or alloys. The opening of TGV 115 can be formed using any suitable process, including, for example, direct laser drilling or laser-induced etching processes (which may also be referred to as laser patterning or selective laser activation). For any TGV 115, a manufacturing method utilizing a dual-pad as described herein (e.g.) can be used. Figure 4 The method shown is used to perform through-hole metallization. Therefore, although not in Figure 1 or Figure 2 The figures are shown in detail, but any TGV 115 shown in these figures may be as described above. Figure 4 The manufacturing method shown in the figure is implemented as described (e.g., as having such Figures 5A-5C (The conductive vias of the dual-pad shown). In some embodiments, the TGV 115 disclosed herein may have a spacing between 50 micrometers and 500 micrometers, for example, as measured from the center of one TGV 115 to the center of the adjacent TGV 115. The TGV 115 may have any suitable size and shape. In some embodiments, the TGV 115 may have a circular, rectangular, or other shaped cross-section. In some embodiments, at least some of the TGV 115s may have an hourglass shape, for example, as shown in the diagram. Figure 2 As shown in the figure. In some embodiments, at least some of the TGV 115s may gradually taper from one side of the glass core 110 to the other, for example, from the top surface of the glass core 110 to the bottom surface of the glass core 110.

[0037] Substrate 107 (e.g., additional layer 111) can be coupled to package substrate 102 via STPS interconnect 150. Specifically, the top surface of package substrate 102 may include a set of conductive contacts 146. Conductive contacts 144 on the bottom surface of substrate 107 can be electrically and mechanically coupled to the conductive contacts 146 on the top surface of package substrate 102 via STPS interconnect 150. Package substrate 102 may include an insulating material (e.g., a dielectric material formed in a multilayer as known in the art) and one or more conductive paths to route power, ground, and signals through the dielectric material (e.g., including conductive traces and / or conductive vias, as shown). In some embodiments, the insulating material of the encapsulation substrate 102 may be a dielectric material, such as an organic dielectric material, a flame retardant grade 4 material (FR-4), bismaleimide triazine (BT) resin, a polyimide material, a glass-reinforced epoxy resin matrix material, an organic dielectric with inorganic fillers, or a low-k and ultra-low-k dielectric (e.g., carbon-doped dielectric, fluorine-doped dielectric, porous dielectric, and organic polymer dielectric). Specifically, when the encapsulation substrate 102 is formed using a standard PCB process, the encapsulation substrate 102 may include FR-4, and the conductive paths in the encapsulation substrate 102 may be formed by patterned copper sheets separated by accumulated layers of FR-4. Depending on the application, the conductive paths in the encapsulation substrate 102 may be defined by padding materials such as adhesive pads and / or barrier pads. In some embodiments, the encapsulation substrate 102 may be formed using a photolithographically defined through-hole encapsulation process. In some embodiments, the encapsulation substrate 102 may be manufactured using a standard organic encapsulation manufacturing process, and therefore the encapsulation substrate 102 may take the form of an organic encapsulation. In some embodiments, the encapsulation substrate 102 may be a set of redistribution layers formed on a panel carrier by lamination or spin coating onto a dielectric material, and conductive vias and lines are created by laser drilling and electroplating. In some embodiments, the encapsulation substrate 102 may be formed on a removable carrier using any suitable technique such as redistribution layer technology. Any method known in the art for manufacturing the encapsulation substrate 102 may be used, and for the sake of brevity, such methods will not be discussed in further detail herein.

[0038] In some embodiments, the package substrate 102 may be a lower-density dielectric, and the die 114 may be a higher-density dielectric, or have regions with a higher-density dielectric. As used herein, the terms “lower density” and “higher density” are relative terms, indicating that the conductive paths (e.g., including conductive interconnects, conductive lines, and conductive vias) in the lower-density dielectric are larger and / or have greater spacing than the conductive paths in the higher-density dielectric. In some embodiments, the higher-density dielectric may be fabricated using an improved semi-additive process or a semi-additive accumulation process with advanced lithography (having small vertical interconnect features formed by advanced laser or lithography processes), while the lower-density dielectric may be a PCB fabricated using standard PCB processes (e.g., a standard subtractive process using etch chemistry to remove unwanted copper areas and having rough vertical interconnect features formed by standard laser processes). In other embodiments, the higher-density dielectric may be fabricated using semiconductor manufacturing processes, such as single damascene or dual damascene processes. In some embodiments, additional dies may be disposed on the top surface of dies 114-2, 114-3. In some embodiments, additional components may be disposed on the top surface of dies 114-2, 114-3. Additional passive components such as surface mount resistors, capacitors and / or inductors may be disposed on the top or bottom surface of the package substrate 102, or embedded in the package substrate 102.

[0039] Figure 1The microelectronic assembly 100 may also include an underfill material 127. In some embodiments, the underfill material 127 may extend between the substrate 107 and the package substrate 102, surrounding the associated STPS interconnect 150. In some embodiments, the underfill material 127 may extend between the top surfaces of the substrate 107, surrounding the different dies in the top dies 114-2, 114-3 and the associated DTS interconnect 140, and extend between the top dies 114-2, 114-3, surrounding the bridging die 114-1 and the DTD interconnect 130. The underfill material 127 may be an insulating material, such as a suitable epoxy resin material. In some embodiments, the underfill material 127 may include capillary underfill, non-conductive film (NCF), or molded underfill. In some embodiments, the underfill material 127 may include epoxy flux that facilitates soldering the multilayer die subassembly 104 to the package substrate 102 when the STPS interconnect 150 is formed, and then polymerizing and encapsulating the STPS interconnect 150. The underfill material 127 may be selected to have a CTE, which can mitigate or minimize stress between the substrate 107 and the package substrate 102 caused by uneven thermal expansion in the microelectronic assembly 100. In some embodiments, the CTE of the underfill material 127 may have a value between the CTE of the package substrate 102 (e.g., the CTE of the dielectric material of the package substrate 102) and the CTE of the die 114 and / or dielectric material 112 of the substrate 107.

[0040] The STPS interconnect 150 disclosed herein may take any suitable form. In some embodiments, a set of STPS interconnects 150 may include solder (e.g., solder bumps or balls formed by thermal reflow to create the STPS interconnect 150), such as... Figure 1 As shown, the STPS interconnect 150 may include solder between conductive contacts 144 on the bottom surface of substrate 107 and conductive contacts 146 on the top surface of encapsulation substrate 102. In some embodiments, a set of STPS interconnects 150 may include anisotropic conductive materials, such as anisotropic conductive films or anisotropic conductive adhesives. The anisotropic conductive materials may include conductive materials dispersed in non-conductive materials.

[0041] The DTD interconnects 130 disclosed herein can take any suitable form. In a microelectronic assembly, the DTD interconnects 130 can have a finer pitch than the STPS interconnects 150. In some embodiments, the die 114 on either side of a set of DTD interconnects 130 can be an unpackaged die, and / or the DTD interconnects 130 can include small conductive bumps (e.g., copper bumps). The DTD interconnects 130 may have a pitch too fine to be directly coupled to the package substrate 102 (e.g., too fine to be used as DTS interconnects 140 or STPS interconnects 150). In some embodiments, a set of DTD interconnects 130 can include solder. In some embodiments, a set of DTD interconnects 130 can include anisotropic conductive materials, such as any of the materials discussed above. In some embodiments, the DTD interconnects 130 can be used as data transmission channels, while the STPS interconnects 150 can be used as power lines and ground lines, etc. In some embodiments, some or all of the DTD interconnects 130 in the microelectronic assembly 100 can be metal-to-metal interconnects (e.g., copper-to-copper interconnects, or plated interconnects). In such embodiments, DTD interconnects 130 may be bonded together (e.g., under elevated pressure and / or temperature) without using intermediate solder or anisotropic conductive materials. Any conductive contacts disclosed herein (e.g., conductive contacts 122, 124, 144, and / or 146) may include, for example, bonding pads, solder bumps, conductive pillars, or any other suitable conductive contacts. In some embodiments, some or all of the DTD interconnects 130 and / or DTS interconnects 140 in the microelectronic assembly 100 may be solder interconnects, comprising solders with a higher melting point than the solders included in some or all of the STPS interconnects 150. For example, when the DTD interconnects 130 and DTS interconnects 140 in the microelectronic assembly 100 are formed prior to the formation of the STPS interconnects 150, the solder-based DTD interconnects 130 and DTS interconnects 140 may use solders with higher temperatures (e.g., melting points above 200 degrees Celsius), while the STPS interconnects 150 may use solders with lower temperatures (e.g., melting points below 200 degrees Celsius). In some embodiments, higher temperature solders may include tin; tin and gold; or tin, silver and copper (e.g., 96.5% tin, 3% silver and 0.5% copper). In some embodiments, lower temperature solders may include tin and bismuth (e.g., eutectic tin-bismuth) or tin, silver and bismuth. In some embodiments, lower temperature solders may include indium, indium and tin or gallium.

[0042] In the microelectronic assembly 100 disclosed herein, some or all of the DTS interconnects 140 and STPS interconnects 150 may have a spacing greater than that of some or all of the DTD interconnects 130. The DTD interconnects 130 may have a smaller spacing than the STPS interconnects 150 because the materials in the different dies 114 on either side of a set of DTD interconnects 130 are more similar than the materials between the substrate 107 and top dies 114-2, 114-3 on either side of a set of DTS interconnects 140, and between the substrate 107 and the package substrate 102 on either side of a set of STPS interconnects 150. In particular, differences in the material composition of the substrate 107 and the die 114 or package substrate 102 may lead to different expansion and contraction due to heat generated during operation (and heat applied during various manufacturing operations). To mitigate damage caused by these different expansions and contractions (e.g., cracks, solder bridging, etc.), the DTS interconnect 140 and STPS interconnect 150 can be formed larger and more widely spaced than the DTD interconnect 130. Due to the greater material similarity of the pair of dies 114 on either side of the DTD interconnect, the DTD interconnect 130 may experience less thermal stress. In some embodiments, the DTS interconnect 140 disclosed herein may have a pitch between 25 micrometers and 250 micrometers. In some embodiments, the STPS interconnect 150 disclosed herein may have a pitch between 55 micrometers and 1000 micrometers, while the DTD interconnect 130 disclosed herein may have a pitch between 25 micrometers and 100 micrometers.

[0043] Figure 1 The microelectronic assembly 100 may also include a circuit board (not shown). The package substrate 102 may be coupled to the circuit board via a second-level interconnect on the bottom surface of the package substrate 102. The second-level interconnect can be any suitable second-level interconnect, including solder balls for a ball grid array arrangement, pins in a pin grid array arrangement, or contacts in a contact grid array arrangement. For example, the circuit board may be a motherboard and may have other components attached thereto. As known in the art, the circuit board may include conductive paths and other conductive contacts for routing power, ground, and signals through the circuit board. In some embodiments, the second-level interconnect may not couple the package substrate 102 to the circuit board, but may instead couple the package substrate 102 to another IC package, inserter, or any other suitable component. In some embodiments, the substrate 107 may not be coupled to the package substrate 102, but may instead be coupled to a circuit board, such as a PCB.

[0044] although Figure 1A microelectronic assembly 100 is depicted having a substrate with a specific number of dies 114 and conductive paths provided by conductive material 108 coupled to the other dies 114, but this number and arrangement are illustrative only, and the microelectronic assembly 100 may include any desired number and arrangement of dies 114. Although Figure 1 Die 114-1 is shown as a dual-sided die, and dies 114-2 and 114-3 are shown as single-sided dies, but dies 114-2 and 114-3 can be dual-sided dies, and die 114 can be a single-pitch die or a mixed-pitch die. In some embodiments, additional components may be disposed on the top surface of dies 114-2 and / or 114-3. In this context, a dual-sided die refers to a die having connections on both surfaces. In some embodiments, a dual-sided die may include through-holes (TSVs) to form connections on both surfaces. The active surfaces of a dual-sided die containing one or more active devices and a majority of interconnects can be oriented in either direction depending on design and electrical requirements.

[0045] Figure 1 Many elements of the microelectronic assembly 100 are included in other figures in the accompanying drawings; when discussing these figures, the discussion of these elements will not be repeated, and any of these elements may take any form disclosed herein. Furthermore, various elements are... Figure 1 The components are shown as included in the microelectronic assembly 100; however, in various embodiments, some of these components may not be included. For example, in various embodiments, additional layers 111, underfill material 127, and packaging substrate 102 may not be present in the microelectronic assembly 100. In some embodiments, individual microelectronic assemblies in the microelectronic assembly 100 disclosed herein may be used as system-in-package (SiP), comprising multiple dies 114 with different functionalities. In such embodiments, the microelectronic assembly 100 may be referred to as a SiP.

[0046] Figure 2 This is a schematic cross-sectional view of another example microelectronic assembly 100 according to some embodiments of the present disclosure. Apart from the differences as further described, the configuration of the embodiment shown in the figure is similar to that of the embodiment shown in the figure. Figure 1 The configuration. Instead of, for example... Figure 1 The diagram shows a glass core 110 as part of a substrate 107. Figure 2 The microelectronic assembly 100 includes its own glass core 110, wherein one or more dies 114 can be coupled to the glass core 110. Figure 2In this process, the multilayer die subassembly 104 includes a glass core 110 and a plurality of dies 114 as described above. The multilayer die subassembly 104 may have a first surface 160-1 (e.g., a bottom surface) and opposing second surfaces 160-2 (e.g., a top surface). The glass core 110 may be... Figure 2 The multilayer die assembly 104 and / or microelectronic assembly 100 provide mechanical stability, reduce warpage, and provide a more robust surface for attaching the multilayer die assembly 104 to the packaging substrate 102 or other substrates (e.g., inserters or circuit boards).

[0047] The glass core 110 may include a cavity 129 having an opening facing the second surface 160-2, and the die 114-1 may be wholly or at least partially nested within the cavity 129. Figure 2 As shown, when die 114-1 is fully nested in cavity 129, the top surface of die 114-1 may be coplanar with or below the top surface of glass core 110. When die 114-1 is partially nested in cavity 129, the top surface of die 114-1 may extend above the top surface of glass core 110. As described above, cavity 129 may be at least partially filled with dielectric material 112A or 112B. Die 114-1 may be attached to the bottom surface of cavity 129 via die attachment film (DAF) 132. DAF 132 may be any suitable material, including non-conductive adhesive, die attachment film, B-stage underfill material, or polymer film with adhesive properties. DAF 132 may have any suitable dimensions; for example, in some embodiments, DAF 132 may have a thickness (e.g., height or z-height) between 5 micrometers and 10 micrometers.

[0048] Die 114-1 can be coupled to dies 114-2 and 114-3 in the layer above die 114-1 via DTD interconnect 130. DTD interconnect 130 can be disposed between some conductive contacts 122 at the bottom of dies 114-2 and 114-3 and some conductive contacts 124 at the top of die 114-1. Other conductive contacts 122 at the bottom of dies 114-2 and / or 114-3 can also be coupled to one or more of dies 114-2 and 114-3 to glass core 110 via glass core-to-die (GCTD) interconnect 142. GCTD interconnect 142 can be disposed between some conductive contacts 122 at the bottom of dies 114-2 and 114-3 and some conductive contacts 128 at the top of glass core 110. As described above, GCTD interconnect 142 can be similar to DTS interconnect 140. In some embodiments, the underfill material 127 may extend between different dies 114 in the die 114 surrounding the associated DTD interconnect 130 and / or GCTD interconnect 142. In some embodiments, dies 114-2 and / or dies 114-3 may be embedded in an insulating material 133. In some embodiments, the total thickness (e.g., z-height) of the insulating material 133 may be between 200 micrometers and 800 micrometers (e.g., substantially equal to the thickness of dies 114-2 or 114-3 and the underfill material 127). In some embodiments, the insulating material 133 may be formed in a multilayer (e.g., a dielectric material formed in a multilayer as known in the art), and one or more dies 114 may be embedded in one layer. In some embodiments, the insulating material 133 may be a dielectric material, such as an organic dielectric material, a flame retardant grade 4 material (FR-4), BT resin, a polyimide material, a glass-reinforced epoxy matrix material, or a low-k and ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, and an organic polymer dielectric). In some embodiments, the insulating material 133 may be a mold material, such as an organic polymer having inorganic silica particles.

[0049] like Figure 2 As shown, the glass core 110 may further include a conductive contact 126 at the bottom of the glass core 110, and the TGV 115 may extend and be electrically connected between the conductive contact 126 at the bottom of the glass core 110 and the conductive contact 128 at the top of the glass core 110. The conductive contacts 126, 128 may be similar to other conductive contacts disclosed herein (e.g., conductive contacts 122, 124, 144 and / or 146) and may include, for example, bonding pads, solder bumps, conductive pillars, or any other suitable conductive contacts. Figure 2As shown, in some embodiments, at least some of the TGV 115s may have an hourglass shape. For example, at least some of the TGV 115s may have a first width at a first surface of the glass core 110 (e.g., at the bottom surface of the glass core 110), a second width at a second surface of the glass core 110 (e.g., at the top surface of the glass core 110), and a third width between the first and second surfaces of the glass core 110, wherein the third width is smaller than the first and second widths.

[0050] Dies 114-2 and 114-3 can be electrically coupled to package substrate 102 via TGV 115 and Glass Core to Package Substrate (GCTPS) interconnect 152, which can be a power delivery interconnect or a high-speed signal interconnect. As described above, GCTPS interconnect 152 can be similar to STPS interconnect 150. The top surface of package substrate 102 may include a set of conductive contacts 146, and the multilayer die subassembly 104 may include a set of conductive contacts 126 on a first surface 160-1. GCTPS interconnect 152 can couple conductive contacts 146 to corresponding conductive contacts 126 between conductive contacts 146 and conductive contacts 126. In some embodiments, an underfill material 127 may extend between package substrates 102, surrounding glass core 110 and associated GCTPS interconnect 152.

[0051] For reference Figure 1 or Figure 2 The glass core 110 included in the microelectronic assembly 100, or any other glass core 110 included in the microelectronic assembly or device, may be subjected to TGV stress before being included in the microelectronic assembly 100. For example, according to some embodiments of this disclosure, Figure 3 The surface of glass core 110 is shown, at which TGV stress can begin. (See diagram.) Figure 3 As shown, the glass core 110 may have a first surface 190-1 and an opposing second surface 190-2. For example, when the glass core 110 is included in the microelectronic assembly 100, it may be a bottom surface and a top surface (wherein, the first and second surfaces 190-1, 190-2 together may be referred to as "surface 190"). The glass core 110 may also include a side 190-3, which is a surface of the glass core 110 and may be referred to as an edge or sidewall of the glass core 110, i.e., a surface extending between the first surface 190-1 and the second surface 190-2. Figure 3As further shown, a TGV opening 192 may be formed in the glass core 110, extending between a first surface 190-1 and a second surface 190-2. Sidewalls 190-4 may refer to one or more sidewalls of the TGV opening 192. When conductive material is deposited in the TGV opening 192, TGV stress may begin at the sidewalls 190-4 due to the CTE mismatch between the glass material of the glass core 110 and the conductive material in the TGV opening 192.

[0052] Before including the glass core 110 in the microelectronic assembly 100, techniques involving the use of dual pads for TGV stress relief, as described herein, can be applied to reduce TGV stress at the sidewalls 190-4. Specifically, a method for providing dual pads for TGV is shown as follows: Figure 4 Method 400. Although the operations of method 400 are illustrated in a specific order and only once per illustration, the operations can be performed in any suitable order and repeated as needed. For example, one or more operations can be performed in parallel to fabricate multiple TGVs with double liner substantially simultaneously. In another example, one or more operations can be performed in parallel to fabricate TGVs with double liner substantially simultaneously in multiple glass cores. Furthermore, example fabrication method 400 may include... Figure 4 Other operations not specifically shown herein include, for example, various cleaning or planarization operations as known in the art. For instance, in some embodiments, the glass core 110 and various other material layers subsequently deposited thereon may be cleaned before, after, or during any process of method 400, for example, to remove oxides, surface-bound organic and metallic contaminants, and subsurface contaminants. In some embodiments, cleaning may be performed using, for example, chemical solutions (e.g., peroxides), and / or ultraviolet (UV) radiation combined with ozone, and / or surface oxidation (e.g., using thermal oxidation) followed by oxide removal (e.g., using hydrofluoric acid (HF)). Figures 5A-5D Cross-sectional side views are provided for various stages of manufacturing an example glass core according to method 400 according to some embodiments. Figure 5D The microelectronic assembly 508 shown may be an example of any microelectronic assembly 100 described herein. Figures 5A-5D A cross-sectional side view of a portion of the glass core 110 is shown (e.g., a view in the yz plane of the example coordinate system 105 described herein), wherein... Figure 4 The manufacturing process of the method shown forms three TGVs with double pads.

[0053] Turning Figure 4 The manufacturing method shown in the figure, method 400 may begin with process 402, including providing a glass core having one or more TGV openings therein. Figure 5AAn assembly 502, which could be an example result of process 402, is shown, illustrating a glass core 110 having a TGV opening 520. Although Figure 5A as well as Figures 5B-5D A TGV opening 520 extending between a first face 190-1 and a second face 190-2 of the glass core 110 is shown, but the description provided herein applies to openings that are blind openings, such as openings that begin at one of the faces 190 and extend toward the other face of the faces 190 but do not reach said face. Furthermore, although in Figure 5A as well as Figures 5B-5D Three TGV openings 520 are shown, but in other embodiments, the microelectronic assembly described herein may include any number of one or more TGV openings 520. In various embodiments, the TGV openings 520 may be formed in the glass core 110 using any suitable subtractive technique, such as direct laser drilling or laser-induced etching, possibly combined with any suitable patterning technique, such as photolithography or electron beam (e-beam) patterning. In other embodiments, the TGV openings 520 may be formed during the fabrication of the glass core 110 itself, for example, when molten glass is filled into a mold having spaces for future TGV openings 520.

[0054] Next, method 400 may include process 404, wherein the TGV opening 520 of process 402 may be lined with a first gasket. For this purpose, a first gasket may be deposited on the sidewall of the TGV opening 520 formed in process 402, and for those TGV openings 520 that can be implemented as blind openings, a first gasket may also be deposited on the bottom of the TGV opening 520. Figure 5BThe illustration shows an assembly 504, which may be an example result of process 404, with a glass core 110 in which a TGV opening 520 is lined with a first liner 522. In various embodiments, the first liner 522 can be deposited using any suitable deposition technique such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). In some embodiments, in addition to being set as a liner in the TGV opening 520, the first liner 522 may also be deposited on a first surface 190-1, a second surface 190-2, or both surfaces 190, depending on the deposition technique used to provide the first liner 522. In such embodiments, the first liner 522 deposited on the first surface 190-1 and / or the second surface 190-2 may be materially continuous with the first liner 522 on the sidewalls of the TGV opening 520. In some embodiments, a portion of the first pad 522 on the sidewall of the TGV opening 520 may contact the sidewall of the TGV opening 520 (e.g., contact the glass core 110 at the sidewall of the TGV opening 520). In some embodiments, the thickness of the first pad 522 may be between approximately 200 nanometers and approximately 10 micrometers, for example, between approximately 200 nanometers and approximately 5 micrometers, or between approximately 500 nanometers and approximately 1 micrometer. In some embodiments, the first pad 522 may be deposited as a conformal layer, i.e., it may conform to the shape of the underlying surface on which the first pad 522 is deposited.

[0055] The first liner 522 may comprise any suitable material that separates the glass material of the glass core 110 at the sidewall of the TGV opening 520 from the conductive material to be deposited later in the TGV opening 520, facilitating a smooth glass surface at the sidewall of the TGV opening 520 and resisting tensile stresses caused by, for example, the shrinkage of metal subsequently filled into the TGV opening 520. In some embodiments, the first liner 522 may comprise a material having a relatively high modulus, for example, having a Young's modulus greater than about 30 GPa, for example, greater than about 50 GPa, for example, between about 85 GPa and about 190 GPa or between about 100 GPa and about 600 GPa, wherein Young's modulus can be defined as the ratio of stress to strain in a material undergoing deformation. In various embodiments, the first liner 522 may comprise a material having a modulus greater than that of the second liner 524 deposited in a subsequent process. In some embodiments, the first liner 522 may comprise a material having a modulus greater than that of the glass core 110 and / or a modulus greater than that of the conductive filler material 528 deposited in subsequent processes (e.g., Young's modulus). In some embodiments, the CTE of the first liner 522 may be less than that of the conductive filler material 528, for example, less than about 17 ppm / K or less than about 15 ppm / K or 10 ppm / K. For example, the CTE of the first liner 522 may be between about 3 ppm / K and about 12 ppm / K, or between about 3 ppm / K and about 10 ppm / K. Placing a material with such a relatively low CTE as the material in contact with the sidewall of the TGV opening 520, compared to the metal(s) of the conductive filler material 528, reduces the CTE difference of the glass material of the glass core 110, which can help reduce stress caused by CTE mismatch. Some examples of materials that can be used as the first liner 522 are inorganic materials, such as inorganic materials comprising silicon and oxygen (e.g., silicon oxide), materials comprising silicon and nitrogen (e.g., silicon nitride), materials comprising silicon, oxygen, and nitrogen (e.g., silicon oxynitride), or materials comprising one or more metals and oxygen (e.g., metal oxides such as aluminum oxide or hafnium oxide). Other examples of materials that can be used as the first liner 522 are organosilicones (e.g., materials that contain organic (carbon-based) and inorganic (e.g., silicon-based) components in their chemical structure), such as methylsiloxane (dimethylsiloxane), phenylsiloxane (diphenylsiloxane), or polysilsesquioxane.

[0056] Next, method 400 may include process 406, wherein the TGV opening 520, which was lined with a first liner 522 at the end of process 404, may be lined with a second liner. For this purpose, a second liner may be deposited on top of the first liner 522. Figure 5CAn assembly 506, which may be an example result of process 406, is shown, illustrating a glass core 110 in which the TGV opening 520 is lined not only with a first liner 522 but also with a second liner 524. In various embodiments, the second liner 524 can be deposited using any suitable deposition technique such as CVD, ALD, or PVD. In some embodiments, in addition to being positioned within the TGV opening 520, the second liner 524 may also be disposed on the first surface 190-1, the second surface 190-2, or both surfaces 190, depending on the deposition technique used to provide the second liner 524. In such embodiments, the second liner 524 deposited on the first surface 190-1 and / or the second surface 190-2 may be materially continuous with the second liner 524 on the sidewall of the TGV opening 520. In some embodiments, portions of the second liner 524 on the sidewall of the TGV opening 520 may contact portions of the first liner 522 on the sidewall of the TGV opening 520. In some embodiments, the thickness of the second pad 524 may be between approximately 200 nanometers and approximately 10 micrometers, for example, between approximately 200 nanometers and approximately 5 micrometers, or between approximately 500 nanometers and approximately 1 micrometer. In some embodiments, the second pad 524 may be deposited as a conformal layer, i.e., it may conform to the shape of the underlying surface on which the second pad 524 is deposited.

[0057] The second liner 524 may comprise any suitable material that can contribute to a stress-absorbing layer between the glass material of the glass core 110 at the sidewall of the TGV opening 520 and the conductive material to be deposited later in the TGV opening 520. In some embodiments, the second liner 524 may comprise a material having a relatively low modulus, for example, having a Young's modulus below about 30 GPa, for example, below about 10 GPa, for example, between about 3 GPa and 30 GPa or between about 1 GPa and 30 GPa. In various embodiments, the second liner 524 may comprise a material having a modulus less than that of the first liner 522 deposited in process 404. In some embodiments, the second liner 524 may comprise a material having a modulus less than that of the glass core 110 and / or having a modulus less than that of the conductive filler material 528 deposited in a subsequent process. In some embodiments, the CTE of the second pad 524 may be less than the CTE of the conductive filler material 528, for example, less than about 17 ppm / K or less than about 15 ppm / K or 10 ppm / K; although in other embodiments, the CTE of the second pad 524 may be approximately the same or greater. In some embodiments, the second pad 524 may comprise a polymeric material, such as an organic polymer, like polyimide (PI). In other embodiments, the second pad 524 may comprise organic materials other than polymers, such as monomers or oligomers. In some embodiments, the second pad 524 may comprise a homopolymer, which is a polymer composed of repeating units of a single type of monomer. Simple signal chemistry system organic pads such as homopolymers may be particularly advantageous for use as the second pad 524 because they can be manufactured relatively easily and because they can be readily adapted for use as the second pad 524. In some embodiments, the second pad 524 may comprise parylene (which is also commonly referred to as "parylene"), such as parylene N, parylene C, parylene D, or halogen-free parylene. In other embodiments, the second liner 524 may include a heteropolymer, which is a polymer composed of repeating units of two or more types of monomers or oligomers. For example, the second liner 524 may include a heteropolymer such as polyester (PET), polyurethane (PU), polycarbonate (PC), polyvinyl chloride (PVC), or polybenzoxazole (PBO).

[0058] Then method 400 can proceed to process 408, in which TGV metallization can be performed on assembly 506, wherein TGV opening 520 is lined with a double liner including a first liner 522 and a second liner 524. Figure 5DA combination 508, which can be an example result of process 408, is shown. TGV metallization can include depositing a seed material layer 526 to line a TGV opening 520 lined with a first pad 522 and a second pad 524, and then at least partially filling the remaining space in the TGV opening 520 with a conductive filler material 528 to form a conductive via in the form of the TGV opening 520. The TGV opening 520 filled with conductive material is an example of any TGV 115 described herein. The seed material 526 can include any suitable conductive material, such as a metal, metal alloy, or combination of metals, such as a low-resistivity metal like copper, which can be deposited as a thin layer on the substantially non-conductive surface (e.g., sidewall) of the TGV opening 520 lined with the first pad 522 and the second pad 524. The seed material 526 provides a conductive surface for the uniform and controlled deposition of the conductive filler material in subsequent steps of the TGV metallization process 408. For example, the seed material 526 can be used as a base or substrate for subsequent electroplating of thicker metal layers. In some embodiments, seed material 526 may comprise one or more metals, such as copper, ruthenium, nickel, gold, palladium, platinum, or silver. In various embodiments, the thickness of the seed material 526 layer, measured, for example, in a direction perpendicular to the sidewall of the TGV opening 520, may be between approximately 5 nanometers and 20 micrometers, for example, between approximately 10 nanometers and 15 micrometers, or between approximately 10 nanometers and 1 micrometer. In various embodiments, seed material 526 may be deposited using any suitable deposition technique such as CVD, ALD, or PVD. In some embodiments, seed material 526 may be deposited as a conformal layer. In some embodiments, seed material 526 may comprise two or more layers of different conductive materials sequentially deposited on the second pad 524. For example, seed material 526 may comprise a first material layer deposited on the second pad 524, and then a second material layer deposited on the first material. The first material may be a conductive material, and may have good adhesion between the first material and the second pad 524. The second material can be a conductive material that protects the first material from oxidation before and / or during the deposition of the conductive filler material in subsequent processes. For example, the first seed material 526 may include titanium, while the second seed material 526 may include copper. In other embodiments, the seed material 526 may include a single layer of conductive material, such as a copper layer or a ruthenium layer. The conductive filler material 528 may include any suitable conductive material, such as any material described with reference to the seed material 526. In some embodiments, the material composition of the seed material 526 and the conductive filler material 528 may be substantially the same; for example, both may be copper, or may include copper. In other embodiments, the material composition of the seed material 526 and the conductive filler material 528 may be different.The conductive filler material 528 can be deposited using any suitable deposition technique such as electroplating, ALD, CVD or PVD.

[0059] The various embodiments of the TGV with dual pads described above can be advantageously manufactured in parallel with conventional manufacturing techniques for glass core substrates. For example... Figure 1 The various arrangements of the microelectronic assembly 100 and glass core 110 shown in Figure 5 do not represent an exhaustive set of microelectronic assemblies and glass cores with double-padded TGV as described herein that can be implemented, but are merely illustrative examples. In particular, Figure 1 The number and location of the various elements shown in Figure 5 are purely illustrative, and in various other embodiments, other numbers of these elements provided in other locations relative to each other may be used in consideration of the general architecture described herein. For example, although not specifically shown in the present figures, in some embodiments, the microelectronic assembly 100 may include... Figure 1 and Figure 2 The redistribution layer (RDL) between any pair of layers shown in the figure includes multiple interconnect structures (e.g., conductive lines and conductive vias) to facilitate signal and / or power routing between components. In another example, although not specifically shown in the current figures, in some embodiments, the packaging substrate 102 of the microelectronic assembly 100 may include one or more recesses. In such embodiments, the bottom surface of the recess in the packaging substrate 102 may be provided by a solid material of the packaging substrate 102. The recesses may be formed in the packaging substrate 102 in any suitable manner (e.g., via 3D printing, laser cutting, or drilling the recesses into an existing packaging substrate). At least a portion of the substrate 107 or the glass core 110 may be located above or at least partially within such a recess. In yet another example, Figure 1 any of the features in -5 can be related to Figure 1 -5 features combined. For example, in some embodiments, some portions of glass core 110 may include one or more TGVs having a double liner manufactured using method 400, while other portions of glass core 110 may include TGVs without a double liner.

[0060] The microelectronic assembly 100 and / or glass core 110 disclosed herein (especially the glass core 110 having one or more TGVs and dual pads as described herein) may be included in any suitable electronic component. Figure 6-9 Various examples of devices that may be included or incorporated in any microelectronic assembly 100 and / or glass core 110 disclosed herein are shown.

[0061] Figure 6This is a top view of a wafer 1500 and a die 1502 that may be included in any microelectronic assembly 100 as described herein. For example, die 1502 may be any die 114 described herein. Wafer 1500 may be made of semiconductor material and may include one or more dies 1502 having an IC structure formed on the surface of wafer 1500. Each die 1502 may be a repeating unit of a semiconductor product including any suitable IC. After the semiconductor product is manufactured, wafer 1500 may undergo a dicing process in which dies 1502 are separated from each other to provide discrete “chips” of the semiconductor product. Die 1502 may include one or more transistors (e.g., discussed below). Figure 7 Some transistors 1640) and / or supporting circuit modules are used to route electrical signals to the transistors and any other IC components. In some embodiments, wafer 1500 or die 1502 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridged RAM (CBRAM) devices, etc.), logic devices (e.g., AND gates, OR gates, NAND gates, or NOR gates) or any other suitable circuit elements. Multiple devices of these devices may be combined on a single die 1502. For example, a memory array formed by multiple memory devices may be associated with a processing device (e.g., a processor) configured to store information in the memory devices or execute instructions stored in the memory array. Figure 9 The processing device 1802 or other logic is formed on the same die 1502.

[0062] Figure 7 This is a side cross-sectional view of an IC device 1600, which may be included in any microelectronic assembly 100 as described herein. For example, the IC device 1600 may be disposed on / in any die 114 described herein. The IC device 1600 may be formed on a substrate 1602 (e.g., Figure 6 On a 1500 wafer, and may be included on a die (e.g., Figure 6The substrate 1602 may be a semiconductor substrate composed of a semiconductor material system including, for example, an n-type or p-type material system (or a combination of both). The substrate 1602 may include, for example, a crystalline substrate formed using bulk silicon or silicon-on-insulator (SOI) substructures. In some embodiments, the substrate 1602 may be formed using alternative materials, which may or may not be bonded to silicon. Alternative materials include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as Group III-V materials (i.e., materials from Groups III and V of the periodic table), Group II-VI materials (i.e., materials from Groups II and IV of the periodic table), or Group IV materials (i.e., materials from Group IV of the periodic table) may also be used to form the substrate 1602. While several examples of materials from which the substrate 1602 may be formed are described herein, any material that can be used as the basis for the IC device 1600 may be used. The substrate 1602 may be a diced die (e.g., Figure 6 The die 1502) or wafer (e.g., Figure 6 A portion of the 1500 wafer.

[0063] IC device 1600 may include one or more device layers 1604 disposed on substrate 1602. Device layer 1604 may include features of one or more transistors 1640 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on substrate 1602. Device layer 1604 may include, for example, one or more source and / or drain (S / D) regions 1620, a gate 1622 controlling the current in the transistors 1640 between S / D regions 1620, and one or more S / D contacts 1624 routing electrical signals to / from S / D regions 1620. For clarity, transistors 1640 may include additional features not depicted, such as device isolation regions, gate contacts, etc. Transistor 1640 is not limited to... Figure 7 The types and configurations described herein may include a variety of other types and configurations, such as planar transistors, non-planar transistors, or combinations thereof. Planar transistors may include bipolar junction transistors (BJTs), heterojunction bipolar transistors (HBTs), or high electron mobility transistors (HEMTs). Non-planar transistors may include FinFET transistors, such as dual-gate or tri-gate transistors, and gate-all-around or fully-all-around transistors, such as nanoribbon and nanowire transistors.

[0064] Each transistor 1640 may include a gate 1622 formed of at least two layers, a gate dielectric, and a gate electrode. The gate dielectric may include a single layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when using a high-k material, an annealing process may be performed on the gate dielectric to improve its quality.

[0065] Depending on whether transistor 1640 is a p-type metal-oxide-semiconductor (PMOS) or an n-type metal-oxide-semiconductor (NMOS) transistor, the gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or an n-type work function metal. In some embodiments, the gate electrode may consist of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers, and at least one metal layer is a filler metal layer. Additional metal layers, such as barrier layers, may be included for other purposes. For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any metals discussed below with reference to NMOS transistors (e.g., for work function regulation). For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any metals discussed above with reference to PMOS transistors (e.g., for work function regulation).

[0066] In some embodiments, when a cross-section of transistor 1640 is viewed along the source-channel-drain direction, the gate electrode may be composed of a U-shaped structure including a bottom portion substantially parallel to the substrate surface and two sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, at least one metal layer forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the substrate and does not include the sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may be composed of a combination of U-shaped structures and planar non-U-shaped structures. For example, the gate electrode may be composed of one or more U-shaped metal layers formed on one or more planar non-U-shaped layers.

[0067] In some embodiments, a pair of sidewall spacers may be formed on opposite sides of the gate stack to support the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming the sidewall spacers are well known in the art and typically include deposition and etching steps. In some embodiments, multiple pairs of spacers may be used; for example, two, three, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0068] The S / D region 1620 may be formed within a substrate 1602 adjacent to the gate 1622 of each transistor 1640. For example, the S / D region 1620 may be formed using an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion-implanted into the substrate 1602 to form the S / D region 1620. An annealing process, activating the dopants and allowing them to diffuse further into the substrate 1602, may follow the ion implantation process. In the latter process, the substrate 1602 may be etched first to form a recess at the location of the S / D region 1620. An epitaxial deposition process may then be performed to fill the recess using the material used to fabricate the S / D region 1620. In some implementations, a silicon alloy such as silicon germanium or silicon carbide may be used to fabricate the S / D region 1620. In some embodiments, the epitaxially deposited silicon alloy may be in-situ doped with dopants such as boron, arsenic, or phosphorus. In some embodiments, the S / D region 1620 may be formed using one or more alternative semiconductor materials such as germanium or group III-V materials or alloys. In other embodiments, one or more layers of metal and / or metal alloys may be used to form the S / D region 1620.

[0069] One or more interconnect layers disposed on device layer 1604 (in Figure 7 The interconnect layers (1606, 1608, and 1610) route electrical signals, such as power and / or input / output (I / O) signals, to and from the device layer 1604 (e.g., transistor 1640). For example, conductive features of the device layer 1604 (e.g., gate 1622 and S / D contact 1624) may be electrically coupled to the interconnect structure 1628 of the interconnect layers 1606, 1608, and 1610. One or more interconnect layers 1606, 1608, and 1610 may form a metallization stack (also referred to as an "ILD stack") 1619 of the IC device 1600.

[0070] Interconnection structure 1628 can be arranged within interconnection layers 1606-1610 to route electrical signals according to various designs (in particular, this arrangement is not limited to...). Figure 7 The specific configuration of the interconnect structure 1628 depicted in the document). Although Figure 7The illustration depicts a specific number of interconnect layers 1606, 1608, and 1610, but embodiments of this disclosure include IC devices with more or fewer interconnect layers than the depicted IC device.

[0071] In some embodiments, the interconnect structure 1628 may include lines 1628a and / or vias 1628b filled with a conductive material (e.g., metal). Lines 1628a may be arranged to route electrical signals in a planar direction substantially parallel to the surface of the substrate 1602 on which the device layer 1604 is formed. For example, from... Figure 7 From this angle, line 1628a can route electrical signals in the direction of entering and exiting the page. Via 1628b can be arranged to route electrical signals in a planar direction substantially perpendicular to the surface of substrate 1602, on which device layer 1604 is formed. In some embodiments, via 1628b can electrically couple lines 1628a of different interconnect layers 1606, 1608, and 1610 together.

[0072] Interconnect layers 1606, 1608, and 1610 may include a dielectric material 1626 disposed between interconnect structures 1628, such as... Figure 7 As shown in the figure. In some embodiments, the dielectric material 1626 disposed between interconnect structures 1628 in different layers of interconnect layers 1606, 1608 and 1610 may have different compositions; in other embodiments, the composition of the dielectric material 1626 between different interconnect layers 1606, 1608 and 1610 may be the same.

[0073] A first interconnect layer 1606 may be formed over the device layer 1604. In some embodiments, as shown, the first interconnect layer 1606 may include a line 1628a and / or a via 1628b. The line 1628a of the first interconnect layer 1606 may be coupled to a contact (e.g., an S / D contact 1624) of the device layer 1604.

[0074] A second interconnect layer 1608 may be formed over a first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 may include a via 1628b to couple a line 1628a of the second interconnect layer 1608 to a line 1628a of the first interconnect layer 1606. Although for clarity, the line 1628a and the via 1628b are structurally depicted as lines within each interconnect layer (e.g., within the second interconnect layer 1608), in some embodiments, the line 1628a and the via 1628b may be structurally and / or materially continuous (e.g., simultaneously filled during a dual damascene process).

[0075] According to similar techniques and configurations described in conjunction with the second interconnect layer 1608 or the first interconnect layer 1606, a third interconnect layer 1610 (and additional interconnect layers, as needed) may be continuously formed on the second interconnect layer 1608. In some embodiments, the “higher” interconnect layers (i.e., further away from the device layer 1604) in the metallization stack 1619 of the IC device 1600 may be thicker.

[0076] IC device 1600 may include solder resist 1634 (e.g., polyimide or similar material) and one or more conductive contacts 1636 formed on interconnect layers 1606, 1608, and 1610. Figure 7 In the diagram, conductive contact 1636 is shown in the form of a bonding pad. Conductive contact 1636 may be electrically coupled to interconnect structure 1628 and is configured to route electrical signals from transistor(s) 1640 to other external devices. For example, solder joints may be formed on one or more conductive contacts 1636 to mechanically and / or electrically couple a chip including IC device 1600 to another component (e.g., a circuit board). IC device 1600 may include additional or alternative structures to route electrical signals from interconnect layers 1606, 1608, and 1610; for example, conductive contact 1636 may include other similar features (e.g., posts) for routing electrical signals to external components.

[0077] Figure 8 The following is a side cross-sectional view of an IC device assembly 1700 according to any embodiment disclosed herein, which may include a glass core having one or more TGVs with dual pads. The IC device assembly 1700 includes multiple components disposed on a circuit board 1702 (e.g., which may be a motherboard). The IC device assembly 1700 includes components disposed on a first surface 1740 and an opposing second surface 1742 of the circuit board 1702; typically, components may be disposed on one or both surfaces 1740 and 1742. Any IC package discussed below with reference to the IC device assembly 1700 may take the form of any embodiment of the microelectronic assembly 100 discussed above, for example, may include, as referenced... Figure 1 and Figure 2 One or more microelectronic assemblies 100 are discussed, and / or may include, as referenced Figure 3 -5. One or more glass cores are discussed.

[0078] In some embodiments, circuit board 1702 may be a printed circuit board comprising multiple metal layers separated from each other by dielectric material layers and interconnected by conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals between components coupled to circuit board 1702 (optionally in conjunction with other metal layers). In other embodiments, circuit board 1702 may be a non-PCB substrate.

[0079] Figure 8 The IC device assembly 1700 shown includes an interposer-on-package structure 1736 coupled to a first side 1740 of a circuit board 1702 via a coupling assembly 1716. The coupling assembly 1716 can electrically and mechanically couple the interposer-on-package structure 1736 to the circuit board 1702 and may include solder balls (such as...). Figure 8 (as shown), the protrusions and recesses of the socket, adhesive, underfill material and / or any other suitable electrical and / or mechanical coupling structure.

[0080] The on-mount package structure 1736 may include an IC package 1720 coupled to the package inserter 1704 via a coupling component 1718. The coupling component 1718 may take any form suitable for the application, such as the form discussed above with reference to coupling component 1716. Although Figure 8 A single IC package 1720 is shown, but multiple IC packages can be coupled to package inserter 1704; in fact, additional inserters can be coupled to package inserter 1704. Package inserter 1704 can provide an intermediate substrate for bridging circuit board 1702 and IC package 1720. IC package 1720 can be or include, for example, a die (die 1502 of FIG. 5), an IC device (e.g., any IC device described herein, or any combination of such IC devices), or any other suitable component. Typically, package inserter 1704 can extend connections to wider spacing or reroute connections to different connections. For example, package inserter 1704 can couple IC package 1720 (e.g., die) to a set of ball grid array (BGA) conductive contacts of coupling assembly 1716 for coupling to circuit board 1702. Figure 8 In the illustrated embodiment, the IC package 1720 and the circuit board 1702 are attached to opposite sides of the package inserter 1704; in other embodiments, the IC package 1720 and the circuit board 1702 may be attached to the same side of the package inserter 1704. In some embodiments, three or more components may be interconnected via the package inserter 1704.

[0081] In some embodiments, the package inserter 1704 may be formed as a glass core having one or more TGVs having a dual pad as described herein, for example, any embodiment of the glass core 110 as described herein. In some embodiments, the package inserter 1704 may be formed as a PCB. In some embodiments, the package inserter 1704 may be formed of epoxy resin, glass fiber reinforced epoxy resin, epoxy resin with inorganic fillers, ceramic materials, or polymeric materials such as polyimide. In some embodiments, the package inserter 1704 may be formed of alternative rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other group III-V and group IV materials. In any of these embodiments, the package inserter 1704 may include a plurality of metal layers separated from each other by a dielectric material layer and interconnected by conductive vias. The package inserter 1704 may include metal lines 1710 and vias 1708, including but not limited to conductive vias 1706. If the package inserter 1704 is a glass core, such as glass core 110 as described herein, then the conductive via 1706 can be a TGV 115 as described herein, such as a TGV with dual pads as described herein. The package inserter 1704 may also include embedded devices 1714, including passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the package inserter 1704. The on-insert package structure 1736 can take the form of any on-insert package structure known in the art.

[0082] IC device assembly 1700 may include IC package 1724 coupled to a first side 1740 of circuit board 1702 via coupling component 1722. Coupling component 1722 may take the form of any embodiment discussed above with reference to coupling component 1716, and IC package 1724 may take the form of any embodiment discussed above with reference to IC package 1720.

[0083] Figure 8The IC device assembly 1700 shown includes a package-on-package structure 1734 coupled to a second side 1742 of a circuit board 1702 via a coupling assembly 1728. The package-on-package structure 1734 may include IC packages 1726 and 1732 coupled together via a coupling assembly 1730, such that IC package 1726 is disposed between the circuit board 1702 and IC package 1732. Coupling assemblies 1728 and 1730 may take the form of any embodiment of the coupling assembly 1716 described above, and IC packages 1726 and 1732 may take the form of any embodiment of the IC package 1720 described above. The package-on-package structure 1734 can be configured according to any package-on-package structure known in the art.

[0084] Figure 9 This is a block diagram of an example communication device 1800, which may include any one or more microelectronic assemblies 100 and / or one or more glass cores 110 according to the embodiments disclosed herein. A handheld or laptop communication device may be an example of the communication device 1800. Any suitable component of the communication device 1800 may include one or more of the microelectronic assemblies 100, IC packages 1720, 1724, IC device assemblies 1700, IC devices 1600, or dies 1502 disclosed herein. In particular, any suitable component of the communication device 1800 may include one or more glass cores 110 as described herein, for example, as part of the microelectronic assembly 100 described herein. Figure 9 The diagram illustrates several components included in the communication device 1800, but any one or more of these components may be omitted or copied, as appropriate for the application. In some embodiments, some or all of the components included in the communication device 1800 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated on a single system-on-a-chip (SoC) die.

[0085] Furthermore, in various embodiments, the communication device 1800 may not include... Figure 9 The communication device 1800 may include one or more components as shown, but may include interface circuit modules for coupling to one or more components. For example, the communication device 1800 may not include the display device 1806, but may include display device interface circuitry (e.g., connector and driver circuit modules) to which the display device 1806 may be coupled. In another set of examples, the communication device 1800 may not include the audio input device 1824 or the audio output device 1808, but may include audio input or output device interface circuitry (e.g., connector and support circuit modules) to which the audio input device 1824 or the audio output device 1808 may be coupled.

[0086] Communication device 1800 may include processing device 1802 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to convert that electronic data into other electronic data that can be stored in registers and / or memory. Processing device 1802 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (dedicated processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. Communication device 1800 may include memory 1804, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic RAM (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or hard disk drives. In some embodiments, memory 1804 may include memory that shares a die with processing device 1802. This memory may be used as cache memory and may include embedded DRAM (eDRAM) or spin-transfer torque magnetic RAM (STT-MRAM).

[0087] In some embodiments, the communication device 1800 may include a communication module 1812 (e.g., one or more communication modules). For example, the communication module 1812 may be configured to manage wireless communication for transmitting data to and from the communication device 1800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., which can transmit data via modulated electromagnetic radiation through a non-solid medium. This term does not imply that the associated devices do not contain any wires, although in some embodiments they may not contain any wires. The communication module 1812 may be or may include any microelectronic assembly 100 disclosed herein.

[0088] The communication module 1812 can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendments), Long Term Evolution (LTE) projects, and any amendments, updates, and / or revisions (e.g., Advanced LTE projects, Ultra Mobile Broadband (UMB) projects (also known as “3GPP2”). IEEE 802.16 compliant Broadband Wireless Access (BWA) networks are often referred to as WiMAX networks, an acronym for Global Interoperability of Microwave Access, which is implemented through IEEE... The certification mark for products that have passed 802.16 standard conformance and interoperability testing. Communication module 1812 can operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High-Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. Communication module 1812 can operate according to Enhanced Data GSM Evolution (EDGE), GSMEDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). Communication module 1812 can operate according to Code Division Multiple Access (CDMA). The communication module 1812 can operate according to Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolved Data Optimization (EV-DO) and its derivative protocols, as well as any other wireless protocols designated as 3G, 4G, 5G and above. In other embodiments, the communication module 1812 may operate according to other wireless protocols. The communication device 1800 may include an antenna 1822 for facilitating wireless communication and / or receiving other wireless communications (e.g., AM or FM radio transmissions). The antenna 1822 may include one or more microelectronic assemblies 100 and / or one or more glass cores 110 as described herein, for example as part of the microelectronic assembly 100 described herein.

[0089] In some embodiments, communication module 1812 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, communication module 1812 may include multiple communication modules. For example, a first communication module 1812 may be dedicated to short-range wireless communications such as Wi-Fi or Bluetooth, while a second communication module 1812 may be dedicated to long-range wireless communications such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, etc. In some embodiments, the first communication module 1812 may be dedicated to wireless communications, while the second communication module 1812 may be dedicated to wired communications. In some embodiments, communication module 1812 may support millimeter-wave communications.

[0090] The communication device 1800 may include a battery / power circuit module 1814. The battery / power circuit module 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuit modules for coupling components of the communication device 1800 to a power source (e.g., AC line power) that is separate from the communication device 1800.

[0091] The communication device 1800 may include a display device 1806 (or a corresponding interface circuit module, as described above). The display device 1806 may include any visual indicator, such as a head-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0092] The communication device 1800 may include an audio output device 1808 (or a corresponding interface circuit module, as described above). The audio output device 1808 may include any device that generates auditory indicators, such as a speaker, headphones, or earphones.

[0093] The communication device 1800 may include an audio input device 1824 (or a corresponding interface circuit module, as described above). The audio input device 1824 may include any device that generates a signal representing sound, such as a microphone, microphone array, or digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output).

[0094] Communication device 1800 may include GPS device 1818 (or a corresponding interface circuit module, as described above). As is known in the art, GPS device 1818 can communicate with satellite-based systems and can receive the location of communication device 1800.

[0095] The communication device 1800 may include other output devices 1810 (or corresponding interface circuit modules, as described above). Examples of other output devices 1810 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices.

[0096] The communication device 1800 may include other input devices 1820 (or corresponding interface circuit modules, as described above). Examples of other input devices 1820 may include accelerometers, gyroscopes, compasses, image capture devices, keyboards, cursor control devices (e.g., mice, styluses, touchpads), barcode readers, quick-response (QR) code readers, any sensors, or radio frequency identification (RFID) readers.

[0097] The communication device 1800 may have any desired form factor, such as a handheld or mobile communication device (e.g., a cellular phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA), ultra-mobile personal computer, etc.), desktop communication device, server or other networked computing component, printer, scanner, monitor, set-top box, entertainment control unit, vehicle control unit, digital camera, digital video recorder, or wearable communication device. In some embodiments, the communication device 1800 may be any other electronic device that processes data.

[0098] The following paragraphs provide examples of various embodiments of the examples disclosed herein.

[0099] Example 1 provides a microelectronic assembly including a glass layer having a first side and a second side opposite to the first side; a TGV in the glass layer extending from the first side toward the second side and including a conductive material; a first pad in the TGV between the conductive material and the glass layer; and a second pad in the TGV between the conductive material and the glass layer, wherein the first pad is between the glass layer and the second pad, and wherein the modulus of the first pad is higher than the modulus of the second pad.

[0100] Example 2 provides a microelectronic assembly according to Example 1, wherein the first pad has a modulus of at least about 30 gigapascals.

[0101] Example 3 provides a microelectronic assembly according to Example 1 or 2, wherein the CTE of the first pad is less than the CTE of the conductive material.

[0102] Example 4 provides a microelectronic assembly according to Example 3, wherein the CTE of the first pad is between about 3 ppm and about 10 ppm.

[0103] Example 5 provides a microelectronic assembly according to any of the foregoing embodiments, wherein the first pad comprises an inorganic material.

[0104] Example 6 provides a microelectronic assembly according to any of the foregoing embodiments, wherein the first pad comprises silicon and oxygen, or silicon and nitrogen, or silicon, oxygen and nitrogen.

[0105] Example 7 provides a microelectronic assembly according to any of the foregoing embodiments, wherein the first pad comprises one or more metals and oxygen.

[0106] Example 8 provides a microelectronic assembly according to any of the foregoing embodiments, wherein the first pad comprises an organosilicon.

[0107] Example 9 provides a microelectronic assembly according to any of the foregoing embodiments, wherein the modulus of the second pad is less than 30 gigapascals.

[0108] Example 10 provides a microelectronic assembly according to any of the foregoing embodiments, wherein the second pad comprises an organic material.

[0109] Example 11 provides a microelectronic assembly according to any of the foregoing embodiments, wherein the second pad comprises a polymer.

[0110] Example 12 provides a microelectronic assembly according to any of the foregoing embodiments, wherein the second pad comprises parylene.

[0111] Example 13 provides a microelectronic assembly according to any of the foregoing embodiments, wherein the second pad comprises a homopolymer.

[0112] Example 14 provides a microelectronic assembly according to any of the foregoing embodiments, wherein a first pad is in direct physical contact with a glass layer.

[0113] Example 15 provides a microelectronic assembly according to any of the foregoing embodiments, wherein the second pad is in direct physical contact with the first pad.

[0114] Example 16 provides a microelectronic assembly including a glass core having a first side and a second side opposite to the first side, and including an opening extending from the first side toward the second side; an inorganic material in the opening; an organic material in the opening; and a conductive material in the opening, wherein: the inorganic material is between a sidewall of the glass core and the organic material, and the organic material is between the inorganic material and the conductive material.

[0115] Example 17 provides a microelectronic assembly according to Example 16, wherein the modulus of the organic material is less than that of the inorganic material.

[0116] Example 18 provides a microelectronic assembly according to Example 16 or 17, wherein at least a portion of the inorganic material is in contact with the sidewall of the glass core, and at least a portion of the organic material is in contact with the inorganic material.

[0117] Example 19 provides a method of manufacturing a microelectronic assembly, the method comprising depositing an inorganic material on the sidewall of a via opening in a glass structure, wherein the glass structure has a first surface and a second surface opposite to the first surface, and wherein the via opening extends from the first surface toward the second surface; depositing an organic material on the inorganic material on the sidewall of the via opening; depositing a seed material on the organic material at the sidewall of the via opening, wherein the organic material is between the inorganic material and the seed material, and wherein the inorganic material is between the sidewall of the via opening and the organic material; and depositing a conductive filler material in the via opening, wherein the seed material is located between the organic material and the conductive filler material.

[0118] Example 20 provides a method according to Example 19, wherein: an inorganic material is deposited as a first liner conformally to the sidewall of a through-hole opening, and an organic material is deposited as a second liner conformally to the sidewall of a through-hole opening having an inorganic material.

[0119] Example 21 provides a method according to Example 19 or 20, wherein the microelectronic assembly is a microelectronic assembly according to any one of Examples 1-18.

[0120] Example 22 provides a microelectronic assembly according to any of the foregoing embodiments, wherein the cross-section of the glass core in a plane perpendicular to the surface of the assembly is substantially rectangular.

[0121] Example 23 provides a microelectronic assembly according to any of the foregoing embodiments, wherein the cross-section of the glass core in a plane parallel to the surface of the assembly is substantially rectangular.

[0122] Example 24 provides a microelectronic assembly according to any of the foregoing embodiments, wherein the glass core is a glass layer comprising at least 23% silicon by weight.

[0123] Example 25 provides a microelectronic assembly according to any of the foregoing embodiments, wherein the glass core is a glass layer containing at least 26% oxygen by weight.

[0124] Example 26 provides a microelectronic assembly according to any of the foregoing embodiments, wherein the glass core is a glass layer comprising at least 23% silicon by weight and at least 26% oxygen by weight.

[0125] Example 27 provides a microelectronic assembly according to any of the foregoing embodiments, wherein the glass core is a glass layer comprising at least 5% aluminum by weight.

[0126] Example 28 provides a microelectronic assembly according to any of the foregoing embodiments, wherein the glass core is a glass layer that does not include organic adhesives or organic materials.

[0127] Example 29 provides a microelectronic assembly according to any of the foregoing embodiments, wherein the glass core is a glass layer having a thickness in the range of 50 micrometers (µm) to 1.4 millimeters (mm), a first length in the range of 10 mm to 250 mm, and a second length in the range of 10 mm to 250 mm, the first length being perpendicular to the second length.

[0128] Example 30 provides a microelectronic assembly according to any of the foregoing embodiments, wherein the glass core is a glass layer having a thickness in the range of 50 μm to 1.4 mm.

[0129] Example 31 provides a microelectronic assembly according to any of the foregoing embodiments, wherein the glass core is a glass layer having a first length in the range of 10 mm to 250 mm and a second length in the range of 10 mm to 250 mm, the first length being perpendicular to the second length.

[0130] Example 32 provides a microelectronic assembly according to any of the foregoing embodiments, wherein the glass core is a glass layer comprising a rectangular prism.

[0131] Example 33 provides a microelectronic assembly according to any of the foregoing embodiments, wherein the glass core is a glass layer comprising a rectangular prism having a first side and a second side perpendicular to the first side, the first side having a length in the range of 10 mm to 250 mm, and the second side having a length in the range of 10 mm to 250 mm.

[0132] Example 34 provides a microelectronic assembly according to any of the foregoing embodiments, wherein the glass core is a glass layer including a rectangular prism and a through-hole extending from a first side of the rectangular prism to a second side of the rectangular prism, the through-hole comprising metal.

[0133] Example 35 provides a microelectronic assembly according to any of the foregoing embodiments, wherein the glass core is a solid glass layer.

[0134] The foregoing description of the illustrated implementation of this disclosure, including the description in the abstract, is not intended to be exhaustive or to limit this disclosure to the precise form disclosed. While specific implementations and examples of this disclosure have been described herein for illustrative purposes, various equivalent modifications are possible within the scope of this disclosure, as will be recognized by those skilled in the art. These modifications can be made to this disclosure based on the detailed description above.

Claims

1. A microelectronic assembly, comprising: A glass layer having a first surface and a second surface opposite to the first surface; The glass layer contains through-glass vias (TGVs) that extend from the first surface toward the second surface and include a conductive material. The first pad in the TGV is located between the conductive material and the glass layer; and The second liner in the TGV is located between the conductive material and the glass layer, wherein the first liner is located between the glass layer and the second liner, and wherein the modulus of the first liner is higher than that of the second liner.

2. The microelectronic assembly according to claim 1, wherein, The modulus of the first liner is at least about 30 gigapascals.

3. The microelectronic assembly according to claim 2, wherein, The coefficient of thermal expansion (CTE) of the first pad is less than that of the conductive material.

4. The microelectronic assembly according to claim 3, wherein, The CTE of the first liner is between approximately 3 ppm and approximately 10 ppm.

5. The microelectronic assembly according to claim 1, wherein, The first liner comprises inorganic material.

6. The microelectronic assembly according to claim 1, wherein, The first pad includes: Silicon and oxygen, or Silicon and nitrogen, or Silicon, oxygen, and nitrogen.

7. The microelectronic assembly according to claim 1, wherein, The first liner comprises one or more metals and oxygen.

8. The microelectronic assembly according to claim 1, wherein, The first liner comprises an organosilicon.

9. The microelectronic assembly according to claim 1, wherein, The modulus of the second liner is less than 30 gigapascals.

10. The microelectronic assembly according to claim 1, wherein, The second liner comprises organic material.

11. The microelectronic assembly according to claim 1, wherein, The second liner comprises a polymer.

12. The microelectronic assembly according to claim 1, wherein, The second liner comprises parylene.

13. The microelectronic assembly according to claim 1, wherein, The second liner comprises a homopolymer.

14. The microelectronic assembly according to claim 1, wherein, The first gasket is in direct physical contact with the glass layer.

15. The microelectronic assembly according to claim 1, wherein, The second pad is in direct physical contact with the first pad.

16. A microelectronic assembly comprising: A glass core having a first surface and a second surface opposite to the first surface, and including an opening extending from the first surface toward the second surface; Inorganic material in the opening; Organic material in the opening; as well as The conductive material in the opening. in: The inorganic material is located between the sidewall of the glass core and the organic material, and The organic material is located between the inorganic material and the conductive material.

17. The microelectronic assembly according to claim 16, wherein, The modulus of the organic material is less than that of the inorganic material.

18. The microelectronic assembly according to claim 16, wherein: At least a portion of the inorganic material is in contact with the sidewall of the glass core, and At least a portion of the organic material is in contact with the inorganic material.

19. A method for manufacturing a microelectronic assembly, the method comprising: Inorganic material is deposited on the sidewall of a through-hole opening in a glass structure, wherein the glass structure has a first surface and a second surface opposite to the first surface, and wherein the through-hole opening extends from the first surface toward the second surface. Organic material is deposited on the inorganic material at the sidewall of the through-hole opening; Seed material is deposited on the organic material at the sidewall of the through-hole opening, wherein the organic material is between the inorganic material and the seed material, and wherein the inorganic material is between the sidewall of the through-hole opening and the organic material; and A conductive filler material is deposited in the through-hole opening, wherein the seed material is between the organic material and the conductive filler material.

20. The method of claim 19, wherein: The inorganic material is deposited as a first liner conforming to the sidewall of the through-hole opening, and The organic material is deposited as a second liner conformally to the sidewall having the through-hole opening of the inorganic material.

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