Semiconductor device

Abstract

A semiconductor device is provided with a semiconductor element (30) having an emitter electrode formed on the front surface and a collector electrode formed on the back surface. The collector electrode and a heat sink (40) disposed on the back surface side of the semiconductor element (30) are connected via solder (80). A plurality of wire pieces (90) are provided on the solder joint. All the wire pieces (90) are bonded to the mounting surface (40a) of the heat sink (40) and protrude toward the semiconductor element (30). The solder (80) has, in plan view, a central region (80a) that overlaps a central portion of the semiconductor element (30) including the element center (30c), and an outer peripheral region (80b) that surrounds the central region (80a). In the outer peripheral region, at least four wire pieces are disposed so as to correspond to at least the four corners of the semiconductor element (30). At least one of the wire pieces extends toward the center of the element in plan view.

Description

[0001] Divisional Application Instructions

[0002] This invention is a divisional application of Chinese national patent application No. 202080069629.5, filed on September 25, 2020, entitled "Semiconductor Device". Technical Field

[0003] The disclosures in this specification relate to semiconductor devices. Background Technology

[0004] Patent Document 1 discloses a Ni ball that ensures solder thickness. The description of technical elements in this specification is based on prior art documents referenced by way of reference.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent No. 5510623 Summary of the Invention

[0008] The application of Ni balls is limited. For example, in the case of solder die bonding, a significant portion of the Ni balls melts in the solder melting furnace. This raises the risk that the minimum guaranteed thickness of the solder (bonded component) cannot be guaranteed. From the above perspectives, or other perspectives not mentioned, further improvements are required for semiconductor devices.

[0009] One purpose of this disclosure is to provide highly reliable semiconductor devices.

[0010] The semiconductor device disclosed herein includes:

[0011] A semiconductor device, as a main electrode, has a surface electrode and a back electrode. The surface electrode is formed on the surface, and the back electrode is formed on the back side opposite to the surface in the thickness direction of the plate, and its area is larger than that of the surface electrode.

[0012] A joining component that is sandwiched between the first opposing surface and the second opposing surface to form a joint;

[0013] Wiring components electrically connected to the main electrode via a bonding component; and

[0014] Multiple laminations are disposed within the engaging component, fixed to the first opposing surface, and protrude from the first opposing surface.

[0015] The wiring component includes a back-side wiring component disposed on the back side and connected to the back electrode.

[0016] The bonding component includes a back-side bonding component that forms a bonding portion between a back electrode and a back-side wiring component and is configured with multiple wire pieces.

[0017] The back-side bonding member has: a central region that, when viewed from above along the thickness direction, overlaps with the central portion of a semiconductor element containing the element center; and an outer peripheral region that includes a portion overlapping with the outer peripheral portion of the semiconductor element surrounding the central portion, and surrounds the central region.

[0018] In the outer peripheral region, at least four or more laminations are arranged corresponding to the four corners of the semiconductor element.

[0019] At least one of the laminations extends toward the center of the element when viewed from above.

[0020] According to the disclosed semiconductor device, a lamination is fixed to a first opposing surface. The lamination protruding from the first opposing surface ensures the thickness of the bonding component. Even if warping occurs in a semiconductor device with main electrodes on both sides, the thickness of the bonding component can be ensured by the lamination located in the outer peripheral region. Furthermore, the lamination extending towards the center of the device makes it difficult to obstruct solder flow during wetting and expansion. Based on the above, a semiconductor device with high reliability can be provided.

[0021] The various methods disclosed in this specification employ different technical means to achieve their respective purposes. The reference numerals within parentheses in the claims are used to illustratively indicate the correspondence with portions of the embodiments described later and are not intended to limit the scope of the technology. The purposes, features, and effects disclosed in this specification become clearer with reference to the following detailed description and the accompanying drawings. Attached Figure Description

[0022] Figure 1 This is a circuit diagram of a power conversion device applicable to a semiconductor device according to the first embodiment.

[0023] Figure 2 This is a top view of a semiconductor device.

[0024] Figure 3 It is along Figure 2 A cross-sectional view of line III-III.

[0025] Figure 4 It is along Figure 2 A cross-sectional view of line IV-IV.

[0026] Figure 5 This is a top view omitting the sealing resin body.

[0027] Figure 6 This is a top view omitting the heat sink on the emitter electrode side.

[0028] Figure 7 It is a top view showing the positional relationship between semiconductor elements and wafers.

[0029] Figure 8 It is a three-dimensional diagram showing the arrangement of the line pieces.

[0030] Figure 9 It is along Figure 7 A cross-sectional view of the IX-IX line.

[0031] Figure 10 It is a three-dimensional diagram showing the warping of semiconductor components and the effect of the wires.

[0032] Figure 11 This is a top view showing the height of the laminations in the semiconductor device of the second embodiment.

[0033] Figure 12 This is a top view showing the positional relationship between the semiconductor elements and the wafers in the semiconductor device of the third embodiment.

[0034] Figure 13 It is along Figure 12 A cross-sectional view of line XIII-XIII.

[0035] Figure 14 It is a cross-sectional view of a semiconductor device when it is tilted.

[0036] Figure 15 This is a top view showing the arrangement of the wafers in the semiconductor device according to the fourth embodiment.

[0037] Figure 16 This is a top view showing a variation.

[0038] Figure 17 This is a top view showing the positional relationship between the semiconductor elements and the wafers in the semiconductor device of the fifth embodiment.

[0039] Figure 18 This is a top view showing the configuration of the line pieces.

[0040] Figure 19 It is along Figure 17 A cross-sectional view of the XIX-XIX line.

[0041] Figure 20 This is a top view showing a variation.

[0042] Figure 21 This is a top view showing the positional relationship between the semiconductor elements and the wafers in the semiconductor device of the sixth embodiment.

[0043] Figure 22 It is a schematic cross-sectional view showing the effect of the positional relationship between the upper and lower lines.

[0044] Figure 23 This is a schematic cross-sectional view showing the stacked structure of one arm of the semiconductor device according to the seventh embodiment.

[0045] Figure 24 This is a top view showing the arrangement of the wires in each solder.

[0046] Figure 25 This diagram shows the differences between the semiconductor device of the eighth embodiment and the terminals of the comparative example.

[0047] Figure 26 This is a perspective view showing an example of the connection structure between the semiconductor element and the heat sink in the semiconductor device according to the ninth embodiment.

[0048] Figure 27 It is along Figure 26 A cross-sectional view of the XXVII-XXVII line.

[0049] Figure 28 It is a three-dimensional representation of line pieces.

[0050] Figure 29 This is a cross-sectional view showing another example of a line sheet.

[0051] Figure 30 It is a cross-sectional view showing the manufacturing process of a semiconductor device.

[0052] Figure 31 It is a cross-sectional view showing the manufacturing process of a semiconductor device.

[0053] Figure 32 It is a cross-sectional view showing the manufacturing process of a semiconductor device.

[0054] Figure 33 It is a cross-sectional view showing the manufacturing process of a semiconductor device.

[0055] Figure 34 It is a cross-sectional view showing the manufacturing process of a semiconductor device.

[0056] Figure 35 This is a cross-sectional view showing an example of a warp-free semiconductor device.

[0057] Figure 36 This is a cross-sectional view showing an example of a semiconductor element that has developed an upward-convex warp.

[0058] Figure 37 This is a cross-sectional view showing an example of a semiconductor element that has developed a downward bulge and warping.

[0059] Figure 38 It is a cross-sectional view showing the effect of having flat sections at both ends.

[0060] Figure 39 This is a cross-sectional view showing another example of a semiconductor device.

[0061] Figure 40 These are simulation results showing the relationship between the volume of the wafer and the solder strain in the semiconductor device according to the tenth embodiment.

[0062] Figure 41 It is a diagram showing the construction of a line sheet.

[0063] Figure 42 It is a cross-sectional view used to illustrate the height of the line segment between the collector electrode and the heat sink.

[0064] Figure 43 It is a cross-sectional view used to illustrate the height of the wire between the emitter electrode and the terminal.

[0065] Figure 44 It is a cross-sectional view showing the manufacturing method of the wire sheet.

[0066] Figure 45 It is a cross-sectional view showing the manufacturing method of the wire sheet.

[0067] Figure 46 It is a cross-sectional view showing the manufacturing method of the wire sheet.

[0068] Figure 47 It is a cross-sectional view showing the manufacturing method of the wire sheet.

[0069] Figure 48 It is a cross-sectional view showing the manufacturing method of the wire sheet. Detailed Implementation

[0070] Hereinafter, several embodiments will be described based on the accompanying drawings. In several embodiments, functionally and / or structurally corresponding parts and / or related parts are sometimes labeled with the same reference numerals. For corresponding parts and / or related parts, please refer to the description of other embodiments.

[0071] (First Implementation)

[0072] First, based on Figure 1 This section describes a power conversion device applicable to semiconductor devices.

[0073] <Power Conversion Device>

[0074] Figure 1 The power conversion device 1 shown is, for example, installed in an electric vehicle or a hybrid vehicle. The power conversion device 1 performs power conversion between a DC power source 2 and an electric generator 3. The power conversion device 1, together with the DC power source 2 and the electric generator 3, constitute the vehicle's drive system.

[0075] DC power supply 2 is a rechargeable secondary battery such as a lithium-ion battery or a nickel-metal hydride battery. Electric generator 3 is a three-phase AC rotating electric motor. Electric generator 3 functions as the vehicle's driving force, i.e., an electric motor. During regeneration, electric generator 3 functions as a generator.

[0076] The power conversion device 1 includes a smoothing capacitor 4 and an inverter 5, which acts as a power converter. The positive terminal of the smoothing capacitor 4 is connected to the high-potential side of the DC power supply 2, i.e., the positive terminal, and the negative terminal is connected to the low-potential side of the DC power supply 2, i.e., the negative terminal. The inverter 5 converts the input DC power into three-phase AC power of a specified frequency and outputs it to the electric generator 3. The inverter 5 converts the AC power generated by the electric generator 3 into DC power. The inverter 5 is a DC-AC conversion unit.

[0077] The inverter 5 is configured with three-phase upper and lower arm circuits 6. The upper and lower arm circuits 6 are sometimes referred to as legs. Each phase's upper and lower arm circuits 6 have two arms 6H and 6L connected in series between the high-potential power line 7 (which serves as the positive side) and the low-potential power line 8 (which serves as the negative side). In each phase's upper and lower arm circuits 6, the connection point of the upper arm 6H and the lower arm 6L is connected to the output line 9 of the generator 3.

[0078] In this embodiment, n-channel insulated-gate bipolar transistors 6i (hereinafter referred to as IGBT6i) are used as switching elements constituting each arm. Each IGBT6i is connected in reverse parallel with a diode (FWD6d) for return current. Each phase of the upper and lower arm circuit 6 has two IGBT6i. In the upper arm 6H, the collector electrode of the IGBT6i is connected to the high-potential power supply line 7. In the lower arm 6L, the emitter electrode of the IGBT6i is connected to the low-potential power supply line 8. Furthermore, the emitter electrode of the IGBT6i in the upper arm 6H and the collector electrode of the IGBT6i in the lower arm 6L are interconnected.

[0079] In addition to the smoothing capacitor 4 and inverter 5 described above, the power conversion device 1 may also include a converter that is a different power converter from the inverter 5, a drive circuit constituting the inverter 5 and the switching elements of the converter, and filter capacitors. The converter is a DC-DC conversion unit that converts DC voltage into DC voltages of different values. The converter is located between the DC power supply 2 and the smoothing capacitor 4. The filter capacitor is connected in parallel to the DC power supply 2. For example, the filter capacitor removes power supply noise from the DC power supply 2.

[0080] Semiconductor Devices

[0081] Next, based on Figures 2-6 Here is an example of a semiconductor device. Figure 3 , Figure 4 It is along Figure 2 Cross-sectional views of lines III-III and IV-IV. Figure 5 It is relative to Figure 2 The diagram of the sealing resin body has been omitted. Figure 6 It is relative to Figure 5 The heat sink on the emitter electrode side is omitted from the diagram. For some elements constituting a semiconductor device, the reference numerals are marked with "H" to indicate the upper arm 6H side and "L" to indicate the lower arm 6L side. For other parts of the elements, for convenience, the upper arm 6H and the lower arm 6L are marked with common reference numerals.

[0082] Hereinafter, the thickness direction of the semiconductor element is represented as the Z direction, and a direction orthogonal to the Z direction, specifically the arrangement direction of two semiconductor elements, is represented as the X direction. Furthermore, a direction orthogonal to both the Z and X directions is represented as the Y direction. Unless otherwise specified, the shape viewed from the Z direction, in other words, the shape along the XY plane defined by the X and Y directions, is defined as a planar shape. Additionally, the view from the Z direction is simply represented as a top view.

[0083] like Figures 2-6 As shown, the semiconductor device 10 includes a sealing resin body 20, a semiconductor element 30, a heat sink 40, a heat sink 50, a terminal 55, connectors 60-62, main terminals 70-72, and a signal terminal 75. The semiconductor device 10 constitutes the upper and lower arm circuit 6 of one phase described above.

[0084] The sealing resin body 20 seals a portion of other elements constituting the semiconductor device 10. The remaining portions of the other elements are exposed outside the sealing resin body 20. The sealing resin body 20 is made of, for example, an epoxy resin. The sealing resin body 20 is formed, for example, by transfer molding. Figures 2-4 As shown, the sealing resin body 20 has a planar, generally rectangular shape. The sealing resin body 20 has a surface 20a and a back surface 20b opposite to the surface 20a in the Z direction. The surface 20a and the back surface 20b are, for example, flat surfaces.

[0085] Semiconductor element 30 is formed on a semiconductor substrate made of silicon (Si) or a wide-bandgap semiconductor with a wider bandgap than silicon. Examples of wide-bandgap semiconductors include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond. Semiconductor element 30 is sometimes referred to as a semiconductor chip.

[0086] The device is vertically oriented to allow the main current to flow in the Z direction. Vertically oriented devices can include IGBTs, MOSFETs, diodes, etc. In this embodiment, IGBT 6i and FWD 6d, forming one arm, are formed as vertically oriented devices. The vertically oriented device is an RC (Reverse Conducting) IGBT. The semiconductor device 30 has a gate electrode (not shown). The gate electrode is, for example, in a trench configuration. The semiconductor device 30 has main electrodes on both sides in its thickness direction, i.e., the Z direction. Specifically, as main electrodes, an emitter electrode 31 is provided on the surface side, and a collector electrode 32 is provided on the back side. The emitter electrode 31 also serves as the anode electrode of FWD 6d. The collector electrode 32 also serves as the cathode electrode of FWD 6d. The emitter electrode 31 corresponds to the surface electrode, and the collector electrode 32 corresponds to the back electrode.

[0087] Semiconductor element 30 is planar and roughly rectangular in shape. For example... Figure 6 As shown, the semiconductor element 30 has pads 33 formed on its surface at a different location than the emitter electrode 31. Both the emitter electrode 31 and the pads 33 are exposed from a protective film (not shown) on the surface of the semiconductor substrate. The emitter electrode 31 is formed on a portion of the surface of the semiconductor element 30. The collector electrode 32 is formed on approximately the entire back surface. Viewed from above, the area of ​​the collector electrode 32 is larger than the area of ​​the emitter electrode 31.

[0088] The pad 33 is a signal electrode. The pad 33 is electrically separated from the emitter electrode 31. The pad 33 is formed in the Y direction at the end opposite to the formation region of the emitter electrode 31. The pad 33 includes a gate pad 33g for the gate electrode. In this embodiment, the semiconductor element 30 has five pads 33. Specifically, it includes a Kelvin emitter pad for detecting the potential of the gate pad 33g and the emitter electrode 31, a current sensor for detecting the anode potential of a temperature sensor (thermal diode) for detecting the temperature of the semiconductor element 30, and also a cathode potential pad. The five pads 33 are concentrated at one end in the Y direction in the generally rectangular planar semiconductor element 30 and are arranged in the X direction.

[0089] The semiconductor device 10 includes two semiconductor elements 30. Specifically, it includes a semiconductor element 30H constituting the upper arm 6H and a semiconductor element 30L constituting the lower arm 6L. The semiconductor elements 30H and 30L have the same configuration. The semiconductor elements 30H and 30L are arranged along the X direction. The semiconductor elements 30H and 30L are arranged at approximately the same position in the Z direction.

[0090] The heat sink 40 is a wiring component disposed in the Z direction on the back side of the semiconductor element 30 and electrically connected to the collector electrode 32 via solder 80. The solder 80 connects (bonds) the heat sink 40 to the collector electrode 32. The heat sink 40 corresponds to the back-side wiring component, and the solder 80 corresponds to the back-side bonding component. The heat sink 40 has a mounting surface 40a, which is the surface opposite to the semiconductor element 30, and a back surface 40b, which is the surface opposite to the mounting surface 40a. Solder 80 is sandwiched between the mounting surface 40a of the heat sink 40 and the collector electrode 32 of the semiconductor element 30, forming a solder joint.

[0091] The heat sink 40 dissipates heat from the semiconductor element 30 to the outside. The heat sink 40 can be, for example, a metal plate made of Cu, Cu alloys, or a DBC (Direct Bonded Copper) substrate. It can also have a Ni or Au coating on its surface. In this embodiment, the heat sink 40 is a metal plate made of Cu. The heat sink 40 is sometimes referred to as a heat dissipation component, a conductive component, or a lead frame. The semiconductor device 10 includes two heat sinks 40. Specifically, it includes a heat sink 40H constituting the upper arm 6H and a heat sink 40L constituting the lower arm 6L.

[0092] like Figure 6 As shown, radiators 40H and 40L are roughly rectangular in shape. Radiators 40H and 40L are arranged along the X direction. Figure 3 as well as Figure 4 As shown, heat sinks 40H and 40L have approximately the same thickness and are positioned at approximately the same location in the Z direction. Solder joints are formed between the mounting surface 40a of heat sink 40H and the collector electrode 32 of semiconductor element 30H, and between the mounting surface 40a of heat sink 40L and the collector electrode 32 of semiconductor element 30L.

[0093] When viewed from above in the Z direction, heat sinks 40H and 40L enclose the corresponding semiconductor element 30. The back surface 40b of heat sinks 40H and 40L is exposed from the sealing resin body 20. The back surface 40b is sometimes referred to as the heat dissipation surface or exposed surface. The back surface 40b and the back surface 20b of the sealing resin body 20 are approximately the same surface. The back surfaces 40b of heat sinks 40H and 40L are arranged along the X direction.

[0094] The heat sink 50 and the terminal 55 are wiring components disposed in the Z direction on the surface side of the semiconductor element 30 and electrically connected to the emitter electrode 31 via solders 81 and 82. The terminal 55 is sandwiched between the semiconductor element 30 and the heat sink 50 in the Z direction. Solder 81 connects (joins) the terminal 55 to the emitter electrode 31. Solder 82 connects (joins) the heat sink 50 to the terminal 55.

[0095] Terminal 55 has a first end face 55a, which is opposite to the semiconductor element 30, and a second end face 55b, which is opposite to the first end face 55a. Heat sink 50 has a mounting surface 50a, which is opposite to the second end face 55b, and a back surface 50b, which is opposite to the mounting surface 50a. The mounting surface 50a is the side facing the semiconductor element 30 in the heat sink 50. Solder 81 is sandwiched between the first end face 55a of terminal 55 and the emitter electrode 31 of the semiconductor element 30, forming a solder joint. Solder 82 is sandwiched between the second end face 55b of terminal 55 and the mounting surface 50a of heat sink 50, forming a solder joint. Heat sink 50 and terminal 55 correspond to surface-side wiring components. Solder 81 corresponds to surface-side bonding components.

[0096] Terminal 55 is located midway between the semiconductor element 30 (emitter electrode 31) and the heat sink 50 in the conductive and heat-conducting path. Terminal 55 is made of a metallic material such as Cu or Cu alloy. It may also have a coating on its surface. Terminals 55H and 55L are planar, approximately rectangular cylindrical bodies with a size approximately the same as the emitter electrode 31 when viewed from above. Terminal 55 is sometimes referred to as a metal block or a relay component. The semiconductor device 10 has two terminals 55. Specifically, it has a terminal 55H forming the upper arm 6H and a terminal 55L forming the lower arm 6L. Solder joints are formed between the first end face 55a of terminal 55H and the emitter electrode 31 of semiconductor element 30H, and between the first end face 55a of terminal 55L and the emitter electrode 31 of semiconductor element 30L.

[0097] Heat sink 50 dissipates heat from semiconductor element 30 to the outside. Heat sink 50 has the same configuration as heat sink 40. In this embodiment, heat sink 50 is a metal plate made of Cu. Semiconductor device 10 includes two heat sinks 50. Specifically, it includes a heat sink 50H forming the upper arm 6H and a heat sink 50L forming the lower arm 6L.

[0098] like Figure 5 As shown, radiators 50H and 50L are roughly rectangular in shape. Radiators 50H and 50L are arranged along the X direction. Figure 3 as well as Figure 4 As shown, heat sinks 50H and 50L have approximately the same thickness and are positioned at approximately the same location in the Z direction. Solder joints are formed between the mounting surface 50a of heat sink 50H and the second end face 55b of terminal 55H, and between the mounting surface 50a of heat sink 50L and the second end face 55b of terminal 55L.

[0099] When viewed from the Z direction, heat sinks 50H and 50L include the corresponding semiconductor element 30 and terminal 55. A groove 51 for accommodating overflowing solder 82 is formed on the mounting surface 50a of heat sinks 50H and 50L. The groove 51 surrounds the solder joint on the mounting surface 50a. The groove 51 is, for example, formed in an annular shape. The back surface 50b of heat sinks 50H and 50L is exposed from the sealing resin body 20. The back surface 50b is sometimes referred to as the heat dissipation surface or exposed surface. The back surface 50b and the surface 20a of the sealing resin body 20 are approximately one surface. The back surfaces 50b of heat sinks 50H and 50L are arranged along the X direction.

[0100] Connectors 60 and 62 connect the elements constituting the upper and lower arm circuits 6. Connectors also connect the elements constituting the semiconductor device 10. For example... Figure 3 as well as Figure 6 As shown, connector 60 is connected to radiator 40L. The thickness of connector 60 is thinner than that of radiator 40L. Connector 60 is positioned approximately on the same surface as the mounting surface 40a of radiator 40L, and is connected to the opposing surface (side surface) opposite to radiator 40H. Connector 60 has two bends, thus forming a roughly crank-like shape in the ZX plane. Connector 60 is covered by sealing resin body 20. Connector 60 can be integrally connected to radiator 40L, can be provided as another component, or can be connected via a joint. In this embodiment, connector 60 is integrally provided with radiator 40L as part of the lead frame.

[0101] like Figure 3 as well as Figure 5 As shown, connectors 61 and 62 are connected to their respective radiators 50. Connector 61 is connected to radiator 50H. Connector 62 is connected to radiator 50L. The thickness of connectors 61 and 62 is thinner than that of their respective radiators 50. Connectors 61 and 62 are covered by a sealing resin body 20. Connectors 61 and 62 can be integrally connected to radiators 50, can be provided as other components, or can be connected by a joint. In this embodiment, connectors 61 and 62 are integrally provided to their respective radiators 50H and 50L. Connectors 61 and 62 extend along the X direction from opposite sides of the two radiators 50H and 50L.

[0102] The heat sink 50H, including the connector portion 61, and the heat sink 50L, including the connector portion 62, are common components. The configuration of the heat sink 50H, including the connector portion 61, and the heat sink 50L, including the connector portion 62, is quadratically symmetrical about the Z-axis. Solder 83 is sandwiched between the opposing surfaces of the connector portion 60 and the connector portion 61, forming a solder joint.

[0103] A groove 63 for accommodating overflowing solder 83 is formed on the mating surface of the joint portion 61. The groove 63 is formed in an annular shape to surround the solder joint portion. Similarly, a groove 63 for accommodating overflowing solder is also formed on the mating surface of the joint portion 62. In this embodiment, the groove 63 is formed by stamping. Therefore, the joint portions 61 and 62 have a protrusion 64 on the back side of the groove 63.

[0104] Main terminals 70-72 and signal terminal 75 are external connection terminals. Main terminals 70 and 71 are power supply terminals. Main terminal 70 is electrically connected to the positive terminal of smoothing capacitor 4. Main terminal 71 is electrically connected to the negative terminal of smoothing capacitor 4. Therefore, main terminal 70 is sometimes referred to as the P terminal, and main terminal 71 is sometimes referred to as the N terminal.

[0105] like Figure 5 as well as Figure 6 As shown, the main terminal 70 is connected to one end of the heat sink 40H in the Y direction. The thickness of the main terminal 70 is thinner than that of the heat sink 40H. The main terminal 70 is approximately the same surface as the mounting surface 40a and is connected to the heat sink 40H. The main terminal 70 extends from the heat sink 40H in the Y direction and protrudes outward from the side surface 20c of the sealing resin body 20. The main terminal 70 has a bend in the middle of the portion covered by the sealing resin body 20 and protrudes from near the center in the Z direction on the side surface 20c.

[0106] like Figure 4 as well as Figure 5 As shown, the main terminal 71 is connected to the connector portion 62. Solder 84 is sandwiched between the opposing surfaces of the main terminal 71 and the connector portion 62, forming a solder joint. The main terminal 71 extends along the Y direction and protrudes from the same side 20c as the main terminal 70 beyond the sealing resin body 20. The main terminal 71 has a connecting portion 71a near one end in the Y direction that connects to the connector portion 62. A portion of the main terminal 71 including the connecting portion 71a is covered by the sealing resin body 20, and the remaining portion protrudes from the sealing resin body 20. The thickness of the connecting portion 71a is greater than the thickness of the portion protruding from the sealing resin body 20. The thickness of the connecting portion 71a is, for example, approximately the same as the thickness of the heat sink 40. The main terminal 71 also has a bend, similar to the main terminal, protruding from near the center in the Z direction on the side 20c.

[0107] Main terminal 72 is connected to the connection point of upper arm 6H and lower arm 6L. Main terminal 72 is electrically connected to the winding (stator coil) of the corresponding phase of the electric generator 3. Main terminal 72 is also called output terminal, AC terminal, or O terminal. Main terminal 72 is connected to one end of the radiator 40L in the Y direction. The thickness of main terminal 72 is thinner than that of radiator 40L. Main terminal 72 is approximately the same surface as mounting surface 40a and is connected to radiator 40L. Main terminal 72 extends from radiator 40L in the Y direction and protrudes from the same side 20c as main terminal 70 outward from the sealing resin body 20. Main terminal 72 also has a bend, similar to main terminal 71, protruding from near the center of side 20c in the Z direction. The three main terminals 70 to 72 are arranged in the X direction in the order of main terminal 70, main terminal 71, and main terminal 72.

[0108] Signal terminals 75 are electrically connected to the pads 33 of the corresponding semiconductor element 30. In this embodiment, the electrical connection is achieved via bonding wires 87. The signal terminals 75 extend in the Y direction and protrude outward from the side surface 20d of the sealing resin body 20. Side surface 20d is the surface opposite to side surface 20c in the Y direction. In this embodiment, five signal terminals 75 are provided for one semiconductor element 30.

[0109] in addition, Figure 2 , Figure 5 as well as Figure 6 The reference numeral 88 in the attached figure indicates a suspension lead. The heat sink 40 (40H, 40L), connector 60, main terminals 70-72, and signal terminals 75 form a lead frame as a common component. This lead frame is a shaped strip with varying thicknesses in certain areas. Before cutting, the signal terminals 75 are connected to the suspension lead 88 via connecting rods. Unnecessary parts of the lead frame, such as the connecting rods, are cut (removed) after the sealing resin body 20 is formed.

[0110] As described above, in the semiconductor device 10, a plurality of semiconductor elements 30 constituting the upper and lower arm circuits 6 of a phase are sealed by a sealing resin body 20. The sealing resin body 20 integrally seals a portion of each of the plurality of semiconductor elements 30, a portion of each of the heat sinks 40 and 50, a terminal 55, connectors 60-62, main terminals 70-72, and a portion of each of the signal terminals 75.

[0111] A semiconductor element 30 is disposed between heat sinks 40 and 50 in the Z direction. This allows heat from the semiconductor element 30 to be dissipated to both sides in the Z direction. The semiconductor device 10 has a double-sided heat dissipation structure. The back surface 40b of the heat sink 40 and the back surface 20b of the sealing resin body 20 are approximately one surface. The back surface 50b of the heat sink 50 and the surface 20a of the sealing resin body 20 are approximately one surface. Since the back surfaces 40b and 50b are exposed, heat dissipation is improved.

[0112] <Line Sheet>

[0113] Next, based on Figures 7-9 The line sheet is explained. Figure 7 It's enlarged. Figure 6 A top view of the semiconductor element 30H on the upper arm 6H side. Figure 7 The positional relationship between the semiconductor element and the wire lamination is shown. Figure 7 For convenience, the terminal 55H, solder 81, emitter electrode 31, pad 33, and bonding wire 87 are omitted from the diagram. Figure 8 It is a three-dimensional diagram showing the arrangement of the line pieces. Figure 9 It is along Figure 7 A cross-sectional view of the IX-IX line.

[0114] like Figures 7-9 As shown, the semiconductor device 10 further includes a lamination 90. The lamination 90 is disposed at at least one solder joint that electrically connects the main electrode to the wiring component. The lamination 90 is disposed within the solder. Multiple laminations 90 are distributed in a plurality of manners for a single solder. The plurality of laminations 90 are fixed (joined) to a first opposing surface, which is one of the opposing surfaces constituting the solder joint, and protrude toward a second opposing surface, which is the other opposing surface.

[0115] The lamination 90 has a specified height to ensure a minimum solder film thickness. The height of the lamination 90 is set such that even when multiple laminations 90 are in contact with the second opposing surface, the shortest distance between the first and second opposing surfaces is at least the minimum film thickness. The minimum film thickness refers to the minimum thickness required to ensure the desired connection reliability. The height of the lamination 90 is, for example, a value with a margin added to the minimum film thickness. The lamination 90 is a small portion of the bonding wire. The lamination 90 is sometimes referred to as a protrusion or cylindrical bond.

[0116] In this embodiment, multiple laminations 90 are disposed on solder 80 between the collector electrode 32 of the semiconductor element 30H and the mounting surface 40a of the heat sink 40H. All laminations 90 are fixed (bonded) to the mounting surface 40a of the heat sink 40H, but not fixed to the back surface of the semiconductor element 30H, i.e., the collector electrode 32. The mounting surface 40a of the heat sink 40H corresponds to the first opposing surface, and the back surface of the semiconductor element 30H corresponds to the second opposing surface. Multiple laminations 90 are fixed to the mounting surface 40a. Each lamination 90 is a small portion of a bonding wire made of aluminum or an aluminum alloy. All laminations 90 fixed to the mounting surface 40a are disposed within the solder 80.

[0117] The solder 80 has a central region 80a that overlaps with the central portion of the semiconductor element 30H when viewed from above, and an outer peripheral region 80b surrounding the central region 80a. The central portion of the semiconductor element 30H is the element center 30c and its surrounding portion. The semiconductor element 30H has an outer peripheral portion surrounding the central portion. The outer peripheral portion is, for example, a portion extending from each of the four sides of a planar rectangular shape. For example, the central portion is the active region where the element is formed, and the outer peripheral portion is the outer peripheral withstand voltage region surrounding the active region. The outer peripheral region 80b includes a portion that overlaps with the outer peripheral portion of the semiconductor element 30H. A plurality of laminations 90 are respectively disposed in the central region 80a and the outer peripheral region 80b.

[0118] Multiple pieces 90a, which are part of the pieces 90 fixed to the mounting surface 40a, are arranged in the central region 80a in such a way that they surround the center 30c of the element when viewed from above. Figure 7 The center line CL shown is a virtual line that passes through the component center 30c and extends along the Z direction. The line pieces 90a of the central region 80a surround this center line CL. To surround the component center 30c, three or more line pieces 90a are arranged in the central region 80a. In this embodiment, three line pieces 90a are arranged in the central region 80a. The three line pieces 90a are in a triangularly symmetrical position relative to the component center 30c.

[0119] Multiple sheets 90b, which are part of the sheet 90 fixed to the mounting surface 40a, are arranged in the outer peripheral region 80b such that they surround the center 30c of the element when viewed from above. The multiple sheets 90b are arranged corresponding to at least four corners of the semiconductor element 30H, which is in the shape of a planar rectangle. Therefore, more than four sheets 90b are arranged in the outer peripheral region 80b. In this embodiment, four sheets 90b are arranged in the outer peripheral region 80b. The sheets 90b are arranged in portions overlapping the four corners of the semiconductor element 30H. Furthermore, the four corners do not refer to the four corners (vertices) of the planar rectangle, but rather to a portion including a defined area of ​​the vertices (the portion around the corner).

[0120] Furthermore, the lower arm 6L side also has the same configuration. That is, multiple tabs 90 are arranged on the solder 80 between the collector electrode 32 of the semiconductor element 30L and the mounting surface 40a of the heat sink 40L. The multiple tabs 90 are fixed to the mounting surface 40a. Therefore, the description is omitted.

[0121] <Methods for Manufacturing Semiconductor Devices>

[0122] Next, the manufacturing method of the semiconductor device 10 described above will be explained. In this embodiment, the semiconductor device 10 is formed using a solder die bonding method.

[0123] First, a wire sheet 90 is formed. An aluminum bonding wire is ultrasonically bonded to the mounting surface 40a of the heat sink 40 within the lead frame. The bonding wire typically has a first bonding portion and a second bonding portion to electrically connect two parts. Here, the wire is cut at the moment the first bonding portion is formed, resulting in the wire sheet 90.

[0124] Next, molten solder is applied to form a laminate. First, molten solder (solder 80) is applied to the mounting surface 40a, and the semiconductor element 30 is disposed on the molten solder with the collector electrode 32 facing the mounting surface 40a side. Next, molten solder (solder 81) is applied to the emitter electrode 31 of the semiconductor element 30, and the terminal 55 is disposed on the molten solder with the first end face 55a facing the semiconductor element 30 side. Then, molten solder (solder 82) is applied to the second end face 55b of the terminal 55. In addition, molten solder (solder 83, 84) is also applied to the connector portion 60 and the connection portion 71a. The molten solder can be applied, for example, using a transfer method. The applied molten solder solidifies, thereby obtaining a laminate of the heat sink 40, the semiconductor element 30, and the terminal 55.

[0125] All solders 80-84 can be cured (solidified) simultaneously or in the order of their lamination. Performing this simultaneously simplifies the manufacturing process (e.g., shortens manufacturing time). The connection of the bonding wires 87 can be performed in the laminated state or while the solder 80 is cured, before applying solder 81. Joining in the laminated state after all solders 80-84 have been applied is preferred because it can suppress defects caused by contact issues with the coating apparatus.

[0126] The semiconductor device 10, with its double-sided heat dissipation structure, is clamped from both sides in the Z direction by a cooler (not shown). This necessitates high parallelism of the surfaces in the Z direction and high dimensional accuracy between the surfaces. Therefore, the solder 82 is configured to absorb height deviations of the semiconductor device 10. That is, a larger amount of solder 82 is used. For example, the solder 82 is thicker than solders 80 and 81.

[0127] Next, the heat sink 50 is positioned on a pedestal (not shown) with its mounting surface 50a facing upwards. Then, a laminate is placed on the heat sink 50 with solder 82 facing the mounting surface 50a, and reflow is performed. During reflow, a load (hollow arrow) is applied from the heat sink 40 side along the Z direction to bring the height of the semiconductor device 10 to a predetermined height. Specifically, by applying the load, a spacer (not shown) is brought into contact with both the mounting surface 40a of the heat sink 40 and the mounting surface of the pedestal. This brings the height of the semiconductor device 10 to a predetermined height.

[0128] Through reflow, terminal 55 is connected (joined) to heat sink 50 via solder 82. That is, emitter electrode 31 is electrically connected to heat sink 50. Solder 82 absorbs height deviations caused by dimensional tolerances and assembly tolerances of the elements constituting semiconductor device 10. For example, if the full amount of solder 82 is required to make the height of semiconductor device 10 a specified height, the full amount of solder 82 remains in the connection area inside the groove 51. On the other hand, if a portion of solder 82 overflows in order to achieve the specified height, the overflowing solder 82 is collected in the groove 51. The same applies to solders 83 and 84, so descriptions are omitted.

[0129] Next, the sealing resin body 20 is formed using a transfer molding method. Although not shown in the figure, in this embodiment, the sealing resin body 20 is formed so that the heat sinks 40 and 50 are completely covered, and then cut after forming. The sealing resin body 20, along with a portion of the heat sinks 40 and 50, is cut together. This exposes the back surfaces 40b and 50b. The back surface 40b and the back surface 20b are approximately one surface, and the back surface 50b and the surface 20a are approximately one surface. Alternatively, the sealing resin body 20 can be formed while the back surfaces 40b and 50b are pressed against the cavity wall of the molding die and pressed tightly against it. In this case, the back surfaces 40b and 50b are exposed from the sealing resin body 20 at the moment of forming. Therefore, post-forming cutting is not required.

[0130] Next, by removing connecting rods (not shown) and the like, the semiconductor device 10 can be obtained.

[0131] Furthermore, although an example is shown where the heat sink 50 is placed after the laminate is formed and reflow is performed, it is not limited to this. The heat sink 50 may also be placed on the molten solder after applying molten solder (solder 82) to the second end face 55b of the terminal 55. Alternatively, all solders 80-84 may be cured (solidified) together to form a laminate including the heat sink 50. That is, the semiconductor device 10 may be obtained without reflow.

[0132] <Summary of the First Implementation>

[0133] Sometimes, reducing the number of components and reducing costs is achieved by using the heat sink 40 as a common component for various (multiple product numbers) semiconductor elements 30. The semiconductor element 30 has an emitter electrode 31 on its surface and a collector electrode 32 on its back side, with different areas for the emitter electrode 31 and the collector electrode 32. In this configuration, warping may occur in different directions depending on the product type due to factors such as film thickness, film deposition method, chip size, and electrode area. For example, in one product, warping occurs protruding towards the heat sink 40, i.e., downward, while in another product, warping occurs protruding to the side opposite to the heat sink 40, i.e., upward. Even with the same element size (chip size), there may be cases where the warping direction differs, for example, due to different film deposition methods (film composition). Furthermore, due to variations in manufacturing conditions, sometimes the warping direction differs even within the same product type.

[0134] In contrast, in this embodiment, a plurality of tabs 90 are provided at the solder joint between the collector electrode 32 of the semiconductor element 30 and the heat sink 40. The tabs 90 are fixed to the mounting surface 40a of the heat sink 40, which serves as the first opposing surface, and protrude toward the back side of the semiconductor element 30, which serves as the second opposing surface. Three or more tabs 90a are arranged in the central region 80a of the solder 80 to surround the center 30c of the element. At least four or more tabs 90b are arranged in the outer peripheral region 80b of the solder 80, corresponding to each of the four corners of the semiconductor element 30.

[0135] Therefore, as Figure 10 As shown, when the semiconductor element 30 warps downwards, the minimum film thickness of the solder 80 can be ensured by using the laminations 90a arranged to surround the center 30c of the element. For example, the semiconductor element 30 can be supported by three or more laminations 90a arranged to surround the center 30c of the element. As a result, the tilting of the semiconductor element 30 can be suppressed, and the minimum film thickness can be ensured across the entire surface.

[0136] Furthermore, in the event of an upward warping of the semiconductor element 30, the minimum solder thickness 80 can be ensured by means of the laminations 90b disposed at least at the four corners of the semiconductor element 30. For example, the semiconductor element 30 can be supported by the laminations 90b disposed at the four corners. This suppresses the tilting of the semiconductor element 30 and ensures a minimum solder thickness across the entire surface. Thus, even when the laminations 90 are in contact with the collector electrode 32, the minimum solder thickness 80 can be ensured by the height of the laminations 90.

[0137] Furthermore, the lamination 90 is fixed to the heat sink 40. That is, it is not thrown into the solder melting furnace and coated with molten solder together. Even if the lamination 90 is coated with molten solder, it can maintain its shape.

[0138] Based on the above, even if the semiconductor element 30 experiences any warping, such as downward or upward bulges, the solder film thickness 80 can be guaranteed. This ensures the solder film thickness 80 can be maintained even when using various semiconductor elements 30. Therefore, a highly reliable semiconductor device 10 can be provided. Furthermore, since the solder thickness can be guaranteed, the detection accuracy of the ultrasonic testing device (SAT) for voids can be improved. Moreover, compared to methods using Ni balls, costs can be reduced. Additionally, in Figure 10 For convenience, solder 80 is omitted from the diagram.

[0139] While an example of fixing the wire 90 to the mounting surface 40a of the heat sink 40 is shown, it is not limited to this. The wire 90 may also be fixed to the collector electrode 32 of the semiconductor element 30. That is, the back surface of the semiconductor element 30 may also be used as the first opposing surface. However, the configuration of fixing the wire 90 to the heat sink 40 (backside wiring component) has less impact on the bonding of the wire 90, and is therefore preferred.

[0140] The number and arrangement of the laminations 90 are not limited to the examples described above. Depending on the warpage of the semiconductor element 30, laminations 90 may be arranged only in the central region 80a or only in the outer peripheral region 80b. Alternatively, four or more laminations 90a may be arranged in the central region 80a to surround the center 30c of the element. Furthermore, in the outer peripheral region 80b, laminations 90b may also be arranged in the areas outside the four corners. That is, five or more laminations 90b may be arranged to surround the center 30c of the element. The position of the laminations 90 may also be adjusted to match the size (dimensions) of the semiconductor element 30 when setting them.

[0141] The configuration of the semiconductor device 10 is not limited to the examples described above. For example, it may be configured without the terminal 55. In this case, it is sufficient to connect the emitter electrode 31 to the mounting surface 50a of the heat sink 50. Alternatively, a protrusion may be provided on the mounting surface 50a of the heat sink 50, and a solder joint may be formed between the front end of the protrusion and the emitter electrode 31.

[0142] It can also be applied to configurations that do not have surface wiring components, i.e., terminals 55 and heat sinks 50. For example, a bonding wire can be connected to the emitter electrode 31, and the upper arm 6H and the lower arm 6L can be connected, as well as to the main terminal. Alternatively, the wire strip 90 can be provided only on one side of the solder 80 on the upper arm 6H side and the solder 80 on the lower arm 6L side.

[0143] (Second Implementation)

[0144] This embodiment is a variation of the prior embodiment as the basic method, and the description of the prior embodiment can be referenced.

[0145] As shown in the prior embodiment, in the semiconductor device 10, the lamination 90 can either be in contact with the second opposing surface or not. Preferably, as... Figure 11 As shown, it is better to make the sheet 90 not in contact with the collector electrode 32, which serves as the second opposing surface. Figure 11 This is a cross-sectional view showing the periphery of the connection between the semiconductor element and the heat sink in the semiconductor device 10 of this embodiment. Figure 11 and Figure 9 Corresponding. In Figure 11 For simplicity, the electrodes on the surface side of the semiconductor element 30 are omitted in the illustration. The configuration of the semiconductor device 10 is, for example, the same as in the first embodiment. Figure 11 The configuration shown is the same on the upper arm 6H side and the lower arm 6L side.

[0146] The lamination 90 is fixed to the mounting surface 40a of the heat sink 40 and disposed within the solder 80. In the joint of the solder 80, the mounting surface 40a forms a first opposing surface, and the surface of the collector electrode 32 forms a second opposing surface. Furthermore, the protrusion height H1 of the lamination 90, based on the mounting surface 40a, is less than the thickness T1 of the solder 80. The lamination 90 does not contact the collector electrode 32, and a gap exists between them. The protrusion height H1 is a height that ensures a minimum film thickness, as described above. The protrusion height H1 is, for example, approximately 50 to 100 μm. The target value for the solder 80 is, for example, approximately 150 μm.

[0147] <Summary of the Second Implementation>

[0148] According to this embodiment, the protrusion height H1 of the lamination 90 is less than the thickness T1 of the solder 80. Therefore, during the formation of the semiconductor device 10, the lamination 90 does not contact the second opposing surface. This suppresses crushing of the lamination 90 due to contact, thereby ensuring the specified solder thickness.

[0149] Furthermore, in this embodiment, the main electrode becomes the second opposing surface. That is, a wire sheet 90 is fixed on the surface opposite to the main electrode. Therefore, by satisfying the condition that the protrusion height H1 is less than the thickness T1 of the solder 80, it is also possible to suppress the situation where the wire sheet 90 comes into contact with the collector electrode 32 and damages the collector electrode 32.

[0150] While examples of the above relationships applied to the configuration of the first embodiment have been shown, the invention is not limited thereto. For example, it can also be applied to configurations where the number of laminations 90 disposed in the solder 80 differs from that in the first embodiment (e.g., a total of three). Furthermore, it is preferable that there are multiple laminations 90 disposed within the solder 80, preferably three or more. More preferably, the configuration described in the first embodiment is preferred.

[0151] Furthermore, the application is not limited to the lamination 90 within the solder 80. Any solder incorporating the lamination 90 is suitable. It is particularly suitable for solder joints of the main electrode. For example, if applied to a configuration where the lamination 90 is placed within the solder 81 and fixed to the terminal 55, the required solder thickness can be ensured, and damage to the emitter electrode 31 can be suppressed. Alternatively, the above relationship can be satisfied only on one side, the upper arm 6H side or the lower arm 6L side.

[0152] (Third Implementation)

[0153] This embodiment is a variation of the prior embodiment as the basic method, and the description of the prior embodiment can be referenced.

[0154] In this embodiment, the lathe 90 is as follows Figure 12 As shown, it is only configured in the outer peripheral region 80b. Figure 12 This is a top view showing the positional relationship between the semiconductor element 30 and the lamination 90 in the semiconductor device 10 of this embodiment. Figure 12 and Figure 7 Correspondingly, the lamination 90 is disposed in the outer peripheral region 80b at positions corresponding to the four corners of the semiconductor element 30. Figure 12 In the middle, the line piece 90 is only arranged at the four corners. The line piece 90 is not arranged in the central area 80a. Figure 12 The configuration shown is the same on the upper arm 6H side and the lower arm 6L side.

[0155] Although not illustrated, the emitter electrode 31 of the semiconductor element 30 has a base electrode portion formed on the surface of a semiconductor substrate using an Al-based material such as AlSi, and a connection electrode portion formed on the base electrode portion. The base electrode portion is formed, for example, by sputtering. The connection electrode portion is formed by plating. The connection electrode portion includes, for example, a Ni layer formed on the base electrode portion and an Au layer formed on the Ni layer. The collector electrode 32 is formed by sputtering. The collector electrode 32 includes an Al layer formed on the back side of the semiconductor substrate using an Al-based material such as AlSi, and a Ni layer formed on the Al layer. The emitter electrode 31 formed by plating is thicker than the collector electrode 32.

[0156] <Summary of the Third Implementation>

[0157] Figure 13 It is along Figure 12 The cross-sectional view along line XIII-XIII shows the connection structure between the semiconductor element 30 and the heat sink 40. In the electrode configuration described above, as... Figure 13 As shown, the semiconductor element 30 will exhibit a downward bulge. In this embodiment, the supply amount of solder 80 is set to ensure a minimum solder film thickness. The solder 80 is supplied to ensure a predetermined thickness above the minimum film thickness while allowing the junction between the semiconductor element 30 (collector electrode 32) and the heat sink 40 to be wetted and expanded. Figure 13 As shown, the semiconductor element 30 is supported on the solder 80 and does not contact the lamination 90. During soldering, the semiconductor element 30 floats on the molten solder. The solder 80 is supplied to the protruding tip of the semiconductor element 30; in other words, the solder thickness between the center of the element and the heat sink 40 ensures a minimum film thickness. Figure 13 This illustrates an ideal configuration where the semiconductor element 30 is not tilted relative to the heat sink 40.

[0158] Figure 14 This is a cross-sectional view of semiconductor element 30 when it is arranged at an angle. (Example) Figure 14 As shown, when the semiconductor element 30, which has a downwardly convex warp, is tilted, the semiconductor element 30 contacts a portion of a plurality of laminations 90. Since the laminations 90 support the semiconductor element 30, a minimum solder 80 film thickness is ensured. The laminations 90 have a height that ensures a minimum solder 80 film thickness even when the warped semiconductor element 30 is tilted. Since the laminations 90 are positioned at at least four corners of the outer peripheral region 80b, at least one lamination 90 can be used for support regardless of the direction in which the semiconductor element 30 is tilted. Therefore, the semiconductor device 10 according to this embodiment can guarantee the solder 80 film thickness even when a downwardly convex warp occurs on the semiconductor element 30. Thus, a semiconductor device 10 with high reliability (connection reliability) can be provided.

[0159] The semiconductor element 30 is not limited to the examples described above in that it has a downwardly convex, warped electrode configuration.

[0160] In the outer peripheral region 80b, line pieces 90 may also be arranged outside the four corners, together with the four corners. That is, more than five line pieces 90b may be arranged to surround the center 30c of the component.

[0161] (Fourth Implementation)

[0162] This embodiment is a variation of the prior embodiment as the basic method, and the description of the prior embodiment can be referenced.

[0163] The extension direction of the line piece 90 is not particularly limited on the first opposing surface. It can extend in any direction. Preferably, it is... Figure 15 It is better to extend the line piece 90 degrees in the specified direction. Figure 15 This is a top view showing the periphery of the connection between the semiconductor element and the heat sink in the semiconductor device 10 of this embodiment. Figure 15 and Figure 7 Corresponding. In Figure 15 In this diagram, to clearly indicate the wafer 90, a dashed line is used to represent the semiconductor element 30, and a solid line is used to represent the wafer 90. The configuration of the semiconductor device 10 is, for example, the same as in the first embodiment. Figure 15 The configuration shown is the same on the upper arm 6H side and the lower arm 6L side.

[0164] The laminations 90 are fixed to the mounting surface 40a of the heat sink 40. The number and arrangement of the laminations 90 are the same as in the first embodiment (see reference). Figure 7 The same applies. In this embodiment, the lamination 90 extends toward the component center 30c when viewed from above. That is, the extension direction (length direction) of the lamination 90 is approximately parallel to the virtual line connecting the lamination 90 to the component center 30c. The lamination 90 extends along this virtual line. The three laminations 90a disposed in the central region 80a of the solder 80 all extend toward the component center 30c. The four laminations 90b disposed in the outer peripheral region 80b of the solder 80 all extend toward the component center 30c.

[0165] <Summary of the Fourth Implementation>

[0166] According to this embodiment, since the laminations 90 extend toward the component center 30c, they are less likely to obstruct the flow of the applied molten solder during wetting and expansion. This helps to suppress the formation of voids in the solder 80 and unfilled portions between opposing surfaces. Furthermore, by having at least one of the laminations 90 extend in the aforementioned direction, numerous other effects can be achieved. In this embodiment, all the laminations 90 disposed on the solder 80 extend toward the component center 30c. This enhances the aforementioned effects and further improves connection reliability.

[0167] While examples of applying the above relationships to the configuration of the first embodiment have been shown, it is not limited thereto. For example, the number and arrangement of the laminations 90 disposed on the solder 80 may also be applied to configurations different from the first embodiment. For example, it may also be as follows: Figure 16 The modified example shown is applicable to the third embodiment (see reference). Figure 12 The solder 80 is configured such that the laminations 90 disposed on the outer peripheral region 80b extend toward the component center 30c. This achieves the effects described in the third embodiment and improves connection reliability. Furthermore, by having at least one of the laminations 90 extend in the aforementioned direction, numerous other effects can be achieved. Figure 16In this configuration, all the laminations 90 located in the outer peripheral region 80b extend toward the component center 30c. This further improves connection reliability.

[0168] Furthermore, the control of the extension direction is not limited to the lamination 90 within the solder 80. It can be applied to any solder in which the lamination 90 is configured. For example, it can be applied to the lamination 90 when it is configured on solder 81. It can also be applied to the lamination 90 when it is configured on solder 82. Additionally, the aforementioned extension direction may be satisfied only on one side, either the upper arm 6H side or the lower arm 6L side.

[0169] Furthermore, considering solder strain, it is preferable to set the extension length as follows. When viewed from above, if the extension length of the lamination 90 is less than or equal to a predetermined length, the solder strain becomes maximum at the end (outer periphery) of the solder 80. Conversely, if the extension length exceeds the predetermined length, the solder strain becomes maximum at the end of the lamination 90. If the extension length increases, the solder strain at the end of the lamination increases; if it exceeds the predetermined length, the relationship between the magnitudes of the solder strain at the end of the lamination and the solder end is reversed. Therefore, it is preferable to set the extension length within a range where the solder strain at the end of the lamination 90 does not exceed the solder strain at the end of the solder 80. For example, it is preferable to set the length of the lamination 90 to 350 μm or less relative to the diameter of the aluminum bonding wire forming the lamination 90 (80 μm). Specifically, it is preferable to set it within the range of 200 to 350 μm.

[0170] (Fifth Implementation)

[0171] This embodiment is a variation of the prior embodiment as the basic method, and the description of the prior embodiment can be referenced.

[0172] like Figures 17-19 As shown, the wire 90 can also be positioned on the solder 81 that bonds the surface electrode to the surface wiring component. In this case, Figures 17-19 The position shown is better for the line piece to be positioned at 90 degrees. Figure 17 The positional relationship between the lamination 90 disposed on the solder 81 and the semiconductor element 30 in the semiconductor device 10 of this embodiment is shown. Figure 18 The configuration of the wire piece 90 in terminal 55 is shown. Figure 19 It is along Figure 17 A cross-sectional view of the XIX-XIX line. In Figure 19 For simplicity, gate wiring 34 is omitted from the illustration. The configuration of the semiconductor device 10 in this embodiment is, for example, the same as in the first embodiment. The configuration of the lamination 90 disposed on the solder 81 is the same on the upper arm 6H side and the lower arm 6L side.

[0173] Multiple leads 90 are disposed at the solder joint between the emitter electrode 31 of the semiconductor element 30 and the first end face 55a of the terminal 55. All leads 90 are fixed (joined) to the first end face 55a of the terminal 55, but not fixed to the emitter electrode 31 or surface of the semiconductor element 30. The first end face 55a of the terminal 55 corresponds to a first opposing surface, and the surface of the semiconductor element 30 corresponds to a second opposing surface. Multiple leads 90 are fixed to the first end face 55a. All leads 90 fixed to the first end face 55a are disposed within the solder 81.

[0174] The semiconductor element 30 has a gate pad 33g as described above. The semiconductor element 30 has a gate wiring 34 formed on the surface side and connected to the gate pad 33g, and a gate wiring protection portion 35 that is part of a protective film formed on the surface and protects the gate wiring 34. The emitter electrode 31 is divided into two in the X direction, and a gate wiring 34 is formed between adjacent emitter electrodes 31 using aluminum or the like.

[0175] A protective film made of polyimide or similar material is formed on the surface of the semiconductor element 30, with the emitter electrode 31 and pad 33 exposed from the protective film. The gate wiring protection portion 35 is part of this protective film and covers the gate wiring 34. Figure 17 In the diagram, the portion of the gate wiring protection section 35 that overlaps with the terminal 55 when viewed from above is represented by a dashed line. Figure 18 In order to indicate the positional relationship, the gate wiring protection section 35 is represented as a single-dotted dashed area on the first end face 55a of the terminal 55.

[0176] The lamination 90 is positioned so as not to overlap with the gate wiring protection portion 35 when viewed from above. For example... Figure 17 as well as Figure 18 As shown, a wire piece 90 is fixed near the center of the first end face 55a, at a position that does not overlap with the gate wiring protection portion 35. Additionally, wire pieces 90 are fixed at each of the four corners of the first end face 55a, which is generally rectangular in shape. Thus, five wire pieces 90 are fixed to the first end face 55a.

[0177] <Summary of the Fifth Implementation>

[0178] In this embodiment, a plurality of laminations 90 are arranged within the solder 81. This ensures a minimum film thickness for the solder 81.

[0179] Furthermore, all the traces 90 within the solder 81 are positioned so as not to overlap with the gate wiring protection portion 35 when viewed from above. This prevents the traces 90 from contacting the gate wiring protection portion 35 and damaging the protective film during the formation of the semiconductor device 10. Consequently, it also prevents the solder 81 from penetrating the gate wiring 34 side from the damaged portion of the protective film, thus preventing short circuits between the gate electrode and the emitter electrode 31, i.e., gate leakage.

[0180] The area of ​​the emitter electrode 31 is smaller than the area of ​​the collector electrode 32. In other words, the joint of the solder 81 is smaller than the joint of the solder 80 when viewed from above. Therefore, even if the semiconductor element 30 experiences upward warping, the semiconductor element 30 can be supported by a lamination 90 located near the center of the first end face 55a. This ensures a minimum solder thickness. Furthermore, even if the semiconductor element 30 experiences downward warping, the semiconductor element 30 can be supported by laminations 90 located at the four corners. This ensures a minimum solder thickness. Through these measures, a semiconductor device 10 with high reliability can be provided.

[0181] While an example of fixing the wire piece 90 to the first end face 55a of the terminal 55 is shown, the method is not limited thereto. The wire piece 90 may also be fixed to the emitter electrode 31 of the semiconductor element 30. That is, the surface of the semiconductor element 30 may also be used as the first opposing surface. However, the configuration of fixing the wire piece 90 to the terminal 55 (surface wiring component) has a smaller impact on the engagement of the wire piece 90, and is therefore preferred.

[0182] The number and arrangement of the laminations 90 in the solder 81 are not limited to the examples described above. They can be arranged within a range that does not overlap with the gate wiring protection portion 35 when viewed from above. For example, multiple laminations 90 may be arranged near the center of the first end face 55a. In addition, laminations 90 may also be arranged near the outer periphery of the first end face 55a, in addition to the four corners. Alternatively, the above arrangement may be satisfied only on one side, the upper arm 6H side or the lower arm 6L side.

[0183] While examples of applying the above relationships to the configuration of the first embodiment have been shown, the invention is not limited thereto. At least one of the configurations of the second embodiment, the third embodiment, and the fourth embodiment can be combined with the laminations 90 disposed on the solder 81. For example, it can also be applied to a configuration where the number of laminations 90 disposed on the solder 80 is different from that of the first embodiment. For example, the number of laminations 90 disposed on the solder 80 and 81 can be the same.

[0184] exist Figure 20In the modified example shown, laminations 90 are arranged at the four corners of the outer peripheral region 80b of solder 80, and laminations 90 are arranged at the four corners of solder 81. That is, four laminations 90 are arranged in solder 80 and 81 respectively. Even if the semiconductor element 30 experiences downward warping, the laminations 90 arranged in solder 81 can support the semiconductor element 30. This ensures the minimum film thickness of solder 81. The laminations 90 in solder 81 are arranged in a position that does not overlap with the gate wiring protection portion 35. Each lamination 90 arranged in solder 80 and 81 and Figure 16 The configuration shown is the same, extending toward the center 30c of the component. Figure 20 This is a top view of terminal 55 viewed from the second end face. Figure 20 In the diagram, dashed lines represent the pieces 90 disposed on solder 80, and single-dot dashed lines represent the pieces 90 disposed on solder 81.

[0185] Alternatively, instead of arranging the laminations 90 on solder 80, the laminations 90 can be arranged on solder 81 as described above. This embodiment can also be applied to configurations that do not include a back-side wiring component, i.e., a heatsink 40.

[0186] While an example of a semiconductor device 10 having a terminal 55 has been shown, it is not limited to this. Configurations without a terminal 55 can also be applied. For example, the wire 90 can be fixed to the mounting surface 50a of the heat sink 50 in the solder joint between the emitter electrode 31 and the mounting surface 50a of the heat sink 50.

[0187] (Sixth Implementation Method)

[0188] This embodiment is a variation of the prior embodiment as the basic method, and the description of the prior embodiment can be referenced.

[0189] When solder 80 and 81 are configured with lamination 90, the configuration of lamination 90 is not particularly restricted. It can also be as follows: Figure 21 The line piece 90 is configured as shown. Figure 21 This is a top view of the terminal block as seen from the second end face side in the semiconductor device 10 of this embodiment. Figure 21 and Figure 7 Correspondingly, the configuration of the semiconductor device 10 is the same as that in the first embodiment. Figure 21 The configuration shown is the same on the upper arm 6H side and the lower arm 6L side.

[0190] Semiconductor device 10 includes a plurality of laminations 90 disposed on solder 80 and a plurality of laminations 90 disposed on solder 81. Hereinafter, laminations 90 disposed on solder 80 will sometimes be referred to as laminations 900, and laminations 90 disposed on solder 81 will sometimes be referred to as laminations 901. Figure 21 In the diagram, dashed lines represent line 900, and single-dot dashed lines represent line 901.

[0191] The sheet 900 is the same as the sheet 90 described in the first embodiment (see reference). Figure 7 The same configuration applies. For example, the tabs 900 are fixed to the mounting surface 40a of the heat sink 40. Three tabs 900 are arranged in the central region 80a of the solder 80, surrounding the center 30c of the component. In the outer peripheral region 80b, four tabs 900 are arranged corresponding to the four corners of the semiconductor component 30.

[0192] The sheet 901 is the same as the sheet 90 described in the fifth embodiment (see reference). Figure 17 The same configuration. For example, a wire piece 901 is fixed to the first end face 55a of the terminal 55. A wire piece 901 is positioned near the center of the first end face 55a. Wire pieces 901 are positioned at the four corners of the first end face 55a. (e.g.) Figure 21 As shown, line piece 900 and line piece 901 are positioned so that they do not overlap when viewed from above.

[0193] <Summary of the Sixth Implementation>

[0194] Figure 22 This is a schematic diagram illustrating the differences between the comparative example and the present example (this embodiment). In the comparative example, elements that are the same as or related to elements in this embodiment (this example) are indicated by adding "r" to the end of the reference numerals in the drawings of this embodiment. Figure 22 For simplicity, the main electrodes of the semiconductor components are omitted from the diagram.

[0195] The laminations 900r and 901r are formed using aluminum-based materials as described above. Their wettability to solder 80r and 81r is lower than that of the unshown main electrode of semiconductor element 30r, heat sink 40r, and terminal 55r. Therefore, a gap 86r is formed between the laminations 900r and 901r and the solder 80r and 81r. This gap 86r hinders heat conduction. As in the comparative example, if the laminations 900r and 901r overlap when viewed from above, the gap 86r also overlaps. Because the gap 86r exists on both sides of semiconductor element 30r in the Z-direction, it is difficult to dissipate heat from the portion of semiconductor element 30r that overlaps with the gap 86r (laminations 900r and 901r) in the Z-direction. This increases thermal resistance.

[0196] In this embodiment (this example), similar to the comparative example, gaps 86 are formed between the lamination 900 and the solder 80, and between the lamination 901 and the solder 81. However, the laminations 900 and 901 are positioned so that they do not overlap when viewed from above, therefore the gaps 86 in the solders 80 and 81 do not overlap when viewed from above, or if they do overlap, it is only a very small portion. This allows heat from the semiconductor element 30 to be released in at least one direction in the Z-direction. Therefore, compared to the comparative example, thermal resistance can be reduced and heat dissipation improved. Furthermore, in other embodiments, the gaps 86 are omitted from the illustration.

[0197] In this embodiment, the sheet 900 has the same configuration as in the first embodiment. Therefore, in addition to the effects described in this embodiment, the effects described in the first embodiment can also be achieved. Furthermore, the sheet 901 has the same configuration as in the fifth embodiment. Therefore, in addition to the effects described in this embodiment, the effects described in the fifth embodiment can also be achieved. However, the number and arrangement of the sheets 900 and 901 can be selected within a range that satisfies the condition that the sheets 900 and 901 do not overlap when viewed from above. That is, the number and arrangement are not limited to the examples described above.

[0198] For example, only the sheet 900 can be configured the same as in the first embodiment, while the sheet 901 can be configured differently from the fifth embodiment. Alternatively, only the sheet 901 can be configured the same as in the fourth embodiment, while the sheet 900 can be configured differently from the first embodiment. Furthermore, the number of sheets 900 and 901 can be the same. Figure 20 In the configuration shown, the number of laminations 90 of solder 80 and 81 is the same. The laminations 90 on the solder 80 side of lamination 900 and the laminations 90 on the solder 81 side of lamination 901 are arranged in a position that does not overlap when viewed from above.

[0199] While an example of fixing the wire 900 to the heat sink 40 is shown, it can also be fixed to the back side (collector electrode 32) of the semiconductor element 30. While an example of fixing the wire 901 to the terminal 55 is shown, it can also be fixed to the surface (emitter electrode 31) of the semiconductor element 30. Alternatively, the wire 900 can be fixed to the heat sink 40, and the wire 901 can be fixed to the semiconductor element 30. Alternatively, the wire 900 can be fixed to the semiconductor element 30, and the wire 901 can be fixed to the terminal 55. Alternatively, it can be configured without the terminal 55. In this case, the wire 901 is provided at the solder joint between the heat sink 50 and the semiconductor element 30 (emitter electrode 31).

[0200] The configuration of this embodiment can also be combined with at least one of the configurations of the second embodiment, the third embodiment, and the fourth embodiment. The configuration of the second embodiment can also be combined with at least one of the sheet elements 900 and 901. The configuration of the third embodiment can also be combined with at least one of the sheet elements 900 and 901. The configuration of the fourth embodiment can also be combined with at least one of the sheet elements 900 and 901. Furthermore, the configuration of this embodiment can be satisfied only on one side, the upper arm 6H side or the lower arm 6L side.

[0201] (Seventh Implementation)

[0202] This embodiment is a variation of the prior embodiment as the basic method, and the description of the prior embodiment can be referenced.

[0203] like Figure 23 As shown, the laminations 90 can also be positioned on the solder 82. In this case, the laminations 90 of each solder 80, 81, and 82 are positioned as follows: Figure 24 The configuration shown is better. Figure 23 This is a schematic cross-sectional view showing the stacked body between the heat sinks 40 and 50 in the semiconductor device 10 of this embodiment. Figure 24 This is a top view showing an example of a preferred configuration of the laminations 90 in each of the solders 80, 81, and 82. Figure 24 and Figure 21 Corresponding. In Figure 24 In the diagram, line segment 900 is represented by a dashed line, and line segment 901 is represented by a dotted line. The configuration of the semiconductor device 10 in this embodiment is, for example, the same as that in the first embodiment. Figure 23 as well as Figure 24 The configuration shown is roughly the same on the upper arm 6H side and the lower arm 6L side.

[0204] like Figure 23 As shown, multiple laminations 90 are arranged in solders 80, 81, and 82 respectively. Hereinafter, laminations 90 arranged in solder 80 will sometimes be referred to as lamination 900, laminations 90 arranged in solder 81 as lamination 901, and laminations 90 arranged in solder 82 as lamination 902. The number of laminations 90 varies among solders 80, 81, and 82. Lamination 900 is the most numerous, and lamination 902 is the least numerous. Lamination 901 has fewer laminations than lamination 900 but more than lamination 902.

[0205] exist Figure 23 In the middle, the wire piece 900 is fixed to the heat sink 40. In addition, the wire piece 901 is fixed to the first end face 55a of the terminal 55, and the wire piece 902 is fixed to the second end face 55b.

[0206] like Figure 24 As shown, the sheet 900 is the same as the sheet 90 described in the first embodiment (see reference). Figure 7 The same configuration is used. The laminations 900 are fixed to the mounting surface 40a of the heat sink 40. Three laminations 900 are arranged in the central region 80a of the solder 80, surrounding the center 30c of the component. In the outer peripheral region 80b, four laminations 900 are arranged corresponding to the four corners of the semiconductor component 30.

[0207] The sheet 901 is the same as the sheet 90 described in the fifth embodiment (see reference). Figure 17 The same configuration. A wire piece 901 is fixed to the first end face 55a of the terminal 55. A wire piece 901 is positioned near the center of the first end face 55a. Wire pieces 901 are positioned at the four corners of the first end face 55a.

[0208] The wire piece 902 is fixed to the second end face 55b of the terminal 55. Three wire pieces 902 are fixed to the second end face 55b. The multiple wire pieces 902 are arranged to surround the center 30c of the component. Figure 24 As shown, the laminations 900, 901, and 902 are positioned so as not to overlap when viewed from above. Furthermore, terminal 55 corresponds to the first wiring component, and heat sink 50 corresponds to the second wiring component. Solder 81 corresponds to the first bonding component as a surface-mount bonding component, and solder 82 corresponds to the second bonding component.

[0209] <Summary of the Seventh Implementation>

[0210] In this embodiment, multiple laminations 90 are arranged on the solder 82. This ensures a minimum film thickness for the solder 82. Furthermore, multiple laminations 90 are arranged on each of the solders 80, 81, and 82. This ensures a minimum film thickness for all solders 80, 81, and 82 that form the conductive and heat-conducting paths of the heat sinks 40 and 50 on both sides of the semiconductor element 30 in the Z direction.

[0211] In this embodiment, the number of laminations 90 varies depending on each solder 80, 81, and 82. The solder 80 with the largest electrode area, collector electrode 32, has the most laminations 90 (laminations 900). Conversely, the solder 81 with the smaller electrode area than collector electrode 32, closer to semiconductor element 30, has fewer laminations 90 (laminations 901) than laminations 900. Furthermore, the solder 82 farther from semiconductor element 30 has the fewest laminations 90 (laminations 902). Specifically, the semiconductor device 10 has seven laminations 900, five laminations 901, and three laminations 902 as laminations 90.

[0212] Solder 80 and 81 are affected by the warpage of semiconductor element 30. By arranging the largest number of laminations 90 on top of the solder 80 (which has the largest area when viewed from above and connected to collector electrode 32), the minimum film thickness of solder 80 can be ensured. By arranging the laminations 900 in the same way as in the first embodiment, the minimum film thickness can be ensured even with the warpage of semiconductor element 30. Solder 81 connects the emitter electrode 31, which has a smaller area than collector electrode 32, to the terminal 55, which is a metal block. By providing a lamination 90 near the center, the upward convex warpage of semiconductor element 30 can be accommodated. By arranging fewer laminations 90 than solder 80, the minimum film thickness of solder 81 can be ensured. By arranging the laminations 901 in the same way as in the fifth embodiment, the minimum film thickness can be ensured even with the warpage of semiconductor element 30.

[0213] Solder 82 connects terminal 55 to heat sink 50. Unlike semiconductor element 30, no warping occurs at terminal 55 or on heat sink 50. Furthermore, since terminal 55 exists between the solder 82 and semiconductor element 30, it is not affected by warping of semiconductor element 30. Therefore, the minimum film thickness of solder 82 can be ensured with a minimum number of laminations 90. By reducing the number of laminations 901 and 902 compared to lamination 900, the gaps 86 in solder 81 and 82 can be reduced compared to a configuration with the same number of laminations 900. This ensures a minimum film thickness and improves heat dissipation. Moreover, since the number of laminations 902 is less than that of laminations 901, heat dissipation is improved compared to a configuration with the same number of laminations 901. Additionally, the overall number of laminations 90 in semiconductor device 10 can be reduced.

[0214] In addition, the laminations 900, 901, and 902 are positioned so as not to overlap when viewed from above. In the Z direction, the gaps 86 do not overlap, or if they do, the overlap is minimal, thus improving heat dissipation.

[0215] When the number of laminations 90 in solders 80, 81, and 82 differs from each other, the total number is not limited to the examples described above. It is acceptable as long as the relationship is satisfied: number of laminations 900 > number of laminations 901 > number of laminations 902. Alternatively, the number of laminations 900 can be greater than the number of laminations 901, which equals the number of laminations 902. It is also acceptable to have the number of laminations 900 equal to the number of laminations 901, which greater than the number of laminations 902. By making some of the laminations 90 in solders 80, 81, and 82 different from the remaining laminations 90, although the effect is weakened, improved heat dissipation and a reduction in the number of laminations 90 can be achieved.

[0216] If a minimum film thickness is ensured in each of solders 80, 81, and 82, the number of wafers 90 can be set more freely. The number of wafers 90 can also be the same in solders 80, 81, and 82. By configuring multiple, preferably three or more, wafers 90 respectively, the solder thickness can be easily ensured.

[0217] Alternatively, the configuration of this embodiment may be satisfied only on one side of the upper arm 6H and the lower arm 6L. Although an example of the wire piece 90 being disposed on solder 80, 81, 82 is shown, it may also be disposed on at least one side of solder 83, 84.

[0218] (Eighth Implementation Method)

[0219] This embodiment is a variation of the prior embodiment as the basic method, and the description of the prior embodiment can be referenced.

[0220] The shape of terminal 55 is not particularly limited. Preferably, the wire piece 90 is in... Figure 25 The shape shown in this example is better. Figure 25 This is a schematic diagram showing the differences between the comparative example and the present example (this embodiment) regarding the connection terminals. In the comparative example, elements that are the same as or related to elements in this embodiment (this example) are indicated by adding "r" to the end of the reference numerals in this embodiment. Both the comparative example and the present example are top views viewed from side A on the paper, with the top of the paper being a side view. The semiconductor device 10 of this embodiment is, for example, the same as that of the first embodiment. Figure 25 The configuration shown is roughly the same on the upper arm 6H side and the lower arm 6L side.

[0221] The terminal is formed by stamping from a metal sheet. The wire piece is formed by identifying the corner of the terminal's end face using a camera, and then ultrasonically bonding the joint wire at a predetermined position using the corner as a position reference. In the comparative example, the terminal 55r has a stamped R-shaped portion 550r at one corner of its end face in the Z direction. Therefore, when the wire piece 90r is formed on the end face side of the R-shaped portion 550r, there is a risk of reduced accuracy in the formation position of the wire piece 90r compared to the end face side without the R-shaped portion 550r.

[0222] In this embodiment (this example), similar to the comparative example, the terminal 55 in the punched state has an R-shaped portion (not shown) at a corner of one end face. However, after punching, the R-shaped portion is chamfered, for example, a C-shaped chamfer. A C-shaped chamfer is a chamfer with a chamfer angle of approximately 45 degrees. The terminal 55 has a chamfered portion 550.

[0223] <Summary of the Eighth Implementation>

[0224] As described above, the terminal 55 of this embodiment has a chamfered portion 550. Therefore, when the wire piece 90 is formed on the end face of the side where the R portion is formed during punching, the corner portion can be identified with high precision by taking a picture. As a result, the wire piece 90 can be formed with good positional accuracy.

[0225] The configuration of this embodiment can be applied to configurations including the terminal 55. It can be combined with various prior embodiments. Furthermore, the connection object of the wire piece 90 is not limited to the terminal 55. It can be applied to components formed by stamping metal sheets and in which the R-section is formed during stamping. By chamfering the R-section after stamping, the wire piece 90 can be formed with good positional accuracy on the side where the R-section is formed during stamping.

[0226] (Ninth Implementation)

[0227] This embodiment is a variation based on a prior embodiment, and the description of the prior embodiment can be referenced. In this embodiment, the construction and manufacturing method of the line sheet 90 are characterized.

[0228] As described above, the wire sheet 90 is formed by ultrasonically joining aluminum bonding wires and then wire-cutting at the moment of the first joining. One preferred embodiment of this wire sheet 90 is shown in... Figures 26-29 middle.

[0229] Figure 26 The connection structure between the semiconductor element 30 and the heat sink 40 in the semiconductor device 10 of this embodiment is shown. Figure 27 It is along Figure 26 A cross-sectional view of the XXVII-XXVII line. Figure 28 It means applicable Figure 26 as well as Figure 27 A 3D diagram of a 90° line sheet. Figure 29 Another example of sheet 90 is shown. Figure 26 as well as Figure 27 In this case, the number of 90-degree segments is three. Figure 26 , Figure 27 as well as Figure 28 For convenience, the illustration of the main electrode is omitted. The semiconductor device 10 in this embodiment is, for example, the same as that in the first embodiment. Figures 26-28 The configuration shown is roughly the same on the upper arm 6H side and the lower arm 6L side.

[0230] Semiconductor device 30 has a surface 30a on which an emitter electrode 31 (not shown) is formed, and a back surface 30b on which a collector electrode 32 (not shown) is formed. The collector electrode 32 constitutes the back surface 30b. Figure 21 as well as Figure 22As shown, a plurality of tabs 90 are arranged on the solder 80. The tabs 90 are engaged (fixed) to the mounting surface 40a of the heat sink 40. The mounting surface 40a corresponds to the fixing surface in the wiring component. The tabs 90 protrude from the mounting surface 40a toward the back surface 30b. The tabs 90 are held in the heat sink 40. Therefore, the heat sink 40 is sometimes referred to as a retainer. The tabs 90 have a fixing portion 91, a flat portion 92, and a non-fixed portion 93. The fixing portion 91 is a fixing part (engagement part) that is fixed to the heat sink 40 on the side of the tab 90 opposite to the heat sink 40.

[0231] The flat portion 92 is a portion of the laminate 90 formed on the side opposite to the back surface 30b of the semiconductor element 30 and substantially parallel to the mounting surface 40a of the heat sink. The non-fixed portion 93 is a portion of the laminate 90 on the side opposite to the heat sink 40 that is connected to the fixed portion 91 but not fixed to the heat sink 40. The non-fixed portion 93 is away from the mounting surface 40a in the Z direction. The non-fixed portion 93 floats relative to the fixed portion 91. The laminate 90 is configured to be elastically deformable in the Z direction. Solder 80 enters the gap between the non-fixed portion 93 and the mounting surface 40a. The laminate 90 has a fixed portion 91 and a non-fixed portion 93 on the side of the heat sink 40 in the Z direction, and a flat portion 92 on the side opposite to the fixed portion 91 and the non-fixed portion 93.

[0232] The line 90 extends along the X direction. Figure 27 as well as Figure 28 The shown lamination 90 has a flat portion 92 and a non-fixed portion 93 at both ends in the extending direction. The flat portion 92 is located at a position that overlaps with the non-fixed portion 93 when viewed from above. The height from the mounting surface 40a to the flat portions 92 at both ends is approximately equal to each other. The lamination 90 is approximately U-shaped or approximately C-shaped in the ZX plane. The flat portions 92 at both ends contact the back surface 30b of the semiconductor element 30, respectively.

[0233] Figure 29 Another example of a lamination 90 is shown. This lamination 90 has a flat portion 92 only at one end in the extending direction, not at both ends. Non-fixed portions 93 are provided at both ends in the extending direction. In the lamination 90, the height from the mounting surface 40a to the upper parts of both ends is different. The flat portion 92 is formed at the end of the side with a higher protrusion height from the mounting surface 40a. The lamination 90 is approximately J-shaped in the ZX plane. The flat portion 92 is formed at the end of the side furthest from the element center 30c (not shown).

[0234] <Manufacturing Method>

[0235] Next, the manufacturing method of the semiconductor device 10, and in particular the manufacturing method of the connector between the semiconductor element 30 and the heat sink 40, will be described. Here, it is shown that... Figure 29 The example shown is a piece 90.

[0236] First, such as Figure 30 As shown, a wire sheet 90 is formed on the mounting surface 40a of the heat sink 40. The bonding wire is joined to the heat sink 40 using ultrasonic waves from a tool not shown, forming a fixing portion 91. This fixing portion 91 is the first bonding portion. Then, after the ultrasonic waves are applied, the bonding wire is cut off such that a non-fixed portion 93 remains relative to the fixing portion 91 in the extension direction. Thus, the bonding wire is cut without forming a second bonding portion. Since the wire sheet 90 is formed using only the first bonding side, the forming time can be shortened compared to a structure with two bonding bodies, namely a first bonding portion and a second bonding portion. Furthermore, the size of the wire sheet 90 can be miniaturized, for example, by shortening its extension length. This is also advantageous from the viewpoint of solder strain described above.

[0237] Furthermore, as described above, the bonding wire is made of aluminum or aluminum alloy, and can be selected according to the size of the semiconductor device 30 and the thickness of the solder 80. Here, a bonding wire with a diameter of 80 μm is used to form a wire piece 90 with a protrusion height of 110 μm from the mounting surface 40a and an extension length of 350 μm.

[0238] Next, as Figure 31 as well as Figure 32 As shown, a flat portion 92 is formed on the online sheet 90. That is, a leveling process is performed. Specifically, a fixture 98 with a surface (hereinafter referred to as the contact surface) parallel to the mounting surface 40a is used, such as... Figure 31 A load is applied to the sheet 90 as shown by the hollow arrow. For example, a clamp 98 is mounted on a press, and a load is applied to the sheet 90. The clamp 98 is pressed against the sheet 90 while maintaining the parallelism between the contact surface and the mounting surface 40a. The clamp 98 contacts one end of the sheet 90, which is approximately J-shaped. In addition, the sheet 90 elastically deforms, and at least a portion of the non-fixed portion 93 contacts the mounting surface 40a. If the clamp 98 is pressed further in, the sheet 90 plastically deforms, forming a flat portion 92. The sheet 90 plastically deforms according to the amount of pressing. The flat portion 92 is formed on the side of the end that initially contacts the clamp 98.

[0239] After the flat portion 92 is formed, by releasing the load, the lamination 90 recovers from its elastic deformation state, and the portion of the non-fixed portion 93 that was in contact with it leaves the mounting surface 40a. Thus, as... Figure 32 As shown, a line piece 90 with a flat portion 92 at a position overlapping the non-fixed portion 93 when viewed from above can be obtained. Through flattening, the height of the line piece 90 relative to... Figure 30 The density decreases. Here, it is set to approximately 75 μm. Through the above-described process, multiple wafers 90 are formed on the mounting surface 40a. To suppress the tilting of the semiconductor element 30, it is preferable to form multiple, more preferably three or more wafers 90. It is even more preferable to adopt the configuration described in the prior embodiment.

[0240] Next, as Figure 33 As shown, molten solder 80S is applied. Molten solder 80S is applied to the mounting surface 40a of the heat sink 40. The lamination 90 is covered by the applied molten solder 80S. Since semiconductor components 30 need to be configured with the molten solder 80S, the heat sink 40 is heated as needed. Here, the molten solder 80S is applied by a transfer method.

[0241] Next, as Figure 34 As shown, a semiconductor element 30 is mounted. The semiconductor element 30 is held in place by a clamp (not shown) and lowered from above the mounting surface 40a toward the molten solder 80S. As it descends, the back surface 30b of the semiconductor element 30 comes into contact with the molten solder 80S, pressing the solder 80S away. Once it reaches a predetermined position, the clamp is released. The molten solder 80S spreads and wets the back surface 30b and the mounting surface 40a. Due to variations in the thickness of the heat sink 40, the semiconductor element 30, warpage, and mounting accuracy, the semiconductor element 30 may sometimes be pressed against the lamination 90.

[0242] Then, after cooling (not shown), it is possible to obtain... Figure 29 The connection structure shown. Additionally, for Figure 27 as well as Figure 28 The sheet 90 shown can also be formed in the same way. Specifically, after forming the fixing part 91, the joining line is cut to make the heights of both ends approximately equal to form the sheet 90, and the flat parts 92 are formed at both ends using the clamp 98.

[0243] <Summary of the Ninth Implementation>

[0244] If a line piece 90 without a flat section is used, that is... Figure 30 In the state shown, stress concentrates on the semiconductor element 30 when it comes into contact with the wire lay 90. In particular, if the height deviation of the wire lay 90 is large, the likelihood of contact between the semiconductor element 30 and the wire lay 90 increases. In contrast, in the wire lay 90 according to this embodiment, stress concentration is suppressed because the semiconductor element 30 contacts the flat portion 92. Furthermore, by forming the flat portion 92, the height deviation of the wire lay 90 is reduced. As a result, the thickness of the solder 80 is stabilized, improving connection reliability. For example, solder crack life under temperature cycling conditions can be ensured. The wire lay 90 with the flat portion 92 can be formed using wire bonding technology and simple pressing, thus reducing costs.

[0245] Furthermore, the lamination 90 has a non-fixed portion 93. This allows the lamination 90 to elastically deform. Therefore, even when the semiconductor element 30 comes into contact with the lamination 90, stress concentration in the semiconductor element 30 can be suppressed through the elastic deformation of the lamination 90. In particular, in this embodiment, a flat portion 92 is formed at the position overlapping the non-fixed portion 93 when viewed from above. This allows the flat portion 92, which contacts the semiconductor element 30, to easily deform in the direction of stress release. Consequently, stress concentration is suppressed more effectively.

[0246] The configuration of the lamination 90 is not limited to the examples above. Other examples will be shown below. Figures 35-38 middle. Figures 35-38 The examples shown all involve two laminations 90 arranged on a cross-section including the Z direction. Furthermore, the laminations 90 are in contact with the semiconductor element 30.

[0247] exist Figures 35-37 In the example shown, the two line pieces 90 and Figure 29 The shown sheet pieces 90 are identical, each having only one flat portion 92. The flat portion 92 is formed at the outer end of each sheet 90 in the arrangement direction (X direction). Figure 35 As shown, without causing warping of the semiconductor element 30, each lamination 90 has a flat portion 92 in contact with the semiconductor element 30. This suppresses stress concentration in the semiconductor element.

[0248] like Figure 36 As shown, when the semiconductor element 30 experiences upward warping, the flat portion 92 of the lamination 90 also contacts the semiconductor element 30. This suppresses stress concentration in the semiconductor element. On the other hand, as... Figure 37 As shown, when the semiconductor element 30 warps downwards, as indicated by the solid arrow in the figure, the inner end of the lamination 90 comes into contact with the semiconductor element 30. Thus, depending on the amount of warping, there is a risk that the semiconductor element 30 may come into contact with the end of the side where the flat portion 92 is not formed.

[0249] Alternatively, the flat portion 92 can be formed at the end of the sheet 90. Accordingly, even if... Figure 37 The warping shown is also mitigated by the contact between the flat portion 92 located at the inner end and the semiconductor element 30, which suppresses stress concentration. However, if upwardly protruding semiconductor elements 30 and downwardly protruding semiconductor elements 30 are mixed in the same assembly batch, for example, if the position of the flat portion 92 is aligned with the upwardly protruding semiconductor element 30, there is a risk of stress concentration on the downwardly protruding semiconductor element 30.

[0250] In contrast, Figure 38 In the example shown, the two line pieces 90 and Figure 27 as well as Figure 28 The sheet 90 shown is identical to the one shown, having flat portions 92 at both ends. Thus, when the semiconductor element 30 experiences downward warping, the inner flat portion 92 contacts the semiconductor element 30. Although not shown, when the semiconductor element 30 experiences upward warping, the outer flat portion 92 contacts the semiconductor element 30. Therefore, stress concentration can be suppressed regardless of the direction of warping in the semiconductor element 30.

[0251] The configuration of the lamination 90 in this embodiment is not limited to a lamination 90 disposed on the solder 80. Any lamination 90 located at the solder joint between the main electrode and the wiring component can be used. For example, in Figure 39 In the example shown, a strip 90 is disposed on the solder 81 between the emitter electrode 31 (not shown) and the terminal 55, and a flat portion 92 is also formed on this strip 90. Additionally, in Figure 39 In the middle, a flat portion 92 is formed only at one end of the line 90, but of course, a flat portion 92 can also be formed at both ends.

[0252] This configuration can also be applied to configurations that do not have terminals 55, but instead form a solder joint between the heat sink 50 and the emitter electrode 31. In this case, it is sufficient that the wire 90 bonded to the mounting surface 50a has a flat portion 92. Alternatively, it can be applied to configurations that only have one of the front-side wiring components and the back-side wiring components.

[0253] The structure of the lamination 90 described in this embodiment can be combined with the lamination 90 of the prior embodiment. Furthermore, the manufacturing method of the lamination 90 described in this embodiment can be applied to the formation of the lamination 90 described in the prior embodiment. Although an example of a lamination 90 having a non-fixed portion 93 is shown, it is not limited to this. At least a flat portion 92 is sufficient. Alternatively, the flat portion 92 can be provided in a position that does not overlap with the non-fixed portion 93 when viewed from above. This embodiment is applicable to laminations disposed at the junction of the main electrode of a semiconductor element and a wiring component. The arrangement of the laminations is not limited to the arrangement shown in the prior embodiment.

[0254] (Tenth Implementation)

[0255] This embodiment is a variation based on prior embodiments, and the description of those prior embodiments can be referenced. In this embodiment, a preferred embodiment of the sheet 90 is also shown.

[0256] <Size of the line>

[0257] First, based on Figures 40-43 The preferred size of the lamination 90 will be described below. The lamination 90 is disposed on solder that connects the main electrode of the semiconductor element 30 to the wiring component. The solder here is, for example, solder 80 or 81.

[0258] Figure 40 This is the simulation result showing the relationship between the volume of the lamination 90 and the solder strain. The horizontal axis represents the volume of the lamination 90 (×10). 7 μm 3 The vertical axis represents solder strain (in any unit). The horizontal axis is a logarithmic axis. Figure 41 This is a diagram showing the line sheet 90 in this embodiment. Figure 41 In the diagram, the top of the paper shows a side view, and the bottom of the paper shows a top plan view. Figure 42 This is a cross-sectional view used to illustrate the maximum height of the lamination 90 disposed on the solder 80. Figure 43 This is a cross-sectional view used to illustrate the maximum height of the lamination 90 disposed on the solder 81.

[0259] according to Figure 40 The simulation results show that if the volume of the lamination 90 is large, the thermal stress (in other words, the solder strain) based on the difference in the coefficients of linear expansion between the lamination 90 and the solder will increase. If this exceeds the specified volume, component damage such as cracks will occur. If the solder strain becomes... Figure 40 Values ​​above the dashed line indicate component damage. Therefore, to suppress component damage, it is preferable to set the volume of the lamination 90 to 1.0 × 10⁻⁶. 7 μm 3 Hereinafter, in the semiconductor device 10 of this embodiment, the volume of each wafer 90 is set to 1.0 × 10⁻⁶. 7 μm 3 the following.

[0260] Next, we will explain the configuration that satisfies the above-mentioned volume relationship and can suppress the height deviation of the lamination 90 without leveling. Hereinafter, we will illustrate the lamination 90 connected to the heat sink 40.

[0261] like Figure 41 As shown, the wire sheet 90 is divided into three parts in its extending direction. The wire sheet 90 has a connecting portion 94, a feed portion 95, and a tail portion 96. The connecting portion 94 is located between the feed portion 95 and the tail portion 96 in the extending direction of the wire sheet 90. The connecting portion 94 is the part that connects to the heat sink 40. The connecting portion 94 has a fixing portion 91 on the side opposite to the heat sink 40. The connecting portion 94 is the part that includes the fixing portion 91 and overlaps with the fixing portion 91 when viewed from above. That is, the connecting portion 94 is the part directly above the fixing portion 91. The connecting portion 94 is equivalent to a connecting part. The connecting portion 94 is crushed by the load from the tool during ultrasonic bonding. Therefore, the width of the connecting portion 94 is wider than the width of the feed portion 95 and the tail portion 96.

[0262] The feed section 95 is connected to the joining section 94 on the front end side of the strip 90. The feed section 95 is the portion not joined to the heat sink 40. The feed section 95 has a non-fixed section 93 on the side opposite to the heat sink 40. The feed section 95 is the portion that includes the non-fixed section 93 on the front end side and overlaps with the non-fixed section 93 when viewed from above. That is, the feed section 95 is the non-fixed section 93 on the front end side and the portion directly above the non-fixed section 93. The feed section 95 does not have a flat section 92 on the side opposite to the semiconductor element 30 (not shown).

[0263] Tail portion 96 is connected to the coupling portion 94 on the rear end side of the strip 90. Like the feed portion 95, tail portion 96 is a portion not coupled to the heat sink 40. Tail portion 96 has a non-fixed portion 93 on the side opposite to the heat sink 40. Tail portion 96 is the portion that includes the non-fixed portion 93 on the rear end side and overlaps with the non-fixed portion 93 when viewed from above. That is, tail portion 96 is the non-fixed portion 93 on the rear end side and the portion directly above it. Tail portion 96 does not have a flat portion 92 on the side opposite to the semiconductor element 30 (not shown).

[0264] The feed section 95 and the tail section 96 correspond to the non-joining section. The front end side refers to the side that has an end (cut end) before ultrasonic joining. The rear end side refers to the end side formed after ultrasonic joining due to cutting the joining line. Although not shown in the figure, the radiator 40 has a cut made when cutting the joining line directly below the rear end of the strip 90.

[0265] Hereinafter, the length of the extending part 94 in the direction of extension is sometimes denoted as LB, the length of the extending part 95 in the direction of extension is sometimes denoted as LF, and the length of the extending part 96 in the direction of extension is sometimes denoted as LT. The length (total length) of the lath 90 in the direction of extension is sometimes denoted as LW, and the width of the joining part 94 is sometimes denoted as WB. Width WB is the length in the joining part 94 in the direction orthogonal to the extending direction. Additionally, the height of the joining part 94 is sometimes denoted as HB, the height of the feeding part 95 as HF, and the height of the tail 96 as HT. Furthermore, the lengths of the feeding part 95 (LF) and the tail 96 (LT) are as follows: Figure 41 As shown, the length is the length of the side opposite to the semiconductor element 30 (upper surface side), not the side opposite to the heat sink 40 (lower surface side). The height refers to the height of the portion furthest from the first opposing surface, which serves as the mating surface, in the Z direction.

[0266] When forming the lamination 90 using a bonding wire with a diameter of 80 μm, the length LB of the bonding portion 94 is approximately the same as in this embodiment, provided that the flat portion 92 is also present. For example, the length LB is 260 μm ± 100 μm. To make the volume of the lamination 90 1.0 × 10⁻⁶ mm... 7 μm 3Hereinafter, it is preferable to set the total length LW of the wire piece 90 to 400μm or more and 450μm or less, and the lengths LF and LT of the feed section 95 and the tail section 96 to 100μm or less.

[0267] In the configuration where the flat portion 92 is provided, the length of the flat portion 92 needs to be ensured in the extending direction. If the flat portion 92 is provided on both ends, the total length of the sheet 90 exceeds 450 μm, for example, becomes about 500 μm. In this embodiment, since the flat portion 92 is not provided, the lengths LF and LT of the feed portion 95 and the tail portion 96, which are non-jointing portions, can be shortened to less than 100 μm each. Therefore, even if there is a deviation in length LB, the total length LW of the sheet 90 can be less than 450 μm. That is, the sheet 90 can be miniaturized. Therefore, it is easy to make the volume of the sheet 90 1.0 × 10⁻⁶. 7 μm 3 Furthermore, due to the shorter lengths LF and LT, deviations in heights HF and HT can be suppressed.

[0268] Furthermore, it is preferable to set the height HF of the feed section 95 and the height HT of the tail section 96 to be between 80 μm and 100 μm. The height of 80 μm is equal to the wire diameter. In this case, although the feed section 95 and the tail section 96 are in contact with the mounting surface 40a of the heat sink 40, they are not engaged.

[0269] In cases where semiconductor element 30 may experience downward bulging warping, such as Figure 42 As shown, the volume of the space between the semiconductor element 30 and the heat sink 40, where no warping occurs, becomes the largest. When the volume of the space is the largest, the solder 80, which serves as the bonding area to ensure the solder wets and expands across approximately the entire surface of the collector electrode 32, is required in the largest amount. This required solder volume becomes the smallest when the semiconductor element 30 is supported on the lamination 90. The minimum required solder volume is obtained by subtracting the recessed portion of the solder 80 from the volume of the portion overlapping the semiconductor element 30 (collector electrode 32) when the thickness of the solder 80 is equal to the heights HF and HT in a top view.

[0270] If the heights HF and HT are greater than 110 μm, there is a risk that the specified supply amount of solder 80 will be lower than the minimum required solder volume. This can be seen from the simulation results. In this case, there is a risk that the solder 80 will only wet and spread on a portion of the collector electrode 32. If the solder heights HF and HT are less than 100 μm, the specified supply amount of solder 80 will exceed the minimum required solder volume. Thus, the solder 80 wets and spreads on approximately the entire surface of the collector electrode 32, ensuring reliable connection.

[0271] The same applies to the solder 81 on the emitter electrode 31 side. In cases where the semiconductor element 30 may experience downward bulging warping, such as... Figure 43 As shown, the volume of the space between the semiconductor element 30 and the terminal 55 becomes largest when the warpage is at its maximum (e.g., 0.1 μm). When the volume of the space is at its maximum, the maximum amount of solder 81 is required to ensure the solder wets and expands the bonding area across approximately the entire surface of the emitter electrode 31. This required solder volume is minimized when the semiconductor element 30 is supported on the lamination 90.

[0272] If the heights HF and HT are greater than 110 μm, there is a risk that the specified supply amount of solder 80 will be lower than the minimum required solder volume. This can be seen from the simulation results. In this case, there is a risk that the solder 81 will only wet and spread on a portion of the emitter electrode 31. If the solder heights HF and HT are less than 100 μm, the specified supply amount of solder 81 will exceed the minimum required solder volume. Therefore, by ensuring that the solder 81 wets and spreads across approximately the entire surface of the emitter electrode 31, reliable connection can be ensured.

[0273] Additionally, as in the prior implementation method (see...) Figure 14 As shown, even when the downward-protruding semiconductor element 30 is arranged at an angle, as long as the heights HF and HT are 70 μm or more, it is possible to pass through the line plates 90 (refer to) arranged at least at the four corners. Figure 12 as well as Figure 20 The minimum film thickness of solders 80 and 81 is guaranteed. The minimum film thickness that ensures reliable connection is, for example, 43 μm. In this embodiment, the line diameter is 80 μm, and the minimum heights HF and HT are 80 μm. Therefore, even when the downwardly protruding semiconductor element 30 is arranged at an angle, reliable connection can be ensured.

[0274] If the lengths LF and LT are shortened as described above, the ratio (LF / LB, LT / LB) of the lengths LF and LT of the feed section 95 or tail section 96 to the length LB of the joint section 94 is smaller than that of the configuration with the flat section 92. This is to make the volume of the lamination 90 1.0 × 10⁻⁶. 7 μm 3 It is preferable that LF / LB and LT / LB be 0.1 or higher and 0.65 or lower. By satisfying this relationship, the length of the feed section 95 and the tail section 96 can be suppressed relative to the joint 94, thereby miniaturizing the wire piece 90. In addition, deviations in height HF and HT can be suppressed.

[0275] Furthermore, it is preferable that the ratio (WB / LB) of the width WB of the joint 94 to the length LB of the joint 94 is 0.2 or more and 0.7 or less. That is, it is preferable to narrow the width WB. This reduces the volume of the sheet 90. In addition, it can suppress deviations in height HF and HT.

[0276] More specifically, it is preferable to form the lamination 90 in a manner that satisfies the following dimensions: The overall length LW of the lamination 90 is preferably 420 μm ± 20 μm, the length LF of the feed portion 95 is preferably 85 μm ± 15 μm, and the length LT of the tail portion 96 is preferably 70 ± 30 μm. The length LB of the joining portion 94 is preferably 260 μm ± 100 μm, the height HB of the joining portion is preferably 70 μm ± 5 μm, and the width WB of the joining portion 94 is preferably 90 μm + 15 μm - 5 μm. The height HF of the feed portion 95 is preferably 85 μm + 15 μm - 5 μm, and the height HT of the tail portion 96 is preferably 85 μm ± 5 μm.

[0277] <Methods for Manufacturing Wire Sheets>

[0278] Next, based on Figures 44-48 The manufacturing method of the lamination 90 that meets the above-mentioned volume and size requirements will be described. Hereinafter, an example of the lamination 90 being provided on the heat sink 40 is shown, but the same applies to the terminal 55.

[0279] like Figure 44 As shown, the ultrasonic bonding apparatus includes a wire guide 100, a tool 101, and a cutter 102. First, the bonding wire 99, which is led out from the wire guide 100, is positioned at a predetermined position on the mounting surface 40a of the heat sink 40. At this time, the bonding wire 99 is positioned with the bonding portion of the tool 101 as a reference, and the feed portion 95 is positioned in a manner that ensures the aforementioned predetermined length.

[0280] Next, as Figure 45 As shown, ultrasonic bonding is performed using tool 101. Through ultrasonic bonding, a joint 94 is formed. The bonding line 99 is significantly crushed due to the power of the ultrasonic bonding and the load imposed by tool 101. Consequently, the width of the joint 94 increases. In this embodiment, the power and load are adjusted so that the width WB of the joint 94 is not excessively large, but falls within the range of 90μm + 15μm - 5μm, in other words, 85μm to 105μm.

[0281] By ultrasonic bonding, such as Figure 45 As indicated by the middle arrow, compressive stress is applied to the upper surface of the feed section 95. On the other hand, tensile stress is applied to the lower surface of the feed section 95, in other words, to the radiator 40 side. As a result, the feed section 95 bounces off the mounting surface 40a of the radiator 40. The portion of the non-fixed part 93 that was previously in contact with the feed section 95 leaves the mounting surface 40a.

[0282] After the ultrasonic bonding is completed, such as Figure 46 As shown, tool 101 (ultrasonic bonding device) is retracted. Figure 46The amount of retraction of tool 101, indicated by a hollow arrow, is determined based on the cutting position of cutter 102, i.e., the length of tail 96. Specifically, the amount of retraction is determined in such a way that the length LT of tail 96 and the total length of wire 90 are both specified lengths.

[0283] Next, as Figure 47 As shown, wire cutting is performed. With tool 101 pressing down on the joining wire 99 in the retracted position described above, the joining wire 99 is cut using cutter 102. Wire cutting forms a wire sheet 90. After wire cutting, as shown... Figure 48 As shown, the ultrasonic bonding device containing tool 101 is retracted. By cutting to release the load, the tail 96 of the wire 90 recovers from its elastic deformation state and springs back relative to the mounting surface 40a of the heat sink 40. The portion of the non-fixed part 93 that was in contact leaves the mounting surface 40a.

[0284] Through wire cutting, such as Figure 48 As shown, a cut 41 is formed in the heat sink 40. The cut 41 is formed directly below the tail 96 at both ends of the extension direction of the lamination 90.

[0285] <Summary of the Tenth Implementation>

[0286] In this embodiment, the volume of the lamination 90 is set to 1.0 × 10⁻⁶. 7 μm 3 Therefore, thermal stress can be reduced, thereby suppressing component damage. That is, the reliability of the semiconductor device 10 can be improved.

[0287] Additionally, in the prior implementation method (see...) Figure 28 In this configuration, the aforementioned volume relationship can also be satisfied. However, if flat sections 92 are provided at both ends, the total length LW of the sheet 90 becomes longer. Furthermore, without leveling, the deviation in line height, or in other words, height HF and HT, is significant. Leveling is required, which increases the number of processes and consequently, the manufacturing cost.

[0288] In this embodiment, to satisfy the aforementioned volume requirements, the overall length LW of the lamination 90 is between 400 μm and 450 μm, and the lengths LF and LT of the feed section 95 and the tail section 96 are between 100 μm and 96. Since the flattening section 92 is not provided, the lengths LF and LT of the feed section 95 and the tail section 96, as well as the overall length LW of the lamination 90, can be shortened. Furthermore, leveling processing is unnecessary, which reduces manufacturing costs.

[0289] In particular, the lengths LF and LT of the feed section 95 and the tail section 96 are shortened relative to the length LB of the joint 94. Specifically, the ratios LF / LB and LT / LB are set to 0.1 or more and 0.65 or less. This helps to suppress deviations in the heights HF and HT.

[0290] In this embodiment, the height HF of the feed section 95 and the height HT of the tail section 96 are set to be 80 μm or more and 100 μm or less. This ensures reliable connection.

[0291] In this embodiment, the ratio (WB / LB) of the width WB of the joint 94 to the length LB of the joint 94 is between 0.2 and 0.7. By narrowing the width WB, the volume of the lamination 90 can be reduced. Furthermore, by narrowing the width WB, the power and load during ultrasonic bonding are suppressed within a range that ensures bonding strength. This reduces the amount of crushing, thereby suppressing deviations in height HF and HT.

[0292] The line sheet 90 shown in this embodiment, which does not have a flat portion 92, can be combined with the first to eighth embodiments. For example, it is suitable for... Figure 12 , Figure 20 The configuration shown is such that the laminations 90 are arranged only at the four corners. This embodiment is applicable to laminations arranged at the junction of the main electrode of a semiconductor element and a wiring component. The arrangement of the laminations is not limited to the arrangement shown in the prior embodiments.

[0293] (Other implementation methods)

[0294] The disclosure in this specification and accompanying drawings is not limited to the illustrated embodiments. The disclosure includes the illustrated embodiments and modifications made by those skilled in the art based on them. For example, the disclosure is not limited to combinations of components and / or elements shown in the embodiments. The disclosure can be implemented in various combinations. The disclosure may have additional portions that can be added to the embodiments. The disclosure includes cases where components and / or elements of the embodiments are omitted. The disclosure includes substitutions or combinations of components and / or elements between one embodiment and other embodiments. The scope of the disclosure is not limited to the description of the embodiments. Several technical scopes of the disclosure are indicated by the description in the claims and should be understood to include all modifications within the meaning and scope equivalent to the description in the claims.

[0295] The disclosures in the specification and drawings are not limited by the claims. The disclosures in the specification and drawings encompass the technical ideas described in the claims, and involve a wider range of technical ideas than those described in the claims. Therefore, without being bound by the claims, various technical ideas can be extracted from the disclosures in the specification and drawings.

[0296] While an example of applying the semiconductor device 10 to the inverter 5 has been shown, it is not limited thereto. For example, it can also be applied to a converter. Furthermore, it can be applied to both the inverter 5 and the converter.

[0297] While an example of semiconductor element 30 having an IGBT 6i and an FWD 6d forming one arm is shown, it is not limited to this. The IGBT 6i and FWD 6d can also be different chips (another element). While an example of IGBT 6i is shown as a switching element, it is not limited to this. A MOSFET can also be used, for example. Additionally, a diode can be used as a vertically oriented element with main electrodes on both sides.

[0298] It may also have multiple semiconductor elements 30H, which are connected in parallel to form one of the upper arms 6H. It may also have multiple semiconductor elements 30L, which are connected in parallel to form one of the lower arms 6L.

[0299] While examples showing the back surfaces 40b and 50b of heat sinks 40 and 50 exposed from the sealing resin body 20 are shown, this is not a limitation. It is also possible that at least one of the back surfaces 40b and 50b is covered by the sealing resin body 20. It is also possible that at least one of the back surfaces 40b and 50b is covered by another insulating member (not shown) different from the sealing resin body 20. While examples showing the semiconductor device 10 having the sealing resin body 20 are shown, this is not a limitation. It is also possible that it does not have the sealing resin body 20.

[0300] While an example has been shown of a semiconductor device 10 comprising multiple semiconductor elements 30 constituting an upper and lower arm circuit 6 of one phase, it is not limited thereto. It may also comprise only a semiconductor element constituting one arm. For example, the semiconductor device 10 may comprise a semiconductor element 30 constituting one arm and a pair of heat sinks 40, 50 configured to hold the semiconductor element 30. Alternatively, it may comprise semiconductor elements constituting an upper and lower arm circuit 6 of three phases as a single package.

[0301] While an example is shown where the signal terminal 75 is connected to the pad 33 via the bonding wire 87, it is not limited to this. For example, the signal terminal 75 may also be connected to the pad 33 via solder. Since no space is needed for the bonding wire 87, a configuration without the terminal 55 may be used.

[0302] While an example is shown where slot 51 is provided in the radiator 50 and slot 63 is provided in the connector portions 61 and 62, this is not a limitation. It is also possible to configure the device so that at least one of slots 51 and 63 is excluded. While an example is shown where a connection portion connecting the upper arm 6H and the lower arm 6L is implemented using a connection structure with two connector portions 60 and 61, this is not a limitation. It is also possible to configure the connector portion connected to one of the radiators 40L and 50H to be connected to the other. Furthermore, while an example is shown with connector portion 62, this is not a limitation. It is also possible to configure the main terminal 71 to be connected to the radiator 50L without via connector portion 62.

Claims

1. A method for manufacturing a semiconductor device, comprising the following steps: A wire piece is formed on the mounting surface of the wiring component. The wire piece has a fixing part that engages with and is fixed to the mounting surface, and a non-fixing part that is connected to the fixing part but is not fixed to the mounting surface but is away from the mounting surface. A flat portion is formed at at least one end of the wire piece in the extension direction of the wire piece, and at a position on the side opposite to the wiring component in the thickness direction of the plate and overlapping with the non-fixed portion. Solder is applied to the mounting surface in such a way that it covers the sheet on which the flat portion is formed; as well as The semiconductor element is mounted on the wiring component by pressing open the solder.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, During the formation of the wire sheet The fixing part is formed by ultrasonically bonding a portion of the joint line disposed on the mounting surface. After the ultrasonic bonding, the bonding line is cut to a predetermined length such that non-fixed portions remain on both sides of the extension direction of the fixed portion.

3. The method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that, When forming the flat portion The flat portion is formed by elastically deforming the non-fixed portion using the clamp.

4. The method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that, When forming the flat portion The flat portion is formed at both ends of the line piece in the extending direction.

5. The method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that, During the formation of the wire sheet Multiple strips are formed on the mounting surface.

6. A semiconductor device, characterized in that, have: The wiring component, the bonding component formed by the solder, the plurality of the laminations, and the semiconductor element mounted on the mounting surface via the bonding component and the plurality of the laminations are manufactured by the semiconductor device manufacturing method according to any one of claims 1 to 5.

7. The semiconductor device according to claim 6, characterized in that, The semiconductor element, serving as the main electrode, has a surface electrode and a back electrode. The surface electrode is formed on the surface, and the back electrode is formed on the back side, which is opposite to the surface in the thickness direction of the plate. The wiring component includes: a back wiring component disposed on the back side and connected to the back electrode; and a surface wiring component disposed on the surface side and connected to the surface electrode. The bonding component includes: a back-side bonding component forming a bonding portion between the back electrode and the back wiring component; and a front-side bonding component forming a bonding portion between the surface electrode and the surface wiring component. The laminations include a plurality of back-side laminations disposed on the back-side bonding member and a plurality of front-side laminations disposed on the front-side bonding member.

8. The semiconductor device according to claim 6 or 7, characterized in that, The semiconductor device also includes a sealing resin body. The semiconductor element includes a first semiconductor element constituting the upper arm of the inverter's upper and lower arm circuits, and a second semiconductor element constituting the lower arm. The sealing resin seals the first semiconductor element, the second semiconductor element, and the wiring component, the bonding component, and the plurality of wires respectively disposed corresponding to the first semiconductor element and the second semiconductor element.

9. The semiconductor device according to claim 8, characterized in that, It also features multiple power terminals, output terminals, and multiple signal terminals. The plurality of power terminals and the output terminals protrude from one side of the sealing resin body. The plurality of signal terminals protrude from the side of the sealing resin body opposite to the side of one of the sides.

10. An inverter comprising a three-phase upper and lower arm circuit having the first semiconductor element and the second semiconductor element as described in claim 8 or 9.

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