Fault detection device and UPS system

Abstract

The invention provides a fault detection device and a UPS system. The input end of the fault detection device is connected with the first output end of a processor of the UPS system. The output end of the fault detection device is connected with the control end of a bypass module of the UPS system; the fault detection device is configured to output a first driving signal based on an output signal output by a first output end of the processor; wherein when the processor is in a normal state, the output signal is a non-constant signal, and the first driving signal is a first level; when the processor is in a fault state, the output signal is a constant signal, and the first driving signal is a second level; and the second level is used for triggering the bypass module to be switched into a bypass output state.

Description

Technical Field

[0001] This disclosure relates to the field of integrated electronic circuit technology, and more particularly to a fault detection device and a UPS system. Background Technology

[0002] In modern society, which is highly dependent on electricity supply, uninterruptible power supply (UPS) systems have become a core infrastructure for ensuring the stable operation of critical equipment. UPS systems are widely used in data centers, communication base stations, medical equipment, industrial automation, and other fields to ensure seamless switching to backup power in the event of mains power outages or other power failures, thereby providing continuous and stable power support to the load equipment. However, the reliability and performance of a UPS system depend not only on the quality of its hardware components but also on its internal intelligent control unit, in which the digital signal processor (DSP) plays a crucial role.

[0003] The DSP is the core control chip of a UPS system, responsible for handling complex signal acquisition, analysis, and control tasks. It can monitor mains voltage and frequency in real time, precisely control the inverter's output waveform, adjust battery charging current, and comprehensively monitor the overall operating status of the UPS system. Through high-speed computing and precise algorithms, the DSP can achieve rapid fault diagnosis, protection mechanism triggering, and dynamic adjustment of system parameters. However, due to the complexity of the UPS system's operating environment and its long-term uninterrupted operation, the DSP itself may also malfunction, such as program errors, hardware damage, or communication failures. These failures may cause the UPS system to malfunction. For example, when the UPS system malfunctions, it needs to switch to bypass output, and bypass output control requires DSP intervention. If the DSP fails, it may be unable to effectively trigger the UPS system to switch to bypass output, posing a risk of power loss to the system output. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a fault detection device and a UPS system.

[0005] To achieve the above objectives, the technical solution of this disclosure embodiment is implemented as follows:

[0006] In a first aspect, this disclosure provides a fault detection device, wherein the input terminal of the fault detection device is connected to the first output terminal of the processor of the UPS system; the output terminal of the fault detection device is connected to the control terminal of the bypass module of the UPS system; and the fault detection device is configured to output a first drive signal based on the output signal output by the first output terminal of the processor.

[0007] Wherein, when the processor is in normal state, the output signal is a non-constant signal, and the first drive signal is a first level; when the processor is in fault state, the output signal is a constant signal, and the first drive signal is a second level; the second level is used to trigger the bypass module to switch to bypass output state.

[0008] In one optional embodiment, the fault detection device includes a DC blocking module and a signal processing module; the signal processing module includes a first switching transistor; wherein,

[0009] The input terminal of the DC blocking module is connected to the first output terminal of the processor and is configured to: turn off the first switch when the output signal is the constant signal; and turn on the first switch intermittently when the output signal is the non-constant signal.

[0010] The input terminal of the signal processing module is connected to the output terminal of the DC blocking module and is configured to output the first level when the first switch is intermittently turned on, and output the second level when the first switch is turned off.

[0011] In one optional implementation, the signal processing module further includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a second switching transistor, a diode, and a first capacitor;

[0012] The first end of the first resistor is connected to the output end of the DC blocking module, and the second end of the first resistor is connected to the cathode of the diode, the first end of the second resistor, and the base of the first switching transistor. The anode of the diode, the second end of the second resistor, and the emitter of the first switching transistor are all grounded.

[0013] The first end of the third resistor is connected to the power supply level, the second end of the third resistor is connected to the first end of the fourth resistor and the collector of the first switching transistor, the second end of the fourth resistor is connected to the base of the second switching transistor, the emitter of the second switching transistor is connected to the power supply level, the collector of the second switching transistor is connected to the first end of the fifth resistor and the first end of the sixth resistor, and the second end of the fifth resistor is grounded.

[0014] The first electrode of the first capacitor is connected to the second terminal of the sixth resistor, and the second electrode of the first capacitor is grounded.

[0015] When the first switch is intermittently turned on, the second switch is intermittently turned on, and the first capacitor is in a dynamic stable state.

[0016] In one optional implementation, the signal processing module further includes a comparator, a seventh resistor, an eighth resistor, and a second capacitor;

[0017] The positive input terminal of the comparator is connected to the first electrode of the first capacitor;

[0018] The first terminal of the seventh resistor, the first terminal of the eighth resistor, and the first electrode of the second capacitor are all connected to the negative input terminal of the comparator.

[0019] The second terminal of the eighth resistor and the second electrode of the second capacitor are both grounded;

[0020] The second terminal of the seventh resistor is connected to the power supply level;

[0021] The comparator's negative input receives a threshold level; when the first capacitor is in the dynamic stable state, the level at the comparator's positive input is greater than the threshold level, and the comparator outputs a third level; when the first capacitor is in the non-dynamic stable state, the level at the comparator's positive input is less than the threshold level, and the comparator outputs a fourth level.

[0022] In one alternative implementation, the signal processing module further includes a ninth resistor and a light-emitting diode;

[0023] The first end of the ninth resistor is connected to the power supply level, and the second end of the ninth resistor is connected to the anode of the light-emitting diode.

[0024] The cathode of the light-emitting diode is connected to the output terminal of the comparator;

[0025] Specifically, when the comparator outputs the fourth level, the light-emitting diode is turned on.

[0026] In one alternative implementation, the signal processing module further includes a tenth resistor and a third capacitor;

[0027] The first end of the tenth resistor is connected to the power supply level; the second end of the tenth resistor is connected to the first electrode of the third capacitor, and both are connected to the output terminal of the signal processing module; the second electrode of the third capacitor is grounded.

[0028] Specifically, when the comparator outputs the third level, the first driving signal is the first level; when the comparator outputs the fourth level, the first driving signal is the second level.

[0029] In one optional embodiment, the first switching transistor is an N-type transistor, the second switching transistor is a P-type transistor, and the resistance values ​​of the second resistor, the third resistor, the fourth resistor, the fifth resistor, and the sixth resistor are all the same.

[0030] Secondly, this disclosure provides a UPS system, including:

[0031] processor;

[0032] The fault detection device described in any of the above embodiments; the input terminal of the fault detection device is connected to the first output terminal of the processor, and is configured to: perform fault detection on the processor based on the output signal of the processor, and output the first drive signal;

[0033] Main power module; the control terminal of the main power module is connected to the second output terminal of the processor, and the input terminal of the main power module receives the mains power signal;

[0034] A bypass module; the control terminal of the bypass module is connected to the third output terminal of the processor and to the output terminal of the fault detection device; the first input terminal of the bypass module is connected to the output terminal of the main power module, and the second input terminal of the bypass module receives the bypass power signal.

[0035] In an alternative implementation, the processor is further configured to:

[0036] The operating parameters of the UPS system are acquired, detection is performed based on the operating parameters, and a second drive signal is output. When the operating parameters indicate that the UPS system is in a normal state, the second drive signal is at the fifth level; when the operating parameters indicate that the UPS system is in an abnormal state, the second drive signal is at the sixth level. The sixth level is used to trigger the bypass module to switch to the bypass output state.

[0037] In one optional implementation, the bypass module includes logic circuitry and switching circuitry;

[0038] The first input terminal of the logic circuit is connected to the output terminal of the fault detection device; the second input terminal of the logic circuit is connected to the third output terminal of the processor; the output terminal of the logic circuit is connected to the control terminal of the switching circuit; the first input terminal of the switching circuit is connected to the bypass power signal; and the second input terminal of the switching circuit is connected to the output terminal of the main power module.

[0039] The logic circuit is configured to: output a control signal; when the first driving signal is the second level or the second driving signal is the sixth level, the control signal is the seventh level; the seventh level is used to control the switching circuit to output the bypass power signal; when the first driving signal is the first level and the second driving signal is the fifth level, the control signal is the eighth level; the eighth level is used to control the switching circuit to output the output signal of the main power module.

[0040] In the technical solution provided in this disclosure, the fault detection device can detect the processor fault based on the output signal of the processor in the UPS system. When the processor is in a fault state, the output can trigger the bypass module to switch to the bypass output state. Thus, when the processor fails, the UPS system can also effectively switch to the bypass output state, thereby avoiding the UPS output power failure due to DSP failure and effectively improving the reliability of the UPS system. Attached Figure Description

[0041] Figure 1 A schematic diagram of a UPS system provided in an embodiment of this disclosure;

[0042] Figure 2 A schematic diagram of a fault detection device provided in an embodiment of this disclosure;

[0043] Figure 3 Circuit diagram of the fault detection device provided in the embodiments of this disclosure;

[0044] Figure 4 This is a schematic diagram of a bypass module provided in an embodiment of this disclosure. Detailed Implementation

[0045] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0046] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0047] In the accompanying drawings, the same reference numerals denote the same elements throughout.

[0048] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0049] In modern society, which is highly dependent on electricity supply, UPS systems have become a core infrastructure for ensuring the stable operation of critical equipment. UPS systems are widely used in data centers, communication base stations, medical equipment, industrial automation, and other fields to ensure seamless switching to backup power in the event of mains power outages or other power failures, thereby providing continuous and stable power support to the load equipment. However, the reliability and performance of a UPS system depend not only on the quality of its hardware components but also on its internal intelligent control unit, in which the DSP plays a crucial role.

[0050] The DSP is the core control chip of a UPS system, responsible for handling complex signal acquisition, analysis, and control tasks. It can monitor mains voltage and frequency in real time, precisely control the inverter's output waveform, adjust battery charging current, and comprehensively monitor the overall operating status of the UPS system. Through high-speed computing and precise algorithms, the DSP can achieve rapid fault diagnosis, protection mechanism triggering, and dynamic adjustment of system parameters. However, due to the complexity of the UPS system's operating environment and its long-term uninterrupted operation, the DSP itself may also malfunction, such as program errors, hardware damage, or communication failures. These failures may cause the UPS system to malfunction. For example, when the UPS system malfunctions, it needs to switch to bypass output, and bypass output control requires DSP intervention. If the DSP fails, it may be unable to effectively trigger the UPS system to switch to bypass output, posing a risk of power loss to the system output.

[0051] In view of this, in order to avoid the UPS system losing power due to DSP failure, the present disclosure proposes the following implementation method.

[0052] This disclosure provides a fault detection device for UPS systems. Figure 1 A schematic diagram of a UPS system including a fault detection device provided in an embodiment of this disclosure, with reference to... Figure 1The input terminal of the fault detection device 101 is connected to the first output terminal of the processor 102 of the UPS system; the output terminal of the fault detection device 101 is connected to the control terminal of the bypass module 103 of the UPS system; the fault detection device 101 is configured to output a first drive signal based on the output signal output from the first output terminal of the processor 102; wherein, when the processor 102 is in a normal state, the output signal is a non-constant signal, and the first drive signal is a first level; when the processor 102 is in a fault state, the output signal is a constant signal, and the first drive signal is a second level; the second level is used to trigger the bypass module 103 to switch to the bypass output state. Here, the processor 102 may include a DSP.

[0053] In this embodiment of the present disclosure, the fault detection device 101 can detect the fault of the processor 102 based on the output signal of the processor 102, and when the processor 102 is in a fault state, it outputs a second level that can trigger the bypass module 103 to switch to the bypass output state. Thus, when the processor 102 fails, the UPS system can also effectively switch to the bypass output state, thereby avoiding the UPS power failure due to DSP failure and effectively improving the reliability of the UPS system.

[0054] In some specific examples, when the processor 102 is in a normal state, the output signal output from the first output terminal of the processor 102 can be a periodically toggling signal, that is, the non-constant signal in the above embodiment can be a square wave signal with a fixed frequency. When the processor 102 is in a fault state, the first output terminal of the processor 102 can no longer periodically toggle the voltage signal, that is, the constant signal in the above embodiment can be a constant voltage signal that is always low or always high. The fault detection device 101 can output a first driving signal with a first level when the output signal is a non-constant signal, or output a first driving signal with a second level when the output signal is a constant signal. The first driving signal with a second level can be used to trigger the bypass module 103 to switch to the bypass output state.

[0055] In some embodiments, Figure 2 This is a schematic diagram of the composition of the fault detection device provided in the embodiments of this disclosure. Figure 3 A circuit diagram of a fault detection device provided as a specific example of this disclosure. (Refer to...) Figures 1 to 3The fault detection device 101 includes a DC blocking module 201 and a signal processing module 202. The signal processing module 202 includes a first switching transistor Q1. The input terminal of the DC blocking module 201 is connected to the first output terminal of the processor 102 and is configured to: turn off the first switching transistor Q1 when the output signal of the processor 102 is a constant signal; and turn on the first switching transistor Q1 intermittently when the output signal of the processor 102 is a non-constant signal. The input terminal of the signal processing module 202 is connected to the output terminal of the DC blocking module 201 and is configured to: output a first level when the first switching transistor Q1 is intermittently turned on; and output a second level when the first switching transistor Q1 is turned off.

[0056] In some specific examples, refer to Figure 3 The output signal of the processor 102 can be DSP_Fault. The DC blocking module 201 can include a capacitor C1. The first electrode of the capacitor C1 receives the output signal of the processor 102, the second electrode of the capacitor C1 is connected to the input terminal of the signal processing module 202, and is connected to the base of the first switching transistor Q1 through the first resistor R1. The DC blocking module 201 can utilize the AC-blocking and DC-blocking characteristics of capacitor C1. When the output signal of processor 102 is a constant signal, the level on the second electrode of capacitor C1 is constant at ground level GND, and the level on the base of the first switch Q1 is also constant at ground level GND, so the first switch Q1 is turned off. When the output signal of processor 102 is a non-constant signal, capacitor C1 can output a pulse signal from the second electrode, and the frequency of the pulse signal is the same as the frequency of the output signal. Since the emitter of the first switch Q1 is grounded, when the pulse signal makes the level on the base of the first switch Q1 higher than the turn-on level of the first switch Q1, the first switch Q1 is turned on. When the pulse signal makes the level on the base of the first switch Q1 lower than the turn-on level of the first switch Q1, the first switch Q1 is turned off. Thus, the first switch Q1 can be turned on intermittently.

[0057] In some embodiments, refer to Figure 3The signal processing module 202 also includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a second switch Q2, a diode D1, and a first capacitor C2. The first end of the first resistor R1 is connected to the output terminal of the DC blocking module 201. The second end of the first resistor R1 is connected to the cathode of diode D1, the first end of the second resistor R2, and the base of the first switching transistor Q1. The anode of diode D1, the second end of the second resistor R2, and the emitter of the first switching transistor Q1 are all grounded. The first end of the third resistor R3 is connected to the power supply level VD. The second end of the third resistor R3 is connected to the first end of the fourth resistor R4 and the collector of the first switching transistor Q1. The second end of the fourth resistor R4 is connected to the base of the second switching transistor Q2. The emitter of the second switching transistor Q2 is connected to the power supply level VD. The collector of the second switching transistor Q2 is connected to the first end of the fifth resistor R5 and the first end of the sixth resistor R6. The second end of the fifth resistor R5 is grounded. The first electrode of the first capacitor C2 is connected to the second end of the sixth resistor R6. The second electrode of the first capacitor C2 is grounded.

[0058] In the signal processing module 202, when the first switch Q1 is intermittently turned on, the second switch Q2 is intermittently turned on, and the first capacitor C2 is in a dynamically stable state. Specifically, when the second switch Q2 is turned on, the voltage division of the power supply level VD by the sixth resistor R6 can charge the first capacitor C2. When the second switch Q2 is turned off, the first capacitor C2 discharges. When the second switch Q2 is intermittently turned on at a fixed frequency, the first capacitor C2 can be charged and discharged at a fixed frequency, and the level on its first electrode is in a dynamically stable state.

[0059] In some specific examples, when the voltage level on the first electrode of the first capacitor C2 is in a dynamically stable state, the capacitance value of the first capacitor C2, the resistance value of the sixth resistor R6, and the switching frequency of the first switching transistor Q1 should satisfy the following relationship (1):

[0060] 1 / (2π*r*c)≤f / k (1)

[0061] Where r is the resistance value of the sixth resistor R6; c is the capacitance value of the first capacitor C2; f is the switching frequency of the first switch Q1, which can also be approximately equal to the frequency of the output signal of the processor 102 when it is in normal state; k is a constant whose value ranges from 3 to 10.

[0062] In a specific example, k is 5, then the capacitance value of the first capacitor C2 and the resistance value of the sixth resistor R6 should satisfy the following relationship (2):

[0063] r*c≥5 / (2π*f ) (2)

[0064] In some specific examples, the first switching transistor Q1 is an N-type transistor, the second switching transistor Q2 is a P-type transistor, and the resistance values ​​of the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6 are all the same.

[0065] In a specific example, Figure 3 The power supply level VD can be 15V, and the resistance values ​​of the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6 can all be 10k ohms. The capacitance value of the first capacitor C2 can be 100nF.

[0066] It should be noted that the specific parameters in the above examples are just examples. Under the condition that the above relation (1) is satisfied, this disclosure does not impose specific restrictions on the parameters of each element.

[0067] In some embodiments, refer to Figure 3 The signal processing module 202 also includes a comparator IC, a seventh resistor R7, an eighth resistor R8, and a second capacitor C3; the positive input terminal of the comparator IC is connected to the first electrode of the first capacitor C2; the first terminals of the seventh resistor R7, the eighth resistor R8, and the second capacitor C3 are all connected to the negative input terminal of the comparator IC; the second terminal of the eighth resistor R8 and the second electrode of the second capacitor C3 are both grounded; the second terminal of the seventh resistor R7 is connected to the power supply level VD.

[0068] In the signal processing module 202, the negative input terminal of the comparator IC receives a threshold level. When the first capacitor C2 is in a dynamically stable state (i.e., the first capacitor C2 is charged to a predetermined voltage), the level at the positive input terminal of the comparator IC is greater than the threshold level, and the comparator IC outputs a third level. When the first capacitor C2 is in a non-dynamically stable state (i.e., the first capacitor C2 is not charged to the predetermined voltage), the level at the positive input terminal of the comparator IC is less than the threshold level, and the comparator IC outputs a fourth level. Specifically, the seventh resistor R7 and the eighth resistor R8 are connected in series between the power supply level VD and the ground level GND. The threshold level received by the negative input terminal of the comparator IC is the level at the connection point of the seventh resistor R7 and the eighth resistor R8. By setting the relative values ​​of the seventh resistor R7 and the eighth resistor R8, the value of the threshold level can be set. When the first capacitor C2 is in a dynamically stable state, the level at the positive input terminal of the comparator IC is greater than the threshold level, and the comparator IC outputs a third level. When the first capacitor C2 is in a non-dynamically stable state, the level at the positive input terminal of the comparator IC is less than the threshold level, and the comparator IC outputs a fourth level. Here, the third level can be a high level, and the fourth level can be a low level.

[0069] In some embodiments, refer to Figure 3The signal processing module 202 also includes a ninth resistor R9 and a light-emitting diode D2; the first end of the ninth resistor R9 is connected to the power supply level VD, and the second end of the ninth resistor R9 is connected to the anode of the light-emitting diode D2; the cathode of the light-emitting diode D2 is connected to the output terminal of the comparator IC; wherein, when the comparator IC outputs the fourth level, the light-emitting diode D2 is turned on and emits light.

[0070] In some embodiments, refer to Figure 3 The signal processing module 202 also includes a tenth resistor R10 and a third capacitor C4; the first end of the tenth resistor R10 is connected to the power supply level VD; the second end of the tenth resistor R10 is connected to the first electrode of the third capacitor C4, and both are connected to the output terminal of the signal processing module 202; the second electrode of the third capacitor C4 is grounded.

[0071] For the signal processing module 202, when the comparator IC outputs the third level, the first driving signal output is the first level; when the comparator IC outputs the fourth level, the first driving signal output is the second level.

[0072] In this embodiment, when the processor 102 is in a normal state, the output signal of the processor 102 is a non-constant signal, the first switch Q1 is intermittently turned on, the first capacitor C2 is in a dynamically stable state, the level of the positive input terminal of the comparator IC is greater than the threshold level, the comparator IC outputs a third level, the light-emitting diode D2 is not turned on, and the first driving signal output by the signal processing module 202 is a first level; when the processor 102 is in a fault state, the output signal of the processor 102 is a constant signal, the first switch Q1 is turned off, the level of the positive input terminal of the comparator IC is less than the threshold level, the comparator IC outputs a fourth level, the light-emitting diode D2 is turned on, and the first driving signal output is a second level. Therefore, when the processor 102 malfunctions, the LED of the fault detection device 101 is turned on and illuminates to indicate the fault state of the processor 102. The fault detection device 101 can also output a first drive signal with a second level to trigger the bypass module 103 to switch to bypass output mode. In other words, the fault detection device can detect faults in the processor 102 and can switch the bypass module 103 to bypass output mode when the processor 102 is in a fault state. This can improve the reliability of the UPS system's output switching and effectively avoid the situation where the DSP malfunction prevents the system from switching to bypass output and thus causes a power outage.

[0073] Based on a concept similar to the fault detection device in the above embodiments, this disclosure also provides a UPS system, referring to... Figure 1The UPS system includes: a processor 102; a fault detection device 101 as described in any of the above embodiments; the input terminal of the fault detection device 101 is connected to the first output terminal of the processor 102 and is configured to: perform fault detection on the processor 102 based on the output signal of the processor 102 and output a first drive signal; a main power module 104; the control terminal of the main power module 104 is connected to the second output terminal of the processor 102, and the input terminal of the main power module 104 receives a mains power signal; a bypass module 103; the control terminal of the bypass module 103 is connected to the third output terminal of the processor 102 and to the output terminal of the fault detection device 101; the first input terminal of the bypass module 103 is connected to the output terminal of the main power module 104, and the second input terminal of the bypass module 103 receives a bypass power signal.

[0074] In some specific examples, the main power module 104 may include a rectifier 1041, an inverter 1042, and a DC / DC converter 1043. When the mains power signal is normal and the processor 102 is in normal operation, under the control of the processor 102, the rectifier 1041 and the inverter 1042 can rectify and invert the mains power signal. Furthermore, the mains power signal rectified by the rectifier 1041 can also be output to the DC / DC converter 1043, which can convert the received DC signal into a DC signal matching the charging current of the battery 105, and can charge the battery 105. When the mains power signal is off and the processor 102 is in normal operation, under the control of the processor 102, the battery 105 can output a battery signal, and the DC / DC converter 1043, the rectifier 1041, and the inverter 1042 can ultimately convert the battery signal into an AC signal.

[0075] In some embodiments, refer to Figure 1 The processor 102 is also configured to: acquire the operating parameters of the UPS system, perform detection based on the operating parameters, and output a second drive signal; when the operating parameters indicate that the UPS system is in a normal state, the second drive signal is at the fifth level, and when the operating parameters indicate that the UPS system is in an abnormal state, the second drive signal is at the sixth level; the sixth level is used to trigger the bypass module 103 to switch to the bypass output state.

[0076] In some embodiments, in conjunction with reference Figure 1 and Figure 4The bypass module 103 may include a logic circuit 1031 and a switching circuit 1032. The first input terminal of the logic circuit 1031 is connected to the output terminal of the fault detection device 101, the second input terminal of the logic circuit 1031 is connected to the third output terminal of the processor 102, and the output terminal of the logic circuit 1031 is connected to the control terminal of the switching circuit 1032. The first input terminal of the switching circuit 1032 is connected to the bypass power signal. The second input terminal of the switching circuit 1032 is connected to the output terminal of the main power module 104. The logic circuit 1031 is configured to output a control signal. When the first driving signal is at the second level or the second driving signal is at the sixth level, the control signal is at the seventh level. The seventh level is used to control the switching circuit 1032 to output the bypass power signal. When the first driving signal is at the first level and the second driving signal is at the fifth level, the control signal is at the eighth level. The eighth level is used to control the switching circuit 1032 to output the output signal of the main power module 104.

[0077] In some specific examples, logic circuit 1031 may include suitable logic gates such that when the first drive signal is at a second level or the second drive signal is at a sixth level, i.e., when processor 102 detects that the UPS system is in an abnormal state or fault detection device 101 detects that processor 102 is in a fault state, a control signal with a seventh level can be generated. In this case, bypass module 103 switches to bypass output state, and switching circuit 1032 can output the received bypass power signal to power the load of the UPS system. When the first drive signal is at a first level and the second drive signal is at a fifth level, i.e., when the entire UPS system is in a normal state, logic circuit 1031 can generate a control signal with an eighth level. In this case, bypass module 103 maintains normal output state, and switching circuit 1032 can output the output signal of main power module 104 to power the load of the UPS system.

[0078] In a specific example, taking the first level as low, the second level as high, the fifth level as low, and the sixth level as high, the logic circuit 1031 can include an OR gate, so the seventh level can be high and the eighth level can be low.

[0079] In the UPS system disclosed herein, when the mains power signal is normal and the UPS system is operating normally, the UPS system can output a rectified and inverted mains power signal, and can charge the battery through the mains power signal. When the mains power signal fails and the UPS system is operating normally, the UPS system can output an inverted battery signal. When other hardware components in the UPS system malfunction but the DSP is in normal condition, under the control of the second drive signal output by the DSP, the UPS system can switch to bypass output mode and output a bypass power signal. When the DSP fails, under the control of the first drive signal output by the fault detection device, the UPS system can also switch to bypass output mode and output a bypass power signal. Therefore, the UPS system can maintain the output of electrical signals under various conditions, effectively preventing power outages and exhibiting high reliability.

[0080] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0081] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A fault detection device, characterized in that, The input terminal of the fault detection device is connected to the first output terminal of the processor of the UPS system; the output terminal of the fault detection device is connected to the control terminal of the bypass module of the UPS system; the fault detection device is configured to output a first drive signal based on the output signal output by the first output terminal of the processor. Wherein, when the processor is in normal state, the output signal is a non-constant signal, and the first drive signal is a first level; when the processor is in fault state, the output signal is a constant signal, and the first drive signal is a second level; the second level is used to trigger the bypass module to switch to bypass output state.

2. The fault detection device according to claim 1, characterized in that, The fault detection device includes a DC blocking module and a signal processing module; the signal processing module includes a first switching transistor; wherein... The input terminal of the DC blocking module is connected to the first output terminal of the processor and is configured to: turn off the first switch when the output signal is the constant signal; and turn on the first switch intermittently when the output signal is the non-constant signal. The input terminal of the signal processing module is connected to the output terminal of the DC blocking module and is configured to output the first level when the first switch is intermittently turned on, and output the second level when the first switch is turned off.

3. The fault detection device according to claim 2, characterized in that, The signal processing module further includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a second switching transistor, a diode, and a first capacitor; The first end of the first resistor is connected to the output end of the DC blocking module, and the second end of the first resistor is connected to the cathode of the diode, the first end of the second resistor, and the base of the first switching transistor. The anode of the diode, the second end of the second resistor, and the emitter of the first switching transistor are all grounded. The first end of the third resistor is connected to the power supply level, the second end of the third resistor is connected to the first end of the fourth resistor and the collector of the first switching transistor, the second end of the fourth resistor is connected to the base of the second switching transistor, the emitter of the second switching transistor is connected to the power supply level, the collector of the second switching transistor is connected to the first end of the fifth resistor and the first end of the sixth resistor, and the second end of the fifth resistor is grounded. The first electrode of the first capacitor is connected to the second terminal of the sixth resistor, and the second electrode of the first capacitor is grounded. When the first switch is intermittently turned on, the second switch is intermittently turned on, and the first capacitor is in a dynamic stable state.

4. The fault detection device according to claim 3, characterized in that, The signal processing module also includes a comparator, a seventh resistor, an eighth resistor, and a second capacitor; The positive input terminal of the comparator is connected to the first electrode of the first capacitor; The first terminal of the seventh resistor, the first terminal of the eighth resistor, and the first electrode of the second capacitor are all connected to the negative input terminal of the comparator. The second terminal of the eighth resistor and the second electrode of the second capacitor are both grounded; The second terminal of the seventh resistor is connected to the power supply level; The comparator's negative input receives a threshold level; when the first capacitor is in the dynamic stable state, the level at the comparator's positive input is greater than the threshold level, and the comparator outputs a third level; when the first capacitor is in the non-dynamic stable state, the level at the comparator's positive input is less than the threshold level, and the comparator outputs a fourth level.

5. The fault detection device according to claim 4, characterized in that, The signal processing module also includes a ninth resistor and a light-emitting diode; The first end of the ninth resistor is connected to the power supply level, and the second end of the ninth resistor is connected to the anode of the light-emitting diode. The cathode of the light-emitting diode is connected to the output terminal of the comparator; Specifically, when the comparator outputs the fourth level, the light-emitting diode is turned on.

6. The fault detection device according to claim 4, characterized in that, The signal processing module also includes a tenth resistor and a third capacitor; The first end of the tenth resistor is connected to the power supply level; the second end of the tenth resistor is connected to the first electrode of the third capacitor, and both are connected to the output terminal of the signal processing module; the second electrode of the third capacitor is grounded. Specifically, when the comparator outputs the third level, the first driving signal is the first level; when the comparator outputs the fourth level, the first driving signal is the second level.

7. The fault detection device according to any one of claims 3-6, characterized in that, The first switching transistor is an N-type transistor, and the second switching transistor is a P-type transistor; the resistance values ​​of the second resistor, the third resistor, the fourth resistor, the fifth resistor, and the sixth resistor are all the same.

8. A UPS system, characterized in that, include: processor; The fault detection device according to any one of claims 1 to 7; The input terminal of the fault detection device is connected to the first output terminal of the processor and is configured to: detect faults in the processor based on the output signal of the processor and output the first drive signal; Main power module; The control terminal of the main power module is connected to the second output terminal of the processor, and the input terminal of the main power module receives the mains power signal. Bypass module; The control terminal of the bypass module is connected to the third output terminal of the processor and to the output terminal of the fault detection device; the first input terminal of the bypass module is connected to the output terminal of the main power module, and the second input terminal of the bypass module receives the bypass power signal.

9. The UPS system according to claim 8, characterized in that, The processor is also configured to: The system acquires the operating parameters of the UPS system, performs detection based on the operating parameters, and outputs a second drive signal; when the operating parameters indicate that the UPS system is in a normal state, the second drive signal is at the fifth level, and when the operating parameters indicate that the UPS system is in an abnormal state, the second drive signal is at the sixth level. The sixth level is used to trigger the bypass module to switch to the bypass output state.

10. The UPS system according to claim 9, characterized in that, The bypass module includes logic circuits and switching circuits; The first input terminal of the logic circuit is connected to the output terminal of the fault detection device; the second input terminal of the logic circuit is connected to the third output terminal of the processor; the output terminal of the logic circuit is connected to the control terminal of the switching circuit; the first input terminal of the switching circuit is connected to the bypass power signal; the second input terminal of the switching circuit is connected to the output terminal of the main power module; the logic circuit is configured to output a control signal. Wherein, when the first driving signal is the second level or the second driving signal is the sixth level, the control signal is the seventh level; the seventh level is used to control the switching circuit to output the bypass power signal; when the first driving signal is the first level and the second driving signal is the fifth level, the control signal is the eighth level; the eighth level is used to control the switching circuit to output the output signal of the main power module.

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