Dual-input power priority control circuit and method and electronic equipment

Abstract

The invention relates to the technical field of power management, and discloses a dual-input power priority control circuit and method and electronic equipment. A first input end of the circuit is used for accessing a standby power supply, and a second input end is used for accessing a main power supply. The first input end is electrically connected with the output end through the first switch channel, and the second input end is electrically connected with the output end through the second switch channel; the voltage detection circuit is used for detecting the voltage state of the second input end and controlling the conduction state of the first switch channel and the second switch channel according to a detection result, and when effective voltage exists at the second input end, the second switch channel is controlled to be conducted and the first switch channel is switched off; the power supply priority of the second input end is higher than that of the first input end; the core technical problem of a double-input power supply system is solved through an innovative double PMOS back-to-back connection structure, and the double-input power supply system has the advantages of being low in power consumption, high in reliability, obvious in cost advantage and the like, is particularly suitable for being applied to outdoor electronic equipment powered by new energy, and has wide market prospects.

Description

Technical Field

[0001] This invention relates to the field of power management technology, and more particularly to dual-input power priority control circuits, methods, and electronic devices. Background Technology

[0002] With the global trend towards clean energy transition, solar energy is increasingly being used as a green energy source for powering outdoor electronic devices. This is especially true for outdoor equipment deployed in remote areas (such as security cameras and environmental monitoring devices), where grid coverage is limited, necessitating solar charging to extend their battery life. Simultaneously, backup charging ports (such as USB adapters) need to be available to cope with solar power outages caused by prolonged periods of cloudy or rainy weather.

[0003] To achieve energy supply redundancy, such devices typically employ a dual-input charging architecture (e.g., solar power + USB adapter). However, the coordinated operation of dual-input power supplies presents core technical challenges, including power conflict control, complexity of priority management, and reliability of detection and control. Specifically:

[0004] 1. For power supply conflict control, when two inputs exist at the same time, it is necessary to ensure that only one power supply supplies power to the load to avoid problems such as voltage mismatch and uneven current distribution caused by multiple power supplies in parallel, and to prevent system damage.

[0005] 2. To address the complexity of priority management, dynamic priority control needs to be implemented. The main power source (such as solar power) should have the highest power supply priority, and the backup power source (such as USB) should only be activated when the main power source fails, and the switching process should be smooth and reliable.

[0006] 3. For reliable detection and control, it is necessary to accurately detect the effectiveness of the main power supply and automatically control the power switching based on the detection results to avoid power outages or switching failures caused by misjudgments.

[0007] However, existing technical solutions typically employ simple diode isolation or basic switch control, but suffer from technical drawbacks such as complex control logic, insufficient switching reliability, and inability to effectively avoid power supply conflicts.

[0008] Therefore, a technical solution is needed that can solve the unidirectional isolation problem in scenarios where the polarity of dual input voltages is uncontrollable, while avoiding the heat generation defects of diode solutions. Summary of the Invention

[0009] The purpose of this invention is to provide a dual-input power priority control circuit, method, and electronic device to solve or at least partially solve the technical problems existing in the prior art.

[0010] To achieve this objective, the present invention adopts the following technical solution:

[0011] In a first aspect, the present invention provides a dual-input power priority control circuit, which includes a first input terminal, a second input terminal, an output terminal and a voltage detection circuit, wherein the first input terminal is used to connect to a backup power supply and the second input terminal is used to connect to a main power supply.

[0012] The first input terminal is electrically connected to the output terminal through a first switching channel, and the second input terminal is electrically connected to the output terminal through a second switching channel;

[0013] The voltage detection circuit is used to detect the voltage state of the second input terminal and control the conduction state of the first and second switching channels according to the detection result. When there is a valid voltage at the second input terminal, the second switching channel is turned on and the first switching channel is turned off, so that the second input terminal has a higher power supply priority than the first input terminal.

[0014] Preferably, the first switching channel includes at least two MOSFETs connected in series, and the parasitic diodes of adjacent MOSFETs are connected in reverse series to form a bidirectional blocking structure.

[0015] Specifically, the first switching channel includes a first MOSFET Q1 and a second MOSFET Q2. The source of the first MOSFET Q1 is electrically connected to the source of the second MOSFET Q2, and the gate of the first MOSFET Q1 is electrically connected to the gate of the second MOSFET Q2. The drain of the first MOSFET Q1 is electrically connected to the first input terminal, and the drain of the second MOSFET Q2 is electrically connected to the output terminal.

[0016] Specifically, the second switching channel includes a third MOSFET Q3, the drain of which is electrically connected to the second input terminal and the source of which is electrically connected to the output terminal.

[0017] Preferably, the first MOSFET Q1, the second MOSFET Q2, and the third MOSFET Q3 are all PMOS transistors.

[0018] Preferably, the voltage detection circuit includes a first driving circuit and a second driving circuit, wherein the first driving circuit is used to control the turn-on and turn-off of the first MOSFET Q1 and the second MOSFET Q2, and the second driving circuit is used to control the turn-on and turn-off of the third MOSFET Q3.

[0019] Specifically, the first driving circuit includes a first transistor Q5 and a second transistor Q4. The base of the first transistor Q5 is electrically connected to the connection point between the first input terminal and the drain of the first MOSFET Q1 through a first base resistor R3, and is grounded through a second base resistor R4. The collector is electrically connected to the gate of the first MOSFET Q1 and the gate of the second MOSFET Q2 through a first collector resistor R2, and the emitter is grounded.

[0020] The base of the second transistor Q4 is electrically connected to the connection point between the second input terminal and the drain of the third MOSFET Q3 through the third base resistor R5, and grounded through the fourth base resistor R6. The collector is electrically connected to the connection point between the base of the first transistor Q5 and the first base resistor R3, and the emitter is grounded.

[0021] Specifically, the second driving circuit includes a third transistor Q6. The base of the third transistor Q6 is electrically connected to the connection point between the second input terminal and the drain of the third MOS transistor Q3 through a fifth base resistor R9, and is grounded through a sixth base resistor R10. The collector is electrically connected to the gate of the third MOS transistor Q3 through a seventh base resistor R8, and the emitter is grounded.

[0022] Furthermore, the first driving circuit also includes a first Zener diode Z1 and a first gate pull-up resistor R1. The cathode of the first Zener diode Z1 is electrically connected to the connection point between the source of the first MOSFET Q1 and the source of the second MOSFET Q2, and the anode is electrically connected to the connection point between the gate of the first MOSFET Q1 and the gate of the second MOSFET Q2.

[0023] One end of the first gate pull-up resistor R1 is electrically connected to the connection point between the gate of the first MOSFET Q1 and the gate of the second MOSFET Q2, and the other end is electrically connected to the connection point between the source of the first MOSFET Q1 and the source of the second MOSFET Q2.

[0024] Furthermore, the second driving circuit also includes a second Zener diode Z2, a second gate pull-up resistor R7, and a filter capacitor C1. The cathode of the second Zener diode Z2 is electrically connected to the source of the third MOSFET Q3, and the anode is electrically connected to the gate of the third MOSFET Q3.

[0025] One end of the second gate pull-up resistor R7 is electrically connected to the connection point between the gate of the third MOS transistor Q3 and the seventh base resistor R8, and the other end is electrically connected to the connection point between the source of the third MOS transistor Q3 and the cathode of the second Zener diode Z2.

[0026] One end of the filter capacitor C1 is electrically connected to the base of the third transistor Q6, and the other end is grounded.

[0027] Preferably, the input voltage range of the first input terminal and the second input terminal is 5V to 15V.

[0028] Secondly, the present invention provides a dual-input power supply priority control method, applied to the dual-input power supply priority control circuit described above, comprising the following steps:

[0029] S1. Detect the voltage at the second input terminal;

[0030] S2. When the voltage at the second input terminal is higher than the preset threshold, the first switch channel is turned off and the second switch channel is turned on.

[0031] S3. When the voltage at the second input terminal is lower than the preset threshold, control the first switch channel to turn on and the second switch channel to turn off.

[0032] Thirdly, the present invention provides an electronic device including a load circuit and a dual-input power priority control circuit as described above, wherein the load circuit is electrically connected to the output terminal of the dual-input power priority control circuit.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] 1. The voltage detection circuit automatically identifies the status of the main power supply, realizing intelligent switching between main power supply priority and backup power supply emergency, eliminating the need for manual intervention required in traditional systems and improving the automation level of the system;

[0035] 2. When the main power supply is available, the backup power supply channel is forcibly shut down. When the main power supply fails, the main power supply channel is shut down and the backup power supply is used to supply power, ensuring that only one power supply supplies power to the load at any time, effectively avoiding the conflict problem caused by multiple power supplies in parallel.

[0036] 3. The voltage detection circuit can accurately determine the effectiveness of the main power supply. The control logic is simple and reliable, which reduces the risk of misjudgment and switching failure and improves the stability of the system.

[0037] 4. Simplified circuit structure: The integrated voltage detection and switching control design simplifies the overall circuit structure of the dual-input power supply system, reducing system complexity and cost.

[0038] The present invention has other features and advantages, which will be apparent from or will be set forth in detail in the accompanying drawings and the following detailed description, which together serve to explain the particular principles of the invention. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a structural block diagram of the electronic device provided in an embodiment of the present invention.

[0041] Figure 2 This is a circuit diagram of the dual-input power priority control circuit provided in an embodiment of the present invention.

[0042] Figure 3 This is a flowchart of the dual-input power priority control method provided in an embodiment of the present invention. Detailed Implementation

[0043] To illustrate the possible application scenarios, technical principles, implementable specific solutions, and achievable objectives and effects of this application in detail, the following description, in conjunction with the listed specific embodiments and accompanying drawings, provides a detailed explanation. The embodiments described herein are merely illustrative of the technical solutions of this application and are therefore intended to limit the scope of protection of this application.

[0044] Example 1

[0045] Please see Figure 1 The electronic device 1000 of this embodiment is particularly suitable for application scenarios such as outdoor-deployed IoT devices, security monitoring equipment, and environmental monitoring stations. The electronic device 1000 includes a load circuit 60 and a dual-input power priority control circuit 100. The load circuit 60 is electrically connected to the output terminal 30 of the dual-input power priority control circuit 100 and obtains operating power from the output terminal 30. The load circuit 60 here can be, but is not limited to, the electronic device 1000, and is particularly suitable for application scenarios such as outdoor-deployed IoT devices, security monitoring equipment, and environmental monitoring stations.

[0046] The electronic device 1000 includes a load circuit 60 and a dual-input power priority control circuit 100 as described in Embodiment 1. The load circuit 60 is electrically connected to the output terminal 30 of the dual-input power priority control circuit 100 and obtains operating power from the output terminal 30. The load circuit 60 here includes, but is not limited to, external devices such as IoT sensor modules, wireless communication modules, microcontroller systems, security cameras, and environmental monitoring sensor arrays.

[0047] Please see Figure 1 and Figure 2 The dual-input power priority control circuit 100 of this embodiment includes a first input terminal 10, a second input terminal 20, an output terminal 30, and a voltage detection circuit. The first input terminal 10 is used to connect to a backup power supply 80, such as a USB adapter, and the second input terminal 20 is used to connect to a main power supply 70, such as a solar panel.

[0048] The first input terminal 10 is electrically connected to the output terminal 30 via the first switching channel 40, and the second input terminal 20 is electrically connected to the output terminal 30 via the second switching channel 50. A voltage detection circuit is used to detect the voltage state of the second input terminal 20 and, based on the detection result, controls the conduction state of the first switching channel 40 and the second switching channel 50. When a valid voltage exists at the second input terminal 20, the second switching channel 50 is turned on and the first switching channel 40 is turned off, giving the second input terminal 20 a higher power supply priority than the first input terminal 10. Here, the valid voltage is a voltage sufficient to generate a valid detection signal for the voltage detection circuit.

[0049] Understandably, the main power supply 70 serves as the primary power source, while the backup power supply 80 serves as the emergency power source. When the main power supply 70 is supplying power normally, the second switch channel 50 is turned on and the first switch channel 40 is turned off, at which point only the main power supply 70 supplies power to the output terminal 30. When the main power supply 70 is abnormal, unable to supply power, or has an excessively low supply voltage, the second switch channel 50 is turned off and the first switch channel 40 is turned on, at which point only the backup power supply 80 supplies power to the output terminal 30, thus achieving priority power supply from the main power supply 70 and emergency power supply from the backup power supply 80.

[0050] Preferably, the first switching channel 40 includes at least two MOS transistors connected in series, and the parasitic diodes of adjacent MOS transistors are connected in reverse series to form a bidirectional blocking structure.

[0051] Specifically, the first switching channel 40 includes a first MOSFET Q1 and a second MOSFET Q2, both of which are PMOS transistors. The source of the first MOSFET Q1 and the source of the second MOSFET Q2 are electrically connected to form a common-source junction, and the gate of the first MOSFET Q1 is electrically connected to the gate of the second MOSFET Q2, which can synchronously control the conduction and turn-off of the first MOSFET Q1 and the second MOSFET Q2. The drain of the first MOSFET Q1 is electrically connected to the first input terminal 10, and the drain of the second MOSFET Q2 is electrically connected to the output terminal 30.

[0052] Understandably, in this back-to-back PMOS connection formed by the first MOSFET Q1 and the second MOSFET Q2, the parasitic body diodes of the PMOS transistors point from the source to the drain. Therefore, the cathode of the body diode of the first MOSFET Q1 faces the first input terminal 10, and the cathode of the body diode of the second MOSFET Q2 faces the output terminal 30, with the two body diodes connected in reverse series. When the voltage at the first input terminal 10 is higher than the voltage at the output terminal 30, the body diode of the second MOSFET Q2 is reverse-biased, blocking the current; when the voltage at the output terminal 30 is higher than the voltage at the first input terminal 10, the body diode of the first MOSFET Q1 is reverse-biased, blocking the current. This achieves a completely bidirectional blocking function.

[0053] The second switching channel 50 includes a third MOSFET Q3, which is also a PMOS transistor. The drain of the third MOSFET Q3 is connected to the second input terminal 20, and the source is connected to the output terminal 30. Since the second input terminal 20 (solar energy) has the highest priority and the solar energy does not supply power in reverse, the second switching channel 50 only requires a single PMOS transistor.

[0054] It should be noted that the first MOSFET Q1, the second MOSFET Q2, and the third MOSFET Q3 are model LT1541 SI, but of course, models of the same or similar specifications can also be selected.

[0055] The voltage detection circuit includes a first driving circuit and a second driving circuit. The first driving circuit is used to control the conduction and turn-off of the first MOSFET Q1 and the second MOSFET Q2, and the second driving circuit is used to control the conduction and turn-off of the third MOSFET Q3.

[0056] Preferably, the voltage detection circuit includes a first driving circuit and a second driving circuit, wherein the first driving circuit is used to control the turn-on and turn-off of the first MOSFET Q1 and the second MOSFET Q2, and the second driving circuit is used to control the turn-on and turn-off of the third MOSFET Q3.

[0057] Specifically, the first driving circuit includes a first transistor Q5 and a second transistor Q4. The base of the first transistor Q5 is electrically connected to the connection point between the first input terminal 10 and the drain of the first MOSFET Q1 through a first base resistor R3 (typically 10kΩ), thereby detecting the voltage at the first input terminal 10. The base of the first transistor Q5 is also grounded to GND through a second base resistor R4 (typically 4.7kΩ), forming a voltage divider network. The collector of the first transistor Q5 is electrically connected to the gate of the first MOSFET Q1 and the gate of the second MOSFET Q2 through a first collector resistor R2 (typically 10kΩ), and the emitter is grounded to GND.

[0058] The base of the second transistor Q4 is electrically connected to the junction between the second input terminal 20 and the drain of the third MOSFET Q3 through a third base resistor R5 (typically 10kΩ), enabling the detection of the voltage at the second input terminal 20. The base of the second transistor Q4 is also grounded to GND through a fourth base resistor R6 (typically 4.7kΩ). The collector of the second transistor Q4 is electrically connected to the junction between the base of the first transistor Q5 and the first base resistor R3, and its emitter is grounded to GND.

[0059] It is understandable that this connection method of the first driving circuit implements priority control logic. Specifically, when there is voltage at the second input terminal 20, the second transistor Q4 is turned on, pulling the base of the first transistor Q5 low, causing the first transistor Q5 to be turned off. Then, the gates of the first MOSFET Q1 and the second MOSFET Q2 are pulled high through the first gate pull-up resistor R1, the first MOSFET Q1 and the second MOSFET Q2 are turned off, and the first switching channel 40 is disconnected.

[0060] The second driving circuit includes a third transistor Q6. The base of the third transistor Q6 is electrically connected to the connection point between the second input terminal 20 and the drain of the third MOSFET Q3 through a fifth base resistor R9 (typical value 10kΩ), and is grounded to GND through a sixth base resistor R10 (typical value 4.7kΩ). The collector is electrically connected to the gate of the third MOSFET Q3 through a seventh base resistor R8 (typical value 10kΩ), and the emitter is grounded to GND.

[0061] It should be noted that the second transistor Q4, the first transistor Q5, and the third transistor Q6 are model number 5551, but of course, the same or similar models can also be selected.

[0062] Furthermore, to improve the reliability and stability of the circuit, the first driving circuit also includes a first Zener diode Z1 and a first gate pull-up resistor R1. The cathode of the first Zener diode Z1 (typical value 12V) is electrically connected to the connection point between the source of the first MOSFET Q1 and the source of the second MOSFET Q2, and the anode is electrically connected to the connection point between the gate of the first MOSFET Q1 and the gate of the second MOSFET Q2, in order to limit the gate-source voltage and protect the MOSFETs.

[0063] One end of the first gate pull-up resistor R1 (typical value 100kΩ) is electrically connected to the connection point between the gate of the first MOSFET Q1 and the gate of the second MOSFET Q2, and the other end is electrically connected to the connection point between the source of the first MOSFET Q1 and the source of the second MOSFET Q2, so as to ensure that the MOSFET is reliably turned off when there is no drive signal.

[0064] Furthermore, the second driving circuit also includes a second Zener diode Z2, a second gate pull-up resistor R7, and a filter capacitor C1. The cathode of the second Zener diode Z2 (typically 12V) is electrically connected to the source of the third MOSFET Q3, and the anode is electrically connected to the gate of the third MOSFET Q3. The connection method of the second Zener diode Z2 is similar to that of the first Zener diode Z1, and it is used to limit the gate-source voltage and protect the third MOSFET Q3.

[0065] One end of the second gate pull-up resistor R7 (typical value 100kΩ) is electrically connected to the connection point between the gate of the third MOSFET Q3 and the seventh base resistor R8, and the other end is electrically connected to the connection point between the source of the third MOSFET Q3 and the cathode of the second Zener diode Z2. It is used to ensure that the third MOSFET Q3 can be reliably turned off when there is no drive.

[0066] The filter capacitor C1 (typical value 0.1μF) is electrically connected at one end to the base of the third transistor Q6 and grounded to GND at the other end. The filter capacitor C1 is used to filter out voltage fluctuations at the second input terminal 20 (such as solar energy) to avoid affecting the normal operation of the load circuit 60 due to voltage fluctuations.

[0067] Preferably, the input voltage range of the first input terminal 10 and the second input terminal 20 is 5V to 15V, so as to meet the needs of various conventional main power supplies 70 and backup power supplies 80 in combination.

[0068] The following describes the working process of this embodiment using an example where the second input terminal 20 is connected to solar power and the first input terminal 10 is connected to USB power:

[0069] 1. Sunny Day Scenario (Solar Power Output): The voltage at the second input terminal 20 is divided by the third base resistor R5 and the fourth base resistor R6, turning on the second transistor Q4. The collector of the second transistor Q4 pulls down the base of the first transistor Q5, turning off the first transistor Q5. The gates of the first MOSFET Q1 and the second MOSFET Q2 are pulled up to their source potentials by the first gate pull-up resistor R1, turning off the first MOSFET Q1 and the second MOSFET Q2, and completely disconnecting the first switching channel 40. Simultaneously, the voltage at the second input terminal 20 is divided by the fifth base resistor R9 and the sixth base resistor R10, turning on the third transistor Q6. The collector of the third transistor Q6 pulls down the gate of the third MOSFET Q3, turning on the third MOSFET Q3, and the solar energy supplies power to the load through the third MOSFET Q3.

[0070] 2. Cloudy Day Scenario (No Solar Output): There is no voltage at the second input terminal 20, and both the second transistor Q4 and the third transistor Q6 are cut off. The gates of the first MOSFET Q1 and the second MOSFET Q2 are pulled low by the first transistor Q5 through the first collector resistor R2 (the first transistor Q5 is turned on because there is voltage at the first input terminal 10). The first MOSFET Q1 and the second MOSFET Q2 are turned on, and the USB supplies power to the load through the first switching channel 40. The gate of the third MOSFET Q3 is pulled high through R7, and the third MOSFET Q3 is turned off, isolating the solar energy channel.

[0071] Example 2

[0072] Please see Figures 1-3This embodiment provides a dual-input power supply priority control method, applied to the dual-input power supply priority control circuit 100 described in Embodiment 1, including the following steps:

[0073] S1. Real-time detection of the voltage at the second input terminal 20. Specifically, this is achieved by continuously monitoring the voltage state at the second input terminal 20 through a base voltage divider network of the second transistor Q4 and the third transistor Q6. The detected voltage is compared with a preset threshold. The preset threshold is determined by the base resistor voltage division ratio, with a typical value of 2.5V (corresponding to approximately 0.7V of base-emitter turn-on voltage).

[0074] S2. When the voltage at the second input terminal 20 is higher than a preset threshold, the first switch channel 40 is turned off and the second switch channel 50 is turned on. Specifically, when the voltage at the second input terminal 20 is higher than the preset threshold, a first control signal is generated. At this time, the second transistor Q4 is turned on, pulling down the base of the first transistor Q5, causing the first transistor Q5 to be turned off, and the first MOSFET Q1 and the second MOSFET Q2 are turned off; at the same time, the third transistor Q6 is turned on, pulling down the gate of the third MOSFET Q3, causing the third MOSFET Q3 to be turned on, thus realizing the first switch channel 40 being turned off and the second switch channel 50 being turned on.

[0075] S4. When the voltage at the second input terminal 20 is lower than a preset threshold, the first switching channel 40 is turned on and the second switching channel 50 is turned off. Specifically, when the voltage at the second input terminal 20 is lower than the preset threshold, a second control signal is generated. At this time, the second transistor Q4 and the third transistor Q6 are turned off, and the first transistor Q5 is turned on due to the voltage at the first input terminal 10, pulling down the gates of the first MOSFET Q1 and the second MOSFET Q2, making them turn on; the gate of the third MOSFET Q3 is pulled up by the second gate pull-up resistor R7 and turned off. This achieves the turning on of the first switching channel 40 and the turning off of the second switching channel 50.

[0076] Furthermore, to prevent frequent switching between the two power supplies, the voltage divider resistor values ​​can be designed appropriately to create a difference of approximately 0.5V between the turn-on and turn-off thresholds, giving the control signal switching hysteresis characteristics and avoiding repeated switching near the critical voltage.

[0077] To better understand the usage scenario of this embodiment, in a specific application case, the electronic device 1000 is an outdoor environmental monitoring station:

[0078] The second input terminal 20 connects to a 20W solar panel (open circuit voltage 18V, operating voltage 12-15V). The first input terminal 10 connects to a 5V / 2A USB adapter as a backup power supply 80. The load circuit 60 is a monitoring system containing multiple sensors, with an average power consumption of 500mW. Actual operating results are as follows:

[0079] On sunny days, the system is powered by solar energy, and the USB channel is completely isolated, with no backflow of current.

[0080] On rainy days or at night, it automatically switches to USB power supply without voltage drop during the switching process;

[0081] The long-term operating temperature rise is less than 5℃, which is 20℃ lower than the long-term operating temperature of traditional diode solutions.

[0082] The system reliability has been greatly improved, with a mean time between failures (MTBF) of over 50,000 hours.

[0083] This invention effectively solves the core technical challenges of dual-input power supply systems through an innovative dual-PMOS back-to-back connection structure. It features low power consumption, high reliability, and significant cost advantages, making it particularly suitable for outdoor electronic devices powered by new energy sources. It has broad market prospects.

[0084] Combination Figures 1-3 The present invention has the following beneficial effects:

[0085] 1. The voltage detection circuit automatically identifies the status of the main power supply, realizing intelligent switching between main power supply priority and backup power supply emergency, eliminating the need for manual intervention required in traditional systems and improving the automation level of the system;

[0086] 2. When the main power supply is available, the backup power supply channel is forcibly shut down. When the main power supply fails, the main power supply channel is shut down and the backup power supply is used to supply power, ensuring that only one power supply supplies power to the load at any time, effectively avoiding the conflict problem caused by multiple power supplies in parallel.

[0087] 3. The voltage detection circuit can accurately determine the effectiveness of the main power supply. The control logic is simple and reliable, which reduces the risk of misjudgment and switching failure and improves the stability of the system.

[0088] 4. Simplified circuit structure: The integrated voltage detection and switching control design simplifies the overall circuit structure of the dual-input power supply system, reducing system complexity and cost.

[0089] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A dual-input power supply priority control circuit, characterized in that, It includes a first input terminal, a second input terminal, an output terminal, and a voltage detection circuit. The first input terminal is used to connect to a backup power supply, and the second input terminal is used to connect to a main power supply. The first input terminal is electrically connected to the output terminal through a first switching channel, and the second input terminal is electrically connected to the output terminal through a second switching channel; The voltage detection circuit is used to detect the voltage state of the second input terminal and control the conduction state of the first and second switching channels according to the detection result. When there is a valid voltage at the second input terminal, the second switching channel is turned on and the first switching channel is turned off, so that the second input terminal has a higher power supply priority than the first input terminal.

2. The dual-input power priority control circuit as described in claim 1, characterized in that, The first switching channel includes at least two MOSFETs connected in series, and the parasitic diodes of adjacent MOSFETs are connected in reverse series to form a bidirectional blocking structure.

3. The dual-input power supply priority control circuit as described in claim 2, characterized in that, The first switching channel includes a first MOSFET Q1 and a second MOSFET Q2. The source of the first MOSFET Q1 is electrically connected to the source of the second MOSFET Q2, and the gate of the first MOSFET Q1 is electrically connected to the gate of the second MOSFET Q2. The drain of the first MOSFET Q1 is electrically connected to the first input terminal, and the drain of the second MOSFET Q2 is electrically connected to the output terminal.

4. The dual-input power supply priority control circuit as described in claim 3, characterized in that, The second switching channel includes a third MOSFET Q3, the drain of which is electrically connected to the second input terminal and the source of which is electrically connected to the output terminal.

5. The dual-input power priority control circuit as described in claim 4, characterized in that, The first MOSFET Q1, the second MOSFET Q2, and the third MOSFET Q3 are all PMOS transistors.

6. The dual-input power priority control circuit as described in claim 4, characterized in that, The voltage detection circuit includes a first driving circuit and a second driving circuit. The first driving circuit is used to control the turn-on and turn-off of the first MOSFET Q1 and the second MOSFET Q2, and the second driving circuit is used to control the turn-on and turn-off of the third MOSFET Q3.

7. The dual-input power priority control circuit as described in claim 6, characterized in that, The first driving circuit includes a first transistor Q5 and a second transistor Q4. The base of the first transistor Q5 is electrically connected to the connection point between the first input terminal and the drain of the first MOSFET Q1 through a first base resistor R3, and is grounded through a second base resistor R4. The collector is electrically connected to the gate of the first MOSFET Q1 and the gate of the second MOSFET Q2 through a first collector resistor R2, and the emitter is grounded. The base of the second transistor Q4 is electrically connected to the connection point between the second input terminal and the drain of the third MOSFET Q3 through the third base resistor R5, and grounded through the fourth base resistor R6. The collector is electrically connected to the connection point between the base of the first transistor Q5 and the first base resistor R3, and the emitter is grounded.

8. The dual-input power priority control circuit as described in claim 7, characterized in that: The second driving circuit includes a third transistor Q6. The base of the third transistor Q6 is electrically connected to the connection point between the second input terminal and the drain of the third MOSFET Q3 through a fifth base resistor R9, and is grounded through a sixth base resistor R10. The collector is electrically connected to the gate of the third MOSFET Q3 through a seventh base resistor R8, and the emitter is grounded.

9. The dual-input power supply priority control circuit as described in claim 8, characterized in that, The first driving circuit further includes a first Zener diode Z1 and a first gate pull-up resistor R1. The cathode of the first Zener diode Z1 is electrically connected to the connection point between the source of the first MOSFET Q1 and the source of the second MOSFET Q2, and the anode is electrically connected to the connection point between the gate of the first MOSFET Q1 and the gate of the second MOSFET Q2. One end of the first gate pull-up resistor R1 is electrically connected to the connection point between the gate of the first MOSFET Q1 and the gate of the second MOSFET Q2, and the other end is electrically connected to the connection point between the source of the first MOSFET Q1 and the source of the second MOSFET Q2.

10. The dual-input power supply priority control circuit as described in claim 8, characterized in that, The second driving circuit also includes a second Zener diode Z2, a second gate pull-up resistor R7, and a filter capacitor C1. The cathode of the second Zener diode Z2 is electrically connected to the source of the third MOSFET Q3, and the anode is electrically connected to the gate of the third MOSFET Q3. One end of the second gate pull-up resistor R7 is electrically connected to the connection point between the gate of the third MOS transistor Q3 and the seventh base resistor R8, and the other end is electrically connected to the connection point between the source of the third MOS transistor Q3 and the cathode of the second Zener diode Z2. One end of the filter capacitor C1 is electrically connected to the base of the third transistor Q6, and the other end is grounded.

11. The dual-input power priority control circuit as described in claim 1, characterized in that, The input voltage range of the first and second input terminals is 5V to 15V.

12. A dual-input power supply priority control method, applied to a dual-input power supply priority control circuit as described in any one of claims 1-11, characterized in that, Includes the following steps: Detect the voltage at the second input terminal; When the voltage at the second input terminal is higher than a preset threshold, the first switch channel is turned off and the second switch channel is turned on. When the voltage at the second input terminal is lower than a preset threshold, the first switch channel is turned on and the second switch channel is turned off.

13. An electronic device, characterized in that, It includes a load circuit and a dual-input power priority control circuit as described in any one of claims 1-11, wherein the load circuit is electrically connected to the output terminal of the dual-input power priority control circuit.

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