Coupled inductor zscb based on topology switching and its reclosing-rebreak method

Abstract

The application discloses a coupled inductance type ZSCB based on topology switching and a reclosing-rebreak method thereof, and the ZSCB comprises a circuit breaker topology and a control circuit. DC The anode of the thyristor T is connected with a direct current power supply V DC The cathode is connected with one end of the inductor L1, the other end of the inductor L1 is connected with one end of the inductor L2, the other end of the inductor L2 is connected with a load; S1 and S2 are connected in series and then connected in parallel between the two ends of T and L1, wherein the drain of S1 is connected with the anode of T, and the source of S2 is connected with the connection point of L1 and L2; S3 and S4 are connected in series and then connected with the source of S2 at one end and V DC The other end of the capacitor C is connected with the connection point of S3 and S4; the control circuit changes the connection mode of the capacitor before each reclosing, so that the capacitor voltage can exactly meet the required condition for the next rebreak, and the reclosing-rebreak under permanent fault is realized.

Description

Technical Field

[0001] This invention belongs to the field of DC microgrids, specifically relating to a coupled inductive Z-source DC circuit breaker based on topology switching and its reclosing-re-disconnection method. Background Technology

[0002] Distributed energy generation technologies, represented by photovoltaic and wind power generation, have been widely researched and applied. DC microgrids have a strong capacity to accommodate distributed energy, and can rationally allocate and schedule the electricity generated by distributed generation systems according to actual conditions, maximizing the economic benefits of distributed energy and showing promising application prospects. To ensure the safe and reliable operation of DC microgrids, it is necessary to design DC circuit breakers (DCCBs) that offer fast fault breaking, are arc-free, and highly reliable. Among them, the Z-source DC circuit breaker (ZSCB), derived from the Z-source converter, uses thyristors as the main switch. It can automatically trigger breaking by utilizing the characteristics of the Z-source impedance network itself, without the need for additional monitoring equipment. It has advantages such as simple control and low cost, and has been widely studied in recent years, resulting in various topologies. Based on the type of inductor used in the impedance network, existing ZSCB topologies can be divided into topologies based on discrete inductors and coupled inductors. The latter, due to the use of magnetic integration technology, has advantages in both size and design freedom, and is currently the mainstream of ZSCB research.

[0003] Despite the various topologies, ZSCBs all follow the same operating principle: at the moment a fault occurs, a pulse current opposite to the initial thyristor current is generated by the charging (or discharging) process of the impedance network capacitor, forcing the thyristor current to cross zero, thereby achieving fault disconnection. According to the IEC-62271-100 standard, if the fault persists after the circuit breaker is reclosed (i.e., a permanent fault), it needs to be re-disconnected within a short time, i.e., completing the reclosing-opening (CO) operation. However, in existing ZSCB topologies, the impedance network capacitor voltage cannot return to its initial state after a single disconnection, preventing the CO operation and severely limiting its practical application.

[0004] To enable ZSCB (Zero-Signal Block Cell) to have CO (Cooling) capability, there are currently three main methods: First, by adding a pre-charging branch, the ZSCB impedance capacitor is pre-charged before each reclosing, thus providing initial energy storage. However, this method requires additional charging time and an additional isolating switch to disconnect the load side. Second, a passive energy recovery branch is added across the capacitor, recharging a portion of the fault energy into the capacitor after each disconnection, without additional pre-charging time. However, the actual energy charged into the capacitor by this method is affected by the size of the fault load, reducing the reliability of re-disconnection. Furthermore, to recover fault energy, this method cannot use a buffer energy absorption circuit, resulting in significant overvoltage across the thyristor during disconnection. Simultaneously, to prevent reverse charging of the capacitor, an additional thyristor needs to be connected in series in the main circuit, undoubtedly increasing the overall cost and conduction losses. Third, an improved active fault energy recovery method, compared to the passive method, allows for controllable recovery of fault energy, and the main circuit does not require an additional thyristor. However, this method still cannot use a buffer energy absorption circuit and requires an additional current sensor to control the full-bridge circuit, increasing circuit complexity. Summary of the Invention

[0005] In view of this, the purpose of this invention is to provide a topology-switched coupled inductor ZSCB (i.e., TQ-ZSCB) and its reclosing-re-breaking method. This method can achieve continuous CO operation of the ZSCB without pre-charging time and allows for the addition of a buffer energy-absorbing circuit to reduce thyristor overvoltage. Compared with existing methods, the method of this invention has significant advantages in terms of main circuit conduction loss, thyristor overvoltage, and re-breaking reliability.

[0006] The objective of this invention is achieved through the following technical solution:

[0007] A topology-switched coupled inductor ZSCB includes: a circuit breaker topology and a control circuit, wherein the circuit breaker topology includes: a thyristor T, two Si MOSFETs S1 and S2, two relays S3 and S4, and a resistor R. s1 diode D s1 Resistance R s2 diode D s2 Inductors L1 and L2, capacitor C, where,

[0008] The anode of thyristor T is connected to the DC power supply V. DC The positive terminal of the thyristor T is connected to the positive terminal of the inductor L1, the cathode of the thyristor T is connected to one end of the inductor L1, the other end of the inductor L1 is connected to one end of the inductor L2, and the other end of the inductor L2 is connected to the load.

[0009] The two ends of inductor L1 are connected in anti-parallel by R s1 and D s1The buffer circuit is composed of series connections, with the two ends of inductor L2 connected in antiparallel to R. s2 and D s2 A buffer circuit composed of series connections;

[0010] S1 and S2 are connected in series and then in parallel across the thyristor T and inductor L1. The drain of S1 is connected to the anode of thyristor T, and the source of S2 is connected to the junction of inductors L1 and L2.

[0011] Relays S3 and S4 are connected in series, with one end connected to the source of S2 and the other end connected to a DC power supply V. DC The negative electrode;

[0012] One end of capacitor C is connected to the connection point of S1 and S2, and the other end is connected to the connection point of S3 and S4;

[0013] One end of the load is connected to inductor L2, and the other end is connected to DC power supply V. DC The negative terminal is connected.

[0014] The control circuit changes the connection of capacitor C before each reclosing, so that the capacitor voltage can just meet the conditions required for the next re-disconnection, thus realizing reclosing-re-disconnection under permanent fault conditions.

[0015] Furthermore, assuming a fault occurs on the load side, the load resistance will decrease from the rated value R. o Change to R f The turns ratio n between inductors L1 and L2 is set as follows:

[0016] Furthermore, the control circuit includes a JK flip-flop, a first delay circuit, a second delay circuit, a first monostable multivibrator, and a second monostable multivibrator, wherein...

[0017] The CLK terminal of the JK flip-flop is used to receive the closing signal A, and the main output terminal of the JK flip-flop outputs the drive signal G for relay S3. S3 The complementary output of the JK flip-flop leads to the drive signal G of relay S4. S4 ;

[0018] The first delay circuit is used to delay the drive signal G. S3 Delay the relay by one maximum operating time to generate the drive signal G for S1. S1 ;

[0019] The second delay circuit is used to delay the drive signal G. S4 The drive signal G for S2 is generated by delaying the relay by its maximum operating time. S2 ;

[0020] The first monostable multivibrator is used to respond to the drive signal G. S1Generate a first signal with a preset pulse width;

[0021] The second monostable multivibrator is used to adjust the load according to the drive signal G. S2 Generate a second signal with a preset pulse width;

[0022] The first and second signals are passed through an OR gate to generate the drive signal G for the thyristor T. T To achieve the closing of the circuit breaker.

[0023] Furthermore, the preset pulse width is determined by calculating the thyristor negative voltage withstand time under non-fault conditions and fault conditions on the load side. The preset pulse width is selected as a value within this range with a certain margin.

[0024] This invention also provides a reclosing-re-disconnection method for a coupled inductor ZSCB based on topology switching, comprising:

[0025] The coupled inductor ZSCB based on topology switching is denoted as TQ-ZSCB. Through the control circuit, the working mode of TQ-ZSCB is made to be mode 1, that is, the T-ZSCB topology preparation mode. In mode 1, the thyristor T is not yet turned on, the voltage of the capacitor is 0, and S2 and S4 are turned on. The circuit topology of TQ-ZSCB is the T-ZSCB topology, and the thyristor T is ready to reclose at any time.

[0026] When the closing signal arrives, the control circuit first switches the circuit topology of TQ-ZSCB to Q-ZSCB topology, that is, S2 and S4 are turned off and S1 and S3 are turned on. Then, thyristor T is turned on. If there is no fault on the load side, the operating mode of TQ-ZSCB enters mode 2, that is, the normal conduction mode of Q-ZSCB topology. At this time, when a fault occurs on the load side, TQ-ZSCB clears the fault in Q-ZSCB topology and enters mode 3, that is, the fault clearing mode of Q-ZSCB topology. The capacitor is charged and the capacitor voltage is eventually charged to the power supply voltage. Thyristor T is turned off and enters mode 4, that is, the preparation mode of Q-ZSCB topology. In mode 4, thyristor T is not turned on and the capacitor voltage is the power supply voltage.

[0027] In mode 4, when the closing signal arrives, the circuit is first switched to the T-ZSCB topology and then the thyristor is turned on. If there is no fault on the load side, the circuit will be normally turned on as the T-ZSCB topology. At this time, the circuit enters mode 5, that is, the T-ZSCB normal conduction mode.

[0028] In mode 5, if a fault occurs on the load side, the circuit will perform fault disconnection according to the T-ZSCB working principle. At this time, the circuit enters mode 6, that is, T-ZSCB fault disconnection mode. After that, the capacitor voltage is discharged to 0, and the circuit returns to mode 1.

[0029] If a permanent fault exists on the load side in mode 1, thyristor T is reclosed in mode 1. The circuit topology of TQ-ZSCB is the T-ZSCB topology. Since the capacitor voltage is 0 in mode 1, thyristor T can re-disconnect at the moment of reclosing. After disconnection, the capacitor voltage is charged to the power supply voltage, that is, it returns to mode 4. The process of thyristor T disconnecting again at the moment of reclosing is called mode 7, that is, re-disconnecting mode 1.

[0030] If a permanent fault exists on the load side in mode 4, thyristor T will be reclosed in mode 4. The circuit topology of TQ-ZSCB is the Q-ZSCB topology. Since the capacitor voltage is charged to the power supply voltage in mode 4, thyristor T can re-disconnect at the moment of reclosing. After disconnection, the capacitor voltage discharges to 0, i.e., returning to mode 1. This process of thyristor T disconnecting again at the moment of reclosing is denoted as mode 8, i.e., re-disconnection mode 2.

[0031] The beneficial effects of this invention are:

[0032] (1) The present invention proposes a reclosing-re-disconnection circuit topology for a coupled inductive Z-source DC circuit breaker (i.e., TQ-ZSCB) based on topology switching. It utilizes the characteristics of two typical ZSCB topologies (i.e., T-ZSCB and Q-ZSCB) to switch the circuit topology each time it is reclosed, so that the initial voltage of the capacitor automatically meets the conditions required for re-disconnection. For permanent faults, it can achieve continuous and stable reclosing-re-disconnection operation with high reliability.

[0033] (2) The thyristor drive pulse width design method proposed in this invention can enable the reclosing to take the correct action under different faults and has the ability to distinguish faults.

[0034] (3) The reclosing-reopening circuit method of the coupled inductor Z-source DC circuit breaker based on topology switching proposed in this invention has only one thyristor in the main circuit and can be equipped with an energy buffer circuit, which greatly reduces the conduction loss of the main circuit and the thyristor overvoltage.

[0035] (4) No need to install pre-charging branch, energy recovery circuit and current detection circuit, resulting in lower size and cost.

[0036] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0037] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will now be described in further detail with reference to the accompanying drawings, wherein:

[0038] Figure 1 The topology of T-ZSCB in different states;

[0039] Figure 2 For the T-ZSCB reclosing instantaneous complex frequency domain model;

[0040] Figure 3 The topology of Q-ZSCB in different states;

[0041] Figure 4 For the Q-ZSCB reclosing instantaneous complex frequency domain model;

[0042] Figure 5 This is a waveform diagram of the thyristor voltage during normal reclosing.

[0043] Figure 6 This is a waveform diagram of the thyristor voltage during fault reclosing;

[0044] Figure 7 This is a schematic diagram of the TQ-ZSCB circuit topology proposed in this invention;

[0045] Figure 8 This is a schematic diagram of the TQ-ZSCB circuit mode proposed in this invention;

[0046] Figure 9 This is a schematic diagram of the mode transfer of the circuit proposed in this invention;

[0047] Figure 10 This is a schematic diagram of the circuit control principle proposed in this invention;

[0048] Figure 11 The circuit waveform and its partial magnified view under short-circuit fault conditions are shown.

[0049] Figure 12 The circuit waveform and its partial magnified view under the condition of permanent overload fault are shown. Detailed Implementation

[0050] The specific embodiments of the present invention are described below to enable those skilled in the art to understand the present invention. However, it should be understood that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the present invention as defined and determined by the appended claims. All inventions utilizing the concept of the present invention are protected.

[0051] This invention is based on the existing coupled inductive DC circuit breaker (ZSCB). By designing appropriate capacitor, inductor, coupled inductor turns ratio, and thyristor pulse width, and utilizing the topological characteristics of capacitor discharge DC circuit breaker (T-ZSCB) and capacitor charging DC circuit breaker (Q-ZSCB), a topology switching coupled inductive Z-source DC circuit breaker (TQ-ZSCB) is obtained by designing a switching component that enables the circuit to switch topology each time it is reclosed. TQ-ZSCB enables the initial capacitor voltage to automatically meet the conditions required for re-disconnection, and can achieve continuous and stable reclosing-re-disconnection operation for permanent faults.

[0052] The TQ-ZSCB includes a circuit breaker topology and control circuitry. Among them, Figure 7 This is a schematic diagram of a circuit breaker topology. For example... Figure 7 As shown, the circuit breaker topology includes: a thyristor T, two Si MOSFETs S1 and S2, two relays S3 and S4, and a resistor R. s1 diode D s1 Resistance R s2 diode D s2 Inductors L1 and L2, capacitor C, where,

[0053] The anode of thyristor T is connected to the DC power supply V. DC The positive terminal of the thyristor T is connected to the positive terminal of the inductor. The cathode of the thyristor T is connected to one end of the inductor L1, and the other end of the inductor L1 is connected to one end of the inductor L2. The other end of the inductor L2 is connected to the load resistor R. o Connected;

[0054] The two ends of inductor L1 are connected in anti-parallel by R s1 and D s1 The buffer circuit is composed of series connections, with the two ends of inductor L2 connected in antiparallel to R. s2 and D s2 A buffer circuit composed of series connections;

[0055] S1 and S2 are connected in series and then in parallel across the thyristor T and inductor L1. The drain of S1 is connected to the anode of thyristor T, and the source of S2 is connected to the junction of inductors L1 and L2.

[0056] Relays S3 and S4 are connected in series, with one end connected to the source of S2 and the other end connected to a DC power supply V. DC The negative electrode;

[0057] One end of capacitor C is connected to the connection point of S1 and S2, and the other end is connected to the connection point of S3 and S4;

[0058] Load resistance R o One end is connected to inductor L2, and the other end is connected to DC power supply V. DC The negative terminal is connected.

[0059] The control circuit can change the connection of capacitor C before each reclosing, so that the capacitor voltage can just meet the conditions required for the next re-disconnection, thus realizing reclosing-re-disconnection under permanent fault conditions.

[0060] Figure 10 This is a schematic diagram of the control circuit in the TQ-ZSCB of this invention.

[0061] like Figure 10 As shown, the control circuit includes a JK flip-flop, a first delay circuit, a second delay circuit, a first monostable multivibrator, and a second monostable multivibrator, wherein...

[0062] The CLK terminal of the JK flip-flop is used to receive the closing signal A, and the main output terminal of the JK flip-flop outputs the drive signal G for relay S3. S3 The complementary output of the JK flip-flop leads to the drive signal G of relay S4. S4 ;

[0063] The first delay circuit is used to delay the drive signal G. S3 Delay the relay by one maximum operating time to generate the drive signal G for S1. S1 ;

[0064] The second delay circuit is used to delay the drive signal G. S4 The drive signal G for S2 is generated by delaying the relay by its maximum operating time. S2 ;

[0065] The first monostable multivibrator is used to respond to the drive signal G. S1 Generate a first signal with a preset pulse width;

[0066] The second monostable multivibrator is used to adjust the load according to the drive signal G. S2 Generate a second signal with a preset pulse width;

[0067] The first and second signals are passed through an OR gate to generate the drive signal G for the thyristor T. T To achieve the closing of the circuit breaker.

[0068] Figure 1 This refers to the existing T-ZSCB topology in different states (or stages), where... Figure 1 Figure (a) shows the topology of T-ZSCB under normal operating conditions; Figure 1 Figure (b) shows the topology of T-ZSCB in the fault clearing state; Figure 1 Figure (c) shows the topology of T-ZSCB during the resonance phase; Figure 1 Figure (d) shows the topology of T-ZSCB during the energy absorption phase.

[0069] like Figure 1 As shown in Figure (a), the input voltage is V under normal operating conditions. DC When thyristor T is turned on, the rated current I... n As the current flows through inductors L1 and L2 and the load, capacitor C is charged to V. C0 (Because the thyristor has a forward voltage, capacitor C can only be charged to near the input voltage V.) DC This voltage is denoted as V. C0 When a short circuit or overcurrent fault occurs on the load side, the load resistance will decrease from the rated value R. o Jump to fault value R f T-ZSCB enters the fault clearing phase, such as Figure 1 In Figure (b), capacitor C will pass through the secondary inductor L2 and the fault resistor R. f Discharge occurs (this current is denoted as i) L2 The total discharge current of capacitor C is denoted as i. C， And generate a current I on the primary inductor L1 that is equal to the rated current I n Reverse pulse induced current i p , when i p equals I n At that time, the thyristor turns off due to the current crossing to zero. To ensure i p The maximum value is greater than or equal to I n When designing the turns ratio n of the coupled inductor, it is necessary to satisfy n ≤ R. o / R f -1.

[0070] Subsequently, the circuit breaker entered the following state: Figure 1 The resonant operating state shown in Figure (c) is such that C continues to pass through L2 and R. f Discharge occurs, and the capacitor voltage continues to decrease. When the voltage across L2 becomes negative, the circuit enters the energy absorption phase, such as... Figure 1 As shown in Figure (d). At this time, the buffer circuit (i.e. Figure 1 (d) Resistor R in the figure s and diode D s The circuit (composed of the circuit) operates and consumes all fault energy, and the circuit breaker completes one fault disconnection. (Comparison) Figure 1 As can be seen in Figures (a) and (d), after a single interruption, the capacitor voltage of T-ZSCB changes from V... C0 It dropped to 0.

[0071] The complex frequency domain model of T-ZSCB reclosing instant is as follows: Figure 2 As shown. Where s is a complex frequency domain variable, V DC / s is the expression for the input voltage in the complex frequency domain, where 1 / s is C and V. C0 / s is the initial value of V C0The capacitance C is expressed in the complex frequency domain, and s(L1+M), s(L2+M), and -sM are the complex frequency domain expressions for the coupled inductors L1 and L2 in the T-connection, where M is the coupled inductance and the coupling coefficient (i.e., the coupling coefficient). Let k = 1, then we have By writing the KCL and KVL equations for its complex frequency domain circuit, the expression for the complex frequency domain current flowing through the thyristor can be obtained as follows:

[0072]

[0073] Because the primary and secondary sides of the coupled inductor are both wound on the same iron core, the inductance value satisfies L1 = n 2 L2, according to the initial value theorem, the time-domain expression of the instantaneous current of the thyristor at time t0 can be obtained as follows:

[0074]

[0075] Under a permanent fault, the initial current of the thyristor jumps from 0 to i during reclosing. L1 (t0). When V DC , n and R f At a certain time, i L1 (t0) only interacts with V C0 Related. To ensure that the thyristor does not conduct in this situation, i L1 (t0) needs to satisfy i L1 (t0) is less than or equal to 0. According to equation (2), in order for T-ZSCB to have the ability to disconnect again at the moment of reclosing, its initial capacitor voltage needs to be higher than V. DC / (n+1).

[0076] Figure 3 It is the existing Q-ZSCB topology in different states, where, Figure 3 Figure (a) shows the topology of Q-ZSCB in normal operating condition; Figure 3 Figure (b) shows the topology of Q-ZSCB in the fault clearing state; Figure 3 Figure (c) shows the topology of Q-ZSCB during the resonance phase; Figure 3 Figure (d) shows the topology of Q-ZSCB during the energy absorption phase.

[0077] like Figure 3 As shown in Figure (a), the normal conduction circuit of Q-ZSCB is the same as that of T-ZSCB, but its capacitor C will not be charged under normal operating conditions because it is bypassed by the thyristor. Figure 3As shown in Figure (b), during the fault clearing phase, capacitor C provides a low-impedance path for the rapidly changing fault current. A portion of the fault current flows to the load through inductor L2 and capacitor C, inducing an impedance similar to I in L1. n Reverse fault pulse current i p Consistent with T-ZSCB, when i p equals I n At that time, the thyristor turns off due to the current crossing to zero. To ensure i p The maximum value is greater than or equal to I n When designing the turns ratio n of the coupled inductor, it is also necessary to satisfy n≤R. o / R f -1. After this, Q-ZSCB enters the same resonant operating state and energy absorption state as T-ZSCB, such as... Figure 3 As shown in Figures (c) and (d), C continues through L2 and R. f Discharge occurs, and the capacitor voltage continues to decrease. When the voltage across L2 becomes negative, the circuit enters the energy absorption phase, at which point the buffer circuit (i.e., ...) Figure 3 (d) Resistor R in the figure s and diode D s The circuit breaker completes a fault disconnection by consuming all the fault energy.

[0078] The complex frequency domain model of ZSCB reclosing instant is as follows: Figure 4 As shown. Figure 4 The meaning of each symbol in the Chinese text and Figure 2 Similar to that in the text, I will not repeat it here.

[0079] The same calculations as those for T-ZSCB show that, in order for Q-ZSCB to have the ability to disconnect again at the moment of reclosing, its initial capacitor voltage needs to be lower than nV. DC / (n+1).

[0080] The above analysis shows that, at the moment of reclosing, the current and voltage changes of both Q-ZSCB and T-ZSCB circuit breaker topologies are identical throughout the fault clearing process, and their circuit topologies are completely equivalent (i.e., the coupling inductance turns ratio of both circuit breakers must satisfy n≤R). o / R f -1. Both types of circuit breakers require the same operating states (fault clearing stage, resonance stage, and energy absorption stage) to function, and the required capacitor voltages are dual; for T-ZSCB to reclose successfully, its capacitor voltage must be higher than V. DC For Q-ZSCB to reclose successfully, its capacitor voltage must be lower than nV. DC / (n+1), their sum equals V DC .

[0081] Therefore, it is necessary to set an appropriate turns ratio for the capacitor, inductor, and coupling inductor so that during the fault clearing phase, the capacitor charges or discharges, thereby generating a current I across the inductor that is equal to the rated current I. n Reverse pulse induced current i p At that time, a suitable coupling inductor turns ratio n can guarantee i p Greater than or equal to I n The thyristor then turns off due to the current crossing to zero, and the circuit breaker closes.

[0082] In an embodiment of the present invention, the specific setting is: input voltage V DC 50V, rated load resistance R o R is 25Ω, under both short circuit and overload faults. f The Ω values ​​are 0 and 5 respectively, the coupling coefficient k is 0.99, the turns ratio n is 2, the primary inductance L1 is 525.63μH, the secondary inductance L2 is 132μH, and the capacitor C is 20μF.

[0083] Thyristor pulse width t p Proper settings are also required. A suitable thyristor pulse width t p This allows t to be normal when the load side is normal. p The duration of the negative voltage of the thyristor at this time is greater than t. nc The thyristor recovered normally, and the circuit breaker closed smoothly. When a fault exists on the load side, t p The duration of the negative voltage of the thyristor at this time is less than t. nc In this way, the thyristor will not re-conduct after disconnection, ensuring that the circuit breaker can close reliably and stably.

[0084] The preset pulse width can be determined by calculating the duration of the negative voltage of the thyristor under both non-fault and fault conditions on the load side. The lower limit of the pulse width can be obtained by determining the duration of the negative voltage of the thyristor under non-fault conditions on the load side, and the upper limit of the pulse width can be obtained by determining the duration of the negative voltage of the thyristor under fault conditions on the load side. The preset pulse width, with a certain margin, can be selected as an appropriate intermediate value between the lower and upper limits.

[0085] Specifically, taking T-ZSCB as an example, the time-domain equation of the circuit at the instant of reclosing is obtained from its time-domain circuit:

[0086]

[0087] Among them, R o For the rated load resistance, v C (t) represents the capacitor voltage. From the above equation, the expression for the capacitor voltage can be derived, and thus the thyristor voltage v can be further obtained. T (vT =V DC -v C The expression is:

[0088]

[0089] Specifically, P1 and P2 are as follows:

[0090]

[0091] Q1 and Q2 are respectively:

[0092]

[0093] Substitute the circuit design parameters into the thyristor voltage V T The expression can be used to plot v at this time. T Image as Figure 5 As shown, from Figure 5 The value of t at this time can be read from the text. nc Specifically, it is 19.7 μs. When a load-side fault occurs, the fault resistor R... f Substitute the thyristor voltage v T Replace R in the expression o And by performing a second-order Taylor expansion, we get:

[0094]

[0095] As can be seen from equation (5), with R f Gradually decrease, v T Negative pressure duration t nc Gradually increasing. Substituting the data from this example into n≤R o / R f -1, that is, n=2, R o =25Ω, therefore, the maximum fault resistance R that T-ZSCB can break is... fmax (i.e. R) f The maximum value is specifically 8.33Ω, R fmax The corresponding t nc Minimum, denoted as t nf R fmax Substitute the thyristor voltage v T The expression can be used to express v at this time. T Image as Figure 6 As shown. From Figure 6 t can be read from nc Specifically, it is 34μs.

[0096] In summary, the thyristor drive pulse width t p It should satisfy 19.7μs≤t p ≤34μs. t pWe can take an appropriate midpoint from this interval; for example, we can take t. p =25μs.

[0097] This invention also provides a reclosing-re-disconnection method for a coupled inductor ZSCB based on topology switching. This method includes eight modes of the TQ-ZSCB. Figure 8 The circuit topology diagram for each mode is given. Among them, Figure 8 Figure (a) to Figure 8 The middle (h) diagrams correspond to modes 1 to 8, respectively. Figure 9 This is a schematic diagram of mode transition. (Reference) Figure 8 and Figure 9 The method includes:

[0098] The control circuit makes the TQ-ZSCB's operating mode 1, that is, the T-ZSCB topology preparation mode. In mode 1, the thyristor T is not yet turned on, the voltage of the capacitor is 0, S2 and S4 are turned on, the circuit topology of TQ-ZSCB is the T-ZSCB topology, and the thyristor T is ready to reclose at any time.

[0099] When the closing signal arrives, the control circuit first switches the circuit topology of TQ-ZSCB to Q-ZSCB topology, that is, S2 and S4 are open and S1 and S3 are closed. Then, thyristor T is turned on. If there is no fault on the load side, the operating mode of TQ-ZSCB enters mode 2, that is, the normal conduction mode of Q-ZSCB topology. At this time, when a fault occurs on the load side, TQ-ZSCB clears the fault in Q-ZSCB topology and enters mode 3, that is, the fault clearing mode of Q-ZSCB topology. The capacitor is charged and the capacitor voltage is eventually charged to the power supply voltage. Thyristor T is disconnected and enters mode 4, that is, the preparation mode of Q-ZSCB topology. In mode 4, thyristor T is not turned on and the capacitor voltage is the power supply voltage.

[0100] In mode 4, when the closing signal arrives, the circuit first switches to the T-ZSCB topology and then turns on the thyristor. If there is no fault on the load side, the circuit will conduct normally as a T-ZSCB topology. At this time, the circuit enters mode 5, which is the normal T-ZSCB conduction mode.

[0101] In mode 5, if a fault occurs on the load side, the circuit will perform fault disconnection according to the T-ZSCB operating principle. At this time, the circuit enters mode 6, which is the T-ZSCB fault disconnection mode. Afterward, the capacitor voltage discharges to 0, and the circuit returns to mode 1.

[0102] If a permanent fault exists on the load side in Mode 1, reclosing is performed in Mode 1. The control circuit switches the TQ-ZSCB circuit topology to the T-ZSCB topology. Since the capacitor voltage discharges to 0 in Mode 1, the thyristor T can re-interrupt at the moment of reclosing. After re-interruption, the capacitor voltage charges to the power supply voltage, returning to Mode 4. This process of the thyristor T re-interrupting at the moment of reclosing is denoted as Mode 7, i.e., re-interrupting Mode 1 (i.e., as shown in the image). Figure 9 As shown, when a permanent fault exists on the load side, in mode 1, it enters mode 7, and then returns to mode 4.

[0103] If a permanent fault exists on the load side in mode 4, reclosing is performed in mode 4. The control circuit switches the TQ-ZSCB circuit topology to the Q-ZSCB topology. Since the capacitor voltage charges to the power supply voltage in mode 4, thyristor T can re-disconnect at the moment of reclosing. After disconnection, the capacitor voltage discharges to 0, i.e., returning to mode 1. This process of thyristor T re-disconnecting at the moment of reclosing is denoted as mode 8, i.e., re-disconnecting mode 2 (i.e., as shown in the image). Figure 9 As shown, when a permanent fault exists on the load side, the system transitions from mode 4 to mode 8, and then back to mode 1.

[0104] When the circuit topology undergoes mode switching, a corresponding control circuit needs to be designed. Before each reclosing operation, the S1-S4 switches need to be controlled to change the circuit topology, and then a pulse with a width of t is immediately sent to the thyristor. p The control signal is used to achieve closing. Below is an example of a method implemented using logic devices, such as... Figure 10 As shown.

[0105] It uses a JK flip-flop configured in switching mode. By configuring the levels of the J and K terminals, the initial state of the TQ-ZSCB can be made consistent with mode 1. A closing signal A is input from its CLK terminal, and a relay S3 drive signal G is output from its main output Q terminal. S3 The relay S4 drive signal G is drawn from its complementary output terminal. S4 According to the TQ-ZSCB operating principle, a group of SiMOSFETs and relays controlling the same topology switching need to be synchronously turned on and off. However, since the switching time of the relay is longer than that of the SiMOSFET, synchronous operation may cause S1 and S4 to turn on simultaneously, or S2 and S3 to turn on simultaneously. In this case, the capacitor will charge or discharge through the circuit it forms, causing its initial voltage to not meet the reclosing-turn-off condition. Therefore, to avoid this situation, the relay drive signal is delayed by one relay maximum operating time t. m This is then used as the corresponding drive signal for the Si MOSFET. Subsequently, the Si MOSFET drive signal G... S1 G S2Each pulse with a width of t is generated by a monostable trigger. p The signal is finally passed through an OR gate to form the thyristor drive signal G. T .

[0106] The present invention also provides the following experimental data to verify the effectiveness of the present invention in achieving reclosing-re-disconnection under permanent fault conditions.

[0107] Figure 11 The experimental waveform diagram of the TQ-ZSCB circuit under short-circuit fault (i.e.) Figure 11 Figure (a) and its enlarged view (enlarged view of the working waveform at time t1-t8, i.e.) Figure 11 (Figure b) Figure 11 In Figure (a), T and Q represent the T-ZSCB and Q-ZSCB topologies, respectively. Reclosing operations are performed at times t1 and t3-t7 (indicated by solid blue arrows). Observing the time axis below the waveform, it can be seen that the circuit is in mode 1 at time t0, when the thyristor is not yet turned on. The load side is normal during the time interval t0-t2. After reclosing at time t1, the thyristor current i... T and load current i Load All values ​​rose to their rated values, indicating that reclosing under normal load allowed the circuit to resume normal operation. Simultaneously, the capacitor voltage V... C A value of 0 indicates that the circuit has switched to the Q-ZSCB topology and is operating in mode 2. At time t2, a short-circuit fault occurs on the load side (indicated by the red dashed arrow), and the circuit enters mode 3. T Immediately drops to 0, i Load After the resonance phase, the voltage drops to 0, with a peak value of approximately 20A. Thyristor voltage v T At the moment of the fault, it withstands reverse voltage, with a peak value of approximately -100V. Subsequently, the voltage gradually changes to positive, and its peak value is limited to around 72V by the buffer circuit, consistent with theoretical calculations. C After a fault disconnection, the circuit is charged to 50V, at which point it enters mode 4.

[0108] Figure 12 The operating waveform of the TQ-ZSCB circuit under permanent fault conditions (i.e.) Figure 12 Figure (a) and its enlarged view (enlarged view of the working waveform at time t1-t8, i.e.) Figure 12 In Figure (b), the load side remained short-circuited throughout the time period from t2 to t7, during which a total of 4 consecutive reclosing operations were performed. As can be seen from the waveform, during each reclosing period, i... T Keep it at 0, v T The voltage first drops to negative and then returns to the power supply voltage, indicating that the circuit successfully performed reclosing-disconnection. During this period, i LoadAfter rising to the resonant peak and then falling to 0, its peak value is approximately 20A. C The voltage was changed between 50V and 0V, demonstrating that the circuit topology switched with each reclosing operation. This verified the feasibility and reliability of the proposed method under short-circuit faults. At time t7, the load was restored to normal, and after reclosing, the circuit entered mode 5 and operated normally with the T-ZSCB topology. At time t8, the load was short-circuited, and the circuit entered mode 6 and disconnected the fault according to the T-ZSCB operating principle. As shown in the figure, the circuit can conduct normally under both T-ZSCB and Q-ZSCB topologies, and reclosing under load faults, achieving continuous reclosing-disconnection. This indicates that the proposed method can still operate stably under overload faults, its performance is not affected by the load size, and it has high reliability.

[0109] Experimental verification shows that the present invention can effectively realize the reclosing-re-disconnection action under permanent faults, and the thyristor drive pulse width design method proposed in the present invention is correct.

[0110] In the description of this invention, it should be understood that the terms "center," "thickness," "upper," "lower," "horizontal," "top," "bottom," "inner," "outer," and "radial," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying the relative importance or the number of technical features implicitly specified. Therefore, a feature defined by "first," "second," and "third" may explicitly or implicitly include one or more of that feature.

[0111] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A topology-switching-based coupled-inductor ZSCB, characterized in that, Comprise: Circuit breaker topology and control circuit, wherein the circuit breaker topology comprises: thyristor T, two SiMOSFET S1 and S2, two relays S3 and S4, resistance R s1 , diode D s1 , resistance R s2 , diode D s2 , inductances L1 and L2, capacitor C, wherein, The anode of thyristor T is connected to the DC power supply V. DC The positive terminal of the thyristor T is connected to the positive terminal of the thyristor T. The cathode of the thyristor T is connected to one end of the inductor L1. The other end of the inductor L1 is connected to one end of the inductor L2. The other end of the inductor L2 is connected to the load. The two ends of the inductor L1 are connected in anti-parallel by the buffer circuit composed of R s1 and D s1 in series; the two ends of the inductor L2 are connected in anti-parallel by the buffer circuit composed of R s2 and D s2 in series; S1 and S2 are connected in series and then connected in parallel between the thyristor T and the inductor L1, wherein the drain of S1 is connected to the anode of the thyristor T, and the source of S2 is connected to the connection point of the inductors L1 and L2; The relay S3 and S4 are connected in series with one end connected to the source of S2 and the other end connected to the negative pole of the direct current power supply V DC . One end of the capacitor C is connected to the connection point of S1 and S2, and the other end is connected to the connection point of S3 and S4; One end of the load is connected to the inductor L2, and the other end is connected to the negative electrode of the direct current power supply V DC . The control circuit changes the connection mode of the capacitor C before each reclosing, so that the capacitor voltage can exactly meet the required condition for the next re-breaking, thereby achieving reclosing-re-breaking under permanent fault.

2. A topology-switching-based coupled-inductor ZSCB according to claim 1, wherein, Assuming that the load side fails when the load resistance becomes R o from the rated value R f , the turns ratio n between the inductances L1 and L2 is set to:

3. A topology-switching-based coupled-inductor ZSCB according to claim 1, wherein, The control circuit comprises a JK flip-flop, a first delay circuit, a second delay circuit, a first monostable trigger and a second monostable trigger, wherein The CLK end of the JK flip-flop is used for receiving the closing signal A, and the main output end of the JK flip-flop leads out the driving signal G of the relay S3 S3 , and the complementary output end of the JK flip-flop leads out the driving signal G of the relay S4 S4 . a first delay circuit for delaying the drive signal G S3 by a maximum relay operating time to generate a drive signal G S1 for S1 a second delay circuit for delaying the drive signal G S4 by a maximum relay operating time to generate the drive signal G of S2 S2 ; a first monostable trigger for generating a first signal of a predetermined pulse width in response to a drive signal G S1 generating a first signal of a predetermined pulse width; a second monostable trigger for generating a second signal of a predetermined pulse width in response to the drive signal G S2 generating a second signal of a predetermined pulse width; The first signal and the second signal are passed through an OR gate, thereby generating a drive signal G of the thyristor T T To achieve closing.

4. A topology-switching-based coupled-inductor ZSCB according to claim 3, wherein, The preset pulse width is determined by calculating the thyristor negative voltage bearing time under the conditions of no fault on the load side and fault on the load side, and the preset pulse width is selected as a value between the range with a certain margin.

5. A topology-switching-based coupled-inductor ZSCB reclosing-partial-disconnection method according to any one of claims 1 to 4, characterized in that, Comprise: The coupled inductor type ZSCB based on topology switching is denoted as TQ-ZSCB, and the working mode of the TQ-ZSCB is controlled by the control circuit to be in mode 1, i.e. the T-ZSCB topology preparation mode, in which mode 1, the thyristor T has not yet been turned on, the voltage of the capacitor is 0, S2 and S4 are turned on, and the circuit topology of the TQ-ZSCB is the T-ZSCB topology, and the thyristor T is ready to reclose at any time; When the closing signal arrives, the circuit topology of the TQ-ZSCB is first switched to the Q-ZSCB topology by the control circuit, i.e. S2 and S4 are turned off and S1 and S3 are turned on, and then the thyristor T is turned on, if there is no fault on the load side, the working mode of the TQ-ZSCB enters mode 2, i.e. the Q-ZSCB topology normal conduction mode; at this time, when a fault occurs on the load side, the TQ-ZSCB clears the fault in the Q-ZSCB topology and enters mode 3, i.e. the Q-ZSCB topology fault clearing mode, the capacitor is charged, and the capacitor voltage is finally charged to the power supply voltage, and the thyristor T breaks, then enters mode 4, i.e. the Q-ZSCB topology preparation mode, in which mode 4, the thyristor T is not turned on, and the capacitor voltage is the power supply voltage; In mode 4, when the closing signal arrives, the circuit is first switched to the T-ZSCB topology, and then the thyristor is turned on, at this time, if there is no fault on the load side, the circuit will be normally conducted as the T-ZSCB topology, at this time the circuit enters mode 5, i.e. the T-ZSCB normal conduction mode; In mode 5, if a fault occurs on the load side, the circuit will realize fault breaking according to the working principle of the T-ZSCB, at this time the circuit enters mode 6, i.e. the T-ZSCB fault breaking mode, and then the capacitor voltage is discharged to 0, and the circuit returns to mode 1; If there is a permanent fault on the load side in mode 1, the thyristor T is reclosed in mode 1, and the circuit topology of the TQ-ZSCB is the T-ZSCB topology, and because the capacitor voltage is 0 in mode 1, the thyristor T can re-break at the reclosing moment, after breaking, the capacitor voltage is charged to the power supply voltage, i.e. back to mode 4, and the thyristor T breaks again at the reclosing moment, which is denoted as mode 7, i.e. the re-breaking mode 1. If there is a permanent fault in the load side in mode 4, the thyristor T recloses in mode 4, and the circuit topology of the TQ-ZSCB is the Q-ZSCB topology, since the capacitor voltage is charged to the power supply voltage in mode 4, the thyristor T can reclose and break again at the reclosing moment, and after breaking, the capacitor voltage is discharged to 0, i.e., returns to mode 1, and the thyristor T breaks again at the reclosing moment, which is recorded as mode 8, i.e., the reclosing mode 2.

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