Partition estimation-based non-linear digital background correction method for operational amplifier

Abstract

The invention discloses an operational amplifier nonlinear digital background correction method based on partition estimation, and the method comprises the steps: carrying out the multi-round iteration estimation of a multi-order gain compensation coefficient of an analog-to-digital converter, and stopping the iteration until all first-order coefficient estimation values are the same; in the process of the nth round of iterative estimation, the modules are sequentially used for correcting an output code to obtain a correction code of the (n + 1) th round according to the first-order and high-order coefficient estimated values of the nth round, namely the estimated values of the first-order and high-order gain compensation coefficients; performing partition processing on the correction code of the (n + 1) th round to obtain M partition codes of the (n + 1) th round; determining a first-order coefficient estimation value of the (n + 1) th round according to the partition code of the (n + 1) th round; and determining the high-order coefficient estimation value of the (n + 1) th round according to the difference of the first-order coefficient estimation values of the (n + 1) th round. According to the invention, circuit conciseness and calibration precision can be considered at the same time.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to a method for nonlinear digital back-end correction of operational amplifiers based on partition estimation. Background Technology

[0002] In recent years, with the widespread deployment of 5G technology, the demand for high-performance analog-to-digital converters (ADCs) has increased dramatically. Especially in communication base stations, ADCs need to possess extremely high spurious-free dynamic range (SFDR) and signal-to-noise and distortion ratio (SNDR) to ensure clear transmission and reception of wireless signals. Pipelined-Successive Approximation Analog-to-Digital Converters (Pipelined-SAR ADCs), with their excellent balance between accuracy, speed, and power consumption, have become the preferred architecture for high-speed, high-precision system-level applications. However, unavoidable process variations, such as inter-stage gain errors and operational amplifier nonlinearity errors, severely affect ADC performance. Therefore, continuous calibration using digital back-end correction algorithms is typically employed to optimize the impact of these non-ideal factors.

[0003] With advancements in manufacturing processes, the shrinking of process nodes leads to a decrease in power supply voltage and intrinsic gain of transistors, making the design of traditional closed-loop analog-to-digital converters (ADCs) with high bandwidth, high gain, and low power consumption a major challenge in high-speed ADC design. In contrast, open-loop ADCs, due to their simplified differential stage design, can significantly reduce power consumption and improve response speed without sacrificing gain. This design does not involve complex feedback structures, thus simplifying circuit design and reducing power consumption. However, when using dynamic ADCs in high-precision ADCs, insufficient linearity becomes a key factor affecting the overall system performance. Some traditional op-amp linearity calibration devices have simple structures but limited calibration effects; many others perform well in improving linearity, but their implementation mechanisms are complex, significantly increasing power consumption.

[0004] Therefore, current back-end calibration devices cannot simultaneously achieve both structural simplicity and calibration accuracy. Summary of the Invention

[0005] This invention provides a method for nonlinear digital back-end correction of operational amplifiers based on partition estimation, which can solve the above-mentioned problems.

[0006] In a first aspect, embodiments of the present invention provide a method for correcting the nonlinear digital backend of an operational amplifier based on partition estimation, comprising: The multi-order gain compensation coefficients of the analog-to-digital converter are iteratively estimated in multiple rounds until all first-order coefficient estimates in the current round are the same. The iteration stops then, and the output code of the analog-to-digital converter is corrected based on the first-order and higher-order coefficient estimates in the last round to obtain the correction code. The first-order and higher-order coefficient estimates are the estimates of the first-order and higher-order gain compensation coefficients, respectively. The process of iteratively estimating the multi-order gain compensation coefficients in the nth round includes: The output code is corrected based on the first-order and higher-order coefficient estimates of the nth round to obtain the correction code of the (n+1)th round. The correction code of the (n+1)th round is partitioned to obtain M partition codes of the (n+1)th round; Determine the first-order coefficient estimate of the m+1th round based on the partition code of the mth round; Based on the difference between the first-order coefficient estimates in the (n+1)th round, the higher-order coefficient estimates in the (n+1)th round are determined. Secondly, embodiments of the present invention provide an operational amplifier nonlinear digital backend correction device based on partition estimation, including a compensation module, a partitioning module, M first-order inter-stage gain error modules, and a higher-order coefficient estimation module; The compensation module, partitioning module, inter-stage gain error module, and higher-order coefficient estimation module are used to perform multiple rounds of iterative estimation of the multi-order gain compensation coefficients of the analog-to-digital converter until all first-order coefficient estimates in this round are the same, at which point the iteration stops. The compensation module is also used to correct the output code of the analog-to-digital converter based on the first-order and higher-order coefficient estimates in the last round to obtain the correction code. The first-order and higher-order coefficient estimates are the estimates of the first-order and higher-order gain compensation coefficients, respectively. In the process of iteratively estimating the multi-order gain compensation coefficients in the nth round, the compensation module is used to correct the output code based on the first-order and higher-order coefficient estimates in the nth round to obtain the correction code in the (n+1)th round; the partitioning module is used to partition the correction code in the (n+1)th round to obtain M partition codes in the (n+1)th round; the mth inter-level gain error module is used to determine the first-order coefficient estimate in the (m)th (n+1)th round based on the partition code in the (m)th (n+1)th round; and the higher-order coefficient estimation module is used to determine the higher-order coefficient estimate in the (n+1)th round based on the difference between the first-order coefficient estimates in the (n+1)th round.

[0007] The beneficial effects of this invention compared to existing technologies are as follows: This invention estimates higher-order gain compensation coefficients by the difference in first-order gain compensation coefficients, instead of introducing additional pseudo-random sequence (PN) codes to estimate gain error coefficients using a pseudo-random binary sequence generator (PRBS) as in the interstage gain error (IGE) method. This reduces the number of random sequence generators in the circuit. Furthermore, the difference operation can be implemented using a simple digital circuit like an adder, reducing the overhead of analog circuits and simplifying the circuit structure. Moreover, by estimating the first-order and higher-order gain compensation coefficients and correcting and compensating the ADC output code based on the estimated coefficient values, the first-order error and nonlinear higher-order error in the output code can be eliminated, improving calibration accuracy while balancing structural simplicity and calibration accuracy. Attached Figure Description

[0008] Figure 1 A schematic diagram of the structure of an operational amplifier nonlinear digital back-end correction device based on partition estimation provided in an embodiment of the present invention; Figure 2 A flowchart illustrating the implementation of an operational amplifier nonlinear digital back-end correction method based on partition estimation, provided in an embodiment of the present invention; Figure 3 A schematic diagram of the nonlinear error of an operational amplifier provided in an embodiment of the present invention; Figure 4 A schematic diagram illustrating the second-order and third-order nonlinear errors of an operational amplifier provided in an embodiment of the present invention; Figure 5 A schematic diagram of the specific structure of an operational amplifier nonlinear digital back-end correction device based on partition estimation provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of a correction block provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the structure of an IGE module provided in an embodiment of the present invention; Figure 8 This is a schematic diagram illustrating the variation of a first-order coefficient estimate with the number of iterations, provided by an embodiment of the present invention. Figure 9 This is a schematic diagram comparing the Fourier transform results of the ADC output code and the correction code provided in an embodiment of the present invention. Detailed Implementation

[0009] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of the invention. However, those skilled in the art will understand that the invention can be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of the invention with unnecessary detail.

[0010] It should be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0011] It should also be understood that the term “and / or” as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0012] As used in this specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0013] Furthermore, in the description of this invention and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0014] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of the invention include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0015] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0016] Example 1 Figure 1 The diagram shown is a structural schematic of an operational amplifier nonlinear digital backend correction device based on partition estimation provided in an embodiment of the present invention. As an example and not a limitation, the device may include a compensation module 110, a partitioning module, M first-order inter-stage gain error modules 130, and a higher-order coefficient estimation module 140.

[0017] For example, the compensation module 110 can correct the ADC output code based on the first-order coefficient estimate and the higher-order coefficient estimate of the nth round to obtain the correction code of the (n+1)th round; the partitioning module 120 can partition the correction code of the (n+1)th round according to the voltage magnitude to obtain M partition codes of the (n+1)th round; the mth interstage gain error module 130 can estimate the first-order coefficient estimate of the mth (n+1)th round based on the partition code of the mth (n+1)th round; the higher-order coefficient estimation module can estimate the higher-order coefficient estimate of the (n+1)th round based on the difference between the first-order coefficient estimates of the (n+1)th round. The compensation module 110, partitioning module 120, inter-stage gain error module 130, and higher-order coefficient estimation module 140 can continuously repeat the iterative estimation of the first-order and higher-order gain compensation coefficients until the first-order coefficient estimates output by each inter-stage gain error module 130 are equal. After that, the compensation module 110 corrects the ADC output code based on the first-order and higher-order coefficient estimates of the last round to obtain a gain-stable correction code. At this time, each value represented by the correction code is a constant multiple of the input signal voltage value.

[0018] For example, the first-order and higher-order coefficient estimates refer to the estimates of the first-order and higher-order gain compensation coefficients, respectively.

[0019] Specifically, see Figure 1 The first input terminal of the compensation module 110 is connected to the output terminal of the ADC. The second and third input terminals are respectively connected to the output terminals of an inter-stage gain error module 130 (e.g., the first one) and a higher-order coefficient estimation module 140. The output terminal is connected to the input terminal of the partitioning module 120. The m-th output terminal of the partitioning module 120 is connected to the input terminal of the m-th inter-stage gain error module 130. The output terminal of each inter-stage gain error module 130 is connected to the input terminal of the higher-order coefficient estimation module 140.

[0020] This invention estimates higher-order gain compensation coefficients by the difference of first-order gain compensation coefficients, instead of introducing additional PN codes through PRBS to estimate gain error coefficients as in the IGE method. This reduces the number of random sequence generators in the circuit. Furthermore, the difference operation can be implemented using a simple digital circuit like an adder, reducing the overhead of analog circuits and simplifying the circuit structure. Moreover, by estimating the first-order and higher-order gain compensation coefficients, and correcting and compensating the ADC output code based on the estimated gain compensation coefficients, the first-order error and nonlinear higher-order error in the output code can be eliminated, improving calibration accuracy while balancing structural simplicity and calibration precision.

[0021] Example 2 Figure 2 The diagram illustrates a flowchart of an operational amplifier nonlinear digital back-end correction method based on partition estimation, provided by an embodiment of the present invention. This method is illustrative and not limiting, and can be applied to the operational amplifier nonlinear digital back-end correction device based on partition estimation in Embodiment 1 above. The method includes steps S201-S205, which are described below.

[0022] S201, based on the estimated first-order and higher-order coefficients of the nth round, correct the output code to obtain the correction code for the (n+1)th round.

[0023] In one possible implementation, the value of M can be determined based on the order of the highest-order error between the ADC output code and the voltage value of the input signal.

[0024] Generally, with M=3, the nonlinear relationship between the ADC output code and the voltage value of the input signal can be represented by a third-order polynomial. In this case, the higher-order gain compensation coefficients can include second-order gain compensation coefficients. and third-order gain compensation coefficient .

[0025] For example, if the ADC output code Voltage value of the input signal Through third-order polynomials For details, please refer to [link / reference]. Figure 3 ADC gain The input signal voltage value can be expressed by a second-order polynomial with non-zero coefficients in the first-order term (the derivative of this third-order polynomial): express.

[0026] In one example, the correction code for the (n+1)th round can satisfy the following formula: (1.1) in, This is the correction code for the (n+1)th round. For output code, This represents the second-order coefficient estimate for the nth round. This is the estimated value of the third-order coefficients for the nth round. This is the estimated value of the first-order coefficient for the first nth round.

[0027] S202, partition the correction code of the (n+1)th round to obtain M partition codes of the (n+1)th round.

[0028] In one example, see Figure 3 It can be used as The central area As the first voltage partition, and the two symmetrical intervals before and after this neighborhood respectively. , As the second and third voltage partitions, they are partitioned according to the voltage value of the (n+1)th round of correction code.

[0029] For example, It can be greater than or equal to the absolute value of the minimum or maximum value of the input signal voltage.

[0030] S203, estimate the first-order coefficients of the m-th (n+1)-th round based on the partition code of the m-th (n+1)-th round.

[0031] In one example, the first-order coefficient estimates of the partition code for each (n+1)th round can be estimated using the IGE algorithm. See also Figure 3 Since the IGE algorithm, based on least squares estimation, can only obtain first-order coefficient estimates, i.e., the mean gain within each partition, rather than the actual gain value, step S204 is also required to estimate the second-order and third-order gain compensation coefficients based on the difference in gain between each partition.

[0032] S204. Based on the difference between the first-order coefficient estimates of round n+1, determine the higher-order coefficient estimates of round n+1.

[0033] In one example, the higher-order gain compensation coefficient for the (n+1)th round can be estimated using the following formula: (1.2) (1.3) in: (1.4) (1.5) This is the estimated value of the second-order coefficients for the (n+1)th round. This represents the second-order coefficient estimate for the nth round. The iteration step size used to drive the convergence of the second-order gain compensation coefficients, This is the first-order coefficient estimate for the m-th round n. This is the estimated value of the third-order coefficients for the (n+1)th round. This is the estimated value of the third-order coefficients for the nth round. The iteration step size used to drive the convergence of the third-order gain compensation coefficients.

[0034] For example, the curve of gain versus input signal voltage can be decomposed into, as shown below. Figure 4 The first-order terms shown in (a) and (b) are as follows. and second-order terms ,Depend on Figure 4 It can be seen that, through the error term The slope of the second-order curve can be obtained. ; through error terms Multiples of the second-order curve can be obtained. .

[0035] S205, determine whether the first-order coefficient estimates for the (n+1)th round are all equal.

[0036] In one example, if the first-order coefficient estimates in round n+1 are all equal, the iteration can be stopped, and the first-order and higher-order coefficient estimates in round n+1 can be output.

[0037] In another example, if the first-order coefficient estimates in the (n+1)th round are not all equal, we can let n = n+1 and start the next round of iteration from step S201.

[0038] Through continuous iterations of steps S201-S205, the estimates of the second and third order coefficients will gradually converge to... , The true value, Approaching reality Meanwhile, ERR2 and ERR1 approach zero, thus completing the calibration of the op-amp's nonlinearity.

[0039] Example 3 Based on Example 2, Figure 5 The diagram shown is a schematic representation of a specific structure of an operational amplifier nonlinear digital back-end correction device based on partition estimation, provided in an embodiment of the present invention.

[0040] In one possible implementation, see Figure 5 The compensation module 110 may include a correction block 111, a random sequence generator 112, and a first adder 113.

[0041] For example, the correction block 111 can compensate for the first-order error and nonlinear error of the output code based on the first-order and higher-order coefficient estimates of the nth round to obtain the compensation code for the (n+1)th round. The random sequence generator 112 outputs a digital signal of a PN sequence. The first adder 113 sums and- Obtain the correction code for the (n+1)th round. .

[0042] Specifically, see Figure 5 The first to third input terminals of the correction block 111 can be used as the first to third input terminals of the compensation module 110, and the output terminal can be connected to the first input terminal of the first adder 113. The output terminal of the random sequence generator 112 is connected to the second input terminal of the first adder 113, and the output terminal of the first adder 113 serves as the output terminal of the compensation module 110.

[0043] In one example, see Figure 6 The correction block 111 may include a cube calculator 1111, a first multiplier 1112, a square calculator 1113, a second multiplier 1114, a second adder 1115, a third adder 1116, a third multiplier 1117, and a first delay unit 1118.

[0044] For example, the cube calculator 1111 can calculate the square value of the output code. The first multiplier 1112 calculates the product of the third-order coefficient estimate and the cube value in the nth round, obtaining the cube product. The square calculator 1113 calculates the square value of the output code. The second multiplier 1114 calculates the square value. The product of the second-order coefficient estimate in the nth round is the square product. The second adder 1115 calculates the sum of the square product and the cube product to obtain the first sum term. The third adder 1116 calculates the sum of the first sum term and the output code to obtain the second sum term. The first delay unit 1118 stores and sends the reciprocal of the first-order coefficient estimate to the third multiplier 1117 in the first nth round. The third multiplier calculates The product of the second summation term and the corrected code for the (n+1)th round is obtained. .

[0045] Specifically, see Figure 6The first input terminals of the cube calculator 1111, the square calculator 1113, and the third adder 1116 can serve as the first input terminals of the compensation module 110. The output terminal of the cube calculator 1111 is connected to the first input terminal of the first multiplier 1112. The second input terminals of the first multiplier 1112 and the second multiplier 1114 serve as the third input terminals of the compensation module 110. The output terminal of the first multiplier 1112 is connected to the first input terminal of the second adder 1115. The output terminal of the square calculator 1113 is connected to the second multiplier 1116. The first input terminal of the first multiplier 1114 is connected to the second input terminal of the second multiplier 1115, and the output terminal of the second multiplier 1115 is connected to the second input terminal of the third multiplier 1116. The output terminal of the third multiplier 1116 is connected to the first input terminal of the third multiplier 1117. The input terminal of the first delay unit 1118 serves as the second input terminal of the compensation module 110, and its output terminal is connected to the second input terminal of the third multiplier 1117. The output terminal of the third multiplier 1117 serves as the output terminal of the compensation module 110.

[0046] In one possible implementation, see Figure 7 The interstage gain error module 130 can use a traditional IGE module to calculate the first-order gain compensation coefficient based on the following formula (1.6).

[0047] (1.6) in, , These are the first-order coefficient estimates for the m-th (n+1)th and n-th rounds, respectively. The iteration step size to drive gain convergence, This is the output code of the m-th (n+1)th round.

[0048] In one possible implementation, the higher-order coefficient estimation module 140 may include a parallel second-order coefficient estimation submodule 141 and a third-order coefficient estimation submodule 142, which are used to estimate the second-order and third-order gain compensation coefficients, respectively.

[0049] In one example, see Figure 5 The second-order coefficient estimation submodule 141 may include a fourth adder 1411, a fourth multiplier 1412, a fifth adder 1413, and a second delay 1414.

[0050] For example, the fourth adder 1411 is used to calculate the difference between the first-order coefficient estimates of the second and third nth rounds to obtain the error term. The fourth multiplier 1412 is used to calculate the error value. and The product of these terms yields the first product term. The fifth adder 1413 is used to calculate the second-order coefficient estimate of the first product term and the nth round. The sum yields the second-order coefficient estimate for the (n+1)th round. The second delay unit 1414 is used to store the second-order coefficient estimate for the (n+1)th round. and output to the fifth adder 1413 .

[0051] Specifically, see Figure 5 The input of the fourth adder 1411 is one input of the second-order coefficient estimation submodule 141 and the higher-order coefficient estimation module 140. The output is connected to the input of the fourth multiplier 1412. The output of the fourth multiplier 1412 is connected to the first input of the fifth adder 1413. The output of the fifth adder 1413 is connected to the input of the second delay unit 1414. The output of the second delay unit 1414 is connected to the second input of the fifth adder 1413.

[0052] In one example, see Figure 5 Similarly, the third-order coefficient estimation submodule 142 may include a sixth adder 1421, a fifth multiplier 1422, a seventh adder 1423, and a third delay 1424.

[0053] For example, the sixth adder 1421 calculates the difference between the mean of the first-order coefficient estimates of the first nth round and the first-order coefficient estimates of the second and third nth rounds, and obtains the error term. The fifth multiplier 1422 calculates the error term. and The product of these terms yields the second product term. The seventh adder 1423 calculates the estimated third-order coefficients of the second product term and the nth round. The sum yields the estimated third-order coefficients for the (n+1)th round. The third delay is used to store the third-order coefficient estimates for the (n+1)th round. And output the estimated third-order coefficients of the nth round to the seventh adder 1423. .

[0054] Specifically, see Figure 5 The input of the sixth adder 1421 is one input of the third-order coefficient estimation submodule 142 and the higher-order coefficient estimation module 140. The output is connected to the input of the fifth multiplier 1422. The output of the fifth multiplier 1422 is connected to the first input of the seventh adder 1423. The output of the seventh adder 1423 is connected to the input of the third delay unit 1424. The output of the third delay unit 1424 is connected to the second input of the seventh adder 1423.

[0055] This invention estimates higher-order gain compensation coefficients by the difference in first-order gain compensation coefficients, instead of introducing additional PN codes via PRBS as in the IGE method to estimate gain error coefficients. This reduces the number of random sequence generators in the circuit. Furthermore, the difference operation can be implemented using a simple digital circuit like an adder, reducing the overhead of analog circuitry and simplifying the circuit structure. By estimating the first-order and higher-order gain compensation coefficients and then correcting and compensating the ADC output code based on these estimated coefficients, first-order errors and nonlinear higher-order errors in the output code can be eliminated, improving calibration accuracy while maintaining structural simplicity and calibration precision. In addition, the partitioning of digital codes can be affected by operational amplifier nonlinearity and inter-stage gain errors, leading to inaccurate separation. Therefore, a compensation module calibrates the digital codes before classification. As iterations proceed, the nonlinearity correction coefficients and inter-stage gain compensation coefficients gradually approach their correct values, continuously improving partitioning accuracy and forming a positive feedback mechanism, thereby enhancing the calibration accuracy and robustness of the device.

[0056] To better illustrate the beneficial effects of the present invention, the following simulation experiments were conducted: For example, in simulation experiments, the following methods are used: Figure 8 The conventional dynamic amplifier with common-mode detection module shown is used as the ADC to be calibrated, and its output code is calibrated using the device provided in this invention.

[0057] See Figure 8 A schematic diagram showing the change of the estimated first-order coefficients with the number of iterations. Figure 9 Figures (a) and (b) show the Fourier transform results of the ADC output code and the correction code, respectively. It can be seen that when the iteration reaches 2.5M, the first-order gain compensation coefficient successfully converges, and the device provided by this invention completes the calibration of the first, second, and third-order errors of the operational amplifier. Furthermore, after calibration, the ADC's SNDR is improved by 13.5dB, while the SFDR is improved by 16.2dB. This indicates that this invention effectively eliminates the effects of nonlinearity, resulting in a cleaner and smoother noise floor.

[0058] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

Claims

1. A method for correcting the nonlinear digital backend of an operational amplifier based on partition estimation, characterized in that, include: The multi-order gain compensation coefficients of the analog-to-digital converter are iteratively estimated in multiple rounds until all first-order coefficient estimates in the current round are the same. The iteration stops then, and the output code of the analog-to-digital converter is corrected based on the first-order and higher-order coefficient estimates in the last round to obtain the correction code. The first-order and higher-order coefficient estimates are the estimates of the first-order and higher-order gain compensation coefficients, respectively. The process of iteratively estimating the multi-order gain compensation coefficients in the nth round includes: The output code is corrected based on the first-order and higher-order coefficient estimates of the nth round to obtain the correction code of the (n+1)th round. The correction code of the (n+1)th round is partitioned to obtain M partition codes of the (n+1)th round; Determine the first-order coefficient estimate of the m+1th round based on the partition code of the mth round; The higher-order coefficient estimates for the (n+1)th round are determined based on the difference between the first-order coefficient estimates for the (n+1)th round.

2. The method according to claim 1, characterized in that, M=3, the higher-order gain compensation coefficients include second-order gain compensation coefficients. and third-order gain compensation coefficient .

3. The method according to claim 2, characterized in that, The correction code for the (n+1)th round satisfies the following formula: in, This is the correction code for the (n+1)th round. The output code is... This represents the second-order coefficient estimate for the nth round. This is the estimated value of the third-order coefficients for the nth round. This is the estimated value of the first-order coefficient for the first nth round.

4. The method according to claim 2, characterized in that, The estimated higher-order coefficients of the (n+1)th round satisfy the following formula: in: This is the estimated value of the second-order coefficients for the (n+1)th round. This represents the second-order coefficient estimate for the nth round. The iteration step size used to drive the convergence of the second-order gain compensation coefficients, This is the estimated value of the first-order coefficient for the m-th round n. This is the estimated value of the third-order coefficients for the (n+1)th round. This is the estimated value of the third-order coefficients for the nth round. The iteration step size used to drive the convergence of the third-order gain compensation coefficient.

5. A nonlinear digital back-end correction device for operational amplifiers based on partition estimation, characterized in that, It includes a compensation module, a partitioning module, M first-order inter-stage gain error modules, and a higher-order coefficient estimation module; The compensation module, partitioning module, inter-stage gain error module, and higher-order coefficient estimation module are used to perform multiple rounds of iterative estimation of the multi-order gain compensation coefficients of the analog-to-digital converter until all first-order coefficient estimates in this round are the same, at which point the iteration stops. The compensation module is also used to correct the output code of the analog-to-digital converter based on the first-order and higher-order coefficient estimates in the last round to obtain the correction code. The first-order and higher-order coefficient estimates are the estimates of the first-order and higher-order gain compensation coefficients, respectively. In the process of iteratively estimating the multi-order gain compensation coefficients in the nth round, the compensation module is used to correct the output code based on the first-order and higher-order coefficient estimates in the nth round to obtain the correction code in the (n+1)th round; the partitioning module is used to partition the correction code in the (n+1)th round to obtain M partition codes in the (n+1)th round; the mth inter-level gain error module is used to determine the first-order coefficient estimate in the (m)th (n+1)th round based on the partition code in the (m)th (n+1)th round; and the higher-order coefficient estimation module is used to determine the higher-order coefficient estimate in the (n+1)th round based on the difference between the first-order coefficient estimates in the (n+1)th round.

6. The apparatus according to claim 5, characterized in that, The compensation module includes: A correction block is used to compensate for the first-order error and nonlinear error of the output code based on the first-order and higher-order coefficient estimates of the nth round, so as to obtain the preliminary compensation code of the (n+1)th round. A random sequence generator, the random sequence generator being used to generate random codewords in binary; A first adder is used to sum the preliminary compensation code of the (n+1)th round and the random codeword to obtain the correction code of the (n+1)th round.

7. The apparatus according to claim 6, characterized in that, M=3, the higher-order gain compensation coefficients include second-order gain compensation coefficients. and third-order gain compensation coefficient ; The correction block includes: A cube calculator, used to calculate the cube value of the output code; The first multiplier is used to calculate the product of the third-order coefficient estimate of the nth round and the cube value to obtain the cube product; A square calculator, used to calculate the square value of the output code; The second multiplier is used to calculate the product of the second-order coefficient estimate of the nth round and the squared value to obtain the squared product; The second adder is used to calculate the sum of the square product and the cube product to obtain the first sum term; A third adder is used to calculate the sum of the first summation term and the output code to obtain the second summation term; A first delay unit is used to store and output the reciprocal of the first-order coefficient estimate of the first nth round; The third multiplier is used to calculate the product of the reciprocal of the first-order coefficient estimate of the first nth round and the second summation term to obtain the correction code of the (n+1)th round.

8. The apparatus according to claim 7, characterized in that, The higher-order coefficient estimation module includes: The second-order coefficient estimation submodule is used to estimate the second-order coefficient estimate of the (n+1)th round based on the difference between the first-order coefficient estimates of the 2nd and 3rd rounds. The third-order coefficient estimation submodule is used to estimate the second-order coefficient estimates of the (n+1)th round using all the first-order coefficient estimates of the nth round.

9. The apparatus according to claim 8, characterized in that, The second-order coefficient estimation submodule includes: The fourth adder is used to calculate the difference between the first-order coefficient estimates of the 2nd and 3rd nth rounds, thus obtaining the error term. ; A fourth multiplier is used to calculate the error term. With iteration step size The product of these terms yields the first product term; The fifth adder is used to calculate the sum of the first product term and the third-order coefficient estimate of the nth round to obtain the second-order coefficient estimate of the (n+1)th round. The second delay unit is used to store the second-order coefficient estimate of the (n+1)th round and output the third-order coefficient estimate of the nth round to the fifth adder.

10. The apparatus according to claim 8, characterized in that, The third-order coefficient estimation submodule includes: The sixth adder is used to calculate the difference between the first-order coefficient estimate of the first nth round and the mean of the first-order coefficient estimates of the second and third nth rounds, thus obtaining the error term. ; A fifth multiplier, which is used to calculate the error term. With iteration step size The product of these terms yields the second product term. The seventh adder is used to calculate the sum of the second product term and the second-order coefficient estimate of the nth round to obtain the third-order coefficient estimate of the (n+1)th round. The third delay unit is used to store the third-order coefficient estimate of the (n+1)th round and output the coefficient estimate of the nth round to the seventh adder.

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