Coding method of IRA-LDPC code for DVB-S2 / S2X protocol

Abstract

The embodiment of the invention provides a coding method of an IRA-LDPC code for a DVB-S2 / S2X protocol, and the method comprises the steps: carrying out the preprocessing of each code rate check matrix under the DVB-S2 / S2X protocol, and generating a basic shift matrix of a system part and an index of the basic shift matrix; segmenting the check bit twice, and generating and storing a lookup table by taking the length of the check bit segmented twice as table lookup parallelism; determining a table lookup index value according to the basic shift matrix of the system part and the index of the basic shift matrix, and performing value lookup on the lookup table according to the table lookup index value; determining a target check bit according to the searched check bit value, extracting the target check bit at an interval preset length and interleaving and rearranging to obtain a check sequence, outputting the check sequence to the tail of a system bit as a coding result, and compressing a check matrix through a basic shift matrix and a lookup table to obtain a coding result. And in the encoding process, vector multiplication and addition are replaced by a table look-up method and a cyclic shift method, so that the encoding complexity is low and the encoding efficiency is high.

Description

Technical Field

[0001] This application relates to the field of channel coding technology for wireless communication systems, and more specifically, to an encoding method for IRA-LDPC codes used in the DVB-S2 / S2X protocol. Background Technology

[0002] The DVB-S2X (Digital Video Broadcasting-Satellite Second Generation Extension) protocol, with its high spectral efficiency and flexible modulation and coding schemes (supporting up to 256 APSK, i.e., 256 levels of amplitude-phase joint keying), has become the mainstream choice for satellite ultra-high-definition video broadcasting. For example, several European satellite operators have adopted the DVB-S2X protocol to transmit 4K / 8K programs, supporting the high-quality video needs of home and enterprise users. Furthermore, the DVB-S2X protocol's Adaptive Coding and Modulation (ACM) function can dynamically adjust parameters according to channel conditions, ensuring stable transmission even in remote areas with weak signals.

[0003] The IRA-LDPC (Irregular Repeat-Accumulate Low-Density Parity-Check) encoder, as a core component of the DVB-S2X protocol, has seen continuous breakthroughs in hardware architecture and algorithm optimization.

[0004] However, the following problems are encountered when implementing IRA-LDPC encoding in the DVB-S2X protocol: the large number of code rates and code pattern combinations supported by the protocol leads to huge storage requirements for the corresponding parity check matrix, which in turn causes technical difficulties such as high encoding complexity and low encoding efficiency. Summary of the Invention

[0005] This application provides an encoding method for IRA-LDPC codes used in the DVB-S2 / S2X protocol.

[0006] A first aspect of this application provides an encoding method for IRA-LDPC codes used in the DVB-S2 / S2X protocol, comprising:

[0007] Preprocess the rate check matrices of each code rate check matrix under the DVB-S2 / S2X protocol to generate and store the basic shift matrix and its index of the system part;

[0008] Divide the parity bit into q segments to obtain the parity bit after the first segmentation. Divide each parity bit after the first segmentation into u segments to obtain the parity bit after the second segmentation. Use the length of the parity bit after the second segmentation as the lookup parallelism. Generate and store the lookup table based on the lookup parallelism.

[0009] The lookup table index value is determined based on the basic shift matrix and its index of the system part, and the lookup table is retrieved based on the lookup table index value;

[0010] The target parity bit is determined based on the found parity bit value. The target parity bit is extracted and interleaved at a preset length interval to obtain the parity sequence, which is output to the end of the system bits as the encoding result.

[0011] In an optional embodiment of this application, the preprocessing of the rate check matrices under the DVB-S2 / S2X protocol to generate and store the basic shift coefficients includes:

[0012] The parity check matrix H is split to obtain submatrices H0. s and H p And the verification formula H s *s=H p *p, where s and p are the system bits and parity bits, respectively, and the submatrix H s and H p The dimensions are [nk, k] and [nk, nk], respectively, where k is the number of information symbols and n is the total number of symbols;

[0013] For each submatrix H s and H p Extracting and rearranging rows at intervals of q, yields a matrix. and

[0014] For matrix Extracting and rearranging columns at intervals of q yields a matrix.

[0015] The parity bits are extracted and rearranged at intervals of q to obtain matrix p. shift ;

[0016] Extract the matrix respectively and The cyclic shift values ​​corresponding to each element in the matrix are obtained, and the 0 values ​​in the matrix are replaced by -1 to obtain the basic shift matrix of the system part and the verification part, and stored. The elements of the basic shift matrix are the basic shift coefficients.

[0017] In an optional embodiment of this application, the step of using the length of the parity bits after secondary segmentation as the lookup table parallelism, and generating and storing the lookup table according to the lookup table parallelism, includes:

[0018] Lookup table LUT_TRI V and LUT_O v TRI are matrices of dimension v×v. V and O v :

[0019]

[0020] Where v is the length of the parity bits after the second segmentation.

[0021] In an optional embodiment of this application, determining the lookup index value according to the system portion's basic shift matrix and its index includes:

[0022] After solving the i-th segment, check the bit. In the case of, respectively And λ(i*v+(0:v-1)) as the lookup table LUT_TRI V and LUT_O v The lookup index value is given by , where i is any value from 1 to u, and v is the length of the parity bits after the second segmentation.

[0023]

[0024] Where l is the number of segments in the system bit s, q and l are both positive integers greater than or equal to 1, and κ q-1，l-1 The basic shift matrix elements of the system part index, The basic shift matrix elements of the system part Sub-code blocks s of system bits s l-1 The cyclic shift matrix.

[0025] In an optional embodiment of this application, the cyclic shift matrix of the basic shift matrix elements of the system portion with respect to the sub-code block of system bits s is obtained through the following steps:

[0026] The sub-code blocks of system bits s are divided into segments u using the following expression:

[0027]

[0028] v = M / u

[0029] M = (nk) / q

[0030] Among them, s j Let M be the sub-code block of system bits s, and M be the length of the sub-code block.

[0031] The basic shift matrix elements of the system are partitioned using the following expression:

[0032]

[0033] in, h is the basic shift matrix element of the system part. ceil h is the integer value of the element. floor h is the floor value of the element. mod The modulo value of the element.

[0034] The following expressions are used to segment the sub-code blocks by rounding up and down the elements, respectively. Perform a circular shift:

[0035]

[0036]

[0037] in, and These are intermediate shift results obtained by cyclically shifting the sub-code block of system bit s using the rounded-up and rounded-down values, respectively.

[0038] The following expression concatenates intermediate shift results, shifts the concatenated matrix according to the modulo values ​​of its elements, and extracts the low v bits of the shifted matrix:

[0039]

[0040] in, For segmented sub-code blocks The corresponding circular shift vector, For subcode block s j The corresponding cyclic shift matrix.

[0041] In an optional embodiment of this application, the lookup table is retrieved based on the lookup index value using the following expression:

[0042]

[0043] Where bi2de is the binary to decimal conversion function.

[0044] In an optional embodiment of this application, determining the target parity bit based on the found parity bit value includes:

[0045] Based on the value of i, the check bits are calculated after the i-th segment is divided into two segments. Perform u iterations to obtain the first set of verification sequences.

[0046] The target parity bit is obtained from the first set of parity sequences using the following expression:

[0047]

[0048] Where, p shift For the target parity bit, For the other groups of check sequences, λ1~λ l-1 This is the check value.

[0049] A second aspect of this application provides an encoding apparatus for IRA-LDPC codes of the DVB-S2 / S2X protocol, comprising:

[0050] The generation module is used to preprocess the rate check matrices under the DVB-S2 / S2X protocol, generate and store the basic shift matrix and its index of the system part;

[0051] The segmentation module is used to divide the parity bit into q segments to obtain the parity bit after the first segmentation. Each parity bit after the first segmentation is divided into u segments to obtain the parity bit after the second segmentation. The length of the parity bit after the second segmentation is used as the lookup parallelism. A lookup table is generated and stored based on the lookup parallelism.

[0052] The table lookup module is used to determine the table lookup index value according to the basic shift matrix and its index of the system part, and to look up the value of the lookup table according to the table lookup index value;

[0053] The determination module is used to determine the target parity bit based on the found parity bit value, extract and interleave the target parity bit at a preset interval to obtain the parity sequence, and output it to the end of the system bits as the encoding result.

[0054] A third aspect of this application provides a computer device, including: a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of any of the above encoding methods for IRA-LDPC codes for the DVB-S2 / S2X protocol.

[0055] A fourth aspect of this application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the encoding method for IRA-LDPC code for the DVB-S2 / S2X protocol as described in any of the preceding claims.

[0056] Compared with the prior art, the technical solutions provided in this application have at least some or all of the following advantages:

[0057] The encoding method for IRA-LDPC codes used in the DVB-S2 / S2X protocol described in this application preprocesses the rate parity check matrices under the DVB-S2 / S2X protocol to generate and store the basic shift matrix and its index for the system part; divides the parity bits into q segments to obtain the parity bits after the first segmentation; divides each parity bit after the first segmentation into u segments to obtain the parity bits after the second segmentation; uses the length of the parity bits after the second segmentation as the lookup table parallelism; generates and stores the lookup table based on the lookup table parallelism; determines the lookup table index value according to the basic shift matrix and its index for the system part; and performs a lookup on the lookup table based on the lookup table index value; determines the target parity bit based on the found parity bit value; extracts and interleaves the target parity bit at a preset interval to obtain the parity sequence; outputs it to the end of the system bits as the encoding result; compresses the parity matrix by generating the basic shift matrix and the lookup table; and replaces vector multiplication and addition with lookup table method and cyclic shift method during the encoding process, resulting in low encoding complexity and high encoding efficiency. Attached Figure Description

[0058] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0059] Figure 1 A flowchart illustrating an encoding method for IRA-LDPC codes for the DVB-S2 / S2X protocol, provided as an embodiment of this application;

[0060] Figure 2 A flowchart illustrating an encoding method for IRA-LDPC codes for the DVB-S2 / S2X protocol, provided as another embodiment of this application;

[0061] Figure 3 A schematic diagram of an encoding device for IRA-LDPC codes for the DVB-S2 / S2X protocol provided in one embodiment of this application;

[0062] Figure 4 This is a schematic diagram of a computer device structure provided in one embodiment of this application. Detailed Implementation

[0063] In the process of developing this application, the inventors discovered that the current encoding method of IRA-LDPC code used for the DVB-S2 / S2X protocol is poor in terms of efficiency and complexity.

[0064] To address the aforementioned issues, this application provides an encoding method for IRA-LDPC codes used in the DVB-S2 / S2X protocol, thereby improving encoding efficiency and reducing encoding complexity.

[0065] The solutions in this application embodiment can be implemented using various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0066] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0067] Please see Figure 1 and Figure 2 The encoding method for IRA-LDPC codes for the DVB-S2 / S2X protocol provided in this application includes:

[0068] S100 preprocesses the rate check matrices of each code rate check matrix under the DVB-S2 / S2X protocol, and generates and stores the basic shift matrix and its index of the system part.

[0069] S200, divide the parity bit into q segments to obtain the parity bit after the first segmentation, divide each parity bit after the first segmentation into u segments to obtain the parity bit after the second segmentation, use the length of the parity bit after the second segmentation as the lookup parallelism, and generate and store the lookup table according to the lookup parallelism.

[0070] S300, determine the lookup table index value according to the basic shift matrix and its index of the system part, and perform lookup table lookup based on the lookup table index value;

[0071] S400 determines the target parity bit based on the found parity bit value, extracts and interleaves the target parity bit at preset intervals to obtain the parity sequence, and outputs it to the end of the system bits as the encoding result.

[0072] In an optional embodiment of this application, LDPC is a linear block code defined by a parity check matrix H (with dimensions [nk, n]), and the parity check formula for the linear block code is:

[0073] H*c=[0]

[0074] Where c is the codeword, c = [s; p], with dimensions [n, 1]; s is the system bit, with dimensions [k, 1]; p is the parity bit, with dimensions [nk, 1]; and the code rate is k / n.

[0075] Let the parity check matrix be: H = [H s H p ], submatrix H s , HIf the dimensions of p are [nk, k] and [nk, nk], then the following LDPC verification formula exists after splitting the verification matrix:

[0076] H*c=H s *s+H p *p=[0]

[0077] The following transformation of the verification formula is obtained:

[0078] H s *s=H p *p

[0079] According to the definition of the parity check matrix in the DVB-S2 / S2X protocol, H s For sparse matrices:

[0080]

[0081] H p It is a double diagonal matrix:

[0082]

[0083] By analyzing H s H p Extracting and rearranging rows at intervals of q, we get and And the following verification formula after row transformation of the verification matrix:

[0084]

[0085] Through the Extracting and rearranging columns at intervals of q, we obtain Extract and rearrange p rows at intervals of q to obtain p shift And the following verification formula after row and column transformation is obtained:

[0086]

[0087] remember:

[0088]

[0089] submatrix It is composed of 1 to 3 cyclic shift matrices of dimension [M, M] superimposed, or composed of [0] matrices, where:

[0090] M = (nk) / q; l = k / M

[0091] extract Corresponding cyclic shift value Replacing the [0] matrix with -1 yields the fundamental shift coefficient matrix of the polygonal LDPC system:

[0092]

[0093] Similarly, it can be derived from The fundamental shift coefficient matrix of the polynomial LDPC check part is obtained as follows:

[0094]

[0095] Among them, E M Let [M, M] be the identity matrix. Let be matrices of the same dimension, where All other values ​​are 0:

[0096]

[0097] Divide the system bits s into l segments, denoted as:

[0098]

[0099] The interleaved and rearranged parity bits p shift Divided into q segments, denoted as:

[0100]

[0101] Remember κ i，j for Using the basic shift coefficient index, we obtain the following expression for cyclic shifting instead of matrix multiplication:

[0102]

[0103] Based on the fundamental shift coefficient matrix, the following new verification equations consisting of q equations are obtained:

[0104]

[0105] Solving the combined system of equations yields:

[0106]

[0107] remember:

[0108]

[0109] Therefore, we can derive the formula for calculating the first set of parity bits and the parity bits obtained through iterative solution:

[0110]

[0111] Depend on Composition p shift And through p shiftThe encoding algorithm completes by extracting and rearranging the parity sequence p at interval M and outputting it to the end of the system bits s.

[0112] It is worth noting that all calculations in this application are performed within the GF(2) domain, that is, multiplication (*) is a binary AND operation (&), and addition (+) is a binary XOR operation.

[0113] The encoding method for IRA-LDPC codes used in the DVB-S2 / S2X protocol in this application consists of a fundamental coefficient matrix of dimension [q, l]. The replacement verification matrix H has dimensions [nl, k]. s Storage requirements can be changed to The fundamental coefficient matrix corresponding to the parity bits No storage is required, greatly reducing the parameter storage requirements during software and hardware implementation. With M=360 and n=16200, Taking the bit rate as an example, only 125 cyclic shift values ​​and their corresponding indices (i, j) need to be stored, with an effective storage requirement of no more than 375 bytes, which is much lower than the [1800*16200] bits of the parity check matrix H. At the software implementation level, combined with the parity check matrix compression storage scheme of this application, flexible memory storage of encoding parameters can be achieved, which is compatible with parity check matrices of different bit rates / code types. While meeting the IRA-LDPC encoding performance requirements, it shows comprehensive advantages in terms of flexibility, cost control and other aspects.

[0114] In an optional embodiment of this application, step S100, which involves preprocessing the rate check matrices under the DVB-S2 / S2X protocol to generate and store the basic shift coefficients, includes:

[0115] The parity check matrix H is split to obtain submatrices H0. s and H p And the verification formula H s *s=H p *p, where s and p are the system bits and parity bits, respectively, and the submatrix H s and H p The dimensions are [nk, k] and [nk, nk], respectively, where k is the number of information symbols and n is the total number of symbols;

[0116] For each submatrix H s and H p Extracting and rearranging rows at intervals of q, yields a matrix. and

[0117] For matrix Extracting and rearranging columns at intervals of q yields a matrix.

[0118] The parity bits are extracted and rearranged at intervals of q to obtain matrix p. shift ;

[0119] Extract the matrix respectively and The cyclic shift values ​​corresponding to each element in the matrix are obtained, and the 0 values ​​in the matrix are replaced by -1 to obtain the basic shift matrix of the system part and the verification part, and stored. The elements of the basic shift matrix are the basic shift coefficients.

[0120] The encoding method for IRA-LDPC codes used in the DVB-S2 / S2X protocol presented in this application can transform a large parity-check matrix into a polygonal LDPC fundamental shift coefficient matrix form similar to the 5G NR protocol LDPC basic graph. This can be implemented in software, eliminating the need for significant investment in hardware design and manufacturing, requiring only software development investment. This greatly reduces the entry barrier and upfront costs for startups or small-batch application scenarios. Furthermore, in subsequent maintenance, software upgrades can fix vulnerabilities and optimize performance, making maintenance costs far lower than hardware implementation solutions.

[0121] In an optional embodiment of this application, step S200, which uses the length of the parity bits after secondary segmentation as the lookup table parallelism and generates and stores the lookup table according to the lookup table parallelism, includes:

[0122] Lookup table LUT_TRI V and LUT_O v TRI are matrices of dimension v×v. V and O v :

[0123]

[0124] Where v is the length of the parity bits after the second segmentation, TRI V It is a lower triangular matrix, O v It is a matrix of all 1s.

[0125] The encoding method of IRA-LDPC code for DVB-S2 / S2X protocol in this application uses a lookup table method to implement lower triangular matrix multiplication, which can achieve parallelization of lower triangular matrix multiplication with vectors or matrices.

[0126] In an optional embodiment of this application, step S300, determining the lookup index value according to the system's basic shift matrix and its index, includes:

[0127] After solving the i-th segment, check the bit. In the case of, respectively And λ(i*v+(0:v-1)) as the lookup table LUT_TRI V and LUT_O v The lookup index value is given by , where i is any value from 1 to u, and v is the length of the parity bits after the second segmentation.

[0128]

[0129] Where l is the number of segments in the system bit s, q and l are both positive integers greater than or equal to 1, and κq -1，l-1 The basic shift matrix elements of the system part index, The basic shift matrix elements of the system part Sub-code blocks s of system bits s l-1 The cyclic shift matrix.

[0130] The IRA-LDPC encoding method for the DVB-S2 / S2X protocol in this application uses the cyclic shift matrix and vector multiplication, which can be replaced by the cyclic shift of the vector. It can achieve hardware and software combined IRA-LDPC encoding with the help of parallel devices, efficiently parallelize the IRA-LDPC encoding process at the software level, and effectively reduce the instruction execution cycle, reduce the computation latency, and improve the overall performance by optimizing instruction scheduling and pipeline technology.

[0131] In an optional embodiment of this application, the cyclic shift matrix of the basic shift matrix elements of the system portion with respect to the sub-code block of system bits s is obtained through the following steps:

[0132] The sub-code blocks of system bits s are divided into segments u using the following expression:

[0133]

[0134] v = M / u

[0135] M = (nk) / q

[0136] Among them, s j Let M be the sub-code block of system bits s, and M be the length of the sub-code block.

[0137] The basic shift matrix elements of the system are partitioned using the following expression:

[0138]

[0139] in, h is the basic shift matrix element of the system part. ceil h is the integer value of the element. floor h is the floor value of the element. modThe modulo value of the element.

[0140] The following expressions are used to segment the sub-code blocks by rounding up and down the elements, respectively. Perform a circular shift:

[0141]

[0142] in, and These are intermediate shift results obtained by cyclically shifting the sub-code block of system bit s using the rounded-up and rounded-down values, respectively.

[0143] The following expression concatenates intermediate shift results, shifts the concatenated matrix according to the modulo values ​​of its elements, and extracts the low v bits of the shifted matrix:

[0144]

[0145] in, For segmented sub-code blocks The corresponding circular shift vector, For subcode block s j The corresponding cyclic shift matrix.

[0146] The encoding method for IRA-LDPC codes used in the DVB-S2 / S2X protocol of this application divides the long sequence into short sequences during the cyclic shift process. The number of sub-code blocks after segmentation is used as the parallelism. The cyclic shift vector corresponding to each sub-code block after segmentation is calculated in parallel. The cyclic shift of the long sequence is achieved by the parallel shift of the short sequences, so as to quickly obtain the cyclic shift result and thus improve the encoding efficiency.

[0147] In an optional embodiment of this application, piecewise iterative calculation can be used to obtain... Will Divided into segments u, each segment having a length v, since It is a lower triangular matrix of dimension [M, M], and the i-th segment is a parity bit. for:

[0148]

[0149] In an optional embodiment of this application, in step S300, the lookup table is retrieved based on the lookup index value using the following expression:

[0150]

[0151] Where bi2de is the binary to decimal conversion function.

[0152] The encoding method for IRA-LDPC codes used in the DVB-S2 / S2X protocol in this application encodes the sequence... λ(i*v+(0:v-1)) is treated as the v-bit index value, and each bit is searched for with a length of 2. v Find LUT_TRI V and LUT_O v Tables can eliminate the need for matrix multiplication, enabling fast parallel computation.

[0153] In an optional embodiment of this application, step S400, determining the target check bit based on the found check bit value, includes:

[0154] Based on the value of i, the check bits are calculated after the i-th segment is divided into two segments. Perform u iterations to obtain the first set of verification sequences.

[0155] The target parity bit is obtained from the first set of parity sequences using the following expression:

[0156]

[0157]

[0158] Where, p shift For the target parity bit, For the other groups of check sequences, λ1~λ l-1 This is the check value.

[0159] The IRA-LDPC encoding method for the DVB-S2 / S2X protocol disclosed in this application divides the target parity bits into multiple parity sequences, calculates the intermediate result λ in parallel based on the basic shift coefficient matrix, solves the interleaved parity bits by a lookup table method, and finally obtains the IRA-LDPC encoding result by reverse interleaving. By using parallel computing and a lookup table method that replaces product calculation, the calculation of the target parity bits can be accelerated, thereby improving the encoding efficiency.

[0160] In an optional embodiment of this application, the method further includes:

[0161] The encoding result obtained in step S400 is divided into a first bit sequence, a first 1-byte bit sequence, a padding bit sequence, a second 1-byte bit sequence, and a second bit sequence in sequence. The first 1-byte bit sequence and the second 1-byte bit sequence both include a padding sequence and an information bit sequence.

[0162] Extract the first information bit sequence and the second information bit sequence from the first 1-byte bit sequence and the second 1-byte bit sequence respectively;

[0163] The first bit sequence, the first information bit sequence, the second information bit sequence, and the second bit sequence are concatenated to obtain the target bit sequence.

[0164] The new bit selection position is determined based on the initial bit selection position index and the start and end positions of the padding bits. The output length is matched according to the new bit selection position and the preset rate. A rate-matched output sequence is generated based on the target bit sequence.

[0165] In an optional embodiment of this application, dividing the encoding result obtained in step S400 into a first bit sequence, a first 1-byte bit sequence, a padding bit sequence, a second 1-byte bit sequence, and a second bit sequence in sequence includes:

[0166] In the encoding result obtained in step S400, the whole-byte information bit sequence before the padding bit sequence is taken as the first bit sequence, the first byte bit sequence after the first bit sequence is taken as the first 1-byte bit sequence, the whole-byte padding bit sequence after the first 1-byte bit sequence is taken as the padding bit sequence, the first byte bit sequence after the padding bit sequence is taken as the second 1-byte bit sequence, and the information bit sequence after the second 1-byte bit sequence is taken as the second bit sequence.

[0167] In an optional embodiment of this application, the extraction of the first information bit sequence and the second information bit sequence from the first 1-byte bit sequence and the second 1-byte bit sequence, respectively, includes:

[0168] The end position index of the padding bit sequence in the second 1-byte bit sequence is determined based on the start position and length of the padding bit sequence. The end position index is then logically ANDed with 7 to determine the second information bit sequence in the second 1-byte bit sequence.

[0169] Perform a logical AND operation of 7 on the starting position of the padding bit sequence to determine the first information bit sequence in the first 1-byte bit sequence.

[0170] In an optional embodiment of this application, the step of concatenating the first bit sequence, the first information bit sequence, the second information bit sequence, and the second bit sequence to obtain the target bit sequence includes:

[0171] The number of the second information bit sequence is used as the first shift value for concatenating and shifting the second information bit sequence with the second bit sequence. The second information bit sequence is concatenated with the second bit sequence according to the first shift value to obtain the third bit sequence.

[0172] The number of bits in the first information bit sequence is used as the second shift value for concatenating and shifting the first information bit sequence with the third bit sequence. The first information bit sequence is then concatenated with the third bit sequence according to this second shift value to obtain the fourth bit sequence.

[0173] The first bit sequence is concatenated with the fourth bit sequence to obtain the target bit sequence.

[0174] In an optional embodiment of this application, determining the new bit selection position based on the initial bit selection position index and the start and end positions of the padding bits includes:

[0175] If the initial bit selection position index is before the start position of the padding bits or between the start and end positions of the padding bits, the new bit selection position is before the initial bit selection position and the distance between the new bit selection position and the initial bit selection position is the length of the padding bit sequence.

[0176] If the initial bit selection position index is after the end of the padding bits, the new bit selection position is the initial bit selection position.

[0177] In an optional embodiment of this application, the step of generating a rate-matching output sequence based on the target bit sequence according to the new bit selection position and the preset rate matching output length includes:

[0178] Perform a logical AND operation of 7 on the target bit sequence;

[0179] If the target bit sequence is an integer bit sequence, compare the length of the target bit sequence with the preset rate to match the output length;

[0180] If the target bit sequence length is greater than the preset rate matching output length, the target bit sequence is truncated so that the length of the truncated target bit sequence is the same as the preset rate matching output length, and the truncated target bit sequence is used as the rate matching output sequence.

[0181] If the target bit sequence length is less than the preset rate matching output length, the number of repetitions of the target bit sequence is determined based on the target bit sequence length and the preset rate matching output length. The target bit sequence is repeated according to the number of repetitions, so that the length of the repeated target bit sequence is greater than or equal to the preset rate matching output length. If the length of the repeated target bit sequence is equal to the preset rate matching output length, the repeated target bit sequence is used as the rate matching output sequence. If the length of the repeated target bit sequence is greater than the preset rate matching output length, the repeated target bit sequence is truncated so that the length of the truncated target bit sequence is the same as the preset rate matching output length, and the truncated target bit sequence is used as the rate matching output sequence.

[0182] If the target bit sequence length is equal to the preset rate matching output length, the target bit sequence is used as the rate matching output sequence.

[0183] If the target bit sequence is not an integer bit sequence, the valid bits of the last byte of the target bit sequence are moved to the beginning of the target bit sequence to generate a new target bit sequence. The length of the new target bit sequence is then compared with the preset rate to match the output length.

[0184] If the length of the new target bit sequence is greater than the preset rate matching output length, the new target bit sequence is truncated so that the length of the truncated bit sequence is the same as the preset rate matching output length, and the truncated bit sequence is used as the rate matching output sequence.

[0185] If the length of the new target bit sequence is less than the preset rate matching output length, the number of repetitions of the new target bit sequence is determined based on the length of the new target bit sequence and the preset rate matching output length. The new target bit sequence is repeated according to the number of repetitions, so that the length of the repeated bit sequence is greater than or equal to the preset rate matching output length. If the length of the repeated bit sequence is equal to the preset rate matching output length, the repeated bit sequence is used as the rate matching output sequence. If the length of the repeated bit sequence is greater than the preset rate matching output length, the repeated bit sequence is truncated so that the length of the truncated bit sequence is the same as the preset rate matching output length, and the truncated bit sequence is used as the rate matching output sequence.

[0186] If the length of the new target bit sequence is equal to the preset rate-matching output length, the new target bit sequence will be used as the rate-matching output sequence.

[0187] In an optional embodiment of this application, the step of determining the number of repetitions of the new target bit sequence based on the new target bit sequence length and the preset rate matching output length, and repeating the new target bit sequence according to the number of repetitions, includes:

[0188] The number of repetitions of the new target bit sequence is determined by the following expression, based on the new target bit sequence length and the preset rate matching output length:

[0189] N+b*(CN)≥M

[0190] Where C is the length of the new target bit sequence, N is the number of valid bits in the last byte of the target bit sequence, b is the number of repetitions, and M is the preset rate-matched output length.

[0191] When repeating the new target bit sequence a certain number of times b, repeat the bits in the new target bit sequence excluding the first N bits.

[0192] The encoding method for IRA-LDPC codes in this application is applicable to all encoders of IRA-LDPC codes that approximate the DVB-S2 / S2X protocol. The implemented decoder is compatible with all DVB-S2 / S2X code rates and achieves a maximum decoding throughput of 20.79Gbps. When faced with numerous IRA-LDPC encoding code rates / code patterns in protocols such as DVB-S2, software updates can quickly adapt to new code rates, code pattern combinations, and protocol upgrade requirements, such as support for new DVB-S2X features, without the high-cost and high-risk operations of recompiling the hardware description language for FPGA architectures or re-fabricating ASICs (ASIC re-fabrication is the process of remanufacturing a chip design that has failed verification or testing). This allows for rapid verification of the feasibility of new algorithms during the R&D and testing phase; in practical applications, it can flexibly handle mixed communication standard deployment scenarios and meet the compatibility needs of different customers for multiple communication protocols.

[0193] It should be understood that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order constraint on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the diagram may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0194] Please see Figure 3 One embodiment of this application provides an encoding apparatus 300 for IRA-LDPC codes of the DVB-S2 / S2X protocol, comprising:

[0195] The generation module 310 is used to preprocess the rate check matrices under the DVB-S2 / S2X protocol, generate and store the basic shift matrix and its index of the system part;

[0196] The segmentation module 320 is used to divide the parity bit into q segments to obtain the parity bit after the first segmentation, divide each parity bit after the first segmentation into u segments to obtain the parity bit after the second segmentation, use the length of the parity bit after the second segmentation as the lookup parallelism, and generate and store the lookup table according to the lookup parallelism.

[0197] The lookup module 330 is used to determine the lookup index value according to the basic shift matrix and its index of the system part, and to look up the value of the lookup table according to the lookup index value;

[0198] The determination module 340 is used to determine the target parity bit based on the found parity bit value, extract and interleave the target parity bit at a preset interval to obtain the parity sequence, and output it to the end of the system bits as the encoding result.

[0199] The encoding apparatus for IRA-LDPC codes of the DVB-S2 / S2X protocol in this application further includes:

[0200] The data storage module is used to store system bits, fundamental shift coefficients, and the lookup table LUT_TRI. V and LUT_O v and check bit p shift and p;

[0201] The data exchange module is used to load system bits, parameters, lookup tables, and output parity bits with a parallelism greater than or equal to M into the data storage module in parallel.

[0202] The parallel interleaving module is used by the lookup module to perform parallel interleaving on the sub-code blocks of the system bits in accordance with the basic shift matrix and its index of the system part to obtain the intermediate shift result, wherein the parallelism is greater than or equal to M;

[0203] The parallel splicing and shifting module is used to perform parallel splicing and shifting of intermediate shifting results. It supports splicing of sequences with a length of at least u segments and a shifting range of 0 to v-1.

[0204] Parallel data XOR stacking module, used for parallel addition in the GF(2) domain, wherein the degree of parallelism must be greater than or equal to M.

[0205] For specific limitations regarding the aforementioned device 300, please refer to the limitations on the encoding method of the IRA-LDPC code used for the DVB-S2 / S2X protocol mentioned above, which will not be repeated here. Each module in the aforementioned device 300 can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of the processor in the computer device, or stored in software in the memory of the computer device, so that the processor can call and execute the operations corresponding to each module.

[0206] In one embodiment, a computer device is provided, the internal structure of which can be as follows: Figure 4 As shown. The computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database stores data. The network interface communicates with external terminals via a network connection. When the computer program is executed by the processor, it implements the above-described encoding method for IRA-LDPC codes of the DVB-S2 / S2X protocol. It includes: a memory and a processor; the memory stores a computer program; and the processor, when executing the computer program, implements any step of the above-described encoding method for IRA-LDPC codes of the DVB-S2 / S2X protocol.

[0207] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, can perform any of the steps in the encoding method for the IRA-LDPC code of the DVB-S2 / S2X protocol described above.

[0208] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0209] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0210] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0211] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0212] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0213] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. An encoding method for IRA-LDPC codes used in the DVB-S2 / S2X protocol, characterized in that, include: Preprocess the rate check matrices of each code rate check matrix under the DVB-S2 / S2X protocol to generate and store the basic shift matrix and its index of the system part; Divide the parity bit into q segments to obtain the parity bit after the first segmentation. Divide each parity bit after the first segmentation into u segments to obtain the parity bit after the second segmentation. Use the length of the parity bit after the second segmentation as the lookup parallelism. Generate and store the lookup table based on the lookup parallelism. The lookup table index value is determined based on the basic shift matrix and its index of the system part, and the lookup table is retrieved based on the lookup table index value; The target parity bit is determined based on the found parity bit value. The target parity bit is extracted and interleaved at a preset length interval to obtain the parity sequence, which is output to the end of the system bits as the encoding result.

2. The method according to claim 1, characterized in that, The preprocessing of the rate check matrices under the DVB-S2 / S2X protocol to generate and store the basic shift coefficients includes: The parity check matrix H is split to obtain submatrices H0. s and H p And the verification formula H s *s=H p *p, where s and p are the system bits and parity bits, respectively, and the submatrix H s and H p The dimensions are [nk, k] and [nk, nk], respectively, where k is the number of information symbols and n is the total number of symbols; For each submatrix H s and H p Extracting and rearranging rows at intervals of q, yields a matrix. and For matrix Extracting and rearranging columns at intervals of q yields a matrix. The parity bits are extracted and rearranged at intervals of q to obtain matrix p. shift ; Extract the matrix respectively and The cyclic shift values ​​corresponding to each element in the matrix are obtained, and the 0 values ​​in the matrix are replaced by -1 to obtain the basic shift matrix of the system part and the verification part, and stored. The elements of the basic shift matrix are the basic shift coefficients.

3. The method according to claim 1, characterized in that, The step of using the length of the parity bits after secondary segmentation as the lookup table parallelism, and generating and storing the lookup table based on the lookup table parallelism, includes: Lookup table LUT_TRI V and LUT_O v TRI are matrices of dimension v×v. V and O v : Where v is the length of the parity bits after the second segmentation.

4. The method according to claim 3, characterized in that, The process of determining the lookup index value based on the system's basic shift matrix and its index includes: After solving the i-th segment, check the bit. In the case of, respectively And λ(i*v+(0:v-1)) as the lookup table LUT_TRI V and LUT_O v The lookup index value is given by , where i is any value from 1 to u, and v is the length of the parity bits after the second segmentation. Where l is the number of segments in the system bit s, q and l are both positive integers greater than or equal to 1, and κ q-1，l-1 The basic shift matrix elements of the system part index, The basic shift matrix elements of the system part Sub-code blocks s of system bits s l-1 The cyclic shift matrix.

5. The method according to claim 4, characterized in that, The cyclic shift matrix of the basic shift matrix elements of the system part with respect to the sub-code block of system bits s is obtained through the following steps: The sub-code blocks of system bits s are divided into segments u using the following expression: v = M / u M = (nk) / q Among them, s j Let M be the sub-code block of system bits s, and M be the length of the sub-code block. The basic shift matrix elements of the system are partitioned using the following expression: in, h is the basic shift matrix element of the system part. ceil h is the integer value of the element. floor h is the floor value of the element. mod The modulo value of the element. The following expressions are used to segment the sub-code blocks by rounding up and down the elements, respectively. Perform a circular shift: in, and These are intermediate shift results obtained by cyclically shifting the sub-code block of system bit s using the rounded-up and rounded-down values, respectively. The following expression concatenates intermediate shift results, shifts the concatenated matrix according to the modulo values ​​of its elements, and extracts the low v bits of the shifted matrix: in, For segmented sub-code blocks The corresponding circular shift vector, For subcode block s j The corresponding cyclic shift matrix.

6. The method according to claim 1, characterized in that, The following expression retrieves a value from the lookup table based on the lookup table index: Where bi2de is the binary to decimal conversion function.

7. The method according to claim 1, characterized in that, The step of determining the target parity bit based on the found parity bit value includes: Based on the value of i, the check bits are calculated after the i-th segment is divided into two segments. Perform u iterations to obtain the first set of verification sequences. The target parity bit is obtained from the first set of parity sequences using the following expression: Where, p shift For the target parity bit, For the other groups of check sequences, λ1~λ l-1 This is the check value.

8. An encoding device for IRA-LDPC codes in the DVB-S2 / S2X protocol, characterized in that, include: The generation module is used to preprocess the rate check matrices under the DVB-S2 / S2X protocol, generate and store the basic shift matrix and its index of the system part; The segmentation module is used to divide the parity bit into q segments to obtain the parity bit after the first segmentation. Each parity bit after the first segmentation is divided into u segments to obtain the parity bit after the second segmentation. The length of the parity bit after the second segmentation is used as the lookup parallelism. A lookup table is generated and stored based on the lookup parallelism. The table lookup module is used to determine the table lookup index value according to the basic shift matrix and its index of the system part, and to look up the value of the lookup table according to the table lookup index value; The determination module is used to determine the target parity bit based on the found parity bit value, extract and interleave the target parity bit at a preset interval to obtain the parity sequence, and output it to the end of the system bits as the encoding result.

9. A computer device, comprising: A memory and a processor, the memory storing a computer program, characterized in that, when the processor executes the computer program, it implements the steps of the encoding method for IRA-LDPC codes for the DVB-S2 / S2X protocol as described in any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the encoding method for IRA-LDPC codes for the DVB-S2 / S2X protocol as described in any one of claims 1 to 7.

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