Communication terminal tester, interface time sequence parameter determination method thereof, electronic equipment, chip, storage medium and program product

Abstract

The invention provides a communication terminal tester and an interface time sequence parameter determination method thereof, electronic equipment, a chip, a storage medium and a program product, and relates to the technical field of communication. The interface time sequence parameter determination method of the communication terminal tester comprises the following steps: acquiring corresponding values of a first parameter, a second parameter and a third parameter corresponding to a target subcarrier interval; respectively obtaining a first value range of a fourth parameter, a second value range of a fifth parameter and a third value range of a sixth parameter according to the corresponding values of the first parameter, the second parameter and the third parameter; and outputting the first value range of the fourth parameter, the second value range of the fifth parameter and the third value range of the sixth parameter so as to determine the value of the fourth parameter in the first value range, the value of the fifth parameter in the second value range and the value of the sixth parameter in the third value range by debugging the communication terminal tester.

Description

Technical Field

[0001] This disclosure relates to the field of communication technology, and specifically to a communication terminal tester and a method for determining its interface timing parameters, electronic devices, chips, storage media, and program products. Background Technology

[0002] A communication terminal tester is an instrument used to test and evaluate the performance of communication terminals. It can be applied to the research and development, production, quality inspection, and maintenance of communication terminals. The interface timing of the communication terminal tester is one of the key factors affecting the accuracy of the test results. By precisely controlling the interface timing, the communication terminal tester can verify the performance of the communication terminal in terms of standard compatibility, throughput, latency, and other dimensions.

[0003] Currently, the interface timing settings of communication terminal testers are typically derived from basic planning in non-millimeter-wave scenarios. The timing offset is based on preset values ​​of the main control unit and higher layers, and data interaction with the algorithm module is achieved through timed read and write operations of registers. Such interface timing planning is not standardized or systematic enough, and has poor scalability. It is also highly complex to adapt to new scenario requirements (such as scenarios with large parameter sets and subcarrier spacing), which affects testing efficiency. Summary of the Invention

[0004] To alleviate, mitigate, or eliminate at least one of the above-mentioned technical problems, this disclosure provides a communication terminal tester and a method for determining its interface timing parameters, an electronic device, a chip, a storage medium, and a program product.

[0005] In a first aspect, this disclosure provides a method for determining interface timing parameters of a communication terminal tester. The communication terminal tester includes a first processor, a second processor, and a radio frequency circuit. The first processor is configured to run a scheduler program and an L1 layer control plane program. The scheduler program is used to schedule and control air interface time-frequency resources, and the L1 layer control plane program is used to perform L1 layer resource control and interface interaction. The second processor is configured to run a signal processing algorithm program and interact with the first processor and the radio frequency circuit. The first processor is configured with shared memory for interface interaction with the second processor. The method includes: The values ​​of the first, second, and third parameters corresponding to the target subcarrier interval are obtained. The first parameter is the number of basic time units required for the maximum processing time of the L1 layer control plane program. The second parameter is the number of basic time units required for the maximum processing time of the signal processing algorithm program. The third parameter is the number of basic time units that need to be delayed in the transmission timing after the L1 layer control plane program has finished writing the first partition of the shared memory and before the second processor reads the first partition. The basic time unit is the single time slot length corresponding to the maximum subcarrier interval in the application scenario supported by the communication terminal tester. Based on the corresponding values ​​of the first, second, and third parameters, the first value range of the fourth parameter, the second value range of the fifth parameter, and the third value range of the sixth parameter are obtained respectively. The fourth parameter is the number of basic time units that the scheduler program needs to advance the scheduling relative to the RF circuit's transmission of the RF signal in the transmission timing sequence; the fifth parameter is the number of basic time units that the L1 layer control plane program needs to advance the writing of the first partition relative to the RF circuit's transmission of the RF signal in the transmission timing sequence; and the sixth parameter is the number of basic time units that the L1 layer control plane program needs to delay in reading the second partition of the shared memory relative to the RF circuit's reception of the RF signal in the reception timing sequence. The first value range of the fourth parameter, the second value range of the fifth parameter, and the third value range of the sixth parameter are output so that the value of the fourth parameter in the first value range, the value of the fifth parameter in the second value range, and the value of the sixth parameter in the third value range can be determined by debugging the communication terminal tester.

[0006] Secondly, this disclosure provides a communication terminal tester, comprising: Radio frequency circuits; A first processor is configured to run a scheduler program and an L1 layer control plane program. The scheduler program is used for scheduling and controlling air interface time-frequency resources, and the L1 layer control plane program is used for performing L1 layer resource control and interface interaction. The second processor is configured to run signal processing algorithm programs and interact with the first processor and the radio frequency circuit, wherein the first processor is configured with shared memory for interfacing with the second processor. The radio frequency circuit, the first processor, and the second processor operate according to the interface timing parameters determined by the method described in the first aspect.

[0007] Thirdly, this disclosure provides an electronic device. The electronic device includes: one or more processors; and one or more memories coupled to the one or more processors and storing instructions thereon. When the instructions are executed individually or jointly by the one or more processors, the electronic device performs the method described in the first aspect.

[0008] Fourthly, this disclosure provides a chip. The chip includes a circuit system configured to perform the method described in the first aspect.

[0009] Fifthly, this disclosure provides a non-transitory computer-readable storage medium storing machine-executable instructions. When executed by one or more processors of a machine, the machine-executable instructions cause the machine to perform the method described in the first aspect.

[0010] In a sixth aspect, this disclosure provides a computer program product including machine-executable instructions. When executed by one or more processors of a machine, the machine-executable instructions cause the machine to perform the method described in the first aspect.

[0011] It should be understood that the summary section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0012] The above and other objects, features, and advantages of this disclosure will become more apparent from the more detailed description of some embodiments thereof in the accompanying drawings, in which: Figure 1 An exemplary communication network in which exemplary embodiments of the present disclosure may be implemented is shown; Figure 2 A schematic diagram of the structure of a communication terminal tester according to some embodiments of the present disclosure is shown; Figure 3 A flowchart illustrating a method for determining interface timing parameters of a communication terminal tester according to some embodiments of the present disclosure is shown. Figure 4 A transmission timing diagram of a communication terminal tester according to some embodiments of the present disclosure is shown; Figure 5 A timing diagram of the receiver of a communication terminal tester according to some embodiments of the present disclosure is shown; Figure 6 A simplified block diagram of a device suitable for implementing exemplary embodiments of the present disclosure is shown. Detailed Implementation

[0013] The principles of this disclosure will now be described with reference to some embodiments. It should be understood that these embodiments are described for illustrative purposes only and to assist those skilled in the art in understanding and implementing this disclosure, and do not impose any limitation on the scope of this disclosure. The disclosure described herein may be implemented in ways other than those described below.

[0014] In the following description and claims, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains.

[0015] References to "an embodiment," "embodiment," "exemplary embodiment," etc., herein indicate that the described embodiment may include specific features, structures, or characteristics, but not every embodiment needs to include specific features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an exemplary embodiment, whether explicitly described or not, those skilled in the art will recognize that such feature, structure, or characteristic affects its application to other embodiments.

[0016] It should be understood that while the terms “first” and “second”, etc., may be used herein to describe various objects, these objects should not be limited by these terms. These terms are used only to distinguish one object from another. For example, without departing from the scope of the exemplary embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. The term “and / or” as used herein includes any and all combinations of one or more of the listed terms.

[0017] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments. The singular forms “a,” “an,” and “the” used herein also include the plural forms unless the context clearly indicates otherwise. The terms “a group of elements” or “a collection of elements” as used herein are intended to include one or more elements. It should also be understood that the terms “comprising,” “including,” “having,” “possessing,” “including,” and / or “comprising,” when used herein, specify the presence of the stated features, elements, and / or components, but do not exclude the presence or addition of one or more other features, elements, components, and / or combinations thereof.

[0018] As used herein, the term "circuit" may refer to one or more of the following: (a) Hardware circuit implementation only (e.g., implementation only in analog and / or digital circuits) (b) A combination of hardware circuitry and software, such as (if applicable): (i) A combination of analog and / or digital hardware circuitry with software / firmware; and (ii) Any part of a hardware processor (including a digital signal processor), software, and memory that work together to enable a device such as a mobile phone or server to perform various functions, and (c) Hardware circuitry and / or processors, such as microprocessors or a portion thereof, which require software (e.g., firmware) to operate, but may be absent when software is not required to operate.

[0019] The definition of "circuit" applies to all uses of the term herein, including in any claim. As another example, as used herein, the term "circuit" also includes implementations of hardware circuitry or processors (or processors in general) or a portion thereof and their accompanying software and / or firmware. The term "circuit" also includes, for example, baseband integrated circuits or processor integrated circuits for mobile devices, or similar integrated circuits in servers, cellular network devices, or other computing network devices, if applicable to a particular element.

[0020] As used herein, the term "communication network" refers to a network that conforms to any suitable communication standard, such as Long Term Evolution (LTE), LTE-Advanced (LTE-A), Wideband Code Division Multiple Access (WCDMA), High-Speed ​​Packet Access (HSPA), Narrowband Internet of Things (NB-IoT), New Radio (NR), Non-Terrestrial Network (NTN), etc. Furthermore, communication between terminal devices and network devices in a communication network can be performed according to any suitable generation of communication protocol, including but not limited to first-generation (1G), second-generation (2G), 2.5G, 2.75G, third-generation (3G), fourth-generation (4G), 4.5G, fifth-generation (5G), and future sixth-generation (6G) communication protocols, and / or any other protocols currently known or to be developed in the future. Embodiments of this disclosure can be applied to satellite communication systems. Given the rapid development in communications, future types of communication technologies and systems will naturally exist, and embodiments of this disclosure can be implemented using these technologies and systems. The scope of this disclosure should not be considered limited to the aforementioned systems.

[0021] The term "satellite network equipment" refers to a node located on a satellite or ground segment in a satellite communication network. Terminal devices access the network and receive services through this node. Depending on the terminology and technology used, satellite network equipment can refer to a base station (BS) or access point (AP) that acts as a satellite payload, such as a Node B (NodeB or NB), an evolved Node B (eNodeB or eNB), an NR NB (also called a gNB), a Remote Radio Unit (RRU), a Radio Header (RH), a Remote Radio Header (RRH), or a relay node. An example of a relay node can be an Integrated Access and Backhaul (IAB) node. The Distributed Unit (DU) portion of an IAB node can perform the functions of a "satellite network equipment" and therefore can operate as a network device. In the following description, the terms "satellite network equipment," "BS," and "node" are used interchangeably.

[0022] The term "terminal device" refers to any terminal device capable of wireless communication. As an example and not a limitation, a terminal device may also be referred to as a communication terminal, communication equipment, user equipment (UE), subscriber station (SS), portable subscriber station, mobile station (MS), or access terminal (AT). This terminal device may include, but is not limited to, mobile phones, cellular phones, smartphones, Voice over IP (VoIP) phones, wireless local loop phones, tablets, wearable terminal devices, personal digital assistants (PDAs), portable computers, desktop computers, image capture terminal devices such as digital cameras, gaming terminal devices, music storage and playback devices, in-vehicle wireless terminal devices, wireless endpoints, mobile stations, laptop embedded devices (LEE), laptop installed devices (LME), USB dongles, smart devices, wireless subscriber equipment (CPE), Internet of Things (IoT) devices, watches or other wearable devices, head-mounted displays (HMDs), vehicles, drones, medical devices and applications (e.g., remote surgery), industrial devices and applications (e.g., robots and / or other wireless devices operating in the context of industrial and / or automated processing chains), consumer electronics devices, relay nodes, devices operating on commercial and / or industrial wireless networks, etc. The mobile terminal (MT) portion of an IAB node can perform the functions of a "terminal device" and therefore can operate as a terminal device. In the following description, the terms "terminal device," "communication terminal," "communication equipment," "terminal," "user equipment," and "UE" are used interchangeably.

[0023] The term "L1" refers to layer 1 of the protocol stack. For example, L1 refers to the physical layer.

[0024] The term "L2" refers to layer 2 of the protocol stack. For example, L2 may include the Media Access Control (MAC) layer, the Radio Link Control (RLC) layer, the Packet Data Convergence Protocol (PDCP) layer, and the Service Data Adaptation Protocol (SDAP) layer, which are responsible for functions such as scheduling, segmentation and reassembly, and encryption integrity.

[0025] The term "Communication Processor (CP)" refers to a dedicated processor used to process the communication protocol stack. It is commonly found in base stations, routers, and other similar devices. It is responsible for protocol stack management and carries the L1 and L2 layers of the protocol stack.

[0026] The term "Field-Programmable Gate Array (FPGA)" is responsible for the algorithmic parts of the signal, such as channel coding, modulation, and resource mapping.

[0027] The term "shared memory" refers to a memory unit that can be accessed simultaneously by multiple different devices.

[0028] The term "sub-carrier spacing (SCS)" refers to the subcarrier spacing of a beam, which is the smallest unit of a signal in the frequency domain.

[0029] The term "time slot" refers to the basic unit of time in a beam, and each time slot contains a specific number of symbols.

[0030] While the functions described herein may be implemented in fixed and / or wireless network nodes in various exemplary embodiments, in other exemplary embodiments, they may be implemented in user equipment devices (such as cellular phones, tablet computers, laptop computers, desktop computers, mobile IoT devices, or fixed IoT devices). For example, the user equipment device may suitably have the corresponding capabilities described in relation to fixed and / or wireless network nodes. The user equipment device may be user equipment and / or control devices, such as chipsets or processors, configured to control the user equipment when it is installed therein. Examples of these functions include boot server functions and / or home subscriber servers, which may be implemented in the user equipment device by providing the user equipment device with software configured to cause the user equipment device to perform from the perspective of these functions / nodes.

[0031] Figure 1An exemplary communication network 100 in which embodiments of the present disclosure may be implemented is shown. The communication network 100 includes a satellite network device 110 and terminal devices 120A and 120B served by the satellite network device 110. Terminal devices 120A and 120B may also be collectively referred to as terminal device 120. The communication network 100 may provide a service cell 130 to serve terminal devices 120A and 120B. Figure 1 In the example, as a satellite communication network, communication network 100 also includes ground station 140, gNB 150, next-generation core network NGC 160, and data network 170. The satellite communication network may include low-Earth orbit (LEO), medium-Earth orbit (MEO), or geostationary orbit (GEO) satellites.

[0032] Ground station 140 acts as a gateway, connecting non-terrestrial networks and public data networks. gNB 150 acts as an access network, connecting ground station 140 to the core network NGC 160. NGC 160 can also connect to data network 170 to provide, for example, internet content services. It will be understood that communication network 100 is not required to include... Figure 1 The communication network 100 may also include all the elements shown in the diagram. Figure 1 Other elements not shown in the text.

[0033] In some embodiments, the satellite network device 110 can function as a base station to communicate with terminal devices 120A and 120B, or it can function as a transparent forwarding node to transmit signals sent by the ground station 140 to the terminal devices 120A and 120B. In the former case, the satellite network device 110 possesses all or part of the functions of a base station. For example, the satellite network device 110 can be a gNB or a gNB-DU, and the satellite network device 110 with gNB functionality can have an inter-satellite link (ISL) or not. In the case of a transparent forwarding node, the satellite network device 110 only performs transparent forwarding.

[0034] It should be understood that the number of satellite network devices 110, terminal devices 120A and 120B, and serving cell 130 is for illustrative purposes only and is not intended to impose any limitation. Communication network 100 may include any suitable number of satellite network devices, terminal devices, and serving cells suitable for implementing embodiments of this disclosure. It should be noted that the terms "cell" and "serving cell" are used interchangeably herein.

[0035] In the communication network 100, satellite network device 110 can transmit data and control information to terminal devices 120A and 120B, and terminal devices 120A and 120B can also transmit data and control information to satellite network device 110. The link from satellite network device 110 to terminal devices 120A and 120B is called a downlink (DL) or forward link, while the link from terminal device 120 to satellite network device 110 is called an uplink (UL) or reverse link.

[0036] Communication in communication network 100 can conform to any suitable standard, but is not limited to Long Term Evolution (LTE), LTE Evolution, LTE-Advanced (LTE-A), Wideband Code Division Multiple Access (WCDMA), Code Division Multiple Access (CDMA), and Global System for Mobile Communications (GSM). Furthermore, communication can be performed according to any generation of communication protocols currently known or developed in the future. Examples of communication protocols include, but are not limited to, first-generation (1G), second-generation (2G), 2.5G, 2.75G, third-generation (3G), fourth-generation (4G), 4.5G, fifth-generation (5G), and sixth-generation (6G) communication protocols.

[0037] In communication terminals (such as Figure 1 In the research, development, production, quality inspection, and maintenance of terminal equipment (120) in communication systems, communication terminal testers are typically used to test and evaluate the performance of the communication terminals. Depending on the technology of the communication terminal being tested and the testing scenario, there are various types of instruments. Common communication terminal testers include comprehensive testers, production testers, and Bluetooth / Wi-Fi testers.

[0038] Figure 2 A schematic diagram of the structure of a communication terminal tester according to some embodiments of the present disclosure is shown. For example... Figure 2 As shown, the communication terminal tester 200 includes a first processor 210, a second processor 220, and an radio frequency circuit 230. The first processor 210 is configured to run a scheduler program 211 and an L1 layer control plane program 212. The scheduler program 211 is used for scheduling and controlling air interface time-frequency resources. The L1 layer control plane program 212 is used for performing L1 layer resource control and interface interaction. The second processor 220 is configured to run a signal processing algorithm program and interact with the first processor 210 and the radio frequency circuit 230. The first processor 210 is configured with shared memory 213 for interface interaction with the second processor 220. It will be understood that the communication terminal tester 200 is not required to include... Figure 2 The communication terminal tester 200 may also include all the elements shown in the diagram. Figure 2 Other elements not shown in the text.

[0039] In one exemplary embodiment, the first processor 210 is a CP (Processor Controller), and the second processor 220 is an FPGA (FPGA). The CP and the FPGA interact through a shared memory 213 with a total length of L partitions. For example, the CP writes data to partition idx2 of the shared memory 213, and the FPGA reads data from partition idx2 of the shared memory 213.

[0040] The interface timing of a communication terminal tester is one of the key factors affecting the accuracy of communication terminal test results. This disclosure uses subcarrier spacing (SCS) to differentiate between different satellite communication application scenarios such as frequency ranges FR1 / FR2 and high / low orbit, balancing service logic requirements, chip processing performance, and interface read / write capabilities. It standardizes and regulates the interface timing between the scheduler program, the L1 layer control plane program, and the second processor, reducing internal processing latency of the communication terminal tester and improving testing efficiency.

[0041] Figure 3 A flowchart illustrating a method for determining interface timing parameters of a communication terminal tester according to some embodiments of the present disclosure is shown. It should be understood that the method 300 for determining interface timing parameters of the communication terminal tester may include additional steps not shown and / or some of the shown steps may be omitted, and the embodiments of the present disclosure are not limited thereto.

[0042] In step S310, the first parameter N corresponding to the target subcarrier spacing is obtained. proc The second parameter N algo and the third parameter N send_delay The corresponding values ​​of . Among them, the first parameter N proc The basic time unit T is the maximum processing time required for the L1 layer control plane program. ext_IRQ The number of, the first parameter N proc The second parameter N is an integer. algo The basic time unit T is the maximum processing time required by a signal processing algorithm program. ext_IRQ The number of, the second parameter N algo The third parameter N is an integer. send_delay In the transmission timing, the basic time unit T is the delay required between the L1 layer control plane program writing to the first partition of shared memory and the second processor reading the first partition. ext_IRQ The number of, the third parameter N send_delay It is an integer. Where, the basic time unit T... ext_IRQ This refers to the single-slot length corresponding to the maximum subcarrier spacing in the application scenarios supported by the communication terminal tester. The single-slot length T corresponding to the target subcarrier spacing. scs =n×T ext_IRQn = 1, 2, 4, ... (n is a non-negative integer power of 2). In an exemplary embodiment, the system timing of the communication terminal tester is controlled by an external interrupt of the first processor, with a basic time unit T. ext_IRQ It is equal to the cycle of the external interrupt of the first processor.

[0043] In some embodiments, the first parameter N corresponding to the target subcarrier spacing proc The second parameter N algo and the third parameter N send_delay The corresponding value is determined based on the chip characteristics of the first and second processors and the target application scenario for the communication terminal tester. It can be understood that the first parameter N corresponding to the target subcarrier interval in this embodiment of the disclosure... proc The second parameter N algo and the third parameter N send_delay There are no restrictions on how the corresponding values ​​are obtained. For example, they can be obtained directly from the cloud or a remote server, or they can be obtained locally.

[0044] In some embodiments, the index number of the first partition is determined based on the timeslot number of the radio frequency circuit transmitting radio frequency signals. The index number of the second partition is determined based on the timeslot number of the radio frequency circuit receiving radio frequency signals. In such an embodiment, the index number x of the shared memory partition is determined by the current timeslot number s. For example, x = f_buf_idx(s), where f_buf_idx(s) represents the mapping function between timeslot number s and the index number x of the shared partition. The specific mapping relationship can be determined by debugging according to chip and service requirements.

[0045] In step S320, according to the first parameter N proc The second parameter N algo and the third parameter N send_delay The corresponding values ​​of the fourth parameter N are obtained respectively. sche_ext The first range of values, the fifth parameter N send_para The second range of values ​​and the sixth parameter N recv_para The third range of values. Among them, the fourth parameter N... sche_ext In the transmission timing sequence, the scheduler program issues the scheduling in advance of the basic time unit T, which is required for the radio frequency circuit to transmit the radio frequency signal. ext_IRQ The number of, the fourth parameter N sche_ext It is an integer. The fifth parameter N send_para In the transmission timing, the basic time unit T that needs to be written in advance in the L1 layer control plane program relative to the RF circuit transmitting the RF signal is the first partition. ext_IRQ The number of, the fifth parameter N send_para It is an integer. The sixth parameter N recv_paraIn the receive timing sequence, the basic time unit T that the L1 layer control plane program needs to delay when reading the second partition of shared memory relative to the RF circuit receiving the RF signal is... ext_IRQ The number of, the sixth parameter N recv_para It is an integer.

[0046] In some embodiments, the fourth parameter N is obtained according to the first constraint condition. sche_ext The first range of values. The first constraint condition includes: the fourth parameter N. sche_ext and basic time unit T ext_IRQ The product minus the first parameter N proc and basic time unit T ext_IRQ The product of the second parameter N algo and basic time unit T ext_IRQ The product and the third parameter N send_delay and basic time unit T ext_IRQ The difference between the sums of the products is greater than zero, or the fourth parameter N... sche_ext Subtract the first parameter N proc The second parameter N algo and the third parameter N send_delay The difference between the sums is greater than zero. For example, such a first constraint can be expressed by formula (1) or formula (2), which are illustrated below: N sche_ext ×T ext_IRQ -N proc ×T ext_IRQ -N algo ×T ext_IRQ -N send_delay ×T ext_IRQ >0 (1) N sche_ext -N proc -N algo -N send_delay >0 (2) In some embodiments, the fifth parameter N is obtained according to the second constraint condition. send_para The second range of values. The second constraint includes: the fifth parameter N. send_para The product of the basic time unit and the second parameter N. algo and basic time unit T ext_IRQ The product and the third parameter N send_delay and basic time unit T ext_IRQ The difference between the sums of the products is greater than zero; or the fifth parameter N send_para Subtract the second parameter N algo and the third parameter N send_delayThe difference between the sums is greater than zero. For example, such a second constraint can be expressed by formula (3) or formula (4), which are illustrated below: N send_para ×T ext_IRQ -N algo ×T ext_IRQ -N send_delay ×T ext_IRQ >0 (3) N send_para -N algo -N send_delay >0 (4) In some embodiments, the sixth parameter N is obtained according to the third constraint condition. recv_para The third range of values. The third constraint includes: the sixth parameter N. recv_para and basic time unit T ext_IRQ The product minus the second parameter N algo and basic time unit T ext_IRQ The difference between the products is greater than zero; or the sixth parameter N recv_para Subtract the second parameter N algo The difference is greater than zero. For example, such a third constraint can be expressed by formula (5) or formula (6), with examples of formula (5) and formula (6) as follows: N recv_para ×T ext_IRQ -N algo ×T ext_IRQ >0 (5) N recv_para -N algo >0 (6) In step S330, the fourth parameter N is output. sche_ext The first range of values, the fifth parameter N send_para The second range of values ​​and the sixth parameter N recv_para The third value range is used to determine the fourth parameter N by debugging the communication terminal tester. sche_ext Values ​​within the first range, and the fifth parameter N send_para The values ​​within the second range and the sixth parameter N recv_para The value within the third range.

[0047] The fourth parameter N is determined by debugging the communication terminal tester. sche_ext Values ​​within the first range, and the fifth parameter N send_para The values ​​within the second range and the sixth parameter N recv_paraWithin the third range of values, the interaction stability and internal latency of the communication terminal tester are balanced. In some embodiments, during debugging, the result on the left side of the formula corresponding to the above constraints is made as small as possible to more effectively balance the interaction stability and internal latency of the communication terminal tester.

[0048] In some embodiments, the fifth parameter N can also be used. send_para The sixth parameter N recv_para The seventh parameter N is determined by the corresponding value of the total length L of the shared memory partition. clr The value of . Among them, the seventh parameter N clr The basic time unit T is the interval between the first partition being written to and cleared. ext_IRQ The number of, the seventh parameter N clr L is an integer, where L is the total number of partitions in the shared memory.

[0049] In one exemplary embodiment, the seventh parameter N is determined according to the fourth constraint condition. clr The value of . Among them, the fourth constraint condition includes: the seventh parameter N clr Greater than the fifth parameter N send_para and the sixth parameter N recv_para The largest of the four values ​​is less than the total length L of the shared memory partition. For example, such a fourth constraint can be expressed by formula (7), as exemplified below: max(N send_para , N recv_para ) <N clr <L (7) This disclosure quantifies and standardizes the interface timing within the communication terminal tester to form a set of independently configurable interface timing parameters for various application scenarios, making it suitable for a wide range of applications. For example, for low-speed scenarios, larger values ​​can be taken within the range of interface timing parameters, while for high-speed scenarios, smaller values ​​can be taken within the range of interface timing parameters. Furthermore, the interface timing parameter determination method of the communication terminal tester in this disclosure has good scalability and can adapt to constantly changing technical requirements and different application scenarios.

[0050] After determining the values ​​of the interface timing parameters of the communication terminal tester, these values ​​are configured into the first and second processors of the tester. The radio frequency circuit, the first processor, and the second processor of the tester can then operate according to the determined interface timing parameters. For example, the determined first parameter N... proc The second parameter N algo The third parameter N send_delay The fourth parameter N sche_ext The fifth parameter N send_paraThe sixth parameter N recv_para and the seventh parameter N clr The corresponding values ​​are configured to Figure 2 The communication terminal tester 200 shown contains a first processor 210 and a second processor 220. The following refers to... Figure 4 and Figure 5 The transmission and reception timing of the communication terminal tester 200 are illustrated by way of example.

[0051] Assuming downlink scheduling exists on time slot m, and its next time slot is time slot l, the exemplary transmission timing 400 of the communication terminal tester 200 is illustrated as follows: Figure 4 As shown, Figure 4 The time unit in T is ext_IRQ .

[0052] exist Figure 4 In the illustrated embodiment, scheduler program 211 advances N... sche_ext ×T ext_IRQ The schedule is issued to ensure that subsequent processing units have sufficient processing time. After receiving the schedule from the scheduler program 211, the L1 layer control plane program 212 processes the data through N... proc ×T ext_IRQ After processing the duration, N in advance send_para ×T ext_IRQ The scheduling information is sent to the second processor 220, i.e., N in advance. send_para ×T ext_IRQ Write the required interface parameters to the first partition of shared memory 213. The second processor 220 is delayed by N. send_delay ×T ext_IRQ The time taken is N to read the first partition of shared memory 213, ensuring write and read integrity, and handling scheduling. algo ×T ext_IRQ It is understandable that the maximum processing time for all scheduling scenarios supported by L1 control plane program 212 does not exceed N. proc ×T ext_IRQ .

[0053] Assuming downlink scheduling exists on time slot l, an exemplary receiving timing diagram of the communication terminal tester 200 is shown below. Figure 5 As shown, Figure 5 The time unit in T is ext_IRQ .

[0054] exist Figure 5 In the illustrated embodiment, when the L1 layer control plane program 212 receives the interface data returned by the second processor 220, it delays by N... recv_para ×T ext_IRQ The program reads the second partition of shared memory, performs subsequent processing, and then reports the processing results to the scheduler program 211.

[0055] exist Figure 4 and Figure 5 In the illustrated embodiment, the index number x of the partition of shared memory 213 is determined by the current timeslot number s. The index number of the first partition is determined based on the timeslot number of the radio frequency circuit transmitting radio frequency signals. The index number of the second partition is determined based on the timeslot number of the radio frequency circuit receiving radio frequency signals. Within the total length L of shared memory 213, the storage space of partition x of shared memory 213 is expanded by N after one read / write operation. clr ×T ext_IRQ It was later cleared to improve the utilization of shared memory 213 and prevent data loss.

[0056] Embodiments of this disclosure also provide a chip. The chip includes a circuit system configured to perform reference... Figures 3-5 Any public process discussed.

[0057] Figure 6 This is a simplified block diagram of a device 600 suitable for implementing embodiments of the present disclosure. For example, a satellite network device 110, a terminal device 120, and electronic devices can be implemented by device 600. Figure 6 As shown, device 600 includes one or more processors 610, one or more memories 620 coupled to processor 610, and one or more communication modules 640 coupled to processor 610.

[0058] Communication module 640 is used for bidirectional communication. Communication module 640 has at least one antenna to facilitate communication. The communication interface can represent any interface necessary for communication with other network elements.

[0059] Processor 610 can be any type suitable for a local technology network, and as a non-limiting example, can include one or more of the following: general-purpose computer, special-purpose computer, microprocessor, digital signal processor (DSP), and processor based on a multi-core processor architecture. Device 600 can have multiple processors, such as application-specific integrated circuit chips, which are timely driven to a clock that synchronizes with the main processor.

[0060] Memory 620 may include one or more non-volatile memories and one or more volatile memories. Examples of non-volatile memories include, but are not limited to, read-only memory (ROM) 624, electrically programmable read-only memory (EPROM), flash memory, hard disk, optical disc (CD), digital video disc (DVD), and other magnetic and / or optical storage. Examples of volatile memories include, but are not limited to, random access memory (RAM) 622 and other volatile memories that do not persist during power-off periods.

[0061] Computer program 630 includes computer-executable instructions that are executed by the associated processor 610. Computer program 630 may be stored in ROM 624. Processor 610 may perform any appropriate actions and processes by loading computer program 630 into RAM 622.

[0062] The embodiments of this disclosure can be implemented via program 630, enabling device 600 to execute reference... Figures 3-5 Any process disclosed herein. Embodiments of this disclosure may also be implemented in hardware or by a combination of software and hardware.

[0063] In some embodiments, the computer program 630 may be tangibly contained in a computer-readable medium, which may be contained in device 600 (e.g., memory 620) or other storage device accessible to device 600. Device 600 may load the computer program 630 from the computer-readable medium into RAM 622 for execution. The computer-readable medium may include any type of tangible non-volatile memory, such as ROM, EPROM, flash memory, hard disk, CD, DVD, etc. The computer program 630 is stored on the computer-readable medium.

[0064] Generally, the various embodiments of this disclosure can be implemented in hardware or dedicated circuitry, software, logic, or any combination thereof. Some aspects may be implemented in hardware, while others may be implemented in firmware or software, which may be executed by a controller, microprocessor, or other computing device. Although various aspects of the embodiments of this disclosure are shown and described as block diagrams, flowcharts, or other graphical representations, it should be understood that, as non-limiting examples, the blocks, devices, systems, techniques, or methods described herein may be implemented in hardware, software, firmware, dedicated circuitry or logic, general-purpose hardware or controllers or other computing devices, or some combination thereof.

[0065] Embodiments of this disclosure also provide at least one computer program product tangibly stored on a non-transitory computer-readable storage medium. The computer program product includes computer-executable instructions, such as instructions included in program modules, which execute in a device on a target real or virtual processor to perform the functions described above. Figures 3-5 Any disclosed process discussed. Typically, a program module includes routines, programs, libraries, objects, classes, components, data structures, etc., that perform a specific task or implement a specific abstract data type. In various embodiments, the functionality of a program module can be combined or separated as needed among program modules. The machine-executable instructions for a program module can execute within a local or distributed device. In a distributed device, program modules can reside in both local and remote storage media.

[0066] Program code for performing the methods of embodiments of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus such that, when executed by the processor or controller, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The program code may be executed entirely on a machine, partially on a machine, partially on a remote machine, partially on a remote machine, or entirely on a remote machine or server as a standalone software package.

[0067] In the context of this document, computer program code or related data may be carried by any suitable carrier to enable a device, apparatus, or processor to perform the various processes and operations described above. Examples of carriers include signals, computer-readable media, etc.

[0068] Computer-readable media can be computer-readable signal media or computer-readable storage media. Computer-readable media can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or apparatuses, or any suitable combination thereof. More specific examples of computer-readable storage media include electrical connections having one or more wires, portable computer floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable optical disc read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0069] Furthermore, although the operations are described in a specific order, this should not be construed as requiring that these operations be performed in the specific order or sequence shown, or that all of the operations shown be performed to obtain the desired result. In some cases, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the foregoing discussion, these details should not be construed as limiting the scope of this disclosure, but rather as descriptions of features specific to particular embodiments. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0070] Although this disclosure has been described in language specific to structural features and / or methodological behavior, it should be understood that this disclosure as defined in the appended claims is not necessarily limited to the specific features or behaviors described above. Rather, the specific features and actions described above are disclosed as exemplary forms for implementing the claims.

[0071] It should be fully understood that the use of personally identifiable information should comply with privacy policies and practices generally considered to meet or exceed industry or governmental requirements for protecting user privacy. In particular, personally identifiable information data should be managed and processed to minimize the risk of unintentional or unauthorized access or use, and the nature of authorized use should be clearly indicated to the user.

Claims

1. A method for determining interface timing parameters of a communication terminal tester, characterized in that, The communication terminal tester includes a first processor, a second processor, and an radio frequency circuit. The first processor is configured to run a scheduler program and an L1 layer control plane program. The scheduler program is used to schedule and control air interface time-frequency resources, and the L1 layer control plane program is used to perform L1 layer resource control and interface interaction. The second processor is configured to run a signal processing algorithm program and interact with the first processor and the radio frequency circuit. The first processor is configured with shared memory for interface interaction with the second processor. The method includes: The values ​​of the first, second, and third parameters corresponding to the target subcarrier interval are obtained. The first parameter is the number of basic time units required for the maximum processing time of the L1 layer control plane program. The second parameter is the number of basic time units required for the maximum processing time of the signal processing algorithm program. The third parameter is the number of basic time units that need to be delayed in the transmission timing after the L1 layer control plane program has finished writing the first partition of the shared memory and before the second processor reads the first partition. The basic time unit is the single time slot length corresponding to the maximum subcarrier interval in the application scenario supported by the communication terminal tester. Based on the corresponding values ​​of the first, second, and third parameters, the first value range of the fourth parameter, the second value range of the fifth parameter, and the third value range of the sixth parameter are obtained respectively. The fourth parameter is the number of basic time units that the scheduler program needs to advance the scheduling relative to the RF circuit's transmission of the RF signal in the transmission timing sequence; the fifth parameter is the number of basic time units that the L1 layer control plane program needs to advance the writing of the first partition relative to the RF circuit's transmission of the RF signal in the transmission timing sequence; and the sixth parameter is the number of basic time units that the L1 layer control plane program needs to delay in reading the second partition of the shared memory relative to the RF circuit's reception of the RF signal in the reception timing sequence. The first value range of the fourth parameter, the second value range of the fifth parameter, and the third value range of the sixth parameter are output so that the value of the fourth parameter in the first value range, the value of the fifth parameter in the second value range, and the value of the sixth parameter in the third value range can be determined by debugging the communication terminal tester.

2. The method as described in claim 1, characterized in that, The step of obtaining the first value range of the fourth parameter, the second value range of the fifth parameter, and the third value range of the sixth parameter based on the corresponding values ​​of the first parameter, the second parameter, and the third parameter includes: The first value range of the fourth parameter is obtained according to the first constraint condition, wherein the first constraint condition includes: the difference between the product of the fourth parameter and the basic time unit and the sum of the products of the first parameter and the basic time unit, the second parameter and the basic time unit, and the third parameter and the basic time unit is greater than zero; or the difference between the fourth parameter and the sum of the first parameter, the second parameter, and the third parameter is greater than zero.

3. The method as described in claim 1, characterized in that, The step of obtaining the first value range of the fourth parameter, the second value range of the fifth parameter, and the third value range of the sixth parameter based on the corresponding values ​​of the first parameter, the second parameter, and the third parameter includes: The second range of values ​​for the fifth parameter is obtained according to the second constraint condition, wherein the second constraint condition includes: the difference between the product of the fifth parameter and the basic time unit and the sum of the product of the second parameter and the basic time unit and the product of the third parameter and the basic time unit is greater than zero; or the difference between the fifth parameter and the sum of the second parameter and the third parameter is greater than zero.

4. The method as described in claim 1, characterized in that, The step of obtaining the first value range of the fourth parameter, the second value range of the fifth parameter, and the third value range of the sixth parameter based on the corresponding values ​​of the first parameter, the second parameter, and the third parameter includes: The third range of values ​​for the sixth parameter is obtained based on the third constraint condition, wherein the third constraint condition includes: the difference between the product of the sixth parameter and the basic time unit and the product of the second parameter and the basic time unit is greater than zero; or the difference between the sixth parameter and the second parameter is greater than zero.

5. The method according to any one of claims 1-4, characterized in that, Also includes: The value of the seventh parameter is determined based on the corresponding values ​​of the fifth parameter, the sixth parameter, and the total length of the shared memory partition. The seventh parameter is the number of basic time units required for the first partition to be written to and cleared.

6. The method as described in claim 5, characterized in that, The step of determining the value of the seventh parameter based on the corresponding values ​​of the fifth parameter, the sixth parameter, and the total length of the shared memory partition includes: The value of the seventh parameter is determined according to the fourth constraint, wherein the fourth constraint includes: the seventh parameter is greater than the largest of the fifth and sixth parameters, and less than the total length of the shared memory partition.

7. The method according to any one of claims 1-4, characterized in that, The values ​​of the first, second, and third parameters corresponding to the target subcarrier interval are determined based on the chip characteristics of the first and second processors and the target application scenario for which the communication terminal tester is used.

8. The method according to any one of claims 1-4, characterized in that, The index number of the first partition is determined based on the time slot number of the radio frequency circuit transmitting radio frequency signals; the index number of the second partition is determined based on the time slot number of the radio frequency circuit receiving radio frequency signals.

9. The method according to any one of claims 1-4, characterized in that, The basic time unit is equal to the period of the external interrupt of the first processor.

10. The method as described in claim 5, characterized in that, Also includes: The corresponding values ​​of the first parameter, the second parameter, the third parameter, the fourth parameter, the fifth parameter, the sixth parameter, and the seventh parameter are configured into the first processor and the second processor.

11. A communication terminal tester, characterized in that, include: Radio frequency circuits; The first processor is configured to run a scheduler program and an L1 control plane program. The scheduler program is used to schedule and control air interface time and frequency resources, and the L1 control plane program is used to perform L1 layer resource control and interface interaction. as well as The second processor is configured to run signal processing algorithm programs and interact with the first processor and the radio frequency circuit, wherein the first processor is configured with shared memory for interfacing with the second processor. The radio frequency circuit, the first processor, and the second processor operate according to the interface timing parameters determined by the method as described in any one of claims 1-10.

12. An electronic device, characterized in that, include: One or more processors; as well as One or more memories coupled to the one or more processors and storing instructions thereon, which, when executed individually or jointly by the one or more processors, cause the electronic device to perform the method of any one of claims 1-10.

13. A chip, characterized in that, Includes a circuit system configured to perform the method of any one of claims 1-10.

14. A non-transitory computer-readable storage medium storing machine-executable instructions, which, when executed by one or more processors of a machine, cause the machine to perform the method of any one of claims 1-10.

15. A computer program product comprising machine-executable instructions, which, when executed by one or more processors of a machine, cause the machine to perform the method of any one of claims 1-10.

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